Analog Devices AD8348 Service Manual

O

S

V

50 MHz to 1000 MHz

FEATURES

Integrated I/Q demodulator with IF VGA amplifier
Operating IF frequency 50 MHz to 1000 MHz

(3 dB IF BW of 500 MHz driven from R
Demodulation bandwidth 75 MHz
Linear-in-decibel AGC range 44 dB
Third-order intercept

IIP3 +28 dBm @ minimum gain (FIF = 380 MHz)

IIP3 −8 dBm @ maximum gain (F
Quadrature demodulation accuracy

Phase accuracy 0.5°

Amplitude balance 0.25 dB
Noise figure 11 dB @ maximum gain (FIF = 380 MHz)
LO input −10 dBm
Single supply 2.7 V to 5.5 V
Power-down mode
Compact, 28-lead TSSOP package

APPLICATIONS

QAM/QPSK demodulator
W-CDMA/CDMA/GSM/NADC
Wireless local loop
LMDS

GENERAL DESCRIPTION

= 200 Ω)

S

= 380 MHz)

IF

ENBL

VGIN

IFIP

IFIN

Quadrature Demodulator

AD8348

FUNCTIONAL BLOCK DIAGRAM

IMX

IOF

13

16

QOFS

VCMO

IAIN

6

DIVIDE

BY 2

PHASE

SPLITTER

23

QAIN

VCMO

15

11

10

17

BIAS
CELL

GAIN

CONTROL

REF

24

ENVG21QXMO

8

14

VREF

18

19

MXIN

MXIP

Figure 1.

IOPP3IOPN

4

AD8348

25

QOPP26QOPN

VCMO

5

LOIP

1

28

LOIN

03678-001

The AD8348 is a broadband quadrature demodulator with an
integrated intermediate frequency (IF), variable gain amplifier
(VGA), and integrated baseband amplifiers. It is suitable for use in
communications receivers, performing quadrature demodulation
from IF directly to baseband frequencies. The baseband amplifiers
are designed to interface directly with dual-channel ADCs, such
as the

AD9201, AD9283, and AD9218, for digitizing and post-

processing.

The IF input signal is fed into two Gilbert cell mixers through
an X-AMP® VGA. The IF VGA provides 44 dB of gain control.
A precision gain control circuit sets a linear-in-decibel gain char­acteristic for the VGA and provides temperature compensation.
The LO quadrature phase splitter employs a divide-by-2 frequency
divider to achieve high quadrature accuracy and amplitude balance
over the entire operating frequency range.

Optionally, the IF VGA can be disabled and bypassed. In this
mode, the IF signal is applied directly to the quadrature mixer
inputs via the MXIP and MXIN pins.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Separate I- and Q-channel baseband amplifiers follow the baseband
outputs of the mixers. The voltage applied to the VCMO pin sets
the dc common-mode voltage level at the baseband outputs.
Typically, VCMO is connected to the internal VREF voltage, but
it can also be connected to an external voltage. This flexibility
allows the user to maximize the input dynamic range to the ADC.
Connecting a bypass capacitor at each offset compensation input
(IOFS and QOFS) nulls dc offsets produced in the mixer. Offset
compensation can be overridden by applying an external voltage
at the offset compensation inputs.

The mixers’ outputs are brought off-chip for optional filtering
before final amplification. Inserting a channel selection filter
before each baseband amplifier increases the baseband amplifiers’
signal handling range by reducing the amplitude of high level,
out-of-channel interferers before the baseband signal is fed into
the I/Q baseband amplifiers. The single-ended mixer output is
amplified and converted to a differential signal for driving ADCs.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8348

TABLE OF CONTENTS

Features .............................................................................................. 1

Enable........................................................................................... 18

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Equivalent Circuits........................................................................... 9

Typical Performance Characteristics ........................................... 11

VGA and Demodulator .............................................................11

Demodulator Using MXIP and MXIN.................................... 14

Final Baseband Amplifiers ........................................................15

VGA/Demodulator and Baseband Amplifier......................... 16

Theory of Operation ...................................................................... 18

Baseband Offset Cancellation................................................... 18

Applications..................................................................................... 20

Basic Connections...................................................................... 20

Power Supply............................................................................... 20

Device Enable ............................................................................. 20

VGA Enable ................................................................................ 20

Gain Control............................................................................... 20

LO Inputs..................................................................................... 20

IF Inputs ...................................................................................... 20

MX Inputs ................................................................................... 20

Baseband Outputs ...................................................................... 21

Output DC Bias Level................................................................ 21

Interfacing to Detector for AGC Operation............................... 21

Baseband Filters.......................................................................... 22

LO Generation ............................................................................ 23

VGA.............................................................................................. 18

Downconversion Mixers ........................................................... 18

Phase Splitter............................................................................... 18

I/Q Baseband Amplifiers........................................................... 18

REVISION HISTORY

4/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Specifications................................................................ 3

Changes to IF Inputs Section ........................................................20

Changes to Evaluation Board Section.......................................... 23

Changes to Table 6.......................................................................... 27

Changes to Ordering Guide.......................................................... 28

8/03—Revision 0: Initial Version

Evaluation Board ........................................................................ 23

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. A | Page 2 of 28

AD8348

SPECIFICATIONS

VS = 5 V, TA = 25oC, FLO = 380 MHz, FIF = 381 MHz, PLO = −10 dBm, RS (LO) = 50 Ω, RS (IFIP and MXIP/MXIN) = 200 Ω, unless
otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

OPERATING CONDITIONS

LO Frequency Range External input = 2 × LO frequency 100 2000 MHz
IF Frequency Range 50 1000 MHz
Baseband Bandwidth 75 MHz
LO Input Level 50 Ω source −12 −10 0 dBm
V

(VS) 2.7 5.5 V

SUPPLY

Temperature Range −40 +85 °C
IF FRONT END WITH VGA IFIP to IMXO (QMXO),
ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ

Input Impedance Measured differentially across MXIP/MXIN 200||1.1 Ω||pF

Gain Control Range 44 dB

Maximum Conversion Voltage Gain VGIN = 0.2 V (maximum voltage gain) 25.5 dB

Minimum Conversion Voltage Gain VGIN = 1.2 V (minimum voltage gain) −18.5 dB

3 dB Bandwidth 500 MHz

Gain Control Linearity VGIN = 0.4 V (+21 dB) to 1.1 V (−14 dB) ±0.5 dB

IF Gain Flatness FIF = 380 MHz ± 5% (VGIN = 1.2 V) 0.1 dB p-p

F

Input 1 dB Compression Point (P1dB) VGIN = 0.2 V (maximum gain) −22 dBm

VGIN = 1.2 V (maximum gain) +13 dBm

Second-Order Input Intercept (IIP2) IF1 = 385 MHz, IF2 = 386 MHz

+3 dBm each tone from 200 Ω source, 65 dBm

VGIN = 1.2 V (minimum gain)

−42 dBm each tone from 200 Ω source, 18 dBm

VGIN = 0.2 V (maximum gain)

Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz

VGIN = 1.2 V (minimum gain)

VGIN = 0.2 V (maximum gain)

LO Leakage Measured at IFIP, IFIN −80 dBm

Measured at IMXO/QMXO (LO = 50 MHz) −60 dBm

Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz

Quadrature Phase Error

1

vs. temperature −0.0032 °/°C

vs. baseband frequency (dc to 30 MHz) +0.01 °/MHz

I/Q Amplitude Imbalance

1

vs. temperature 0 dB/°C

vs. baseband frequency (dc to 30 MHz) ±0.0125 dB

Noise Figure (Double Sideband)

Mixer Output Impedance 40

Capacitive Load Shunt from IMXO, QMXO to VCMO 0 10 pF

Resistive Load Shunt from IMXO, QMXO to VCMO 200 1.5 kΩ

Mixer Peak Output Current 2.5 mA

= 900 MHz ± 5% (VGIN = 1.2 V) 1.3

IF

Each tone 10 dB below P1dB from

28 dBm

dB p-p

200 Ω source,

Each tone 10 dB below P1dB from

−8 dBm

200 Ω source,

LO = 380 MHz (LOIP/LOIN 760 MHz) −0.7 ±0.1 +0.7 Degrees

−0.3 ±0.05 +0.3 dB

Maximum gain, from 200 Ω source,
F

= 380 MHz

IF

10.75 dB

Ω

Rev. A | Page 3 of 28

AD8348

Parameter Conditions Min Typ Max Unit

IF FRONT END WITHOUT VGA From MXIP, MXIN to IMXO (QMXO),
ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ

Input Impedance Measured differentially across MXIP/MXIN 200||1.5 Ω||pF
Conversion voltage Gain 10.5 dB
3 dB Output Bandwidth 75 MHz
IF Gain Flatness FIF = 380 MHZ ± 5% 0.1 dB p-p
F
Input 1 dB Compression Point (P1dB) −4 dBm
Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz 14 dBm

LO Leakage Measured at MXIP/MXIN −70 dBm
Measured at IMXO, QMXO −60 dBm
Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz
Quadrature Phase Error

I/Q Amplitude Imbalance 0.25 dB
Noise Figure (Double Sideband) From 200 Ω source, FIF = 380 MHz 21 dB

I/Q BASEBAND AMPLIFIER

Gain 20 dB
Bandwidth 10 pF differential load 125 MHz
Output DC Offset (Differential)

Output Common-Mode Offset (V
Group Delay Flatness 0 MHz to 50 MHz 3 ns p-p
Input-Referred Noise Voltage Frequency = 1 MHz 8 nV/√Hz
Output Swing Limit (Upper) VS −1 V
Output Swing Limit (Lower) 0.5 V
Peak Output Current 1 mA
Input Impedance 50||1 kΩ||pF
Input Bias Current 2 μA

RESPONSE FROM IF AND MX INPUTS TO

BASEBAND AMPLIFIER OUTPUT

Gain From MXIP/MXIN 30.5 dB
From IFIP/IFIN, VGIN = 0.2 V 45.5 dB
From IFIP/IFIN, VGIN = 1.2 V 1.5 dB
CONTROL INPUT/OUTPUTS

VCMO Input Range VS = 5 V 0.5 1 4 V

V

VREF Output Voltage 0.95 1 1.05 V

Gain Control Voltage Range VGIN 0.2 1.2 V

Gain Slope −55 −50 −45 dB/V

Gain Intercept

Gain Control Input Bias Current 1 μA
LO INPUTS

LOIP Input Return Loss

= 900 MHZ ± 5% 0.15 dB p-p

IF

Each tone 10 dB below P1dB from
200 Ω source

LO = 380 MHz (LOIP/LOIN 760 MHz,

−2 ±0.5 +2 Degrees

single-ended)

From IAIN to IOPP/IOPN and QAIN to QOPP/
QOPN, R

= 2 kΩ, single-ended to ground

LOAD

LO leakage offset corrected using 500 pF

− V

capacitor on IOFS, QOFS (V

+ V

IOPP

)/2 − VCMO −75 ±35 +75 mV

IOPN

IOPP

IOPN

)

IMXO and QMXO connected directly to

−50 ±12 +50 mV

IAIN and QAIN, respectively

= 2.7 V 0.5 1 1.7 V

S

Linear extrapolation back to theoretical

55 61 67 dB

gain at VGIN = 0 V

LOIN ac-coupled to ground

−6 dB

(760 MHz applied to LOIP)

Rev. A | Page 4 of 28

AD8348

Parameter Conditions Min Typ Max Unit

POWER-UP CONTROL

ENBL Threshold Low Low = standby 0 VS/2 1 V
ENBL Threshold High High = enable VS − 1 VS/2 V
Input Bias Current 2 μA
Power-Up Time

Time for final baseband amplifiers to be

45 μs

within 90% of final amplitude

Power-Down Time

Time for supply current to be <10% of

700 ns

enabled value

POWER SUPPLIES VPOS1, VPOS2, VPOS3

Voltage 2.7 5.5 V
Current (Enabled) VS = 5 V, V
Current (Standby) VS = 5 V, V

1

These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean.

= 5 V 38 48 58 mA

ENBL

= 0 V 75 μA

ENBL

V

S

Rev. A | Page 5 of 28

AD8348

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage on VPOS1, VPOS2, VPOS3 Pins 5.5 V
LO Input Power 10 dBm (re: 50 Ω)
IF Input Power 18 dBm (re: 200 Ω)
Internal Power Dissipation 450 mW
θ

JA

Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C

68°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 6 of 28

AD8348

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

LOIP

2

VPOS1

IOPN

IOPP

VCMO

IAIN

COM3

IMXO

COM2

IFIN

IFIP

VPOS2

IOFS

VREF

3

4

5

6

7

8

9

10

11

12

13

14

AD8348

TOP VIEW

(Not to Scale)

Figure 2. 28-Lead TSSOP Pin Configuration

Table 3. Pin Function Descriptions—28-Lead TSSOP

Pin No. Mnemonic Description

1, 28 LOIP, LOIN

LO Inputs. For optimum performance, these inputs should be ac-coupled and driven
differentially. Differential drive from single-ended sources can be achieved via a balun.
To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between
LOIP and LOIN. Typical input drive level is equal to −10 dBm.

2, 12, 20

3, 4, 25, 26

5 VCMO

VPOS1, VPOS2,
VPOS3

IOPN, IOPP,
QOPP, QOPN

Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins
should be decoupled with 0.1 μF and 100 pF capacitors.

I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p
differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.

Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dc
common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN,
QOPP, QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference
voltage from another device (typically an ADC).

6, 23 IAIN, QAIN

I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are
referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If
IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If
an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the
source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential

outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.
7, 22 COM3 Ground for Biasing and Baseband Sections.
8, 21 IMXO, QMXO

I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose

bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected

to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a

maximum current of 2.5 mA.
9 COM2 IF Section Ground.
10, 11 IFIN, IFIP

IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should

be ac-coupled into IFIP. The nominal differential input impedance of these pins is 200 Ω.

For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; R

= 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348

R

SHUNT

does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor

can be placed between IFIP and IFIN.
13, 16 IOFS, QOFS

I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)

can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a

fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can

extend the operating frequency range to include dc. The QOFS pin can likewise be used

to null offsets on the Q-channel mixer output (QMXO).
14 VREF

Reference Voltage Output. This output voltage (1 V) is the main bias level for the device

and can be used to externally bias the inputs and outputs of the baseband amplifiers.

The typical maximum drive current for this output is 2 mA.

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LOIN

COM1

QOPN

QOPP

ENVG

QAIN

COM3

QMXO

VPOS3

MXIN

MXIP

VGIN

QOFS

ENBL

03678-002

Equivalent
Circuit

A

B

C

D

H

E

= 174 Ω,

SERIES

F

G

Rev. A | Page 7 of 28

AD8348

Equivalent

Pin No. Mnemonic Description

15 ENBL Chip Enable Input. Active high. Threshold is equal to VS/2. D
17 VGIN

18, 19 MXIP, MXIN

24 ENVG

27 COM1 LO Section Ground.

Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain
control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range
from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and
QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to
IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative
sense (that is, increasing voltage decreases gain).

Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and
MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully
differential inputs that should be ac-coupled to the signal source.

Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP
and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and
IFIP and IFIN inputs are disabled.

Circuit

D

I

D

Rev. A | Page 8 of 28

AD8348

V

V

V

V

V

V

EQUIVALENT CIRCUITS

POS1

LOIN

LOIP

POS3

COM1

Figure 3. Circuit A

COM3

Figure 4. Circuit B

POS3

IOPP, IOPN,
QOPP, QOPN

VCMO

POS3

IAIN, QAIN, VGIN,

ENBL, ENVG

03678-003

COM3

03678-006

Figure 6. Circuit D

POS2

IFIP

IFIN

03678-004

COM3

03678-007

Figure 7. Circuit E

POS3

50µA
MAX

VCMO

COM3

Figure 5. Circuit C

03678-005

Rev. A | Page 9 of 28

IOFS,
QOFS

COM3

Figure 8. Circuit F

03678-008