Analog Devices AD8346 Service Manual

0.8 GHz to 2.5 GHz

FEATURES

High accuracy

1 degree rms quadrature error @ 1.9 GHz

0.2 dB I/Q amplitude balance @ 1.9 GHz Broad frequency range: 0.8 GHz to 2.5 GHz Sideband suppression: −46 dBc @ 0.8 GHz Sideband suppression: −36 dBc @ 1.9 GHz Modulation bandwidth: dc to 70 MHz 0 dBm output compression level @ 0.8 GHz Noise floor: −147 dBm/Hz Single 2.7 V to 5.5 V supply Quiescent operating current: 45 mA Standby current: 1 μA 16-lead TSSOP

APPLICATIONS

Digital and spread spectrum communication systems Cellular/PCS/ISM transceivers Wireless LAN/wireless local loop QPSK/GMSK/QAM modulators Single-sideband (SSB) modulators Frequency synthesizers Image reject mixer

GENERAL DESCRIPTION

The AD8346 is a silicon RFIC I/Q modulator for use from

0.8 GHz to 2.5 GHz. Its excellent phase accuracy and amplitude balance allow high performance direct modulation to RF.

The differential LO input is applied to a polyphase network phase splitter that provides accurate phase quadrature from

0.8 GHz to 2.5 GHz. Buffer amplifiers are inserted between two sections of the phase splitter to improve the signal-tonoise ratio. The I and Q outputs of the phase splitter drive the LO inputs of two Gilbert-cell mixers. Two differential V-to-I converters connected to the baseband inputs provide the baseband modulation signals for the mixers. The outputs of the two mixers are summed together at an amplifier which is designed to drive a 50 Ω load.

Quadrature Modulator

AD8346

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

COM1

LOIN

LOIP

VPS1

ENBL

PHASE

SPLITTER

BIAS

AD8346

Figure 1.

This quadrature modulator can be used as the transmit modulator in digital systems such as PCS, DCS, GSM, CDMA, and ISM transceivers. The baseband quadrature inputs are directly modulated by the LO signal to produce various QPSK and QAM formats at the RF output.

Additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution.

The AD8346 comes in a 16-lead TSSOP package, measuring

6.5 mm × 5.1 mm × 1.1 mm. It is specified to operate over a

−40°C to +85°C temperature range and a 2.7 V to 5.5 V supply voltage range. The device is fabricated on Analog Devices’ high performance 25 GHz bipolar silicon process.

QBBP

QBBN

COM4

VPS2

VOUT

COM3

COM2

05335-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

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AD8346

TABLE OF CONTENTS

Specifications..................................................................................... 3

Bias ............................................................................................... 10

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Equivalent Circuits........................................................................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description......................................................................... 10

Overview...................................................................................... 10

LO Interface................................................................................. 10

V-to-I Converter......................................................................... 10

Mixers .......................................................................................... 10

Differential-to-Single-Ended Converter .................................10

REVISION HISTORY

6/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Figures 30, 31, 32........................................................ 14

Update Outline Dimensions ......................................................... 18

Changes to Ordering Guide.......................................................... 18

Basic Connections...................................................................... 11

LO Drive ...................................................................................... 11

RF Output.................................................................................... 11

Interface to AD9761 TXDAC® .................................................. 12

AC-Coupled Interface ............................................................... 13

Evaluation Board ............................................................................ 14

Characterization Setups................................................................. 16

SSB Setup..................................................................................... 16

CDMA Setup............................................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

3/99—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD8346

SPECIFICATIONS

VS = 5 V; TA = 25°C; LO frequency = 1900 MHz; LO level = –10 dBm; BB frequency = 100 kHz; BB inputs are dc-biased to 1.2 V; BB input level = 1.0 V p-p each pin for 2.0 V p-p differential drive; LO source and RF output load impedances are 50 Ω, dBm units are referenced to 50 Ω unless otherwise noted.

Table 1.

Parameters Conditions Min Typ Max Unit

RF OUTPUT

Operating Frequency 0.8 2.5 GHz Quadrature Phase Error See Figure 35 for setup 1 Degree rms I/Q Amplitude Balance See Figure 35 for setup 0.2 dB Output Power I and Q channels in quadrature −13 −10 −6 dBm Output VSWR 1.25:1 Output P1 dB −3 dBm Carrier Feedthrough −42 −35 dBm Sideband Suppression −36 −25 dBc IM3 Suppression −60 dBc Equivalent Output IP3 20 dBm Output Noise Floor 20 MHz offset from LO −147 dBm/Hz

RESPONSE TO CDMA IS95 BASEBAND SIGNALS

ACPR (Adjacent Channel Power Ratio) See Figure 35 for setup −72 dBc EVM (Error Vector Magnitude) See Figure 35 for setup 2.5 % Rho (Waveform Quality Factor) See Figure 35 for setup 0.9974

MODULATION INPUT

Input Resistance 12 kΩ Modulation Bandwidth −3 dB 70 MHz

LO INPUT

LO Drive Level −12 −6 dBm Input VSWR 1.9:1

ENABLE

ENBL HI Threshold 2.0 V ENBL LO Threshold 0.5 V ENBL Turn-On Time

ENBL Turn-Off Time

POWER SUPPLIES

Voltage 2.7 5.5 V Current Active (ENBL HI) 35 45 55 mA Current Standby (ENBL LO) 1 20 μA

Settle to within 0.5 dB of final SSB

output power

Time for supply current to drop below

2 mA

2.5 μs

12 μs

Rev. A | Page 3 of 20

AD8346

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Min Rating

Supply Voltage VPS1, VPS2 5.5 V Input Power LOIP, LOIN (relative to 50 Ω) 10 dBm Min Input Voltage IBBP, IBBN, QBBP, QBBN 0 V Max Input Voltage IBBP, IBBN, QBBP, QBBN 2.5 V Internal Power Dissipation 500 mW θJA 125°C/W Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 4 of 20

AD8346

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IBBP QBBP

IBBN QBBN

COM1 COM4

LOIN VPS2 LOIP VOUT

VPS1 COM3

ENBL COM2

AD8346

TOP VIEW

(Not to Scale)

05335-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Equivalent

Pin No. Mnemonic Description

1 IBBP

I Channel Baseband Positive Input Pin. Input should be dc-biased to approximately 1.2 V.

Circuit

Circuit A Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input 2 V p-p when IBBN is 180 degrees out of phase from IBBP.

2 IBBN

I Channel Baseband Negative Input Pin. Input should be dc-biased to approximately 1.2 V.

Circuit A Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input 2 V p-p when IBBN is 180 degrees out of phase from IBBP.

3 COM1 Ground Pin for the LO phase splitter and LO buffers. 4 COM1 Ground Pin for the LO phase splitter and LO buffers. 5 LOIN

LO Negative Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This

Circuit B pin must be ac coupled.

6 LOIP

LO Positive Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This pin

Circuit B must be ac-coupled.

7 VPS1

Power Supply Pin for the bias cell and LO buffers. This pin should be decoupled using local 100 pF and 0.01 μF capacitors.

8 ENBL Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C 9 COM2 Ground Pin for the input stage of output amplifier. 10 COM3 Ground Pin for the output stage of output amplifier. 11 VOUT 50 Ω DC-Coupled RF Output. User must provide ac coupling on this pin. Circuit D 12 VPS2

Power Supply Pin for baseband input voltage to current converters and mixer core. This pin should be decoupled using local 100 pF and 0.01 μF capacitors.

13 COM4 Ground Pin for baseband input voltage to current converters and mixer core. 14 COM4 Ground Pin for baseband input voltage to current converters and mixer core. 15 QBBN

Q Channel Baseband Negative Input. Input should be dc biased to approximately 1.2 V.

Circuit A Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when QBBN is 180° out of phase from QBBP.

16 QBBP

Q Channel Baseband Positive Input. Input should be dc-biased to approximately 1.2 V.

Circuit A Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when QBBN is 180° out of phase from QBBP.

Rev. A | Page 5 of 20

AD8346

EQUIVALENT CIRCUITS

VPS2

INPUT

9kΩ

3kΩ

ACTIVE LOADS

BUFFER

TO MIXER CORE

05335-003

ENBL

VPS1

30kΩ

40kΩ

75kΩ

TO BIAS FOR STARTUP/ SHUTDOWN

780Ω

05335-005

Figure 5. Circuit C

VPS2

43Ω

Figure 6. Circuit D

OUT

05335-006

LOIN

LOIP

VPS1

Figure 3. Circuit A

Figure 4. Circuit B

PHASE

SPLITTER

CONTINUES

05335-004

Rev. A | Page 6 of 20

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