Analog Devices AD8345 Service Manual

140 MHz to 1000 MHz

FEATURES

140 MHz to 1000 MHz operating frequency +2.5 dBm P1dB @ 800 MHz

−155 dBm/Hz noise floor

0.5 degree RMS phase error (IS95)

0.2 dB amplitude balance Single 2.7 V to 5.5 V supply Pin-compatible with AD8346 and AD8349 16-lead TSSOP_EP package

APPLICATIONS

Cellular communication systems W-CDMA/CDMA/GSM/PCS/ISM transceivers Fixed broadband access systems LMDS/MMDS Wireless LAN Wireless local loop Digital TV/CATV modulators Single sideband upconverter

PRODUCT DESCRIPTION

Quadrature Modulator

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

COM3

COM1

LOIN

LOIP

VPS1

ENBL

APPLICATIONS

AD8345

PHASE

SPLITTER

BIAS

Figure 1.

AD8345

QBBP

QBBN

COM3

VPS2

VOUT

COM2

COM3

00932-001

The AD8345 is a silicon RFIC quadrature modulator, designed for use from 140 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable the high performance direct modulation of an IF carrier.

The AD8345 accurately splits the external LO signal into two quadrature components through the polyphase phase splitter network. The I and Q LO components are mixed with the baseband I and Q differential input signals. Finally, the outputs of the two mixers are combined in the output stage to provide a single-ended 50 Ω drive at VOUT.

The AD8345 modulator can be used as the IF transmit modulator in digital communication systems such as GSM and PCS transceivers. It can also directly modulate an LO signal to produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV systems.

Additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution.

The AD8345 modulator is supplied in a 16-lead TSSOP_EP package. Its performance is specified over a −40°C to +85°C temperature range. This device is fabricated on Analog Devices’ advanced silicon bipolar process.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8345

TABLE OF CONTENTS

Features.............................................................................................. 1

Basic Connections .......................................................................... 12

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Description......................................................................... 1

Applications....................................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Equivalent Circuits......................................................................... 10

Circuit Description......................................................................... 11

Overview...................................................................................... 11

LO Interface................................................................................. 11

Differential Voltage-to-Current Converter............................. 11

LO Drive...................................................................................... 12

LO Frequency Range ................................................................. 12

Baseband I and Q Channel Drive ............................................ 13

Reduction of LO Leakage.......................................................... 13

Single-Ended I and Q Drive...................................................... 13

RF Output.................................................................................... 14

Application with TxDAC®......................................................... 14

Soldering Information............................................................... 15

Evaluation Board........................................................................ 15

Characterization Setups................................................................. 17

SSB Setup..................................................................................... 17

Modulated Waveform Setup ..................................................... 18

CDMA IS95................................................................................. 18

WCDMA 3GPP.......................................................................... 18

GSM ............................................................................................. 18

Mixers .......................................................................................... 11

Differential-to-Single-Ended Converter ................................. 11

Bias ............................................................................................... 11

REVISION HISTORY

12/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Ordering Guide.......................................................... 19

4/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Part Name .........................................................Universal

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 19

7/01—Revision 0: Initial Version

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. B | Page 2 of 20

AD8345

SPECIFICATIONS

VS = 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V ±0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RF OUTPUT

Operating Frequency

140 1000 MHz

Output Power 0.5 dBm 140 MHz

0.5 dBm 220 MHz

−3 −1 +2 dBm 800 MHz Output P1dB 2.5 dBm Noise Floor −155 dBm/Hz 20 MHz offset from LO, all BB inputs at 0.7 V Quadrature Error 0.5 Degree rms CDMA IS95 setup (see Figure 38) I/Q Amplitude Balance 0.2 dB CDMA IS95 setup (see Figure 38) LO Leakage −41 dBm 140 MHz

−40 dBm 220 MHz

−42 −33 dBm 800 MHz Sideband Rejection −33 dBc 140 MHz

−48 −40 dBc 220 MHz

−42 −34 dBc 800 MHz Third Order Distortion −52 dBc Second Order Distortion −60 dBc Equivalent Output IP3 25 dBm Equivalent Output IP2 59 dBm

Output Return Loss (S22) −20 dB RESPONSE TO CDMA IS95 See Figure 38 BASEBAND SIGNALS

ACPR −72 dBc

EVM 1.3 %

Rho 0.9995 LO INPUT

LO Drive level −10 −2 0 dBm

LOIP Input Return Loss (S11)

−5 dB No termination on LOIP, LOIN at ac ground

−9 dB 50 Ω terminating resistor, differential drive via balun BASEBAND INPUTS

Input Bias Current 10 μA

Input Capacitance 2 pF

DC Common Level 0.6 0.7 0.8 V

Bandwidth (3 dB) 80 MHz Full power (0.7 V ±0.3 V on each input, see Figure 4) ENABLE

Turn-On 2.5 μs Enable high to output within 0.5 dB of final value

Turn-Off 1.5 μs Enable low to supply current dropping below 2 mA

ENBL High Threshold (Logic 1) +VS/2 V

ENBL Low Threshold (Logic 0) +VS/2 V POWER SUPPLIES

Voltage 2.7 5.5 V

Current Active 50 65 78 mA

Current Standby 70 μA

For information on operation below 140 MHz, see Figure 29.

See the LO Interface section for more details on input matching.

= 25°C, unless otherwise noted.

Rev. B | Page 3 of 20

AD8345

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPS1, VPS2 5.5 V Input Power LOIP, LOIN (re 50 Ω) 10 dBm IBBP, IBBN, QBBP, QBBN 0 V, 2.5 V Internal Power Dissipation 500 mW θJA (Exposed Paddle Soldered Down) 30°C/W θJA (Exposed Paddle not Soldered Down) 95°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering 60 sec) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. B | Page 4 of 20

AD8345

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IBBP

IBBN

COM3 COM1

LOIN

LOIP

VPS1

ENBL COM3

AD8345

TOP VIEW

(Not t o Scal e)

QBBP

QBBN

COM3

VPS2

VOUT

COM2

00932-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description Equivalent Circuit

1, 2 IBBP, IBBN

I Channel Baseband Differential Input Pins. These high impedance inputs should be

Circuit A dc-biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications.

3, 9, 13, 14 COM3 Ground Pin for Input V-to-I Converters and Mixer Core. 4 COM1 Ground Pin for the LO Phase Splitter and LO Buffers. 5, 6 LOIN, LOIP

Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ V

= 5 V) is supplied.

Circuit B Pins must be ac-coupled. Single-ended or differential drive is permissible.

7 VPS1

Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors.

8 ENBL Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C 10 COM2 Ground Pin for the Output Stage of Output Amplifier. 11 VOUT 50 Ω DC-Coupled RF Output. Pin should be ac-coupled. Circuit D 12 VPS2

Power Supply Pin for Baseband Input Voltage to Current Converters and Mixer Core. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors.

15, 16 QBBN, QBBP

Q Channel Baseband Differential Input Pins. Inputs should be dc-biased to approxi-

Circuit A mately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications.

Rev. B | Page 5 of 20

AD8345

TYPICAL PERFORMANCE CHARACTERISTICS

–2

–4

–6

–8

–10

–12

SSB POWER (dBm)

–14

–16

–18

–20

250

Figure 3. Single Sideband (SSB) Output Power (P

VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p

= 2.7V, DIFFERENTI AL INPUT = 200mV p-p

300 350 400 450 500 550 600 650 700 750 800 850 900 9501000

LO FREQUENCY (MHz)

) vs. LO Frequency (FLO)

OUT

(I and Q Inputs Driven in Quadrature at Baseband Frequency (F

= 25°C)

1.0

0.5

0.0

–0.5

VS = 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p

–1.0 –1.5

OUTPUT P OWER VARIATION ( d B)

–2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5

0.1

= 5V DIFFERENTIAL INPUT = 1.2V p-p

110

BASEBAND FREQ UENC Y ( M Hz )

Figure 4. I and Q Input Bandwidth

= 25°C, FLO = 800 MHz, LO Level = −2 dBm,

I and Q Inputs Driven in Quadrature)

0 –2 –4 –6 –8

–10 –12 –14 –16

SSB POWER (dBm)

–18 –20 –22 –24 –26

= 2.7V, DIFFERENTIAL INPUT = 200mV p-p

–40

–20 20 60

= 800 MHz, LO Level = −2 dBm, FBB = 1 MHz,

VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p

040

TEMPERATURE (°C)

Figure 5. SSB P

vs. Temperature

OUT

I and Q Inputs Driven in Quadrature)

00932-007

) = 1 MHz;

00932-008

100

00932-009

TA = –40°C

TA = +25°C

= +85°C

500 800

LO FRE QUENCY (MHz)

SSB OUTPUT P 1d B ( dBm)

–10

–12

–14

–16

–2

–4

–6

–8

250

350 650 950300 400 450 550 600 700 750 850 900 1000

Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. F

= 2.7 V, LO Level = −2 dBm,

I and Q Inputs Driven in Quadrature, F

4.0

3.5

SSB OUTPUT P1dB (dBm)

–0.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

250

= +25°C

350 650 950300 400 450 550 600 700 750 850 900 1000

500 800

LO FREQUENCY (MHz )

= –40°C

= +85°C

= 1 MHz)

Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. F

(VS = 5 V, LO Level = −2 dBm,

I and Q Inputs Driven in Quadrature, F

–40

–41

–42

–43

–44

VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p

–45

–46

–47

–48

CARRIER FEEDT HROUGH (dBm)

–49

–50

250

350 650 950300 400 450 550 600 700 750 850 900 1000

VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p

500 800

LO FREQUENCY (MHz)

Figure 8. Carrier Feedthrough vs. F

= 1 MHz)

(LO Level = −2 dBm, TA = 25°C)

00932-010

00932-011

00932-012

Rev. B | Page 6 of 20

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