Analog Devices AD8341 Service Manual

1.5 GHz to 2.4 GHz

FEATURES

Cartesian amplitude and phase modulation

1.5 GHz to 2.4 GHz frequency range
Continuous magnitude control of −4.5 dB to −34.5 dB
Continuous phase control of 0° to 360°
Output third-order intercept 17.5 dBm
Output 1 dB compression point 8.5 dBm
Output noise floor −150.5 dBm/Hz @ full gain
Adjustable modulation bandwidth up to 230 MHz
Fast output power disable

4.75 V to 5.25 V single-supply voltage

APPLICATIONS

RF PA linearization/RF predistortion
Amplitude and phase modulation
Variable attenuators and phase shifters
CDMA2000, WCDMA, GSM/EDGE linear power amplifiers
Smart antennas

GENERAL DESCRIPTION

The AD8341 vector modulator performs arbitrary amplitude
and phase modulation of an RF signal. Since the RF signal path
is linear, the original modulation is preserved. This part can be
used as a general-purpose RF modulator, a variable attenu­ator/phase shifter, or a remodulator. The amplitude can be
controlled from a maximum of −4.5 dB to less than −34.5 dB,
and the phase can be shifted continuously over the entire 360°
range. For maximum gain, the AD8341 delivers an OP1dB of

8.5 dBm, an OIP3 of 17.5 dBm, and an output noise floor of

−150.5 dBm/Hz, independent of phase. It operates over a
frequency range of 1.5 GHz to 2.4 GHz.

The baseband inputs in Cartesian I and Q format control the
amplitude and phase modulation imposed on the RF input
signal. Both I and Q inputs are dc-coupled with a ±500 mV
differential full-scale range. The maximum modulation band­width is 230 MHz, which can be reduced by adding external
capacitors to limit the noise bandwidth on the control lines.

RF Vector Modulator

AD8341

FUNCTIONAL BLOCK DIAGRAM

VPRF

90°

RFIP

RFIM

0°

CMOP

Figure 1.

Both the RF inputs and outputs can be used differentially or
single-ended and must be ac-coupled. The RF input and output
impedances are nominally 50 Ω over the operating frequency
range. The DSOP pin allows the output stage to be disabled
quickly in order to protect subsequent stages from overdrive.
The AD8341 operates off supply voltages from 4.75 V to 5.25 V
while consuming approximately 125 mA.

The AD8341 is fabricated on Analog Devices’ proprietary, high
performance 25 GHz SOI complementary bipolar IC process. It
is available in a 24-lead, Pb-free LFCSP package and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.

VPS2QBBMQBBP

RFOP

RFOM

DSOPIBBMIBBP

04700-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8341

TABLE OF CONTENTS

Specifications..................................................................................... 3

Applications..................................................................................... 12

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics............................................. 6

Theory of Operation ...................................................................... 10

RF Quadrature Generator .........................................................10

I-Q Attenuators and Baseband Amplifiers .............................. 11

Output Amplifier........................................................................ 11

Noise and Distortion.................................................................. 11

Gain and Phase Accuracy.......................................................... 11

RF Frequency Range .................................................................. 11

REVISION HISTORY

7/04—Revision 0: Initial Version

Using the AD8341 ...................................................................... 12

RF Input and Matching ............................................................. 12

RF Output and Matching .......................................................... 13

Driving the I-Q Baseband Controls......................................... 13

Interfacing to High Speed DACs.............................................. 14

CDMA2000 Application............................................................ 14

WCDMA Application ................................................................ 15

Evaluation Board ............................................................................ 17

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Rev. 0 | Page 2 of 20

AD8341

SPECIFICATIONS

VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 1.9 GHz, single-ended, ac-coupled source drive to RFIP through 1.2 nH series inductor, RFIM
ac-coupled through 1.2 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range 1.5 2.4 GHz
Maximum Gain Maximum gain setpoint for all phase setpoints −4.5 dB
Minimum Gain

= V

V

BBI

= 0 V differential

BBQ

(at recommended common-mode level)
Gain Control Range Relative to maximum gain 30 dB
Phase Control Range Over 30 dB control range 360 Degrees
Gain Flatness Over any 60 MHz bandwidth 0.5 dB
Group Delay Flatness Over any 60 MHz bandwidth 50 ps

RF INPUT STAGE RFIM, RFIP (Pins 21 and 22)

Input Return Loss From RFIP to CMRF (with 1.2 nH series inductors) 12 dB

CARTESIAN CONTROL INTERFACE (I AND Q) IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4)

Gain Scaling 2 1/V
Modulation Bandwidth 500 mV p-p, sinusoidal baseband input single-ended 230 MHz
Second Harmonic Distortion 500 mV p-p, 1 MHz, sinusoidal baseband input differential 41 dBc
Third Harmonic Distortion 500 mV p-p, 1 MHz, sinusoidal baseband input differential 47 dBc
Step Response

For gain setpoint from 0.1 to 0.9

(V

BBP

= 0.5 V, V

= 0.55 V to 0.95 V)

BBM

For gain setpoint from 0.9 to 0.1

(V

= 0.5 V, V

BBP

= 0.95 V to 0.55 V)

BBM

Recommended Common-Mode Level 0.5 V

RF OUTPUT STAGE RFOP, RFOM (Pins 9, 10)

Output Return Loss Measured through balun 7.5 dB

f = 1.9 GHz

Gain Maximum gain setpoint −4.5 dB
Output Noise Floor Maximum gain setpoint, no input −150.5 dBm/Hz
P

= 0 dBm, frequency offset = 20 MHz −149 dBm/Hz

IN

Output IP3 f1 = 1900 MHz, f2 = 1897.5 MHz, maximum gain setpoint 17.5 dBm
Adjacent Channel Power

CDMA2000, single carrier, P

= -4 dBm,

OUT

maximum gain, phase setpoint = 45° (See Figure 35)
Output 1 dB Compression Point Maximum gain 8.5 dBm

POWER SUPPLY

VPS2 (Pins 5, 6, and 14), VPRF (Pins 19 and 24),

RFOP, RFOM (Pins 9 and 10)
Positive Supply Voltage 4.75 5 5.25 V
Total Supply Current Includes load current 105 125 145 mA

OUTPUT DISABLE DSOP (Pin 13)

Disable Threshold (See Figure 24) Vs/2 V
Attenuation DSOP = 5 V 33 dB
Enable Response Time

Delay following high-to-low transition until

RF output amplitude is within 10% of final value.
Disable Response Time

Delay following low-to-high transition until

device produces full attenuation

−34.5 dB

45 ns

45 ns

−76 dBm

30 ns

15 ns

Rev. 0 | Page 3 of 20

AD8341

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameters Rating

Supply Voltage VPRF, VPS2 5.5 V
DSOP 5.5 V
IBBP, IBBM, QBBP, QBBM 2.5 V
RFOP, RFOM 5.5V
RF Input Power at Maximum Gain 13 dBm, re: 50 Ω

(RFIP or RFIM, Single-Ended Drive)

Equivalent Voltage 2.8 V p-p
Internal Power Dissipation 825 mW
θJA (With Pad Soldered to Board) 59 °C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie­tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 4 of 20

AD8341

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPRF

CMRF

RFIP

RFIM

CMRF

2322212019

PIN 1
INDICATOR

11

10

RFOP

RFOM

CMOP

CMOP

VPRF

12

CMOP

18
17
16
15
14
13

IFLP
IFLM
IBBP
IBBM
VPS2
DSOP

04700-002

24

QFLP

1

QFLM

2

QBBP

3
4
5
6

AD8341

TOP VIEW

(Not to Scale)

789

CMOP

QBBM

VPS2
VPS2

Figure 2. 24-Lead Lead Frame Chip Scale Package (LFCSP)

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1, 2 QFLP, QFLM

Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass

corner frequency.
3, 4 QBBP, QBBM Q Channel Differential Baseband Inputs.
5, 6, 14, 19, 24 VPS2, VPRF Positive Supply Voltage. 4.75 V − 5.25 V.
7, 8, 11, 12, 20, 23 CMOP, CMRF Device Common. Connect via lowest possible impedance to external circuit common.
9, 10 RFOP, RFOM Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal.
13 DSOP Output disable. Pull high to disable output stage.
15, 16 IBBM, IBBP I Channel Differential Baseband Inputs.
17, 18 IFLM, IFLP

I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass

corner frequency.
21, 22 RFIM, RFIP Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal.

Rev. 0 | Page 5 of 20

AD8341

TYPICAL PERFORMANCE CHARACTERISTICS

0

–5

PHASE SETPOINT = 270°

–10

–15

–20

GAIN (dB)

–25

–30

–35

–40

0.1

0 0.3 0.5 0.9 1.00.80.70.60.40.2

Figure 3. Gain Magnitude vs. Gain Setpoint at Different

Phase Setpoints, RF Frequency = 1900 MHz

6

PHASE SETPOINT = 315°

5
4

PHASE SETPOINT = 270°

3
2
1

0
–1
–2
–3
–4
–5

GAIN CONFORMANCE ERROR (dB)

–6
–7
–8

PHASE SETPOINT = 0°

PHASE SETPOINT = 90°

PHASE SETPOINT = 180°

PHASE SETPOINT = 135°

0 0.1 1.00.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 4. Gain Conformance Error vs. Gain Setpoint at

Different Phase Setpoints, RF Frequency = 1900 MHz

–2
–4
–6

–8
–10
–12
–14
–16

GAIN (dB)

–18
–20
–22
–24
–26
–28

45

Figure 5. Gain Magnitude vs. Phase Setpoint at Different

Gain Setpoints, RF Frequency = 1900 MHz

PHASE SETPOINT = 0°

PHASE SETPOINT = 180°

PHASE SETPOINT = 90°

GAIN SETPOINT

PHASE SETPOINT = 45°

PHASE SETPOINT = 225°

GAIN SETPOINT

GAIN SETPOINT = 1.0

GAIN SETPOINT = 0.5

GAIN SETPOINT = 0.25

GAIN SETPOINT = 0.1

PHASE SETPOINT (Degrees)

04700-003

04700-004

0.9

315270 36018090 135 2250

04700-005

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5

GAIN CONFORMANCE ERROR (dB)

–4.0
–4.5

GAIN SETPOINT = 0.5

GAIN SETPOINT = 0.25

45 315270 36018090 135 2250

GAIN SETPOINT = 1.0

GAIN SETPOINT = 0.1

PHASE SETPOINT (Degrees)

Figure 6. Gain Conformance Error vs. Phase Setpoint at

Different Gain Setpoints, RF Frequency = 1900 MHz

360

315

270

225

180

135

PHASE (Degrees)

90

45

0

GAIN SETPOINT = 0.1

0 3603152702251801359045

GAIN SETPOINT = 0.25

GAIN SETPOINT = 0.5

GAIN SETPOINT = 1.0

PHASE SETPOINT (Degrees)

Figure 7. Phase vs. Phase Setpoint at

Different Gain Setpoints, RF Frequency = 1900 MHz

25

20

15

10

5

0

PHASE ERROR (Degrees)

–5

–10

–15

0 45 90 135 360180 225 270 315

GAIN SETPOINT = 0.1

GAIN SETPOINT = 0.25

GAIN SETPOINT = 0.5

PHASE SETPOINT (Degrees)

GAIN SETPOINT = 1.0

Figure 8. Phase Error vs. Phase Setpoint at Different Gain Setpoints,

RF Frequency = 1900 MHz

04700-006

04700-007

04700-008

Rev. 0 | Page 6 of 20

AD8341

–147

–148

RF PIN = +5dBm

NO RF INPUT

GAIN SETPOINT

RF PIN = 0dBm

RF PIN = –5dBm

04700-009

NOISE (dBm/Hz)

–149

–150

–151

–152

–153

–154

0 1.00.90.80.70.60.50.40.30.20.1

Figure 9. Output Noise Floor vs. Gain Setpoint, Noise in dBm/Hz, No Carrier,

and With 1900 MHz Carrier (Measured at 20 MHz Offset)

Pin = −5, 0, and +5 dBm

0

GAIN SETPOINT = 1.0

–2
–4
–6

GAIN SETPOINT = 0.5

–8
–10
–12

GAIN SETPOINT = 0.25

–14
–16

GAIN (dB)

–18

GAIN SETPOINT = 0.1

–20
–22
–24
–26
–28

1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

FREQUENCY (MHz)

04700-010

0

–1

–2

–3

–4

–5

GAIN (dB)

–6

–7

–8

–9

–10

1500 240023002200210020001900180017001600

–40°C

+25°C

+85°C

FREQUENCY (MHz)

Figure 12. Gain Magnitude vs. Frequency and Temperature,

Maximum Gain, Phase Setpoint = 0°

0

–10

–20

–30

–40

SECOND BASEBAND HARMONIC PRODUCT,

–50

1898MHz, 1902MHz

–60

–70

–80

–90

RF OUTPUT AM SIDEBAND POWER (dBm)

–100

100 1000900800700600500400300200

FUNDAMENTAL POWER, 1899MHz, 1900MHz

THIRD BASEBAND HARMONIC PRODUCT,
1897MHz, 1903MHz

DIFFERENTIAL BB LEVEL (mV p-p)

04700-012

04700-013

Figure 10. Gain vs. Frequency at Different Gain Setpoints,

Phase Setpoint = 0°

–146

–147

–148

–149

–150

–151

NOISE (dBm/Hz)

–152

–153

–154

1500 240023002200210020001900180017001600

FREQUENCY (MHz)

Figure 11. Output Noise Floor vs. Frequency, Maximum Gain,

No RF Carrier, Phase Setpoint = 0°

04700-011

Rev. 0 | Page 7 of 20

Figure 13. Baseband Harmonic Distortion (I and Q Channel,

RF Input = 0 dBm, Output Balun and Cable Losses of Approximately

2 dB Not Accounted for in Plot)

12

10

8

6

OP1dB (dBm)

4

2

0
1500 240023002200210020001900180017001600

–40°C

+25°C

+85°C

FREQUENCY (MHz)

Figure 14. Output 1 dB Compression Point vs. Frequency and

Temperature, Maximum Gain, Phase Setpoint = 0°

04700-014

AD8341

25

20

15

10

OIP3 (dBm)

5

–40°C

+85°C

+25°C

20

15

10

5

OIP3 (dBm)

0

–5

GAIN SETPOINT = 1.0

GAIN SETPOINT = 0.5

GAIN SETPOINT = 0.25

GAIN SETPOINT = 0.1

0

1500 240023002200210020001900180017001600

FREQUENCY (MHz)

Figure 15. Output IP3 vs. Frequency and Temperature,

Maximum Gain, Phase Setpoint = 0°, 2.5 MHz Carrier Spacing

–10

1V p-p BB INPUT

–15

500mV p-p BB INPUT

–20

–25

250mV p-p BB INPUT

–30

RF OUTPUT AM SIDEBAND POWER (dBm)

–35

10 41036031026021016011060

FREQUENCY (MHz)

Figure 16. I/Q Modulation Bandwidth vs. Baseband Magnitude

10

5

GAIN SETPOINT = 1.0

GAIN SETPOINT = 0.5

04700-015

04700-016

–10

0 36045 90 135 180 225 270 315

PHASE SETPOINT (Degrees)

Figure 18. Output IP3 vs. Gain and Phase Setpoints,
RF Frequency = 1900 MHz, 2.5 MHz Carrier Spacing

RBW 30kHz
REF LVL
0dBm

0
–10

–20

–30

–40

–50

–60
–70

OUTPUT POWER (dBm)

–80

SECOND BASEBAND HARMONIC

–90

–100

CENTER 1.9GHz 500kHz/ SPAN 5MHz

DESIRED SIDEBAND

VBW 30kHz
SWT 100ms

RF FEEDTHROUGH

FREQUENCY (MHz)

RF ATT 20dB
UNIT dBm

UNDESIRED SIDEBAND

A

1SA

SECOND BASEBAND HARMONIC

Figure 19. Single-Sideband Performance, RF Frequency = 1900 MHz,

RF Input = −10 dBm; 1 MHz, 500 mV p-p Differential BB Drive

90

120

60

04700-018

04700-019

0

GAIN SETPOINT = 0.25

–5

OP1dB (dBm)

–10

–15

0 36045 90 135 180 225 270 315

GAIN SETPOINT = 0.1

PHASE SETPOINT (Degrees)

Figure 17. Output 1 dB Compression Point vs. Gain and

Phase Setpoints, RF Frequency = 1900 MHz

04700-017

Rev. 0 | Page 8 of 20

180

150

1500MHz

210

240

2400MHz

270

S11 RF PORT WITH 1.2nH INDUCTORS
S11 RF PORT WITHOUT INDUCTORS

Figure 20. Input Impedance Smith Chart

300

30

330

0

04700-020

AD8341

180

90

120

150

1500MHz

210

2400MHz

240

270

SDD22 PORT DIFFERENTIAL
S22 WITH 1 TO 1 TRANSFORMER

Figure 21. Output Impedance Smith Chart

0

–10

60

300

30

330

0

04700-021

0

–5
–10
–15
–20
–25
–30
–35
–40

RF OUTPUT POWER (dBm)

–45
–50
–55

0 5.04.54.03.53.02.52.01.51.00.5

DSOP VOLTAGE (V)

Figure 24. Output Disable Attenuation,

RF Frequency = 1900 MHz, RF Input = −5 dBm

DSOP

04700-024

2V/DIV

–20

–30

–40

–50

PHASE ERROR (Degrees)

–60

–70

PHASE SETPOINT = 0°

PHASE SETPOINT = 45°

PHASE SETPOINT = 90°

0 1.00.90.80.70.60.50.40.30.20.1

GAIN SETPOINT

Figure 22. Phase Error vs. Gain Setpoint by Phase Setpoint,

RF Frequency = 1900 MHz

127

126

125

124

123

SUPPLY CURRENT (mA)

122

V

POS

= 5.25V

V

= 5.00V

POS

V

= 4.75V

POS

04700-022

3

VOLTS

RF OUTPUT

4

CH3 2.0V Ω CH4 100mV Ω M10.0ns 5.0GS/s A CH3 1.84V

TIME (10ns/DIV)

Figure 25. Output Disable Response Time,

RF Frequency = 1900 MHz, RF Input = 0 dBm

100mV/DIV

04700-025

121

–40–30–20–100 1020304050607080

TEMPERATURE (°C)

04700-023

Figure 23. Supply Current vs. Temperature

Rev. 0 | Page 9 of 20

AD8341

(

)

V

THEORY OF OPERATION

The AD8341 is a linear RF vector modulator with Cartesian
baseband controls. In the simplified block diagram given in
Figure 26, the RF signal propagates from the left to the right
while baseband controls are placed above and below. The RF
input is first split into in-phase (I) and quadrature (Q) compo­nents. The variable attenuators independently scale the I and Q
components of the RF input. The attenuator outputs are then
summed and buffered to the output.

By controlling the relative amounts of I and Q components that
are summed, continuous magnitude and phase control of the
gain is possible. Consider the vector gain representation of the
AD8341 expressed in polar form in Figure 27. The attenuation
factors for the I and Q signal components are represented on
the x- and y-axis, respectively, by the baseband inputs, V

. The resultant of their vector sum represents the vector

V

BBQ

gain, which can also be expressed as a magnitude and phase. By
applying different combinations of baseband inputs, any vector
gain within the unit circle can be programmed.

or V

A change in sign of V

BBI

can be viewed as a change in

BBQ

sign of the gain or as a 180° phase change. The outermost
circle represents the maximum gain magnitude of unity. The
circle origin implies, in theory, a gain of 0. In practice, circuit
mismatches and unavoidable signal feedthrough limit the
minimum gain to approximately −34.5 dB. The phase angle
between the resultant gain vector and the positive x-axis is de­fined as the phase shift. Note that there is a nominal, systematic
insertion phase through the AD8341 to which the phase shift is
added. In the following discussions, the systematic insertion
phase is normalized to 0°.

The correspondence between the desired gain and phase set­points, Gain

V

, is given by simple trigonometric identities

BBQ

and PhaseSP, and the Cartesian inputs, V

SP

[]

()

SP

BBI

2

()

VVPhase /arctan=

BBI

BBQSP

//

VVVVGain +=

OBBQO

2

where:

V

is the baseband scaling constant (500 mV).

O

V

and V

BBI

are the differential I and Q baseband voltages,

BBQ

respectively.

Note that when evaluating the arctangent function, the proper
phase quadrant must be selected. For example, if the principal
value of the arctangent (known as the Arctangent(x)) is used,
quadrants 2 and 3 could be interpreted mistakenly as quadrants
4 and 1, respectively. In general, both V

and V

BBI

BBQ

in concert to modulate the gain and the phase.

and

BBI

and

BBI

are needed

Pure amplitude modulation is represented by radial movement
of the gain vector tip at a fixed angle, while pure phase modula­tion is represented by rotation of the tip around the circle at a
fixed radius. Unlike traditional I-Q modulators, the AD8341 is
designed to have a linear RF signal path from input to output.
Traditional I-Q modulators provide a limited LO carrier path
through which any amplitude information is removed.

BBI

LINEAR

ATTENUATOR

LINEAR

ATTENUATOR

VBBQ

V

q

+0.5

|A|

–0.5

θ

A

I-V

OUTPUT
DISABLE

SINGLE-ENDED OR
DIFFERENTIAL
50Ω OUTPUT

V

i

+0.5–0.5

04700-027

SINGLE-ENDED OR

DIFFERENTIAL

50Ω INPUT Z

Figure 26. Simplified Architecture of the AD8341

I CHANNEL INPUT

V-I

0°/90°

V-I

Q CHANNEL INPUT

MAX GAIN

MIN GAIN

Figure 27. Vector Gain Representation

RF QUADRATURE GENERATOR

The RF input is directly coupled differentially or single-ended
to the quadrature generator, which consists of a multistage RC
polyphase network tuned over the operating frequency range of

1.5 GHz to 2.4 GHz. The recycling nature of the polyphase net­work generates two replicas of the input signal, which are in
precise quadrature, i.e., 90°, to each other. Since the passive
network is perfectly linear, the amplitude and phase information
contained in the RF input is transmitted faithfully to both chan­nels. The quadrature outputs are then separately buffered to
drive the respective attenuators. The characteristic impedance
of the polyphase network is used to set the input impedance of
the AD8341.

04700-026

Rev. 0 | Page 10 of 20

AD8341

I-Q ATT ENUATOR S AN D BA SEBAND AMPLIFIERS

The proprietary linear-responding attenuator structure is an
active solution with differential inputs and outputs that offer
excellent linearity, low noise, and greater immunity from mis­matches than other variable attenuator methods. The gain, in
linear terms, of the I and Q channels is proportional to its control
voltage with a scaling factor designed to be 2/V, i.e., a full-scale
gain setpoint of 1.0 (−4.5 dB) for a V

(or a V

BBI

) of 500 mV. The

BBQ

control voltages can be driven differentially or single-ended. The
combination of the baseband amplifiers and attenuators allows
for maximum modulation bandwidths in excess of 200 MHz.

OUTPUT AMPLIFIER

The output amplifier accepts the sum of the attenuator outputs
and delivers a differential output signal into the external load.
The output pins must be pulled up to an external supply,
preferably through RF chokes. When the 50 Ω load is taken
differentially, an output P1dB and IP3 of 8.5 dBm and 17.5 dBm
is achieved, respectively, at 1.9 GHz. The output can be taken in
single-ended fashion, albeit at lower performance levels.

NOISE AND DISTORTION

The output noise floor and distortion levels vary with the gain
magnitude but do not vary significantly with the phase. At the
higher gain magnitude setpoints, the OIP3 and the noise floor
vary in direct proportion with the gain. At lower gain magni­tude setpoints, the noise floor levels off while the OIP3
continues to vary with the gain.

GAIN AND PHASE ACCURACY

There are numerous ways to express the accuracy of the
AD8341. Ideally, the gain and phase should precisely follow the
setpoints. Figure 4 illustrates the gain error in dB from a best fit
line, normalized to the gain measured at the gain setpoint = 1.0,
for the different phase setpoints. Figure 6 shows the gain error
in a different form, normalized to the gain measured at phase
setpoint = 0°; the phase setpoint is swept from 0° to 360° for
different gain setpoints. Figure 8 and Figure 22 show analogous
errors for the phase error as a function of gain and phase
setpoints. The accuracy clearly depends on the region of opera­tion within the vector gain unit circle. Operation very close to
the origin generally results in larger errors as the relative
accuracy of the I and Q vectors degrades.

RF FREQUENCY RANGE

The frequency range on the RF input is limited by the internal
polyphase quadrature phase-splitter. The phase-splitter splits
the incoming RF input into two signals, 90° out of phase, as
previously described in the RF Quadrature Generator section.
This polyphase network has been designed to ensure robust
quadrature accuracy over standard fabrication process
parameter variations for the 1.5 GHz to 2.4 GHz specified RF
frequency range. Using the AD8341 as a single-sideband modu­lator and measuring the resulting sideband suppression is a
good gauge of how well the quadrature accuracy is maintained
over RF frequency. A typical plot of sideband suppression from

1.1 GHz to 2.7 GHz is shown in Figure 28. The level of sideband
suppression degradation outside the 1.5 GHz to 2.4 GHz speci­fied range will be subject to manufacturing process variations.

–15

–20

–25

–30

–35

SIDEBAND SUPPRESSION (dBc)

–40

–45

0.7 2.72.52.32.11.91.71.51.30.9 1.1

Figure 28. Sideband Suppression vs. Frequency

FREQUENCY (GHz)

04700-028

Rev. 0 | Page 11 of 20

AD8341

APPLICATIONS

USING THE AD8341

The AD8341 is designed to operate in a 50 Ω impedance
system. Figure 30 illustrates an example where the RF input is
driven in a single-ended fashion while the differential RF out­put is converted to a single-ended output with an RF balun. The
baseband controls for the I and Q channels are typically driven
from differential DAC outputs. The power supplies, VPRF and
VPS2, should be bypassed appropriately with 0.1 µF and 100 pF
capacitors. Low inductance grounding of the CMOP and CMRF
common pins is essential to prevent unintentional peaking of
the gain.

RF INPUT AND MATCHING

The input impedance of the AD8341 is defined by the charac­teristics of the polyphase network. The capacitive component of
the network causes its impedance to roll-off with frequency
albeit at a rate slower than 6 dB/octave. By using matching
inductors on the order of 1.2 nH in series with each of the RF
inputs, RFIP and RFIM, a 50 Ω match is achieved with a return

loss of >10 dB over the operating frequency range. Different
matching inductors can improve matching over a narrower
frequency range. The single-ended and differential input
impedances are exactly the same.

1.2nH

RF

50Ω

100pF

100pF

1.2nH

RFIM

~1VDC

RFIP

PHASE

Figure 29. RF Input Interface to the AD8341 Showing

Coupling Capacitors and Matching Inductors

The RFIP and RFIM should be ac-coupled through low loss
series capacitors as shown in Figure 29. The internal dc levels
are at approximately 1 V. For single-ended operation, one input
is driven by the RF signal while the other input is ac grounded.

VP

RC

04700-029

IBBM

IBBP

INPUT

QBBP

QBBM

VP

RF

VP

0.1µF

C3

C6

100pF

C5

100pF

C8

0.1µF

100pF

L3

1.2nH

L4

1.2nH

C4

C7
100pF

C12

(SEE TEXT)

IFLP

VPRF

CMRF

RFIM

RFIP

CMRF

VPRF

P

L

Q

F

C11

(SEE TEXT)

100pF

IFLM

AD8341

QFLM

C2

IBBP

QBBP

IBBM

QBBM

DSOP

VPS2

VPS2

VPS2

C9
100pF

C1

0.1µF

CMOP

CMOP

RFOM

RFOP

CMOP

CMOP

C10

0.1µF

120nH

VP

L1

A

OUTPUT
DISABLE

B

L2
120nH

C14

0.1µF

C17

100pF

C18

100pF

VP

ETC1-1-13

RF
OUTPUT

04700-030

Figure 30. Basic Connections

Rev. 0 | Page 12 of 20

AD8341

–

RF OUTPUT AND MATCHING

The RF outputs of the AD8341, RFOP, and RFOM, are open
collectors of a transimpedance amplifier which need to be
pulled up to the positive supply, preferably with RF chokes as
shown in Figure 31. The nominal output impedance looking
into each individual output pin is 25 Ω. Consequently, the
differential output impedance is 50 Ω.

V

P

RFOP

120nH

100pF

100pF

50Ω

DIFFERENTIAL

1:1

RF
OUTPUT

04700-031

R

T

RFOM

±I

SIG

G

M

R

T

Figure 31. RF Output Interface to the AD8341 Showing

Coupling Capacitors, Pull-Up RF Chokes, and Balun

Since the output dc levels are at the positive supply, ac coupling
capacitors will usually be needed between the AD8341 outputs
and the next stage in the system.

A 1:1 RF broadband output balun, such as the ETC1-1-13
(M/A-COM), converts the differential output of the AD8341
into a single-ended signal. Note that the loss and balance of the
balun directly impact the apparent output power, noise floor,
and gain/phase errors of the AD8341. In critical applications,
narrow-band baluns with low loss and superior balance are
recommended.

If the output is taken in a single-ended fashion directly into a
50 Ω load through a coupling capacitor, there will be an imped­ance mismatch. This can be resolved with a 1:2 balun to convert
the single-ended 25 Ω output impedance to 50 Ω. If loss of
signal swing is not critical, a 25 Ω back termination in series
with the output pin can also be used. The unused output pin
must still be pulled up to the positive supply. The user may load
it through a coupling capacitor with a dummy load to preserve
balance. The gain of the AD8341 when the output is single­ended varies slightly with dummy load value as shown in Figure 32.

2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0

GAIN (dB)

–6.5
–7.0
–7.5
–8.0
–8.5

Figure 32. Gain of the AD8341 Using a Single-Ended Output with Different

Dummy Loads, R

RL2 = SHORT

RL2 = 50

Ω

RL2 = OPEN

FREQUENCY (GHz)

, on the Unused Output

L2

RL = 50

Ω

04700-032

3.01.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

The RF output signal can be disabled by raising the DSOP pin
to the positive supply. The output disable function provides
>30 dB attenuation of the input signal even at full gain. The
interface to DSOP is high impedance and the shutdown and
turn-on response times are <100 ns. If the disable function is
not needed, the DSOP pin should be tied to ground.

DRIVING THE I-Q BASEBAND CONTROLS

The I and Q inputs to the AD8341 set the gain and phase be­tween input and output. These inputs are differential and should
normally have a common-mode level of 0.5 V. However, when
differentially driven, the common mode can vary from 250 mV
to 750 mV while still allowing full gain control. Each input pair
has a nominal input swing of ±0.5 V differential around the
common-mode level. The maximum gain of unity is achieved if
the differential voltage is equal to +500 mV or −500 mV. So
with a common-mode level of 500 mV, IBBP and IBBM will
each swing between 250 mV and 750 mV.

The I and Q inputs can also be driven with a single-ended
signal. In this case, one side of each input should be tied to a
low noise 0.5 V voltage source (a 0.1 µF decoupling capacitor
located close to the pin is recommended), while the other input
swings from 0 V to 1 V. Differential drive generally offers superior
even-order distortion and lower noise than single-ended drive.

The bandwidth of the baseband controls exceeds 200 MHz even
at full-scale baseband drive. This allows for very fast gain and
phase modulation of the RF input signal. In cases where lower
modulation bandwidths are acceptable or desired, external filter
capacitors can be connected across Pins IFLP to IFLM and
QFLP to QFLM to reduce the ingress of baseband noise and
spurious signal into the control path.

Rev. 0 | Page 13 of 20

AD8341

The 3 dB bandwidth is set by choosing C

according to the

FLT

following equation:

nF10kHz45

f

≈

3dB

This equation has been verified for values of C

×

pF0.5

+

C

FLT

from 10 pF to

FLT

0.1 µF (bandwidth settings of approximately 4.5 kHz to 43 MHz).

INTERFACING TO HIGH SPEED DACs

The AD977x family of dual DACs is well suited to driving the I
and Q vector controls of the AD8341. While these inputs can in
general be driven by any DAC, the differential outputs and bias
level of the ADI TxDAC® family allows for a direct connection
between DAC and modulator.

The AD977x family of dual DACs has differential current out­puts. The full-scale current is user programmable and is usually
set to 20 mA, that is, each output swings from 0 mA to 20 mA.

The basic interface between the AD9777 DAC outputs and the
AD8341 I and Q inputs is shown in Figure 33. The Resistors R1
and R2 set the dc bias level according to the equation:

Bias Level = Average Output Current × R1

For example, if the full-scale current from each output is 20 mA,
each output will have an average current of 10 mA. Therefore to
set the bias level to the recommended 0.5 V, R1 and R2 should
be set to 50 Ω each. R1 and R2 should always be equal.

If R3 is omitted, this will result in an available swing from
the DAC of 2 V p-p differential, which is twice the maximum
voltage range required by the AD8341. DAC resolution can be
maximized by adding R3, which scales down this voltage
according to the following equation:

=SwingScaleFull

R2

()

MAX

AD9777 AD8341

()

⎡

R3R2R1I

−×+×

1||2

⎢
⎣

⎤
⎥

+

R3R2

⎦

1.15

1.13

1.10

1.08

1.05

1.02

1.00

0.97

0.95

0.92

0.90

0.88

0.85

0.82

0.80

0.77

0.75

DIFFERENTIAL PEAK-TO-PEAK SWING (V)

0.72

0.70

(Ω)

04700-034

13050 55 60 65 70 75 80 85 90 100 105 115 120110 12595

Figure 34. Peak-to -Peak DAC O utput Sw ing vs.

Swing Scaling Resistor R3 (R1 = R2 = 50 Ω)

Figure 34 shows the relationship between the value of R3 and
the peak baseband voltage with R1 and R2 equal to 50 Ω.
From Figure 34, it can be seen that a value of 100 Ω for R3 will
provide a peak-to-peak swing of 1 V p-p differential into the
AD8341’s I and Q inputs.

When using a DAC, low-pass image reject filters are typically
used to eliminate the Nyquist images produced by the DAC.
They also provide the added benefit of eliminating broadband
noise that might feed into the modulator from the DAC.

CDMA2000 APPLICATION

To test the compliance to the CDMA2000 base station standard,
a single-carrier CDMA2000 test model signal (forward pilot,
sync, paging, and six traffic as per 3GPP2 C.S0010-B, Table

6.5.2.1) was applied to the AD8341 at 1960 MHz. A cavity tuned
filter was used to reduce noise from the signal source being
applied to the device. The 6.8 MHz pass band of this filter is
apparent in the subsequent spectral plots.

Figure 35 shows a plot of the spectrum of the output signal
under nominal conditions. P

= 0.353 V, i.e., V

V

BBQ

IBBP

is equal to −4 dBm and V

OUT

− V

= V

QBBP

− V

IBBM

= 0.353 V.

QBBM

Noise and distortion is measured in a 1 MHz bandwidth at
±2.25 MHz carrier offset (30 kHz measurement bandwidth).

BBI

=

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

R1

R2

R1

R2

OPTIONAL
LOW-PASS

FILTER

OPTIONAL

LOW-PASS

FILTER

Figure 33. Basic AD9777 to AD8341 Interface

IBBP

R3

IBBM

QBBP

R3

QBBM

04700-033

Rev. 0 | Page 14 of 20

AD8341

–

–

–

–

–12
–20

–30

–40

–50

–60

–70

–80

–90

100

–112

REF LVL

–12dBm

0.3dB OFFSET

MARKER 1 [T1 ]
–18.47dBm

1.95999900GHz

C11

RBW 30kHz
VBW 100kHz
SWT 500ms

1

1 [T1] –18.47dBm
CH PWR –4.06dBm

ACP UP –77.64dBm
ACP LOW –76.66dBm

C0 C0

C11

CU1

RF ATT 0dB

UNIT dBm

1.95999900GHz

CU1

SPAN 10MHz1MHz/CENTER 1.96Hz

A

1RM1AVG

04700-035

Figure 35. Output Spectrum, 1960 MHz, Single-Carrier CDMA2000

= V

Test Model at −4 dBm, V

= 0.353 V, Adjacent Channel Power

BBI

BBQ

Measured at ±2.25 MHz Carrier Offset in 1 MHz BW Input Signal Filtered

Using a Cavity Tuned Filter (Pass Band = 6.8 MHz)

Holding the differential I and Q control voltages steady at

0.353 V, input power was swept. Figure 36 shows variation in
spurious content, again measured at ±2.25 MHz carrier offset in
a 1 MHz bandwidth, as defined by the 3GPP2 specification.

–70

–72

–74

–76

–78

–80

–82

–84

–86

–88

ACP @ 2.25MHz OFFSET (dBm, 1MHz, BW)

–90

–20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0

OUTPUT POWER (dBm)

04700-036

Figure 36. Adjacent Channel Power vs. Output Power,

CDMA2000 Single Carrier @ 1960 MHz; ACP Measured at

= V

±2.25 MHz Carrier Offset (1 MHz BW ); V

= 0.353 V

BBI

BBQ

With a fixed input power of 2.4 dBm, the output power was
again swept by exercising the I and Q inputs. V

and V

BBI

BBQ

were
kept equal and were swept from 100 mV to 500 mV. The result­ing output power and ACP are shown in Figure 37.

0

–5

–10

–15

–20

OUTPUT POWER (dBm)

–25

–30

0 0.1 0.2 0.3 0.4 0.5

IQ CONTROL VOLTAGE

–60

–65

–70

–75

–80

–85

ACP dBm (1MHz BW) @ 2.25MHz OFFSET

–90

Figure 37. Output Power and ACP vs. I and Q Control Voltages,

= V

CDMA2000 Test Model, V

BBI

BBQ

, ACP Measured at

±2.25 MHz Carrier Offset in 1 MHz BW

Figure 37 shows that for a fixed input power, the ACP (measured in
dBm) tracks the output power as the gain is changed.

WCDMA APPLICATION

Figure 38 shows a plot of the output spectrum of the AD8341
transmitting a single-carrier WCDMA signal (Test Model 1-64
at 2140 MHz). The carrier power is approximately −9 dBm. The
differential I and Q control voltages are both equal to 0.353 V,
that is, the vector is sitting on the unit circle at 45°. At this
power level, an adjacent channel power ratio of −61 dBc is
achieved. The alternate channel power ratio of −72 dBc is
dominated by the noise floor of the AD8341.

MARKER 1 [T1 ]
–28.39dBm

2.14050000GHz

C11

C0

C11

–24
–30

–40

–50

–60

–70

–80

–90

100

–110

120
124

REF LVL

–24dBm

OFFSET 1dB

C12 C12

Figure 38. AD8341 Single-Carrier WCDMA Spectrum at 2140 MHz

RBW 30kHz
VBW 300kHz
SWT 1s

1

1 [T1] –28.39dBm
CH PWR –8.95dBm

ACP UP –60.78dB
ACP LOW –60.82dB
ALT1 UP –72.67dB
ALT1 LOW –72.66dB

C0

CU1

RF ATT 0dB

UNIT dBm

2.14050000GHz

CU1

SPAN 25MHz2.5MHz/CENTER 2.14GHz

A

1RM

CU2

04700-038

04700-037

Figure 39 shows how ACPR and noise vary with varying input
power (differential I and Q control voltages are held at 0.353 V).
At high power levels, both adjacent and alternate channel power
ratios increase sharply. As output power drops, adjacent and
alternate channel power ratios both reach minimums before the
measurement becomes dominated by the noise floor of the
AD8341. At this point, adjacent and alternate channel power
ratios become approximately equal.

Rev. 0 | Page 15 of 20

AD8341

)

As the output power drops, the noise floor, measured in dBm in
1 MHz BW at 50 MHz carrier offset, drops slightly.

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–30 –25 –20 –15 –10 –5 0 5

ADJACENT/ALTERNATE CHANNEL POWER RATIO (dBc

NOISE –50MHz OFFSET

ACPR 5MHz OFFSET

ACPR 10MHz OFFSET

OUTPUT POWER (dBm)

Figure 39. AD8341 ACPR and Noise vs. Output Power;

Single-Carrier WCDMA ( Test Model 1-64 at 2140 MHz)

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

NOISE dBm @ 50MHz CARRIER OFFSET (1MHz BW)

Figure 40 shows how output power, ACPR, and noise vary with
the differential I and Q control voltages. V

and V

BBI

are tied

BBQ

together and are varied from 0.5 V to 50 mV.

04700-039

0

–5

–10

–15

–20

–25

–30

–35

OUTPUT POWER (dBm)

–40

–45

–50

0 0.1 0.2 0.3 0.4 0.5

OUTPUT POWER dBm

ACPR 5MHz OFFSET

ACPR 10MHz OFFSET

NOISE –50MHz OFFSET

IQ CONTROL VOLTAGE

Figure 40. AD8341 Output Power, ACPR and Noise vs. V

–40

–45

–50

–55

–60

–65

–70

ACPR (dBc)

–75

–80

–85

–90

.

IQ

Single-Carrier WCDMA ( Test Model 1-64 at 2140 MHz)

In this case, adjacent channel power ratio remains constant as
the (noise dominated) alternate channel power degrades
roughly 1-for-1 with output power. As the I and Q control volt­age drops, the noise floor again drops slowly.

NOISE dBm @ 50MHz OFFSET (1MHz BW)

04700-040

Rev. 0 | Page 16 of 20

AD8341

EVALUATION BOARD

The evaluation board circuit schematic for the AD8341 is
shown in Figure 41.

The evaluation board is configured to be driven from a
single-ended 50 Ω source. Although the input of the AD8341 is
differential, it may be driven single-ended, with no loss of per­formance.

The low-pass corner frequency of the baseband I and Q chan­nels can be reduced by installing capacitors in the C11 and C12
positions. The low-pass corner frequency for either channel is
approximated by

nF10kHz45

f

3dB

≈

×

+

C

FLT

pF0.5

On this evaluation board, the I and Q baseband circuits are
identical to each other, so the following description applies
equally to each. The connections and circuit configuration for
the Q baseband inputs are described in Table 4.

The baseband input of the AD8341 requires a differential volt­age drive. The evaluation board is set up to allow such a drive by
connecting the differential voltage source to QBBP and QBBM.
The common-mode voltage should be maintained at approxi­mately 0.5 V. For this configuration, Jumpers W1 through W4
should be removed.

The baseband input of the evaluation board may also be driven
with a single-ended voltage. In this case, a bias level is provided
to the unused input from Potentiometer R10 by installing either
W1 or W2.

Setting SW1 in Position B disables the AD8341 output amplifier.
With SW1 set to Position A, the output amplifier is enabled.
With SW1 set to Position A, an external voltage signal, such as a
pulse, can be applied to the DSOP SMA connector to exercise
the output amplifier enable/disable function.

Table 4. Evaluation Board Configuration Options

Components Function Default Conditions

R7, R9, R11,
R14, R15, R19,
R20, R21, C15,
C19, W3, W4

R1, R3, R10,
R12, R13, R16,
R17, R18, C16,
C20, W1, W2

C11, C12

T1, C17, C18,
L1, L2

L3, L4, C5, C6

I Channel Baseband Interface. Resistors R7 and R9 may be installed to accommodate a
baseband source that requires a specific terminating impedance. Capacitors C15 and C19
are bypass capacitors.
For single-ended baseband drive, the Potentiometer R11 can be used to provide a bias level
to the unused input (install either W3 or W4).

Q Channel Baseband Interface. See the I Channel Baseband Interface section.

Baseband Low-Pass Filtering. By adding Capacitor C11 between QFLP and QFLM, and C12

between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can
be reduced from 230 MHz (nominal). See equation in text.

Output Interface. The 1:1 balun transformer, T1, converts the 50 Ω differential output to 50
Ω single-ended. C17 and C18 are dc blocks. L1 and L2 provide dc bias for the output.

Input Interface. The input impedance of the AD8341 requires 1.2 nH inductors in series
with RFIP and RFIM for optimum return loss when driven by a single-ended 50 Ω line. C5
and C6 are dc blocks.

R7, R9 = Not Installed
R11 = Potentiometer, 2 kΩ,
10 Turn (Bourns)
R14 = 4 kΩ (Size 0603)
R15 = 44 kΩ (Size 0603)
R19, R20, R21 = 0 Ω
(Size 0603)
C15, C19 = 0.1 µF
(Size 0603)
W3 = Jumper (Installed)
W4 = Jumper (Open)

R1, R3 = Not Installed
R10 = Potentiometer, 2 kΩ,
10 Turn (Bourns)
R12 = 4 kΩ (Size 0603)
R13 = 44 kΩ (Size 0603)

R16, R17, R18 = 0 Ω
(Size 0603)
C16, C20 = 0.1 µF
(Size 0603)
W1 = Jumper (Installed)
W2 = Jumper (Open)

C11, C12 = Not Installed

C17, C18 = 100 pF
(Size 0603)
T1 = ETC1-1-13 (M/A-COM)

L1, L2 = 120 nH
(Size 0603)

L3, L4 = 1.2 nH (Size 0402)
C5, C6 = 100 pF (Size 0603)

Rev. 0 | Page 17 of 20

AD8341

Components Function Default Conditions

C2, C4, C7,
C9, C14, C1,
C3, C8, C10,
R2, R4, R5, R6

R8, SW1

Supply Decoupling.

Output Disable Interface. The output stage of the AD8341 is disabled by applying a high

voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving
SW1 to Position A. The output disable function can also be exercised by applying an exter­nal high or low voltage to the DSOP SMA connector with SW1 in Position A.

IBBMIBBP

C2, C4, C7, C9, C14 = 0.1 µF
(Size 0603)
C1, C3, C8, C10 = 100 pF
(Size 0603)
R2, R4, R5, R6 = 0 Ω
(Size 0603)

R8 = 10 kΩ (Size 0603)
SW1 = SPDT (Position A,
Output Enabled)

RFIN

VS

VP

C7

0.1µF

C4

0.1µF

C6

100pF

C5

100pF

W4

C15

0.1µF

R14
4kΩ

IFLM

AD8341

QFLM

R11
2kΩ

IBBP

QBBP

C19

0.1µF

R19
0Ω

W3

R15

44kΩ

IBBM

QBBM

R7

(OPEN)

R20

0Ω

DSOP

VPS2

VPS2

VPS2

100pF

VS

CMOP

CMOP

RFOM

RFOP

CMOP

CMOP

C10

R6
0Ω

TEST POINT

C2

0.1µF

R2
0Ω

C1

100pF

R8
10kΩ

L2

120nH

C14

0.1µF

C9

0.1µF

VP

SW1

B

A

L1
120nH

GND

TEST POINT

C18

100pF

C17

100pF

VP

T1

ETC1-1-13

M/A-COM

DSOP

RFOP

R9

(OPEN)

R21

0Ω

C12

(OPEN)

L3

1.2nH

L4

1.2nH

C8
100pF

C3
100pF

IFLP

VPRF

CMRF

RFIN

RFIP

CMRF

VPRF

F

Q

(OPEN)

L

P

C11

R5
0Ω

R4
0Ω

R12

R10

C16

2kΩ

R16
0Ω

C20

0.1µF

R13

44kΩ

W1

VS

R18

0Ω

R3

(OPEN)

QBBM

04700-041

QBBP

R17

0Ω

R1

(OPEN)

4kΩ

0.1µF

W2

Figure 41. Evaluation Board Schematic

Rev. 0 | Page 18 of 20

AD8341

04700-042

Figure 42. Component Side Layout

Figure 43. Component Side Silkscreen

04700-043

Rev. 0 | Page 19 of 20

AD8341

OUTLINE DIMENSIONS

0.60 MAX

19

18

EXPOSED

(BOTTOM VIEW)

13

12

PAD

24

6

7

2.50 REF

1

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

4.00

BSC SQ

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

TOP

VIEW

0.80 MAX

0.65TYP

COMPLIANTTO JEDEC STANDARDS MO-220-VGGD-2

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 44. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body (CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Order Multiple

AD8341ACPZ-WP
AD8341ACPZ-REEL72 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP) CP-24-1 1,500
AD8341-EVAL Evaluation Board 1

1

WP = Waffle pack.

2

Z = Pb-free part.

1, 2

−40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP) CP-24-1 64

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