Analog Devices AD8339 Service Manual

DC to 25 MHz,

Quad I/Q Demodulator and Phase shifter

Preliminary Technical Data

FEATURES

Quad Integrated I/Q Demodulator
16 Phase Select on each Output (22.5° per step)
Quadrature Demodulation Accuracy
Phase Accuracy ±1°
Amplitude Balance ±0.25 dB
Bandwidth

4LO: LF to 100 MHz; RF: LF to 25 MHz
Baseband: determined by external filtering
Output Dynamic Range 158 dB/Hz
LO Drive > –10 dBm (50 Ω); 200 mVpp
Supply: ±5 V
Power Consumption 73 mW/channel (290 mW total)
Power Down via SPI (Each Channel and Complete Chip)

APPLICATIONS
Medical Imaging (CW Ultrasound Beamforming)
Phased Array Systems
Radar
Adaptive Antennas
Communication Receivers

FUNCTIONAL BLOCK DIAGRAM

CH1

RF

– +

AD8339

SCLK

CH2

RF

4Х
LO

CH3

RF

VPOS

VNEG

SDI

SDO

CSB

+
–

+
–

+
–

SERIAL

INTERFACE

0°



÷4

90°

BIAS

CH4

RF

+–

AD8339

Φ

Φ Q1

Φ I2

Φ

Φ

Φ Q3

Φ I4

Φ Q4

I1

Q2

I3

GENERAL DESCRIPTION

The AD8339 is a Quad I/Q demodulator intended to be driven
by a low noise preamplifier with differential outputs; it is
optimized for the LNA in the AD8332/4/5 family of VGAs. The
part consists of four identical I/Q demodulators with a 4× local
oscillator (LO) input that divides this signal and generates the
necessary 0° and 90° phases of the internal LO that drive the
mixers. The four I/Q demodulators can be used independently
of each other (assuming that a common LO is acceptable) since
each has a separate RF input.

The major application is continuous wave (CW) analog
beamforming in ultrasound. Since in a beamforming
application the outputs of many channels are summed
coherently, the signals need to be phase aligned. A reset pin for
the LO divider that synchronizes multiple ICs to start in the
same quadrant is provided. Sixteen discrete phase rotations in

22.5° increments can be selected independently for each
channel. For example, if CH1 is used as a reference and CH2
has an I/Q phase lead of 45°, then by choosing the correct code
one can phase align CH2 with CH1.

Rev. PrB - 5/24/07

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

The mixer outputs are provided in current form so that they can
be easily summed. The summed current outputs, one each for
the I and Q signals, are externally converted to a voltage by a
high dynamic range current-to-voltage (I to V) converter. A
good choice for this transimpedance amplifier is the AD8021
because of its low noise. Following the current summation the
combined signal is presented to a high resolution AD converter
(ADC) like the AD7665 (16b/570 ksps).

An SPI compatible serial interface is provided for ease of
programming the phase of each channel; the interface allows
daisy-chaining by shifting the data through each chip from SDI
to SDO. The SPI also allows for power down of each individual
channel and the complete chip. During power down the serial
interface remains active so that the device can be programmed
again.

The dynamic range is >158 dB/Hz at the I and Q outputs. The
AD8339 is available in a 6x6 mm 40 pin LFCSP, for the
industrial temperature range of -40 C to +85 C

.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2007 Analog Devices, Inc. All rights reserved.

Figure 1. Functional Block Diagram.

www.analog.com

AD8339 Preliminary Technical Data

TABLE OF CONTENTS

FUNCTIONAL BLOCK DIAGRAM......................................... 1

AD8339 Specifications.................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Equivalent Input Circuits ................................................................ 7

Typical Performance Characteristics ............................................. 8

Test Circuits....................................................................................... 9

Theory of Operation ...................................................................... 10

Quadrature Generation ............................................................. 10

I/Q Demodulator and Phase Shifter ........................................ 11

Dynamic Range and Noise........................................................ 11

REVISION HISTORY

Summation of Multiple Channels (Analog Beamforming).. 12

Phase Compensation and Analog Beamforming................... 12

Serial Interface ............................................................................ 13

ENBL Bits ................................................................................ 13

Applications..................................................................................... 15

Logic Inputs and Interfaces....................................................... 15

Reset Input .................................................................................. 15

Evaluation Board ............................................................................ 16

Connections to the Board ......................................................... 16

Using the SPI Port .................................................................. 19

Hard-wired Jumpers .............................................................. 20

Outline Dimensions ....................................................................... 29

Rev. PrB | Page 2 of 29

Preliminary Technical Data AD8339

AD8339 SPECIFICATIONS

Table 1. VS = ±5 V, TA = 25°C, 4×f
unless otherwise noted. Single channel AD8021 LPF values R

= 20 MHz, f

LO

= 5.01 MHz, f

RF

= 10 kHz, P

BB

= 1.58 kΩ and C

FILT

≥ 0 dBm, per channel performance, dBm (50 Ω)

LO

= 1 nF (see Figure 9).

FILT

Parameter Conditions Min Typ Max Unit

OPERATING CONDITIONS

Local Oscillator Frequency Range 4× Internal LO at pins 4LOP and 4LON

Square wave LF 100 MHz

Sine wave TBD 100 MHz

RF Frequency Range Mixing LF 25 MHz

Baseband Bandwidth Limited by external filtering LF 25 MHz

LO Input Level 0 13 dBm

V

(VS)

SUPPLY

±4.5 ±5 ±5.5

Temperature Range -40 +85

V
°C

DEMODULATOR PERFORMANCE

Input Impedance RF—Differential 7||7

LO—Differential 100||1

Transconductance

Demodulated I

; each Ix or Qx output after

OUT/VIN

kΩ||pF
kΩ||pF

low—pass filtering measured from RF inputs
All phases 1.1 mS
Dynamic Range IP1dB minus input referred noise (dBm) 158

dB (1Hz
BW)

Max Input Swing

Differential; inputs biased at 2.5V; pins RFxP,

2.7 Vpp

RFxN
Peak Output Current (No Filtering)

Input P1dB

Third Order Intermodulation (IM3)

0° Phase shift ±2.4

45° Phase shift ±3.3

Ref = 50 Ω

Ref = 1V

f

RMS

= 5.010 MHz, f

RF1

= 5.015 MHz, fLO = 5.023

RF2

14.5 dBm

1.5 dBV

mA
mA

MHz

Equal Input Levels Baseband tones: -7 dBm @ 8 kHz and 13 kHz -75 dBc
Unequal Input Levels

Baseband tones: -1 dBm @ 8 kHz and -31 dBm

TBD dBc

@13 kHz
Third Order Input Intercept (IIP3) Same conditions as IM3 30 dBm
LO Leakage

Measured at RF inputs, worst phase, measured

TBD dBm

into 50 •

Measured at baseband outputs, worst phase,

TBD dBm

AD8021 disabled, measured into 50 •
Conversion Gain All codes, see Figure XX 4.7 dB
Input Referred Noise

Output Current Noise

Output Noise ÷ Conversion Gain (see Figure XX)

Output noise ÷ 1.58 kΩ

TBD

TBD

nV/√Hz
pA/√Hz

Noise Figure With AD8332 LNA

= 50 Ω, RFB = ∞

R

S

= 50 Ω, RFB = 1.1k Ω

R

S

= 50 Ω, RFB = 274 Ω

R

S

TBD dB
TBD dB

Bias Current Pins 4LOP and 4LON -2

Pins RFxP and RFxN -35

TBD dB

μA
μA

LO Common Mode Range Pins 4LOP and 4LON (each pin) 0.2 3.8 V
RF Common Mode Voltage

For maximum differential swing; Pins RFxP and

2.5 V

RFxN (DC-coupled to AD8332 output)
Output Compliance Range Pins IxOP and QxOP -1.5 0.7 V

Rev. PrB Page 3 of 29

AD8339 Preliminary Technical Data

PHASE ROTATION PERFORMANCE One CH is reference, others are stepped

Phase Increment 16 Phase Steps per Channel 22.5
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel-to-Channel Matching

Ix to Qx; all phases, 1σ ±1
Ix to Qx; all phases, 1σ
Phase Match I-to-I and Q-to-Q; -40°C < T
Ampl. Match I-to-I and Q-to-Q; -40°C < T

< 85°C ±1

A

< 85°C ±0.5

A

0.25 dB

LOGIC INTERFACES Pins SDI,CSB,SCLK, RSTS,RSET

Logic Level High 1.5 V
Logic Level Low 0.9 V
Bias Current Logic high (pulled to +5V) 0.5

Logic low (pulled to GND) 0
Input Resistance 4
LO Divider RSET Setup Time

RSET rising edge to 4LOP-4LON (Differential)

5 ns

rising edge
LO Divider RSET High Pulse Width 20 ns
LO Divider RSET Setup Time

RSET falling edge prior to 4LOP-4LON

5 ns

(Differential) rising edge
Phase Response Time Measured from CSB going high TBD

Enable Response Time

Measured from CSB going high (with 0.1 μF cap

15

on pin LODC)

Output Pin SDO

Logic Level High Loaded with 5 pF and next SDI input 1.7 1.9 V
Logic Level Low Loaded with 5 pF and next SDI input 0.2 0.5 V

SPI TIMING CHARACTERISTICS

SCLK Frequency f
CSB to SCLK Setup Time T

Pins SDI,SDO,CSB,SCLK, RSTS

CLK

1

TBD ns
SCLK High Pulse Width T2 TBD ns
SCLK Low Pulse Width T3 TBD ns
Data Access Time after SCLK Falling Edge T

4

Data Setup Time Prior to SCLK Rising Edge T5 TBD ns
Data Hold Time after SCLK Rising Edge T6 TBD ns
CSB High Pulse Width T7 TBD ns
SCLK Fall to CSB Fall Hold Time T8 TBD ns
SCLK Fall to CSB Rise Hold Time T9 TBD

POWER SUPPLY Pins VPOS,VNEG

Supply Voltage

±4.5 ±5 ±5.5

Quiescent Current VPOS, all phase bits = 0 37.5 mA

VNEG, all phase bits = 0 -21 mA

Over Temperature

-40°C < T

< 85°C

A

TBD TBD mA
Quiescent Power Per Channel, all phase bits = 0 73 mW

Per Channel max (depends on phase bits) TBD mW
Disable Current All Channels Disabled; SPI stays on 2.6 mA
PSRR VPOS to Ix/Qx outputs (meas. @ AD8021 output) TBD dB

VNEG to Ix/Qx outputs (meas. @ AD8021 output) TBD dB

°
°

°

dB

μA
μA
MΩ

μs
μs

10 MHz

TBD ns

V

Rev. PrB| Page 4 of 29

AD8339 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltages

Supply Voltage V

S

±6 V

RF Inputs +6 V, GND
4LO Inputs +6 V, GND
Outputs (IxOP, QxOP) +1 V, -6 V
Digital Inputs +6 V, GND
SDO Output +6 V, GND
LODC Pin +6 V (max)

VPOS –1.5 V (min)

Thermal Data —4 Layer Jedec Board
No Air Flow (Exposed Pad Soldered
to PC Board)

θ

JA

θ

JB

θ

JC

Ψ

JT

Ψ

JB

Maximum Junction Temperature

TBD°C/W
TBD°C/W
TBD°C/W
TBD°C/W
TBD°C/W
150°C

Maximum Power Dissipation TBD W

(Exposed Pad Soldered to PC Board)

Operating Temperature Range
Storage Temperature Range

–40°C to +85°C
–65°C to +150°C

Lead Temperature Range (Soldering 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev PrB Page 5 of 29

AD8339 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RF1P

RF1N

RF2N

RF2P

COMM

COMM

SCLK

VPOS

VPOS

RF3P

RF3N

40 39 38 37 36 35 34 33 32 31

1 30

2

PIN 1
INDICATOR

3

4 27

5

CSB

6

7 24

8

9
10

AD8339

TOP VIEW

(Not to Scale)

11 12 13 14 15 16 17 18 19 20

Q2OP

29

I2OP

28

VPOS

VPOS

26

4LOP

25

4LON

VNEG

23

VNEG

22

I3OP

21

Q3OP

VPOS RSTS

SDO SDI

RF4P

RF4N

VPOS VPOS

COMM COMM

LODC RSET

I4OP I1OP

Q4OP Q1OP

VNEG VNEG

Figure 2. 40-Lead LFCSP

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 9, 10,
13, 14, 37,

RF1P-RF4P
RF1N-RF4N

RF Inputs. No internal bias. The optimum common mode voltage for maximum symmetrical input differential
swing is 2.5 V if ±5 V supplies are used.

38
3, 4, 15, 36 COMM Ground
5 SCLK Serial Interface – Clock
6 CSB Serial Interface – Chip Select Bar. Active Low.
7, 8, 11,

16, 27, 28,
35

VPOS

Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF
and 1 nF capacitor between the VPOS pins and ground. Since the VPOS pins are internally connected, one set

of supply decoupling components on each side of the chip should be sufficient.
12 SDO Serial Interface – Data Output. Normally connected to SDI of next chip or left open.
17 LODC

Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. Value of cap

does influence chip enable/disable times.
18, 19, 21, I1OP-I4OP, I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a

22, 29, 30, Q1OP-Q4OP transimpedance amplifier. Multiple outputs can be summed together through simply connecting them
32, 33 (Wire-OR). The bias voltage should be set to 0 V or less by the transimpedance amplifier, see 0.

20, 23, 24,
31

VNEG

Negative Supply. These pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF

and 1 nF capacitor between the pin and ground. Since the VNEG pins are internally connected, one set of

supply decoupling components should be sufficient.
25, 26 4LOP, 4LON

LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be

driven differentially.
34 RSET LO Interface - Reset. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic.
39 SDI

Serial Interface – Data Input. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS

logic.
40 RSTS

Reset for SPI Interface. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic. For

quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to -1.4 V; this

enables all four channels in the Phase (I=1,Q=0) state.

Rev. PrB Page 6 of 29

AD8339 Preliminary Technical Data

EQUIVALENT INPUT CIRCUITS

VPOS

VPOS

PHxx
ENBL
RSET

COMM

Figure 3. Logic Inputs

Figure 4. Local Oscillator Inputs

LOGIC

INTERFACE

RFxP

RFxN

COMM

Figure 6. RF Inpu ts

COMM

VNEG

Figure 7. Output Drivers

IxNO

QxNO

IxPO

QxPO

Figure 5. LO Decoupling Pin

Rev. PrB Page 7 of 29

AD8339 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, fLO = 5 MHz, fRF= 5.01 MHz, fBB = 10 kHz, P
performance, differential voltages, dBm (50), phase select code = 0000, unless otherwise noted (see default test circuit).

≥ 0 dBm (50); single-ended sine wave; per channel

LO

Rev. PrB Page 8 of 29

AD8339 Preliminary Technical Data

TEST CIRCUITS

Rev. PrB Page 9 of 29