Analog Devices AD8335 Service Manual

Quad Low Noise, Low Cost

FEATURES

Low noise preamplifier (PrA)
Voltage noise = 1.3 nV/√Hz typical
Current noise = 2.4 pA/√Hz typical
NF = 7 dB (R
Single-ended input; V
Active input match
Input SNR (noise bandwidth = 20 MHz) = 92 dB

VGA

Differential output
V

max = 5 V p-p, RL = 500 Ω differential

OUT

Gain range (8 dB output gain step)

−10 dB to +38 dB—LO gain mode

−2 dB to +46 dB—HI gain mode
Accurate linear-in-dB gain control

PrA + VGA performance

−3 dB bandwidth of 70 MHz

Excellent overload performance
Supply: 5 V
Power consumption

95 mW/channel (380 mW total)

65 mW/channel (PrA off; 260 mW total)
Power-down

APPLICATIONS

Medical imaging (ultrasound, gamma cameras)
Sonar
Test and measurement
Precise, stable wideband gain control

GENERAL DESCRIPTION

The AD8335 is a quad variable gain amplifier (VGA) with low
noise preamplifier intended for cost and power sensitive
applications. Each channel features a gain range 48 dB, fully
differential signal paths, active input preamplifier matching, and
user-selectable maximum gains of 46 dB and 38 dB. Individual
gain controls are provided for each channel.

The preamplifier (PrA) has a single-ended to differential gain
of ×8 (18.06 dB) and accepts input signals ≤ 625 mV p-p. PrA
noise is 1.2 nV/√Hz and the combined input referred voltage
noise of the PrA and VGA is 1.3 nV/√Hz at maximum gain.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

= RIN = 50 Ω)

S

IN

max = 625 mV p-p

Variable Gain Amplifier

FUNCTIONAL BLOCK DIAGRAM

PON160POP159VIP158VIN153VCM255VCM1

61

63

PIP1

PMD1

PMD2

PIP2
PON2

POP2

VIP2

VIN2

18dB

64

1

18dB

2

4

5

6

7

VMD1

VMD2

INTERPOLATOR

INTERPOLATOR

AD8335

10

VIN3

11

VIP3

12

POP3
PON3

PIP3

PMD3

PMD4

PIP4

13

15

18dB

16

17

18dB

18

VMD3

VMD4

20

21

22

VIP4

POP4

PON4

23

28

VIN4

VCM326VCM4

INTERPOLATOR

INTERPOLATOR

Figure 1.

Assuming a 20 MHz noise bandwidth (NBW), the Nyquist
frequency for a 40 MHz ADC, the input SNR is 92 dB. The
HILO pin optimizes the output SNR for 10-bit and 12-bit
ADCs with 1 V p-p or 2 V p-p full-scale (FS) inputs.

Channels 1 and 2 are enabled through the EN12 pin while
Channels 3 and 4 are enabled through the EN34 pin. For VGA
only applications, the PrAs can be powered down, significantly
reducing power consumption.

The AD8335 is available in a 64-lead lead frame chip scale
(9 mm × 9 mm) package for the industrial temperature range
of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone]

www.analog.com

© 2004 Analog Devices, Inc. All rights reserved.

52

ATTEN

–48dB TO

0dB

ATTEN

–48dB TO

0dB

ATTEN

–48dB TO

0dB

ATTEN

–48dB TO

0dB

29

EN1251SP1249HL12

20dB

TO

28dB

GAIN INT

GAIN INT

20dB

TO

28dB

20dB

TO

28dB

GAIN INT

GAIN INT

20dB

TO

28dB

30

SP3432HL34

EN34

AD8335

47

VOH1

46

VOL1

56

VGN1

50

SL12

54

VGN2

43

VOL2

42

VOH2

39

VOH3

38

VOL3

27

VGN3

31

SL34

25

VGN4

35

VOL4

34

VOH4

04976-001

AD8335

TABLE OF CONTENTS

Specifications..................................................................................... 3

Output Stage ........................................................................... 19

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Test Circuits..................................................................................... 15

Theory of Operation ......................................................................16

Enable Summary......................................................................... 16

Preamp......................................................................................... 17

Noise.........................................................................................17

VGA..............................................................................................18

Optimizing the System Dynamic Range............................. 18

Attenuator................................................................................18

Gain Control........................................................................... 19

REVISION HISTORY

VGA Noise .............................................................................. 19

Applications..................................................................................... 20

Ultrasound................................................................................... 20

Basic Connections...................................................................... 21

Preamp Connections.................................................................. 21

Input Overdrive.......................................................................... 23

Input Overload Protection.................................................... 23

Logic Inputs................................................................................. 23

Common-Mode Pins................................................................. 23

Driving ADCs............................................................................. 23

Outline Dimensions....................................................................... 24

Ordering Guide........................................................................... 24

9/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD8335

SPECIFICATIONS

VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, dBm (50 Ω), unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

PrA CHARACTERISTICS

Gain
Single-ended input to single-ended output 12 dB
Input Voltage Range PrA output limited to 5 V p-p differential 625 mV p-p
Input Resistance RFB = 249 Ω 50 Ω
R
R
R
Input Capacitance PIPx (Pins 2, 15, 18, 63) 1.5 pF

−3 dB Small Signal Bandwidth With RFB = 249 Ω 110 MHz
Input Voltage Noise RS = 0 Ω, RFB = ∞ 1.15 nV/√Hz
Input Current Noise 2.4 pA/√Hz
Noise Figure

Active Termination Match RS = RIN = 50 Ω, RFB = 249 Ω 7 dB
Unterminated RS = 50 Ω, RFB = ∞ 4.4 dB

PrA + VGA CHARACTERISTICS

−3 dB Small Signal Bandwidth Unterminated: RS = 50 Ω, RFB = ∞ 70 MHz
Matched: RS = RIN = 50 Ω 85 MHz
Slew Rate LO gain, VGN = 3 V, V

HI gain, VGN = 3 V, V

Input Voltage Noise Pins VGNx = 3 V, RS = 0 Ω, RFB = ∞ 1.3 nV/√Hz
Noise Figure

Active Termination Match

R

Unterminated RS = 50 Ω, RFB = ∞ 5.0 dB
R
Output Referred Noise LO gain; VGN < 2 V 33 nV/√Hz
HI gain; VGN < 2 V 80 nV/√Hz
Peak Output Voltage Differential, RL ≥ 500 Ω 5 V p-p
Output Resistance f < 1 MHz, Pins VOHx, VOLx 1.2 Ω
Common-Mode Level Set to midsupply for PrA and VGA VS/2 V
Output Offset Voltage Differential (VOHx−VOLx) full gain range −25 5 35 mV
Common-mode (VOHx−VCMx, VOLx−VCMx) −20 0 20 mV
Harmonic Distortion V

HD2 f = 1 MHz −69 dBc

HD3 f = 1 MHz −57 dBc

HD2 f = 10 MHz −57 dBc

HD3 f = 10 MHz −55 dBc
Harmonic Distortion V

HD2 f = 1 MHz −58 dBc

HD3 f = 1 MHz −70 dBc

HD2 f = 10 MHz −55 dBc

HD3 f = 10 MHz −55 dBc
Output 1 dB Compression (OP1dB) VGN = 3 V 18 dBm
VGN = 3 V 8 dBVpk

Single-ended input to differential output 18 dB

= 374 Ω 75 Ω

FB

= 499 Ω 100 Ω

FB

= ∞, low frequency value into PIPx 14.7 kΩ

FB

= 2 V p-p 250 V/µs

OUT

= 2 V p-p 350 V/µs

OUT

Pins VGNx = 3 V, f = 1 MHz to 10 MHz
RS = RIN = 50 Ω 7 dB

= RIN = 100 Ω 4.5 dB

S

= 500 Ω, RFB = ∞ 1.3 dB

S

= 1 V p-p, LO gain, VGN = 2 V

OUT

= 1 V p-p, HI gain, VGN = 2 V

OUT

Rev. 0 | Page 3 of 24

AD8335

Parameter Conditions Min Typ Max Unit

Two-Tone IMD3 Distortion V
f
f
Output IP3 (OIP3) V
f = 1 MHz 33 dBm
f = 10 MHz 31 dBm
Channel-to-Channel Crosstalk V
Overload Recovery Pra or VGA 10 ns
Group Delay Variation Full gain range, f = 1 MHz to 10 MHz 3.0 ns

GAIN CONTROL INTERFACE Pins VGNx

Normal Operating Range 0
Maximum Range No gain foldover 0 VS V
Gain Range LO gain mode; (Pins HLxx = 0 V) −10 to +38 dB
HI gain mode; (Pins HLxx = VS) −2 to +46 dB
Scale Factor Nominal (Pins SL12 and SL34 = 2.5 V) 19.0 20.0 21.0 dB/V
Bias Current −0.3 µA
Response Bandwidth 5 MHz
Response Time 48 dB gain change 350 ns

GAIN ACCURACY Pins VGNx

Absolute Gain Error 0 ≤ VGN ≤ 0.4 V 1.25 7.5 dB

2.6 ≤ VGN ≤ 3 V −7.5 −1.25 dB
Gain Law Conformance Over Temperature 0.4 ≤ VGN ≤ 2.6 V; −40°C < TA < +85°C ±0.75 dB
Intercept LO gain mode; PrA matched to 50 Ω −16.1 dB
HI gain mode; PrA matched to 50 Ω −8.1 dB
Channel-to-Channel Matching 0.4 ≤ VGN ≤ 2.6 V 0.15 dB

LOGIC LEVEL—HILO, SHUTDOWN PREAMP,
and ENABLE INTERFACES

Logic Level High 2.75 5 V
Logic Level Low 0 1 V

BIAS CURRENT—HILO, ENABLE

Logic high 80 µA

Logic low −12 µA
INPUT RESISTANCE—HILO, ENABLE 50 kΩ
BIAS CURRENT – SHUTDOWN PREAMP

Logic high 20 µA

Logic low 0 µA
INPUT RESISTANCE—SHUTDOWN PREAMP 500 kΩ

HILO Response Time 0.6 µs

Enable Response Time 100 µs
POWER SUPPLY Pins VPPx and VPVx

Supply Voltage 4.5 5 5.5 V

Quiescent Current Per channel—PrA and VGA enabled 19 mA

Over Temperature −40°C < TA < +85°C 16 22.8 mA

Quiescent Power Per channel—PrA and VGA enabled 95 mW

Quiescent Current Per channel—PrA disabled, VGA enabled 13 mA

Quiescent Power Per channel—PrA disabled, VGA enabled 65 mW

Quiescent Current All channels enabled 76 mA

Disable Current All channels disabled 0.8 mA

PSRR VGN = 0 V, all bypass capacitors removed, 1 MHz −60 dB

= 1 V p-p, VGN = 3 V

OUT

= 1 MHz, f2 = 1.05 MHz −69 dBc

1

= 10 MHz, f2 = 10.05 MHz −65 dBc

1

= 1 V p-p, VGN = 3 V

OUT

= 1 V p-p, f = 1 to 10 MHz −80 dBc

OUT

3 V

0.4 ≤ VGN ≤ 2.6 V, 1σ

−1.25 ±0.2 +1.25 dB

Pins HLxx, SPxx, and ENxx

Rev. 0 | Page 4 of 24

AD8335

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage

Supply VS 6 V
Preamp Input VS
VGA Inputs VS
Enable, Shutdown Preamp, and HILO

Interfaces

Gain VS
Power Dissipation (4-layer JEDEC Board (2S2P)) 2.46 W
θJA 26.4°C/W
θJC 6.8°C/W
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 s) 300°C

VS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 24

AD8335

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PMD1

PIP1

VPP1

PON1

POP1

VIP1

VIN1

COM1

VGN1

VCM1

VGN2

VCM2

EN12

SP12

646362616059585756555453525150

SL12

HL12
49

PMD2

PIP2

VPP2
PON2
POP2

VIP2

VIN2
COM2
COM3

VIN3

VIP3
POP3
PON3

VPP3

PIP3
PMD3

10
11
12
13
14
15
16

PIN 1

1

IDENTIFIER

2
3
4
5
6
7
8
9

171819202122232425262728293031

PIP4

VPP4

PON4

PMD4

Figure 2. LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 PMD2 Preamp input common—Ch2
2 PIP2 Preamp input—Ch2
3 VPP2 Positive supply preamp—Ch2
4 PON2 Preamp output negative—Ch2
5 POP2 Preamp output positive—Ch2
6 VIP2 VGA input positive—Ch2
7 VIN2 VGA input negative—Ch2
8 COM2 Ground preamp—Ch2
9 COM3 Ground preamp—Ch3
10 VIN3 VGA input negative—Ch3
11 VIP3 VGA input positive—Ch3
12 POP3 Preamp output positive—Ch3
13 PON3 Preamp output negative—Ch3
14 VPP3 Positive supply preamp—Ch3
15 PIP3 Preamp input—Ch3
16 PMD3 Preamp input common—Ch3
17 PMD4 Preamp input common—Ch4
18 PIP4 Preamp input—Ch4
19 VPP4 Positive supply preamp—Ch4
20 PON4 Preamp output negative—Ch4
21 POP4 Preamp output positive—Ch4
22 VIP4 VGA input positive—Ch4
23 VIN4 VGA input negative—Ch4
24 COM4 Ground preamp—Ch4
25 VGN4 Gain control—Ch4
26 VCM4 Common-mode decoupling pin—Ch4
27 VGN3 Gain control—Ch3
28 VCM3 Common-mode decoupling pin—Ch3
29 EN34 Enable—Ch3 and Ch4
30 SP34 Shutdown—preamp3 and preamp4
31 SL34 Slope decoupling pin—Ch3 and Ch4
32 HL34 HILO pin—Ch3 and Ch4

AD8335

TOP VIEW

(Not to Scale)

VIP4

VIN4

POP4

COM4

48

GND1

47

VOH1

46

VOL1

45

VPV1

44

VPV2

43

VOL2

42

VOH2

41

GND2

40

GND3

39

VOH3

38

VOL3

37

VPV3

36

VPV4

35

VOL4

34

VOH4

33

GND4

32

SL34

HL34

SP34

EN34

VGN4

VGN3

VCM4

VCM3

04976-058

Pin No. Mnemonic Function

33 GND4 Ground VGA—Ch4
34 VOH4 VGA output positive—Ch4
35 VOL4 VGA output negative—Ch4
36 VPV4 Positive supply VGA—Ch4
37 VPV3 Positive supply VGA—Ch3
38 VOL3 VGA output negative—Ch3
39 VOH3 VGA output positive—Ch3
40 GND3 Ground VGA —Ch3
41 GND2 Ground VGA — Ch2
42 VOH2 VGA output positive—Ch2
43 VOL2 VGA output negative—Ch2
44 VPV2 Positive supply VGA—Ch2
45 VPV1 Positive supply VGA—Ch1
46 VOL1 VGA output negative—Ch1
47 VOH1 VGA output positive—Ch1
48 GND1 Ground VGA — Ch1
49 HL12 HILO pin—Ch1 and Ch2
50 SL12 Slope decoupling pin—Ch1 and Ch2
51 SP12 Shutdown—preamp1 and preamp2
52 EN12 Enable—Ch1 and Ch2
53 VCM2 Common-mode decoupling pin—Ch2
54 VGN2 Gain control—Ch2
55 VCM1 Common-mode decoupling pin—Ch1
56 VGN1 Gain control—Ch1
57 COM1 Ground preamp—Ch1
58 VIN1 VGA input negative—Ch1
59 VIP1 VGA input positive—Ch1
60 POP1 Preamp output positive—Ch1
61 PON1 Preamp output negative—Ch1
62 VPP1 Positive supply preamp—Ch1
63 PIP1 Preamp input—Ch1
64 PMD1 Preamp input common—Ch1

Rev. 0 | Page 6 of 24

AD8335

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, unless otherwise noted.

50

40

30

20

+25°C

10

GAIN (dB)

0

–10

–20

Figure 3. Gain vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

+85°C, LO GAIN

+25°C, HI GAIN

Figure 4. Gain Error vs. V

6.0

4.0

2.0

0

GAIN ERROR (dB)

–2.0

–4.0

–6.0

1MHz

Figure 5. Gain Error vs. V

+85°C

HI GAIN

LO GAIN

–40°C

1.0 1.50 0.5 2.0 2.5 3.0
V

(V)

GAIN

at Three Temperatures (See Figure 49)

GAIN

+85°C, HI GAIN

+25°C, LO GAIN

–40°C, LO GAIN

–40°C, HI GAIN

1.0 1.50 0.5 2.0 2.5 3.0

(V)

V

GAIN

at Three Temperatures (See Figure 49)

GAIN

5MHz

20MHz

10MHz

1.0 1.50 0.5 2.0 2.5 3.0

(V)

V

GAIN

at Various Frequencies (See Figure 49)

GAIN

04976-002

04976-003

04976-004

20

420 CHANNELS

18

(105 UNITS)

= 1.5V

V

GAIN

16

14

12

10

8

% OF UNITS

6

4

2

0

–0.6 –0.5 –0.4 –0.3 –0.2 0 0.4–0.1 0.1 0.2 0.3 0.5 0.6

GAIN ERROR (dB)

Figure 6. Gain Error Histogram

25

420 CHANNELS

20

(105 UNITS)

= 1.0V

V

GAIN

15
10

5
0

–1.0

–0.9

–0.8

–0.7

–0.6

–0.5

25

% OF UNITS

V

20
15
10

5
0

= 2.0V

GAIN

CH1 TO CH2
CH1 TO CH4
CH1 TO CH3

–1.0

–0.9

–0.8

–0.4

–0.7

–0.6

–0.5

–0.4

CHANNEL-TO-CHANNEL GAIN MATCH (dB)

Figure 7. Gain Match Histogram for V

–0.3

–0.3

–0.2

–0.2

–0.1

–0.1

0

0.1

0.2

0.3

0.4

0

0.1

0.3

0.4

0.2

GAIN

45

420 CHANNELS
(105 UNITS)

40

35

30

25

20

% TOTAL

15

10

5

0

0.5V < V

< 2.5V

GAIN

GAIN SCALING FACTOR

Figure 8. Gain Scaling Factor Histogram for 0.5 V < V

0.6

0.6

0.7

0.7

0.8

0.8

0.9

0.9

0.5

0.5

= 1 V and 2 V

20.419.9 20.0 20.1 20.2 20.3

< 2.5 V

GAIN

1.0

1.0

04976-005

04976-006

04976-007

Rev. 0 | Page 7 of 24

AD8335

25

420 CHANNELS
(105 UNITS)

0.5V < V

20

15

% TOTAL

10

GAIN

< 2.5V

30

25

20

= 249Ω

R

RS = 50Ω

15

= 10mV p-p

V

IN

10

GAIN (dB)

5

FB

RFB = ∞

5

0

–16.7 –16.6 –16.5 –16.4 –16.3 –16.1 –15.7–16.2 –16.0 –15.9 –15.8 –15.6 –15.5

INTERCEPT (dB)

Figure 9. Intercept Histogram

50

V

= 3.0V

GAIN

40

V

= 2.5V

GAIN

30

V

= 2.0V

GAIN

20

V

= 1.5V

GAIN

10

GAIN (dB)

–10

–20

V

= 1.0V

GAIN

0

= 0.5V

V

GAIN

= 0V

V

GAIN

1M100k 10M 100M 1G

FREQUENCY (Hz)

Figure 10. Frequency Response for Various Values of V

50

V

= 3.0V

GAIN

40

30

20

10

GAIN (dB)

0

–10

V
V

V

V

V

V

GAIN
GAIN

GAIN

GAIN

GAIN

GAIN

= 2.5V
= 2.0V

= 1.5V

= 1.0V

= 0.5V

= 0V

(See Figure 49)

GAIN

04976-008

04976-009

0

–5

–10

1M100k 10M 100M 1G

FREQUENCY (Hz)

Figure 12. Frequency Response for a Terminated and Unterminated

50 Ω Source (See Figure 49)

–10

V

= 1V p-p

OUT

–20

–30

–40

–50

–60

V

= 1V

GAIN

CROSSTALK (dB)

–70

–80

–90

–100

V

= 3V

GAIN

V

= 2V

GAIN

100k 10M1M 100M

FREQUENCY (Hz)

V

GAIN

V

GAIN

= 1V

= 2V

V

GAIN

= 3V

Figure 13. Channel-to-Channel Crosstalk vs. Frequency for

Various Values of V

GAIN

80

70

60

50

40

30

GROUP DELAY (ns)

20

10

04976-011

04976-012

–20

1M100k 10M 100M 1G

FREQUENCY (Hz)

Figure 11. Frequenc y Respons e vs. Freque ncy for Various Values of V

HILO = HI (See Figure 49)

04976-010

,

GAIN

Rev. 0 | Page 8 of 24

0
100k 10M1M 100M

FREQUENCY (Hz)

Figure 14. Group Delay v s. Frequenc y

04976-013

AD8335

25

20

15

10

5

0

–5

–10

OFFSET VOLTAGE (mV)

–15

–20

–25

+85°C, HI

+85°C, LO

–40°C, LO

1.0 1.50 0.5 2.0 2.5 3.0
V

GAIN

–40°C, HI

+25°C, HI

+25°C, LO

(V)

04976-014

INPUT IMPEDANCE (Ω)

1k

100

10

RFB = 2.5kΩ

RFB = 1kΩ

= 499Ω

R

FB

= 249Ω

R

FB

RSH = ∞, CSH = 0pF

RSH = 49Ω, CSH = 22pF

1M 10M 1G

FREQUENCY (Hz)

04976-017

Figure 15. Differential Output Offset Voltage vs. V

25

20

15

10

5

0

–5

–10

OFFSET VOLTAGE (mV)

–15

–20

–25

Figure 16. Absolute Offset vs. V

1.0 1.50 0.5 2.0 2.5 3.0
V

(V)

GAIN

at Pins VOHx and VOLx

GAIN

Relative to Pins VCMx

100

VIN = 10mV p-p

10

at Three Temperatures

GAIN

VOHx

VOLx

04976-015

Figure 18. Preamp Input Resistance vs. Frequency for

Various Values of R

FB

VIN = 10mV p-p

–10

–20

–30

–40

–50

0Ω

–60

CROSSTALK (dB)

–70

–80

–90

–100

100k 10M1M 100M

25j

17Ω

–25j

50j

50Ω

START

100kHz

100MHz

–50j

FREQUENCY (Hz)

150Ω

STOP
1GHz

100j

–75j

Figure 19. Smith Chart S11 vs. Frequency, 100 kHz to 1 GHz

250

= 0Ω

R

S

R

= ∞

FB

200

150

04976-018

1

OUTPUT IMPEDANCE (Ω)

0.1
1M100k 10M 1G

FREQUENCY (Hz)

Figure 17. Output Resistance at Pins VOHx and VOLx vs. Frequency

04976-016

Rev. 0 | Page 9 of 24

100

50

OUTPUT REFERRED NOISE (nV/ Hz)

0

1.0 1.50 0.5 2.0 2.5 3.0

Figure 20. Output Referred Noise vs. V

HILO = HI

HILO = LO

(V)

V

GAIN

(See Figure 50)

GAIN

04976-019

AD8335

1.4

1.2

V

= 3.0V

GAIN

1.0

= 0Ω

R

S

= ∞

R

FB

0.8

0.6

0.4

INPUT REFERRED NOISE (nV/ Hz)

0.2

0

0.1 101 100
FREQUENCY (MHz)

04976-020

NOISE FIGURE (dB)

60
55
50
45
40
35
30
25
20
15
10

5
0

f = 10MHz

1.0 1.50 0.5 2.0 2.5 3.0
(V)

V

GAIN

04976-062

Figure 21. Short-Circuit Input Referred Noise vs. Frequency at Maximum Gain

(See Figure 50)

1k

T = +85°C

100

10

NOISE (nV/ Hz)

1.0

0.1

1.0 1.50 0.5 2.0 2.5 3.0

Figure 22. Input Referred Noise vs. V

V

GAIN

T = –40°C

(V)

T = +25°C

at Three Temperatures

GAIN

(See Figure 50)

10

f = 1MHz, V

GAIN

= 3V

04976-021

Figure 24. Noise Fig ure vs. V

for RS = RIN = 50 Ω

GAIN

–35

f = 10MHz

= 1V p-p

V

OUT

–40

–45

–50

–55

DISTORTION (dBc)

–60

–65

–70

200 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k

= 1.5V

V

GAIN

HILO = LO

HD2 HD3

R

(Ω)

LOAD

Figure 25. Harmonic Distortion vs. R

HILO = HI

HD2 HD3

(See Figure 50)

LOAD

–20

f = 10MHz
V

= 1V p-p

OUT

–30

04976-025

HILO = HI,

HD2

HILO = LO

HD3

C

LOAD

(pF)

–40

1.0

INPUT NOISE (nV/ Hz)

0.1

Figure 23. Input Referred Noise vs. R

RS THERMAL NOISE

ALONE

101 100 1k

SOURCE RESISTANCE (Ω)

S

04976-022

–50

–60

DISTORTION (dBc)

–70

–80

0 1020304050

Figure 26. Harmonic Distortion vs. C

HILO = HI,

HD3

HILO = LO,

HD2

(See Figure 53)

LOAD

04976-200

Rev. 0 | Page 10 of 24

AD8335

–20

–30

–40

LO GAIN
V

OUT

f = 10MHz

= 1V p-p

–20

–30

–40

HI GAIN
V

= 1V p-p

OUT

–50

–60

DISTORTION (dBc)

–70

–80

0.5 1.0 1.5 2.0 2.5 3.0

Figure 27. HD2 vs. V

–20

–30

–40

–50

–60

DISTORTION (dBc)

–70

–80

0.5 1.0 1.5 2.0 2.5 3.0

f = 5MHz

f = 1MHz

(V)

V

GAIN

at Three Frequencies, LO Gain (See Figure 53)

GAIN

LO GAIN
V

OUT

f = 10MHz

= 1V p-p

V

GAIN

f = 1MHz

(V)

f = 5MHz

04976-026

04976-027

–50

–60

DISTORTION (dBc)

–70

–80

0.5 1.0 1.5 2.0 2.5 3.0

Figure 30. HD3 vs. V

–35

–40

–45

–50

–55

–60

–65

DISTORTION (dBc)

–70

–75

–80

0.5 1.0 1.5 2.0 2.5 3.0

at Three Frequencies, HI Gain (See Figure 53)

GAIN

1V p-p

f = 1MHz

V

2V p-p

V

f = 10MHz

GAIN

GAIN

f = 5MHz

(V)

f = 1MHz

0.5V p-p

(V)

04976-030

04976-031

Figure 28. HD3 vs. V

–20

–30

DISTORTION (dBc)

–40

–50

–60

–70

–80

f = 10MHz

f = 1MHz

0.5 1.0 1.5 2.0 2.5 3.0

Figure 29. HD2 vs. V

at Three Frequencies, LO Gain (See Figure 53)

GAIN

HI GAIN
V

OUT

f = 5MHz

at Three Frequencies, HI Gain (See Figure 53)

GAIN

= 1V p-p

V

GAIN

(V)

04976-029

Rev. 0 | Page 11 of 24

Figure 31. HD2 vs. V

at Three Output Voltages, LO Gain (See Figure 53)

GAIN

–20

V

GAIN

f = 1MHz

(V)

–30

–40

–50

–60

DISTORTION (dBc)

–70

–80

–90

0.5V p-p

0.5 1.0 1.5 2.0 2.5 3.0

Figure 32. HD3 vs. V

2V p-p

1V p-p

, at Three Output Voltages, LO Gain (See Figure 53)

GAIN

04976-032

AD8335

–35

–40

–45

–50

–55

DISTORTION (dBc)

–60

–65

2V p-p

1V p-p

f = 1MHz

0.5V p-p

IP3 (dBm)

40

V

= 1Vp-p

OUT

35

30

25

20

15

10

5

5MHz (HI)

5MHz (LO)

–70

Figure 33. HD2 vs. V

1.0 1.50 0.5 2.0 2.5 3.0
V

(V)

GAIN

at Three Output Voltages, HI Gain, f = 1 MHz

GAIN

(See Figure 53)

–20

V

GAIN

f = 1MHz

2V p-p

0.5V p-p

(V)

–30

–40

–50

–60

DISTORTION (dBc)

–70

–80

–90

0

0.5 1.0 1.5 2.0 2.5 3.0

Figure 34. HD3 vs. V

1V p-p

at Three Output Voltages, HI Gain (See Figure 53)

GAIN

0

V

= 1V p-p

OUT

IM3 (dBc)

–10

–20

–30

–40

–50

–60

–70

–80

–90

= 3V

V

GAIN

IMD3 (HI)

IMD3 (LO)

1 10 100

FREQUENCY (MHz)

Figure 35. IM D3 vs. Frequ ency

04976-034

04976-035

04976-036

0

Figure 36. Output Referred IP3 (OIP3) vs. V

1.0 1.50 0.5 2.0 2.5 3.0
V

(V)

GAIN

GAIN

5

0

f = 10MHz

–5

HILO = HI

–10

–15

INPUT POWER (dBm)

–20

–25

–30

1.0 1.50 0.5 2.0 2.5 3.0
V

GAIN

Figure 37. Input P1dB (IP1dB) vs. V

(V)

HILO = LO

GAIN

10mV

100

90

10

0

HARMONIC DISTORTION (dBc)

50mV

10ns

Figure 38. Small Signal Pulse Response, LO Gain (See Figure 51)

04976-037

04976-038

04976-039

Rev. 0 | Page 12 of 24

AD8335

10mV

100

90

10
0

HARMONIC DISTORTION (dBc)

50mV

10ns

Figure 39. Large Signal Pulse Response, LO Gain (See Figure 51)

2

V

= 2V

GAIN

INPUT

1

(V)

0

OUT

V

–1

INPUT IS NOT TO SCALE

–2

0 102030405060708090100

C

L

C
C

CL = 0pF

= 47pF

= 22pF

L

= 10pF

L

TIME (ns)

Figure 40. Large Signal Pulse Response for Various Capacitive Loads,

C

= 0 pF, 10 pF, 20 pF, 47 pF Each Output (See Figure 51)

L

04976-039

04976-041

2V

100
90

10

0

HARMONIC DISTORTION (dBc)

100mV

Figure 42. Small Signal Enable Response (See Figure 51)

2V

100

90

10

0

HARMONIC DISTORTION (dBc)

1V

Figure 43. Large Signal Enable Response (See Figure 51)

100µs

100µs

04976-043

04976-044

2V

100

90

10

0

HARMONIC DISTORTION (dBc)

500mV

Figure 41. Gain Response, V

Stepped from 0 V to3 V, V

GAIN

(See Figure 51)

400ns

= 2 V p-p

OUT

04976-042

Rev. 0 | Page 13 of 24

1V

100

90

10
0

HARMONIC DISTORTION (dBc)

1µs

Figure 44. Preamp Overdrive Recovery,

50 mV p-p to 1.5 V p-p at Preamp Input (Measured at Preamp Output)

04976-045

AD8335

95

1V

100

90

10

0

HARMONIC DISTORTION (dBc)

1µs

Figure 45. VGA Overdrive Recovery, 40 mV to 500 mV Input, V

0

–10

V

= 2.5V

GAIN

–20

–30

–40

PSRR (dB)

–50

–60

–70

–80

100k 10M1M 100M

V

GAIN

= 0.5V

FREQUENCY (Hz)

V

GAIN

V

= 0V

GAIN

= 1.5V

Figure 46. PSRR vs. Frequency (All Bypass Capacitors Removed)

GAIN

= 2.5 V

04976-046

04976-100

90

V

= 2.5V

85

80

75

70

65

QUIESCENT SUPPLY CURRENT (mA)

60

–40 –20 0 20 40 60 80 100

GAIN

TEMPERATURE (°C)

Figure 47. Quiescent Supply Current vs. Temperature

2V

100

90

10
0

HARMONIC DISTORTION (dBc)

500mV

Figure 48 HILO Response Time

1µs

04976-047

04976-101

Rev. 0 | Page 14 of 24

AD8335

R

TEST CIRCUITS

NETWORK ANALYZER

0.1µF

49.9Ω

22pF

50Ω

OUT

18nF

AD8335

0.1µF

249Ω

0.1µF

0.1µF

50Ω

IN

237Ω

28Ω

237Ω

28Ω

Figure 49. Test Circuit for Gain and Bandwidth Measurements

18nF

249Ω

AD8335

0.1µF

49.9Ω

50Ω

22pF

0.1µF

Figure 51. Test Circuit for Transient Measurements

0.1µF

0.1µF

237Ω

28Ω

237Ω

28Ω

1:1

04976-048

OSCILLOSCOPE

50Ω

IN

1:1

04976-049

SPECTRUM

ANALYZER

0.1µF

49Ω

22pF

AD8335

0.1µF

0.1µF

0.1µF

50Ω

IN

1:1

Figure 50. Test Circuit Used for Noise Measurements

NETWORK ANALYZER

0.1µF

49.9Ω

22pF

50Ω

18nF

AD8335

0.1µF

249Ω

0.1µF

0.1µF

50Ω

INOUT

237Ω

28Ω

237Ω

28Ω

50Ω

1:1

Figure 52. Test Circuit Used for S11 Measurements

50Ω

04976-050

04976-052

SPECTRUM

1:1

ANALYZER

50Ω

IN

04976-051

SIGNAL

GENERATO

50Ω

LPF

0.1µF

50Ω

22pF

18nF

AD8335

0.1µF

249Ω

0.1µF

0.1µF

237Ω

28Ω

237Ω

28Ω

Figure 53. Test Circuit Used for Distortion Measurements

Rev. 0 | Page 15 of 24

AD8335

THEORY OF OPERATION

Figure 54 is a simplified block diagram of a single channel. Each
channel consists of a low noise preamplifier (PrA) followed by a
VGA with a user-selectable gain of 20 dB or 28 dB. Channels are
enabled in pairs, Channels 1 and 2 and Channels 3 and 4. The
preamps are enabled by grounding Pins SPxx and powered
down by connecting them to the positive supply. The ENxx pins
are connected to the positive supply to enable the VGAs and the
overall channel. HILO configures VGA for a fixed gain of 20 dB
or 28 dB, with 0 V or 5 V applied to the HLxx pins, respectively.
Channels 1 and 2 share Pin HL12, and Channels 3 and 4 share
Pin HL34. The HLxx pins are typically hardwired to adjust the
VGA gain according to an ADC resolution of 12 bits for LO
gain and 10 bits for HI gain.

The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the
preamplifiers are designed to be driven from a single-ended
signal source. Gain values are referenced from the single-ended
PrA input to the differential output of either the PrA or the
VGA. Again referring to Figure 54, the system gain is
distributed as listed in Table 4.

Table 4. Channel Gain Distribution

Section

LO Nominal Gain
(dB)

HI Nominal Gain
(dB)

PrA 18.06 18.06
Attenuator 0 to −48.16 0 to −48.16
Output Amp 20 27.96
Aggregate −10.1 to +38.6 −2.14 to +46.02

Table 5. Control Pin Logic and Power Consumption

EN12 SP12 EN34 SP34 PrA12 VGA12 PrA34 VGA34 IS

H L H L On On On On 76 mA
H H H H Off On Off On 52 mA
L L L L Off Off Off Off 0.8 mA
L H L H Off Off Off Off 0.8 mA

In the remainder of this document, the gain values are
rounded to −10 dB to +38 dB for LO gain mode and to

−2 dB to +46 dB for HI gain mode. If desired, Equation 1
can be used to calculate the gain at value of V

dBGain

dB
V

GN

(1)

ICPTV

+= 20)(

GAIN

:

where ICPT = −16.1 dB for LO gain mode with the preamp
input matched to 50 Ω (R

= 250 Ω) and −10.1 dB for the

FB

unmatched input case. For HI gain mode, these numbers
are −8.1 dB and −2.1 dB, respectively.

Power consumption is 95 mW/channel from a 5 V supply,
or 380 mW for all four channels. Power is distributed 35%
for the PrA, and 65% for the remainder of the circuit. The
preamps can be shut down via the SP12 and SP34 pins if a
user wants to use the VGAs only. However, to avoid
feedthrough around the preamp, feedback resistors should
not be installed.

ENABLE SUMMARY

Table 5 summarizes the enable/shutdown logic and
resulting supply current.

+1

VINx

PONx

RFB

PrA

R

PIPx

S

PMDx

18dB

BIAS

ENxx

POPx

INTERPOLATOR

ATTENx

–48dB TO 0dB

+1

VIPx

Figure 54. Simplified Block Diagram of Single Channel

VCMx

Rev. 0 | Page 16 of 24

OUTPUT AMP

20dB TO 28dB

GAIN INTERFACE

SLxx

VGNx

+1

+1

+1

+1

HILO

HLxx

VOHx

VOLx

04976-054

AD8335

PREAMP

Although the preamp signal path is fully differential, the design
is optimized for single-ended input drive and signal source
resistance matching. Thus, the negative input to the differential
preamplifier Pins PMDx must be ac-grounded to provide a
balanced differential signal at the PrA outputs. Detailed
information regarding the preamplifier architecture is found in
the LNA section of the AD8331/AD8332 data sheet.

The preamplifier consists of a fixed gain amplifier with differen­tial outputs. With the negative output available and a fixed gain
of 8 (18.06 dB), an active input termination is synthesized by
connecting a feedback resistor between the negative output and
the positive input, Pin PIPx. This technique is well known and
results in the input resistance shown in Equation 2.

R

FB

= (2)

R

IN

where A/2 is the single-ended gain, or the gain from the PIPx
inputs to the PONx outputs. Since the amplifier has a gain of ×8
from its input to its differential output, it is important to note
that the gain A/2 is the gain from Pin PIPx to Pin PONx, which
is 6 dB lower, or 12.04 dB (×4). The input resistance is reduced
by an internal bias resistor of 14.7 kΩ in parallel with the source
resistance connected to Pin PIPx, with Pin PMDx ac-grounded.
Equation 3 can be used to calculate the needed R

, and is used for higher values of RIN.

R

IN

R

IN

For example, to set R
simplified Equation 2 is used to calculate R
resulting in a less than 0.1 dB gain error. Factors such as a
widely varying source resistance might influence the absolute
gain accuracy more significantly. At higher frequencies, the
input capacitance of the PrA needs to be considered. The user
must determine the level of matching accuracy and adjust R
accordingly.

The bandwidths (BW) of the preamplifier and VGA are
approximately 110 MHz each, resulting in a cascaded BW of
approximately 80 MHz. Ultimately the BW of the PrA limits the
accuracy of the synthesized R
200 Ω, the best match is between 100 kHz and 10 MHz, where

A

)

1(

+

2

for a desired

FB

R

FB

=

kΩ7.14||

)41( +

(3)

= 200 Ω, the value of RFB is 1.013 kΩ. If the

IN

, the value is 197 Ω,

IN

. For RIN = RS up to approximately

IN

FB

the lower frequency limit is determined by the size of the ac­coupling capacitors, and the upper limit is determined by the
preamplifier BW. Furthermore, the input capacitance and R

S

limits the BW at higher frequencies.

1k

R

= ∞, CSH = 0pF

RIN = 500Ω, RFB = 2.5kΩ

)

Ω

= 200Ω, RFB = 1kΩ

R

IN

100

R

= 100Ω, RFB = 499Ω

IN

= 50Ω, RFB = 249Ω

R

INPUT IMPEDANCE (

IN

10

100k 1M 10M 50M

Figure 55. RIN vs. Frequency for Various Values of RFB.

R

Effects of R

SH

= 50Ω, CSH = 22pF

SH

= ∞, CSH = 0pF

R

SH

R

= 50Ω, CSH = 22pF

SH

FREQUENCY (Hz)

and CSH are also shown.

SH

04976-102

Figure 55 shows RIN vs. frequency for various values of RFB. Note
that at the lowest value, 50 Ω, R

peaks at frequencies greater

IN

than 10 MHz. This is due to the BW roll-off of the PrA as
mentioned earlier. The R

and CSH network shown in Figure 58

SH

reduces this peaking.

However, as can be seen for larger R

values, parasitic

IN

capacitance starts rolling off the signal BW before the PrA can
produce peaking and the R
match. Therefore R

greater than 50 Ω.

R

IN

and CSH should not be used for values of

SH

network further degrades the

SH/CSH

Noise

The total input referred noise (IRN) is approximately 1.3
nV/

√Hz. Allowing for a gain of ×8 in the preamp, the VGA

noise is 0.46 nV/
noise is 1.2 nV/

√Hz referred to the PrA input. The preamp

√Hz. It is important to note that these noise

values include all amplifier noise sources, including the VGA
and the preamplifier gain resistors. Frequently, manufacturer
noise specifications exclude gain setting resistors, and the
voltage noise spectral density of an op amp might be presented
as 1 nV/

√Hz. Including the gain resistors results in a much

higher noise specification.

Rev. 0 | Page 17 of 24

AD8335

Figure 56 shows the simulated noise figure (NF) vs. source
resistance, and various values of preamplifier R

14.7 kΩ, the value seen looking into Pins PIPx when R
shown in the figure, the minimum NF for R
less than 7 dB. Note that, for this preamplifier, the NF is
optimized for the R

from 50 Ω to 200 Ω; for RFB = ∞, the

IN

minimum NF is at approximately 480 Ω. This optimum noise
resistance can also be calculated by dividing the input referred
voltage noise by the current noise.

16

INCLUDES NOISE OF VGA
f = 1MHz

14

R

= 75Ω

12

R

R

IN

R

FB

IN

R

FB

= 14.7kΩ

= ∞

R

10

8

6

4

NOISE FIGURE (dB)

2

SIMULATION

0

10 100 1k

Figure 56. Simulated Noise Figure vs. R

Various Fixed Va lues of R

IN

R

FB

= 100Ω

= 500Ω

(Ω)

S

, Actively Matched

IN

= 375Ω

VGA

As seen in Figure 54, the basic architecture, an X-AMPTM,
consists of a ladder attenuator, followed by a fixed-gain
amplifier with selectable input stages. Earlier examples of this
architecture are to be found in the AD60x series, AD8331/
AD8332, and AD8367 VGAs. Through a proprietary, tempera­ture-compensated interpolator design, the bias currents to the
input g
(decreasing attenuation) resulting in increasing gain.

The HILO (HL12 and HL34) gain pins select one of two output
amplifier networks consisting of the feedback resistors, amplifier
stages, and buffers.

stages are continuously steered from right to left

m

from 50 Ω, to

IN

= 50 Ω is slightly

IN

RIN = 50Ω

= 250Ω

R

FB

R

= 200Ω

IN

= 1kΩ

R

FB

for

S

= ∞. As

FB

04976-066

Optimizing the System Dynamic Range

The VGA output gain switch of 8 dB (×2.5) optimizes the VGA
noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC
input voltage of 1 V p-p.

At low gain the ADC SNR should limit the system noise per­formance, while at high gains the noise is defined by the source
and preamplifier. The maximum voltage swing is bounded by
the full-scale peak-to-peak ADC input voltage (typically 1 V p-p
to 2 V p-p). The noise performance is optimized by adjusting
the noise floor of the VGA according to the ADC resolution.
The SNR of a 12-bit converter is theoretically 12 dB better than
a 10-bit; however, approximately 8 dB is typical in practice,
accounting for the 8 dB gain option of the AD8335. The IRN
and the power consumption of the VGA are unaffected by
either gain setting; therefore, only the output referred noise
(ORN) changes (by 8 dB) without affecting any other
parameters.

Attenuator

The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB – 6.02 dB per tap. The effective input
resistance per side is 320

Ω nominally for a total differential

resistance of 640 Ω. The common-mode voltage of the attenuator
and the VGA is controlled by an amplifier that uses the same
midsupply voltage derived in the preamplifier, permitting dc
coupling of the PrA to the VGA without introducing large
offsets due to common-mode differences. However, when dc
coupling between the PrA and VGA, any offset from the PrA
are amplified as the gain is increased, producing an exponentially
increasing VGA output offset. When the PrA and the VGA are
ac-coupled, the output offset is unchanged with changes in gain
(see Figure 15). As a result, ac coupling is recommended for
most applications. As can be seen from Figure 54, Pins VCMx
connect to the respective midpoints on each channel and are
used to ac decouple the common-mode node at high frequencies.
It is very important that at least a 0.1 µF capacitor be used, with
better decoupling at higher frequencies when another smaller
capacitor (10 nF) is connected in parallel. The internal +1 buffer
provides correct common-mode bias levels and any dynamic
currents have to be absorbed by the external decoupling
capacitors.

Rev. 0 | Page 18 of 24

V

V

Gain Control

The gain control interface has two inputs, V
and VSLP (Pins SLxx). The slope input is intended only as a
decoupling pin, and the only guaranteed gain slope is the
20 dB/V default. However, if a voltage is applied to the VSLP
inputs, the gain slope can be increased by reducing the slope
voltage. For example, if a voltage of 1.67 V is applied to Pins SLxx,
the gain slope changes to 30 dB/V. Use Equation 4 to calculate
the gain slope.

dB/V20V5.2 ×

VSLP

=

Slope

varies the gain of the VGA through the interpolator by

V

GAIN

(4)

selecting the appropriate input stages connected to the input
attenuator. The nominal V

range for 20 dB/V is 0 V to 3 V,

GAIN

with the best gain-linearity from approximately 0.5 V to 2.5 V,
where the error is typically less than ±0.2 dB. For V
above 2.5 V and less than 0.5 V, the error increases (see Figure 4).
The value of the V

voltage can be increased to that of the

GAIN

supply voltage, without gain foldover.

Each channel has separate gain control pins that can be
connected to a common voltage-source such as found in most
ultrasound applications. For control of individual channels,
connect the appropriate gain control signal to each channel.

Output Stage

Duplicate output stages of the VGA provide an 8 dB (×2.5) gain
switch. The gain switch is intended to optimize the output noise
floor for either a 10-bit or 12-bit ADC. The VGA gain is 20 dB
(×10) in LO gain mode and 28 dB (×25) in HI gain mode. The
logic setting of the HILO (Pins HLxx) selects between output
amplifiers including the gain resistors and feedback buffers.

(Pins VGNx)

GAIN

GAIN

voltages

AD8335

dynamic range, and the common-mode level is maintained
automatically at half the supply voltage for maximum signal
swing. The differential signal has the added benefit of suppress­ing the even order harmonics.

The output amplifier is designed to drive a nominal differential
load of 500 Ω or greater; the signal swing can be as large as
5 V p-p differential before clipping occurs. However, that distor­tion increases before reaching the clipping level. Distortion is
shown in Figure 25 through Figure 34 for typical values of
1 V p-p or 2 V p-p (full-scale inputs for many ADCs). The
output is ac-coupled to a differential anti-alias filter driving a
differential ADC. Most modern ADCs have differential inputs
and achieve optimum performance when driven differentially.
For more information, see the Applications section.

VGA Noise

As with all X-AMPs, the output noise of the VGA is constant
with gain. This causes the input referred noise to increase as the
gain is decreased. This characteristic is desirable in receiver
applications where wide dynamic range input signals are com­pressed with a fixed ceiling and noise floor into an ADC. The
VGA output noise is approximately 33 nV/√Hz in LO gain
mode and 2.5 times higher than this, 83 nV/√Hz, in HI gain
mode. As the gain increases, the noise of the preamplifier prevails
and, at the maximum VGA gain, the output noise is approxi­mately 90 nV/√Hz and 225 nV/√Hz for LO and HI gain modes,
respectively.

The output SNR is determined by the noise floor and the largest
signal level, typically limited by the FS of the ADC. Modulation
noise, essentially the noise introduced by the gain control input,
can be troublesome. Normally one tends to look at the main
amplifier signal path for noise, but a VGA is really a multiplier
with the following function

100 MHz bandwidth is maintained between the amplifiers by
changing the compensation capacitance as the gain switches gain
settings. Power consumption is the same for either level of gain.

In certain applications, power consumption can be reduced by
lowering the supply voltage as much as possible; however, the
output dynamic range is affected by the more limited swing. The
fully differential signal path of the AD8335 restores 6 dB of

Rev. 0 | Page 19 of 24

V×= (4)

OUT

where V

GAIN

(bias) and V

REF

IN

V

REF

(gain control interface) are both

GAIN

noise contributors under certain conditions. It is therefore
important that the gain control signals be kept clean, especially
at higher gain control slopes.

AD8335

APPLICATIONS

ULTRASOUND

The primary application for the AD8335 is medical ultrasound.
Figure 57 shows a simplified block diagram of an ultrasound
system. The most critical function of an ultrasound system is
the time gain control (TGC) compensation for physiological
signal attenuation. Because the attenuation of ultrasound signals
is exponential with respect to distance (time), a linear-in-dB
VGA is the optimal solution.

Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low
power, and differential drive to an ADC. Because ultrasound
machines use beamforming techniques requiring large binary
weighted numbers (for example, 32 to 512) of channels, the
lowest power at the lowest possible noise is of key importance.

TX HV AMPs

Most modern machines use digital beamforming. In this
technique, the signal is converted to digital format immediately
following the TGC amplifier; beamforming is done digitally.

Typical ADC resolution in general purpose machines is 10 bits
with sampling rates greater than 40 MSPS, while high end
systems use 12 bits.

Power consumption and low cost are of primary importance in
low-end and portable ultrasound machines, and the AD8335 is
designed for these criteria.

For additional information regarding ultrasound systems, refer
to “How Ultrasound System Considerations Influence Front­End Component Choice”, Analog Dialogue, Vol. 36, No. 3,
May–July 2003.

http://www.analog.com/library/analogDialogue/archives/36-

(
03/ultrasound/index.html)

BEAMFORMER

CENTRAL CONTROL

MULTICHANNEL
TGC USES MANY VGAs

Rx BEAMFORMER
(B AND F MODES)

IMAGE AND

MOTION

PROCESSING

(B MODE)

DISPLAY

COLOR

DOPPLER (PW)

PROCESSING

(F MODE)

04976-053

TRANSDUCER

ARRAY

128, 256 ETC.

ELEMENTS

HV

MUX/

DEMUX

BIDIRECTIONAL

CABLE

T/R

SWITCHES

TIME GAIN COMPENSATION

TGC

TX BEAMFORMER

AD8335

LNAs

CW (ANALOG)

BEAMFORMER

AUDIO

OUTPUT

VGAs

SPECTRAL

DOPPLER

PROCESSING

MODE

Figure 57. Simplified Ultrasound System Block Diagram

Rev. 0 | Page 20 of 24

AD8335

k

×

BASIC CONNECTIONS

Figure 58 shows the basic connections for the AD8335. Input
signals enter from the left and output signals exit from the right,
providing straight-line signal paths. Of course, a device with
four differential VGAs such as this requires a multilayer printed
circuit board. Power supply isolation is shown for the preamps,
and for the VGA sections. If components are mounted to both
sides of the board, those in the signal path should be located on
the top, with power-supply decoupling components on the
wiring side.

PREAMP CONNECTIONS

To configure the AD8335 for input matching a feedback resistor

) is ac-coupled between Pin PONx and Pin PIPx. AC coupling

(R

FB

accommodates dissimilar common-mode voltages at the input
and output ports. For values of R

is simply 5 × R

R

FB

resistor (or R

), along with the exact value and nearest standard

IN

. Table 6 lists a few larger values of source

SOURCE

1% feedback resistor. For values other those than listed in Table 6,

can be calculated using Equation 5. For values larger than

R

FB

1 kΩ, it may be advantageous to simply remove R

between 50 Ω and 200 Ω,

SOURCE

FB

.

Table 6. Feedback Resistor Values for Various Input Resistances

RIN (Ω) Exact RFB Value (Ω) Nearest Standard 1% Value (Ω)

200 1014 1.02k
500 2588 2.61k
1000 5365 5.36k

5

R

)(

R

FB

IN

=Ω (5)

R

IN

1

−

7.14

Rev. 0 | Page 21 of 24

AD8335

PIP2

*SEE TEXT

+5V

PIP3

0.1µF

RSH2

Ω

49.9
C

2

SH

22pF

120nH FB

0.1µF

0.1µF

R

49.9Ω
C

22pF

SH

SH

PIP1

0.1µF

0.1µF

R
249Ω

3

3

PIP4

0.1µF
R

249Ω

FB

+5V

0.1µF

1

R

SH

49.9Ω

1

C

SH

22pF

2

FB

VPP

0.1µF

VPP

0.1µF

3

VPP

0.1µF

0.1µF

0.1µF

0.1µF

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

R

SH

49.9Ω

PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3
VIP3
POP3
PON3
VPP3
PIP3
PMD3

0.1

4

0.1µF

64

µF

PMD1

PMD4

C

SH

22pF

63

4

0.1µF

PIP1

PIP4

0.1µF

VPP

VPP

R

FB

249Ω

VPP1

VPP4

R

FB

249Ω

1

0.1µF

0.1µF

5962 61 60

VIP1

POP1

PON1

POP4

0.1µF

0.1µF

VIP4

23

PON4

20

4

VGN1

57

56 55 5154 53 5258

VIN1

COM1

AD8335

VIN4

COM4

24 29

Figure 58. Basic Connections for R

1nF*

VGN1

VGN4

1nF*

= 50 Ω

IN

0.1µF

VCM1

VCM4

0.1µF

VGN3VGN4

VGN2

1nF*

VGN2

VGN3

1nF*

SL12

H

0.1µF

+5V

EN12

VCM2

VCM3

EN34

2825 26 2717 18 19 21 22

0.1µF

0.1µF
L

HL12

HL34

0.1µF

0.1µF
VOH1

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

VPV

0.1µF

0.1µF

+5V

VOL1

+5V
120nH FB

0.1µF

VOH3
VOL3

VOH4

L

VOL2
VOH2

VOL4

04976-056

48
47
46
45

VPV

44
43
42
41
40
39
38
37
36
35
34
33

H

49

50

SL12

SP12

GND1

VOH1

VOL1

VPV1
VPV2
VOL2

VOH2
GND2
GND3
VOH3

VOL3
VPV3
VPV4
VOL4

VOH4
GND4

SP34

SL34

30

31 32

+5V

SL34

The preamp PMD pins must be capacitively coupled to ground.
Although the preamplifier is a differential design, the PMD pins
are the internal input bias nodes and are made available for
bypassing only. These pins may not be used as signal inputs.

The PIPx inputs must be capacitively coupled from the signal
source because they have a nominal dc level of more than half
the supply voltage. AC coupling capacitors throughout the
circuit should be as large as possible for the application. Although

0.1 µF capacitors are shown in Figure 58 (and used in most
positions in the evaluation board), values of these capacitors
should be determined by the application. Capacitors used for
coupling PMDx and PIPx pins should be the same value.

Rev. 0 | Page 22 of 24

When synthesizing low values of R

, the bandwidth of the

IN

preamplifier produces some peaking at the high end of the
frequency response. The optional series R

x/CSHx network

SH

shown in Figure 58 flattens the response (see Figure 55). With a
50 Ω source, the resistor and capacitor values should be 49.9 Ω
and 22 pF. For R

values greater than 100 Ω, the network is not

S

needed. The circuit is stable in either scenario.

The starred capacitors in Figure 58 (*) on the VGNx pins may
be removed when faster gain control signals are required.

T

R

INPUT OVERDRIVE

Excellent overload behavior is of primary importance in ultra­sound. Both the preamplifier and VGA have built-in overdrive
protection and quickly recover after an overload event.

Input Overload Protection

As with any amplifier, voltage clamping prior to the inputs is
highly recommended if the application is subject to high
transient voltages.

A block diagram of a simplified ultrasound transducer interface
is shown in Figure 59. A common transducer element serves the
dual functions of transmit and receive of ultrasound energy.
During the transmit phase, high voltage pulses are applied to
the ceramic elements. A typical T/R (transmit/receive) switch
may consist of four high voltage diodes in a bridge configuration.
Although they ideally block transmit pulses from the sensitive
receiver input, diode characteristics are not ideal, and resulting
leakage transients impinging on the PIPx inputs can be
problematic.

Since ultrasound is a pulse system, and time-of-flight is used to
determine depth, quick recovery from input overloads is essential.
Overload can occur in the preamp and the VGA. Immediately
following a transmit pulse, the typical VGA gains are low, and
the PrA is subject to overload from T/R switch leakage. With
increasing gain, the VGA can become overloaded from strong
echoes that occur with near field echoes and acoustically dense
materials, such as bone.

Figure 59 illustrates an external overload protection scheme. A
pair of back-to-back Schottky diodes is installed prior to installing
the ac-coupling capacitors. Although the BAS40 is shown, many
types are available and merit investigation by the user. With such
diodes, clamping levels of ±0.5 V or less greatly enhance the
system overload performance.

Rs

RANSDUCE

+HV

OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP

3

2

1

–HV

BAS40-04

Figure 59. Input Overload Protection

PIPx

PMDx

RFB

PrA

18dB

PONx

POPx

04976-057

AD8335

LOGIC INPUTS

The enable Pins EN12 and EN34, the preamp shutdown Pins SP12
and SP34, and the HILO Pins HL12 and HL34 are all logic inputs
of the AD8335. The enable inputs turn on and off each of the
corresponding pairs of channels; the preamp shutdown pins do
the same for the preamplifiers only; inputs HL12 and HL34 set
the HILO gain for Channels 1 and 2, and Channels 3 and 4,
respectively.

Shutting down the preamplifiers allows use of the VGAs alone,
while reducing power consumption. The VGAs cannot be shut
down independently. The SPxx (shutdown preamp) pins are
logic high; thus the pins are grounded to enable the preamplifiers.

The pins can be enabled by connecting to the supply or to
ground for fixed enable or disable, or to the output of a logic
device. Be sure to check the data sheet of the device for voltage
and current requirements.

COMMON-MODE PINS

The common-mode Pins VCMx are provided for bypassing the
internal common-mode reference for each channel to ground.
They require a capacitor at each of the four pins and can neither
be connected together nor driven by an external source.

DRIVING ADCs

The AD8335 VGA is designed to drive 10-bit and 12-bit ADCs
with minimal extra components. Because the AD8335 is a single
supply 5 V part and many of the newest ADCs operate from a
3 V supply, dissimilar common-mode voltages exist between the
VGA output and the ADC input. This level shift is most easily
accommodated by ac coupling, especially if the signal is filtered,
as is the case in most ultrasound and communications
applications.

When an anti-aliasing filter (AAF) is called for, it is advantageous
to implement a differential configuration. A fully differential
AAF requires approximately 1.5 times the number of components
than a single-ended filter, because the components that in the
single-ended case are tied to ground, now connect across the
differential signal path. Although the series components double,
the component count for the differential filter is more economical
when compared to simply building a pair of single-ended filters
requiring twice as many components.

Rev. 0 | Page 23 of 24

AD8335

OUTLINE DIMENSIONS

BSC SQ

PIN 1
INDICATOR

9.00

0.60 MAX

49

48

0.60 MAX

0.30

0.25

0.18

64

1

PIN 1
INDICATOR

4.85
*

4.70 SQ

4.55

16

17

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION

8.75

BSC SQ

0.20 REF

0.45

0.40

0.35

0.05 MAX

0.02 NOM

33

32

EXPOSED PAD

(BOTTOM VIEW)

7.50
REF

Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-64)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8335ACPZ1 −40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-64
AD8335ACPZ-REEL1 −40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-64
AD8335ACPZ-REEL71 −40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-64
AD8335-EVAL Evaluation Board with AD8335ACP

1

Z = Pb-free part.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04976–0–9/04(0)

Rev. 0 | Page 24 of 24