ANALOG DEVICES AD8333 Service Manual

DC to 50 MHz, Dual I/Q Demodulator and

FEATURES

Dual integrated I/Q demodulator
16 phase select on each output (22.5° per step)
Quadrature demodulation accuracy

Phase accuracy: ±0.1°
Amplitude balance: ±0.05 dB

Bandwidth

4 LO: 100 kHz to 200 MHz
RF: dc to 50 MHz

Baseband: determined by external filtering
Output dynamic range: 159 dB/Hz
LO drive > 0 dBm (50 Ω); 4 LO > 1 MHz
Supply: ±5 V
Power consumption: 190 mW/channel (380 mW total)
Power down

APPLICATIONS

Medical imaging (CW ultrasound beamforming)
Phased array systems (radar and adaptive antennas)
Communication receivers

CH1

RF

ENABLE

LOC

OSC

RESET

CH2

RF

Phase Shifter

FUNCTIONAL BLOCK DIAGRAM

CH1

PHASE

SELECT

+

–

AD8333

÷4

+

–

0°

90°

90°

0°

Figure 1.

Φ

Φ

Φ

Φ

CH2

PHASE

SELECT

AD8333

I1

Q1

Q2

I2

05543-001

GENERAL DESCRIPTION

The AD8333 is a dual-phase shifter and I/Q demodulator that
enables coherent summing and phase alignment of multiple
analog data channels. It is the first solid-state device suitable for
beamformer circuits, such as those used in high performance
medical ultrasound equipment featuring CW Doppler. The RF
inputs interface directly with the outputs of the dual-channel,
low noise preamplifiers included in the

A divide-by-4 circuit generates the internal 0° and 90° phases
of the local oscillator (LO) that drive the mixers of a pair of
matched I/Q demodulators.

The AD8333 can be applied as a major element in analog
beamformer circuits in medical ultrasound equipment.

The AD8333 features an asynchronous reset pin. When used in
arrays, the reset pin sets all the LO dividers in the same state.
Sixteen discrete phase rotations in 22.5° increments can be
selected independently for each channel. For example, if CH1 is
used as a reference and the RF signal applied to CH2 has an I/Q
phase lead of 45°, CH2 can be phase aligned with CH1 by
choosing the correct code.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

AD8332.

Phase shift is defined by the output of one channel relative to
another. For example, if the code of Channel 1 is adjusted to
0000 and that of Channel 2 to 0001 and the same signal is
applied to both RF inputs, the output of Channel 2 leads that
of Channel 1 by 22.5°.

The I and Q outputs are provided as currents to facilitate
summation. The summed current outputs are converted to
voltages by a high dynamic-range, current-to-voltage (I-V)
converter, such as the

AD8021, configured as a transimpedance

amplifier. The resultant signal is then applied to a high resolution
ADC, such as the

AD7665 (16 bit/570 kSPS).

The two I/Q demodulators can be used independently in other
nonbeamforming applications. In that case, a transimpedance
amplifier is needed for each of the I and Q outputs, four in total
for the dual I/Q demodulator.

The dynamic range is 161 dB/Hz at each I and Q output, but the
following transimpedance amplifier is an important element in
maintaining the overall dynamic range, and attention needs to
be paid to optimal component selection and design.

The AD8333 is available in a 32-lead LFCSP (5 mm × 5 mm)
package for the industrial temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2007 Analog Devices, Inc. All rights reserved.

AD8333

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Equivalent Input Circuits ................................................................7

Typical Performance Characteristics............................................. 8

Test Circ uit s .....................................................................................14

Theory of Operation ...................................................................... 17

Quadrature Generation............................................................. 17

I/Q Demodulator and Phase Shifter........................................ 17

Dynamic Range and Noise........................................................ 18

Summation of Multiple Channels (Analog Beamforming).. 19

Phase Compensation and Analog Beamforming................... 19

Channel Summing ..................................................................... 20

Dynamic Range Inflation.......................................................... 22

Disabling the Current Mirror and Decreasing Noise............ 22

Applications..................................................................................... 24

Logic Inputs and Interfaces....................................................... 24

Reset Input .................................................................................. 24

Connecting to the LNA of the AD8331/

AD8332/AD8334/AD8335 VGAs............................................ 24

LO Input ...................................................................................... 25

Evaluation Board ........................................................................ 25

Outline Dimensions .......................................................................27

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/07—Rev. A to Rev. B

Changes to Features and Figure 1................................................... 1

Changes to Table 1............................................................................ 3

Changes to Figure 41 to Figure 43................................................ 14

Changes to Figure 44 to Figure 47................................................ 15

Changes to Figure 48 to Figure 51................................................ 16

Changes to Figure 55...................................................................... 20

Changes to Evaluation Board Section.......................................... 25

Changes to Ordering Guide.......................................................... 27

5/06—Rev. 0 to Rev. A

Changes to Figure 62...................................................................... 26

10/05—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD8333

SPECIFICATIONS

VS = ±5 V, TA = 25°C, 4 fLO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm, single-ended, sine wave; per channel performance, dBm
(50 Ω), unless otherwise noted (see

Table 1.

Parameter Conditions Min Typ Max Unit

OPERATING CONDITIONS

LO Frequency Range
Square wave 0.01 200 MHz
Sine wave, see Figure 22 2 200 MHz
RF Frequency Range Mixing DC 50 MHz
Baseband Bandwidth Limited by external filtering DC 50 MHz
LO Input Level See Figure 22 0 13 dBm
V

(VS) ±4.5 ±5 ±6 V

SUPPLY

Temperature Range −40 +85 °C

DEMODULATOR PERFORMANCE

RF Differential Input Impedance 6.7||6.5 kΩ||pF
LO Differential Input Capacitance 0.6 pF
Transconductance

All phases 2.17 mS
Dynamic Range IP1dB, input referred noise (dBm) 159 dB/Hz
Maximum RF Input Swing Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN 2.8 V p-p
Peak Output Current (No Filtering) 0° phase shift ±4.7 mA
45° phase shift ±6.6 mA
Input P1dB
Ref = 1 V
Third-Order Intermodulation (IM3) f

Equal Input Levels Baseband tones: −7 dBm @ 8 kHz and 13 kHz −75 dBc

Unequal Input Levels Baseband tones: −1 dBm @ 8 kHz and −31 dBm @ 13 kHz −77 dBc
Third-Order Input Intercept (IP3)
LO Leakage

Conversion Gain All codes, see Figure 41 4.7 dB
Input Referred Noise Output noise/conversion gain, see Figure 41 10 nV/√Hz
Output Current Noise Output noise ÷ 787 Ω 22 pA/√Hz
Noise Figure With AD8332 LNA
R
R
R
Bias Current Pin 4LOP and Pin 4LON −3 μA
Pin RFxP and Pin RFxN −70 μA
LO Common-Mode Voltage Range Pin 4LOP and Pin 4LON (each pin) 0.2 3.8 V
RF Common-Mode Voltage

Output Compliance Range Pin IxPO and Pin QxPO −1.5 +0.7 V

Figure 41).

4× internal LO at Pin 4LOP and Pin 4LON

Demodulated I

, each Ix or Qx output after low-pass

OUT/VIN

filtering measured from RF inputs

Ref = 50 Ω 14.5 dBm

RMS

= 5.010 MHz, f

RF1

Same conditions as IM3 30 dBm

= 5.015 MHz, fLO = 5.023 MHz

RF2

Measured at RF inputs, worst phase, measured into 50 Ω

1.5 dBV

<−97 dBm

(limited by measurement)
Measured at baseband outputs, worst phase, 8021 disabled,

−60 dBm

measured into 50 Ω

= 50 Ω, RFB = ∞ 7.8 dB

S

= 50 Ω, RFB = 1.1 kΩ 9.0 dB

S

= 50 Ω, RFB = 274 Ω 11.0 dB

S

For maximum differential swing; Pin RFxP and Pin RFxN

2.5 V

(dc-coupled to AD8332 LNA output)

Rev. B | Page 3 of 28

AD8333

Parameter Conditions Min Typ Max Unit

PHASE ROTATION PERFORMANCE One CH is reference, other is stepped

Phase Increment 16 phase steps per channel 22.5 Degrees
Quadrature Phase Error I1 to Q1 and I2 to Q2, 1σ −2 ±0.1 +2 Degrees
I/Q Amplitude Imbalance I1 to Q1 and I2 to Q2, 1σ ±0.05 dB
Channel-to-Channel Matching Phase match I1/I2 and Q1/Q2; −40°C < TA < 85°C ±1 Degrees
Amplitude match I1/I2 and Q1/Q2; −40°C < TA < 85°C ±0.25 dB

LOGIC INTERFACES

Logic Level High Pin PHxx, Pin RSET, and Pin ENBL 1.7 5 V
Logic Level Low Pin PHxx, Pin RSET, and Pin ENBL 0 1.3 V

Bias Current

Pin PHxx and Pin ENBL Logic high 10 40 90 μA

Logic low −30 −7 +10 μA

Pin RSET Logic high 50 120 180 μA

Logic low −70 −20 0 μA
Input Resistance Pin PHxx and Pin ENBL 60 kΩ
Pin RSET 20 kΩ
Reset Hold Time

Minimum Reset Pulse Width 300 ns
Reset Response Time See Figure 35 300 ns
Phase Response Time See Figure 38 5 μs
Enable Response Time See Figure 34 300 ns

POWER SUPPLY Pin VPOS and Pin VNEG

Supply Voltage ±4.5 ±5 ±6 V
Quiescent Current, All Phase Bits = 0 @ 25°C

Pin VPOS 38 44 51 mA

Pin VNEG −24 −20 −16 mA
Over Temperature −40°C < TA < 85°C
Pin VPOS, all phase bits = 0 40 54 mA
Pin VNEG −24 −19 mA
Quiescent Power Per channel, all phase bits = 0 170 mW
Per channel, any 0 or 1 combination of phase bits 190 mW
Disable Current All channels disabled
Pin VPOS 1.0 1.25 1.5 mA
Pin VNEG −300 −200 −100 μA
PSRR
Pin VPOS to Ix/Qx outputs (measured @ AD8021 output) −81 dB
Pin VNEG to Ix/Qx outputs (measured @ AD8021 output) −75 dB

Reset is asynchronous; clock disabled when RSET goes HI
until 300 ns after RSET goes LO; see

Figure 58

300 ns

Rev. B | Page 4 of 28

AD8333

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltages

Supply Voltage, V
RF Pins Input VS, GND
LO Inputs VS, GND
Code Select Inputs, V VS, GND

Thermal Data—4-Layer JEDEC Board No Air

Flow (Exposed Pad Soldered to PCB)
θ

JA

θ

JB

θ

JC

Ψ

JT

Ψ

JB

Maximum Junction Temperature 150°C
Maximum Power Dissipation

(Exposed Pad Soldered to PC Board)

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

S

6 V

41.0°C/W

23.6°C/W

4.4°C/W

0.4°C/W

22.4°C/W

1.5 W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 5 of 28

AD8333

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

P

VPOS

PH11

32

RF1N

VPOS29RF1

PH10

31

30

ENBL25I1NO

28

27

26

PH12
PH13

COMM

4LOP

4LON

LODC

PH23
PH22

1

2

3

4

5

6

7

8

PIN 1
INDICATOR

AD8333

TOP VIEW

(Not to Scale)

9

11

0

PH2110PH2

VPOS

12

13

14

RF2P

RF2N

VPOS

24

I1PO

23

Q1PO

22

Q1NO

21

VNEG

20

COMM

19

Q2NO

18

Q2PO

17

I2PO

15

16

I2NO

RSET

05543-002

Figure 2. 32-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2,
7, 8

PH12, PH13
PH23, PH22

Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0° to 90°, 90° to180°,
180° to 270°, 270° to 360° (see Table 4 ). Logic threshold is at about 1.5 V and therefore can be driven by

3 V CMOS logic (see

Figure 3).
3, 20 COMM Ground. These two pins are internally tied together.
4, 5 4LOP, 4LON

LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum
performance, these inputs should be driven differentially with a signal level that is not less than what is
shown in
correctly (see

Figure 22. Bias current is only −3 μA. Single-ended drive is also possible if the inputs are biased

Figure 4).
6 LODC Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground (see Figure 5).
9, 10,

31, 32
11, 14,

27, 30

PH21, PH20
PH10, PH11

VPOS

Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0°, 22.5°, 45°, 67.5°
(see

Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3).

Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set
of supply decoupling components for all four pins should be sufficient.

12, 13,
28, 29

15 RSET

16, 19,
22, 25

17, 18,
23, 24

21 VNEG

RF2P, RF2N
RF1N, RF1P

I2NO, Q2NO
Q1NO, I1NO

I2PO, Q2PO
Q1PO, I1PO

RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to
the output pins of the
differential swing is 2.5 V if ±5 V supplies are used (see

AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input

Figure 6).

Reset for Divide-by-4 in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by
3 V CMOS logic (see

Figure 3).

Negative I/Q Outputs. These outputs are not connected for normal usage but can be used for filtering if needed.
Together with the positive I/Q outputs, they allow bypassing the internal current mirror if a lower noise output
circuit is available; VNEG needs to be tied to GND to disable the current mirror (see

Figure 7).

Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via
a transimpedance amplifier. Multiple outputs can be summed together by simply connecting them together.
The bias voltage should be set to 0 V or less by the transimpedance amplifier (see

Figure 7).

Negative Supply. This pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the pin and ground.

26 ENBL Chip Enable. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3).

Rev. B | Page 6 of 28

AD8333

4

EQUIVALENT INPUT CIRCUITS

VPOS

VPOS

4LOP

LON

PHxx
ENBL
RSET

COMM

Figure 3. Logic Inputs

VPOS

COMM

Figure 4. Local Oscillator Inputs

VPOS

LOGIC

INTERFACE

05543-003

05543-004

RFxP

RFxN

COMM

05543-006

Figure 6. RF Inputs

COMM

IxNO
QxNO

IxPO
QxPO

VNEG

05543-007

Figure 7. Output Drivers

LODC

COMM

Figure 5. LO Decoupling Pin

05543-005

Rev. B | Page 7 of 28

AD8333

TYPICAL PERFORMANCE CHARACTERISTICS

VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm (50 Ω); single-ended sine wave;
per channel performance, differential voltages, dBm (50 Ω), phase select code = 0000, unless otherwise noted (see

1.5

1.0

0.5

0

–0.5

IMAGINARY (Normalized)

–1.0

–1.5

–2.0

f = 1MHz

Q

I

CODE 1000

CODE 1100

–1.5 –1.0 –0.5 0 0.5 1.0 1.5

REAL (Normalized)

CODE 0100

CODE 0011

CODE 0010

CODE 0001

CODE 0000

2.0

Figure 8. Normalized Vector Plot of Phase, CH2 with Respect to CH1;

CH1 Is Fixed at 0°, CH2 Stepped 22.5°/Step, All Codes Displayed

360

1MHz

315

5MHz

270

05543-008

2

f = 5MHz

1

0

–1

–2

2

f = 1MHz

1

PHASE ERROR (Degrees)

0

–1

–2

0000

0010 0100 0110 1000 1010 1100 1110

CODE (Binary)

Figure 11. Phase Error of CH2 with Respect to CH1 vs.

Code at 1 MHz and 5 MHz

500mV

Figure 41).

1111

05543-011

225

180

135

PHASE (Degrees)

90

45

0

0000

0010 0100 0110 1000 1010 1100 1110

CODE (Binary)

1111

Figure 9. Phase of CH2 with Respect to CH1 vs. Code at 1 MHz and 5 MHz

1.0
f = 5MHz

0.5

0

–0.5

–1.0

1.0
f = 1MHz

0.5

AMPLITUDE ERROR (dB)

0

–0.5

–1.0

0000

0010 0100 0110 1000 1010 1100 1110

CODE (Binary)

1111

Figure 10. Amplitude Error of CH2 with Respect to CH1 vs.

Code at 1 MHz and 5 MHz

05543-009

05543-010

20µs

05543-012

Figure 12. I or Q Output of CH2 with Respect to CH1, First Quadrant Shown

7

CHANNEL 1, I OUTPUT SHOWN

6

CODE 0000
CODE 0001
CODE 0010
CODE 0011

5

GAIN (dB)

4

3

1M

RF FREQUENCY (Hz)

10M

50M

05543-013

Figure 13. Conversion Gain vs. RF Frequency, First Quadrant,

Baseband Frequency = 10 kHz

Rev. B | Page 8 of 28

AD8333

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

QUADRATURE PHASE ERROR (Degrees)

–2.0

1M

10M

RF FREQUENCY (Hz)

100M

Figure 14. Representative Range of Quadrature Phase Errors vs.

RF Frequency, CH1 or CH2, All Codes

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

QUADRATURE PHASE ERROR (Degrees)

–2.0

100

1k 10k

BASEBAND FREQUENCY (Hz)

100k

Figure 15. Range of Quadrature Phase Error vs. Baseband Frequency,

Figure 43)

10M

50M

I/Q AMPLITUDE IMBALANCE (dB)

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

CH1 and CH2 ( see

0

1M

RF FREQUENCY (Hz)

Figure 16. Representative Range of Amplitude Imbalance of I/Q vs.

RF Frequency, CH1 or CH2, All Codes

05543-014

05543-015

05543-016

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

I/Q AMPLITUDE IMBALANCE (dB)

–0.4

–0.5

100

1k 10k

BASEBAND FREQUENCY (Hz)

100k

Figure 17. Representative Range of I/Q Amplitude Imbalance vs.

10M

Figure 43)

fBB = 10kHz
I2/I1 DISPLAYED

50M

Baseband Frequency, CH1 and CH2 ( see

2.0
CODE 0000

–40°C

1.5

+25°C
+85°C

1.0

CODE 0001
–40°C
+25°C

0.5

+85°C

0

CODE 0010

–0.5

–40°C
+25°C
+85°C

AMPLITUDE ERROR (dB)

–1.0

CODE 0011
–40°C

–1.5

+25°C
+85°C

–2.0

1M

RF FREQUENC Y (Hz)

Figure 18. Typical I2/I1 or Q2/Q1 Amplitude Match vs. RF Frequency

First Quadrant, at Three Temperatures

PHASE ERROR (Degrees)

8

CODE 0000
–40°C
+25°C

6

+85°C

CODE 0001
–40°C

4

+25°C
+85°C

2

0

–2

fBB= 10kHz
I2/I1 DISPLAYED

–4

1M

CODE 0010
–40°C
+25°C
+85°C

CODE 0011
–40°C
+25°C
+85°C

RF FREQUE NCY (Hz)

10M 50M

Figure 19. I2/I1 or Q2/Q1 Phase Error vs. RF Frequency,
Baseband Frequency = 10 kHz, at Three Temperatures

05543-017

05543-018

05543-043

Rev. B | Page 9 of 28