ANALOG DEVICES AD8332 Service Manual

Ultralow Noise VGAs with

VINV

V

www.BDTIC.com/ADI

Preamplifier and Programmable R

FEATURES

Ultralow noise preamplifier (preamp)

Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz

3 dB bandwidth

AD8331: 120 MHz
AD8332, AD8334: 100 MHz

Low power

AD8331: 125 mW/channel
AD8332, AD8334: 145 mW/channel

Wide gain range with programmable postamp

−4.5 dB to +43.5 dB in LO gain mode

+7.5 dB to +55.5 dB in HI gain mode
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-bit/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
AD8332 and AD8334 available in lead frame chip scale package

APPLICATIONS

Ultrasound and sonar time-gain controls
High performance automatic gain control (AGC) systems
I/Q signal processing
High speed, dual ADC drivers

GENERAL DESCRIPTION

The AD8331/AD8332/AD8334 are single-, dual-, and quad­channel, ultralow noise linear-in-dB, variable gain amplifiers
(VGAs). Optimized for ultrasound systems, they are usable as a
low noise variable gain element at frequencies up to 120 MHz.

Included in each channel are an ultralow noise preamp (LNA),
a

n X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamp with adjustable output limiting. The LNA gain is 19 dB
with a single-ended input and differential outputs. Using a single
resistor, the LNA input impedance can be adjusted to match a
signal source without compromising noise performance.

The 48 dB gain range of the VGA makes these devices suitable
fo

r a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching.

IN

AD8331/AD8332/AD8334

FUNCTIONAL BLOCK DIAGRAM

INH

LMD

IPLOPLON

LNA

19dB

VCM
BIAS

AD8331/AD8332/AD8334

60

50

40

30

20

GAIN (dB)

10

0

–10

100k 1M 10M 100M 1G

–

48dB

ATTENUATO R

+

VGA BIAS AND

INTERPOLATOR

Figure 1. Signal Path Block Diagram

V

GAIN

V

= 0.8V

GAIN

V

= 0.6V

GAIN

V

= 0.4V

GAIN

V

= 0.2V

GAIN

V

GAIN

FREQUENCY (Hz)

Figure 2. Frequency Response vs. Gain

= 1V

= 0V

V

ENB

CM

MID

3.5dB OR 15.5d B

21dB

GAIN

CONTROL

INTERFACE

GAIN

Differential signal paths result in superb second- and third­order distortion performance and low crosstalk.

The low output-referred noise of the VGA is advantageous in
dr

iving high speed differential ADCs. The gain of the postamp
can be pin selected to 3.5 dB or 15.5 dB to optimize gain range
and output noise for 12-bit or 10-bit converter applications. The
output can be limited to a user-selected clamping level, pre-venting
input overload to a subsequent ADC. An external resistor adjusts
the clamping level.

The operating temperature range is −40°C to +85°C. The
AD8331 is a

vailable in a 20-lead QSOP package, the AD8332 is
available in 28-lead TSSOP and 32-lead LFCSP packages, and
the AD8334 is available in a 64-lead LFCSP package.

PA

CLAMP

HI GAIN

MODE

HILO

VOH

VOL

RCLMP

03199-002

03199-001

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD8331/AD8332/AD8334

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions........................... 8

Typical Performance Characteristics........................................... 12

Test Circuits..................................................................................... 20

Measurement Considerations................................................... 20

Theory of Operation ......................................................................24

Overview...................................................................................... 24

Low Noise Amplifier (LNA) .....................................................25

Variable Gain Amplifier ............................................................ 27

Postamplifier............................................................................... 28

Applications Information.............................................................. 30

LNA—External Components.................................................... 30

Driving ADCs ............................................................................. 32

Overload ......................................................................................32

Optional Input Overload Protection ....................................... 32

Layout, Grounding, and Bypassing.......................................... 33

Multiple Input Matching ...........................................................33

Disabling the LNA...................................................................... 33

Ultrasound TGC Application ...................................................34

High Density Quad Layout....................................................... 34

AD8331 Evaluation board............................................................. 39

General Description................................................................... 39

User-Supplied Optional Components..................................... 39

Measurement Setup.................................................................... 39

Board Layout............................................................................... 39

AD8331 Evaluation Board Schematics.................................... 40

AD8331 Evaluation Board PCB Layers................................... 42

AD8331 Bill of Materials........................................................... 43

AD8332 Evaluation Board ............................................................ 44

General Description................................................................... 44

User-Supplied Optional Components..................................... 44

Measurement Setup.................................................................... 44

Board Layout............................................................................... 44

Evaluation Board Schematics................................................... 45

AD8332 Evaluation Board PCB Layers................................... 47

AD8332 Bill of Materials........................................................... 48

AD8334 Evaluation Board ............................................................ 49

General Description................................................................... 49

Configuring the Input Impedance........................................... 50

Measurement Setup.................................................................... 50

Board Layout............................................................................... 50

Evaluation Board Schematics................................................... 51

AD8334 Evaluation Board PCB Layers................................... 53

AD8334 Bill of Materials........................................................... 54

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 57

Rev. F | Page 2 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

REVISION HISTORY

4/08—Rev. E to Rev. F

Changed R

Changes to Figure 1...........................................................................1

Changes to Table 1, LNA and VGA Characteristics, Output

Offset Voltage, Conditions...............................................................4

Changes to Quiescent Current per Channel and Power Down

Current Parameters...........................................................................6

Changes to Table 2 ............................................................................7

Changes to Table 3, Pin 1 Description ...........................................8

Changes to Table 4, Pin 1 and Pin 28 Descriptions ......................9

Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................9

Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions......10

Changes to Table 6, Pin 61 Description .......................................11

Changes to Typical Performance Characteristics Section,

Default Conditions..........................................................................12

Changes to Figure 25 ......................................................................15

Changes to Figure 39 ......................................................................17

Changes to Figure 55 Through Figure 68 ...................................20

Changes to Theory of Operation, Overview Section .................24

Changes to Low Noise Amplifier Section and Figure 74...........25

Changes to Active Impedance Matching Section, Figure 75,

and Figure 77 ...................................................................................26

Changes to Figure 78 ......................................................................27

Changes to Equation 6, Table 7, Figure 81, and Figure 82.........30

Changes to Figure 83 ......................................................................31

Changes to Figure 88 ......................................................................32

Switched Figure 89 and Figure 90 .................................................33

Changes to Figure 89 ......................................................................33

Changes to Ultrasound TGC Application Section......................34

Incorporated AD8331-EVAL Data Sheet, Rev. A .......................39

Changes to User-Supplied Optional Components Section
a

nd Measurement Setup Section...............................................39

Changes to Figure 95..................................................................39

Changes to Figure 97..................................................................41

dded Figure 98..........................................................................42

A

Incorporated AD8332-EVALZ Data Sheet, Rev. D.....................44

I

ncorporated AD8334-EVAL Data Sheet, Rev. 0 ........................49

Updated Outline Dimensions........................................................55

Changes to Ordering Guide...........................................................57

4/06—Rev. D to Rev. E

A

dded AD8334................................................................... Universal

Changes to Figure 1 and Figure 2....................................................1

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................7

Changes to Figure 7 through Figure 9 and Figure 12.................12

Changes to Figure 13, Figure 14, Figure 16, and Figure 18.......13

FB

to R

Throughout .....................................................4

IZ

Changes to Figure 23 and Figure 24 .............................................14

Changes to Figure 25 through Figure 27......................................15

Changes to Figure 31 and Figure 33 through Figure 36 ............16

Changes to Figure 37 through Figure 42......................................17

Changes to Figure 43, Figure 44, and Figure 48..........................18

Changes to Figure 49, Figure 50, and Figure 54..........................19

Inserted Figure 56 and Figure 57..................................................20

Inserted Figure 58, Figure 59, and Figure 61...............................21

Changes to Figure 60......................................................................21

Inserted Figure 63 and Figure 65..................................................22

Changes to Figure 64......................................................................22

Moved Measurement Considerations Section ............................23

Inserted Figure 67 and Figure 68..................................................23

Inserted Figure 70 and Figure 71..................................................24

Change to Figure 72........................................................................24

Changes to Figure 73 and Low Noise Amplifier Section...........25

Changes to Postamplifier Section .................................................28

Changes to Figure 80......................................................................29

Changes to LNA—External Components Section......................30

Changes to Logic Inputs—ENB, MODE, and HILO Section ...31

Changes to Output Decoupling and Overload Sections............32

Changes to Layout, Grounding, and Bypassing Section............33

Changes to Ultrasound TGC Application Section .....................34

Added High Density Quad Layout Section.................................34

Inserted Figure 94 ...........................................................................38

Updated Outline Dimensions........................................................39

Changes to Ordering Guide...........................................................40

3/06—Rev. C to Rev. D

U

pdated Format .................................................................Universal

Changes to Features and General Description..............................1

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................6

Changes to Ordering Guide...........................................................34

11/03—Rev. B to Rev. C

A

ddition of New Part......................................................... Universal

Changes to Figures............................................................. Universal

Updated Outline Dimensions........................................................32

5/03—Rev. A to Rev. B

E

dits to Ordering Guide.................................................................32

Edits to Ultrasound TGC Application Section ...........................25

Added Figure 71, Figure 72, and Figure 73..................................26

Updated Outline Dimensions........................................................31

2/03—Rev. 0 to Rev. A

dits to Ordering Guide.................................................................32

E

Rev. F | Page 3 of 60

AD8331/AD8332/AD8334

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SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

= ∞, CL = 1 pF, VCM pin floating,

CLMP

Table 1.

Parameter Conditions Min Typ Max Unit

1

LNA CHARACTERISTICS

Gain Single-ended input to differential output 19 dB

Input to output (single-ended) 13 dB

Input Voltage Range AC-coupled ±275 mV

Input Resistance RIZ = 280 Ω 50 Ω
R
R
R
R

= 412 Ω 75 Ω

IZ

= 562 Ω 100 Ω

IZ

= 1.13 kΩ 200 Ω

IZ

= ∞ 6 kΩ

IZ

Input Capacitance 13 pF

Output Impedance Single-ended, either output 5 Ω

−3 dB Small Signal Bandwidth V

= 0.2 V p-p 130 MHz

OUT

Slew Rate 650 V/µs

Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.74 nV/√Hz

Input Current Noise RIZ = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz

Noise Figure f = 10 MHz, LOP output

Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RIZ = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2 V

= 0.5 V p-p, single-ended, f = 10 MHz

OUT

HD2 −56 dBc
HD3 −70 dBc

Output Short-Circuit Current Pin LON, Pin LOP 165 mA
LNA AND VGA CHARACTERISTICS

−3 dB Small Signal Bandwidth V

= 0.2 V p-p

OUT

AD8331 120 MHz
AD8332, AD8334 100 MHz

−3 dB Large Signal Bandwidth V

= 2 V p-p

OUT

AD8331 110 MHz
AD8332, AD8334 90 MHz

Slew Rate

AD8331 LO gain 300 V/µs
HI gain 1200 V/µs
AD8332, AD8334 LO gain 275 V/µs

HI gain 1100 V/µs
Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.82 nV/√Hz
Noise Figure V

= 1.0 V

GAIN

Active Termination Match RS = RIN = 50 Ω, f = 10 MHz, measured 4.15 dB
R

= RIN = 200 Ω, f = 5 MHz, simulated 2.0 dB

S

Unterminated RS = 50 Ω, RIZ = ∞, f = 10 MHz, measured 2.5 dB

R

= 200 Ω, RIZ = ∞, f = 5 MHz, simulated 1.0 dB

S

Output-Referred Noise

AD8331 V
V
AD8332, AD8334 V

V

= 0.5 V, LO gain 48 nV/√Hz

GAIN

= 0.5 V, HI gain 178 nV/√Hz

GAIN

= 0.5 V, LO gain 40 nV/√Hz

GAIN

= 0.5 V, HI gain 150 nV/√Hz

GAIN

Output Impedance, Postamplifier DC to 1 MHz 1 Ω

Rev. F | Page 4 of 60

AD8331/AD8332/AD8334

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Parameter Conditions Min Typ Max Unit

1

Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V

Differential 4.5 V p-p

Output Offset Voltage

AD8331 Differential, V

= 0.5 V −50 ±5 +50 mV

GAIN

Common mode −125 −25 +100 mV
AD8332, AD8334 Differential, 0.05 V ≤ V

≤ 1.0 V −20 ±5 +20 mV

GAIN

Common mode −125 –25 +100 mV
Output Short-Circuit Current 45 mA
Harmonic Distortion V

= 0.5 V, V

GAIN

= 1 V p-p, HI gain

OUT

AD8331

HD2 f = 1 MHz −88 dBc
HD3 −85 dBc
HD2 f = 10 MHz −68 dBc
HD3 −65 dBc

AD8332, AD8334

HD2 f = 1 MHz −82 dBc
HD3 −85 dBc
HD2 f = 10 MHz −62 dBc
HD3 −66 dBc

Input 1 dB Compression Point V

= 0.25 V, V

GAIN

= 1 V p-p, f = 1 MHz to 10 MHz 1 dBm

OUT

Two-Tone Intermodulation Distortion (IMD3)

AD8331 V

V

AD8332, AD8334 V

V

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 1 V p-p, f = 1 MHz −80 dBc

OUT

= 1 V p-p, f = 10 MHz −72 dBc

OUT

= 1 V p-p, f = 1 MHz −78 dBc

OUT

= 1 V p-p, f = 10 MHz −74 dBc

OUT

Output Third-Order Intercept

AD8331 V

V

AD8332, AD8334 V

V

Channel-to-Channel Crosstalk (AD8332, AD8334) V
Overload Recovery V

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns

GAIN

= 1 V p-p, f = 1 MHz 38 dBm

OUT

= 1 V p-p, f = 10 MHz 33 dBm

OUT

= 1 V p-p, f = 1 MHz 35 dBm

OUT

= 1 V p-p, f = 10 MHz 32 dBm

OUT

= 1 V p-p, f = 1 MHz −98 dB

OUT

Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns

ACCURACY

Absolute Gain Error

0.10 V < V

0.95 V < V
Gain Law Conformance
Channel-to-Channel Gain Matching 0.1 V < V

2

3

0.05 V < V

0.1 V < V

< 0.10 V −1 +0.5 +2 dB

GAIN

< 0.95 V −1 ±0.3 +1 dB

GAIN

< 1.0 V −2 −1 +1 dB

GAIN

< 0.95 V ±0.2 dB

GAIN

< 0.95 V ±0.1 dB

GAIN

GAIN CONTROL INTERFACE (Pin GAIN)

Gain Scaling Factor 0.10 V < V

< 0.95 V 48.5 50 51.5 dB/V

GAIN

Gain Range LO gain −4.5 to +43.5 dB

HI gain 7.5 to 55.5 dB

Input Voltage (V

) Range 0 to 1.0 V

GAIN

Input Impedance 10 MΩ
Response Time 48 dB gain change to 90% full scale 500 ns

COMMON-MODE INTERFACE (PIN VCMx)

Input Resistance

4

Current limited to ±1 mA 30 Ω
Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV
Voltage Range V

= 2.0 V p-p 1.5 to 3.5 V

OUT

Rev. F | Page 5 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Parameter Conditions Min Typ Max Unit

ENABLE INTERFACE

1

(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V

Input Resistance Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ

Power-Up Response Time V
V

= 30 mV p-p 300 µs

INH

= 150 mV p-p 4 ms

INH

HILO GAIN RANGE INTERFACE (PIN HILO)

Logic Level to Select HI Gain Range 2.25 5 V

Logic Level to Select LO Gain Range 0 1.0 V

Input Resistance 50 kΩ
OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR

LO GAIN)

Accuracy

HILO = LO R
HILO = HI R

= 2.74 kΩ, V

CLMP

= 2.21 kΩ, V

CLMP

= 1 V p-p (clamped) ±50 mV

OUT

= 1 V p-p (clamped) ±75 mV

OUT

MODE INTERFACE (PIN MODE)

Logic Level for Positive Gain Slope 0 1.0 V

Logic Level for Negative Gain Slope 2.25 5 V

Input Resistance 200 kΩ
POWER SUPPLY (PIN VPS1, PIN VPS2,

PIN VPSV, PIN VPSL, PIN VPOS)

Supply Voltage 4.5 5.0 5.5 V

Quiescent Current per Channel

AD8331 20 25 mA
AD8332 25 27.5 32 mA
AD8334 27 29.5 34

Power Dissipation per Channel No signal

AD8331 125 mW
AD8332, AD8334 138 mW

Power-Down Current VGA and LNA disabled

AD8331 50 240 400 µA
AD8332 50 300 600 µA
AD8334 50 600 1200 µA

LNA Current

AD8331 (ENBL) Each channel 7.5 11 15 mA
AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA

VGA Current

AD8331 (ENBV) 7.5 14 20 mA
AD8332, AD8334 (ENBV) 7.5 17 20 mA

PSRR V

1

All dBm values are referred to 50 Ω.

2

The absolute gain refers to the theoretical gain expression in Equation 1.

3

Best-fit to linear-in-dB curve.

4

The current is limited to ±1 mA typical.

= 0 V, f = 100 kHz −68 dB

GAIN

Rev. F | Page 6 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHx) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V

Power Dissipation

AR Package1 (AD8332) 0.96 W
CP-32 Package (AD8332) 1.97 W
RQ Package1 (AD8331) 0.78 W
CP-64 Package (AD8334) 0.91 W

Temperature

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

θJA

AR Package1 (AD8332) 68°C/W
CP-32 Package22 (AD8332) 33°C/W
RQ Package1 (AD8331) 83°C/W
CP-64 Package3 (AD8334) 24.2°C/W

1

Four-layer JEDEC board (2S2P).

2

Exposed pad soldered to board, nine thermal vias in pad—JEDEC, four-layer

board J-STD-51-9.

3

Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, four-layer

board J-STD-51-9.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 7 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

LMD

INH

VPSL

LON

LOP

COML

VIP

VIN

MODE

GAIN

1

2

3

4

5

6

(Not to Scale)

7

8

9

10

PIN 1
INDICATO R

AD8331

TOP VIEW

20

19

18

17

16

15

14

13

12

11

COMM

ENBL

ENBV

COMM

VOL

VOH

VPOS

HILO

RCLMP

VCM

03199-003

Figure 3. 20-Lead QSOP Pin Configuration (AD8331)

Table 3. 20-Lead QSOP Pin Function Description (AD8331)

Pin No. Mnemonic Description

1 LMD VCM Bias for the LNA
2 INH LNA Input
3 VPSL LNA 5 V Supply
4 LON LNA Inverting Output
5 LOP LNA Noninverting Output
6 COML LNA Ground
7 VIP VGA Noninverting Input
8 VIN VGA Inverting Input
9 MODE Gain Slope Logic Input
10 GAIN Gain Control Voltage
11 VCM Common-Mode Voltage
12 RCLMP Output Clamping Level
13 HILO Gain Range Select (HI or LO)
14 VPOS VGA 5 V Supply
15 VOH Noninverting VGA Output
16 VOL Inverting VGA Output
17 COMM VGA Ground
18 ENBV VGA Enable
19 ENBL LNA Enable
20 COMM VGA Ground

Rev. F | Page 8 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

1

LMD2

INH2

VPS2

LON2

LOP2

COM2

VIP2

VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

2

3

4

5

6

7

(Not to Scale)

8

9

10

11

12

13

14

PIN 1
INDICATO R

AD8332

TOP VIEW

Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)

28

LMD1

27

INH1

26

VPS1

25

LON1

24

LOP1

23

COM1

22

VIP1

21

VIN1

20

VCM1

19

HILO

18

ENB

17

VOH1

16

VOL1

VPSV

15

03199-004

LON1

VPS1

INH1

LMD1

LMD2

INH2

VPS2

LON2

NC = NO CONNECT

1

2

3

4

5

6

7

8

LOP1

COM1

PIN 1
INDICATO R

LOP2

COM2

VIP1

VIN1

VCM1

29303132 28 252627

AD8332

TOP VIEW

(Not to Scale)

VIP2

VIN2

VCM2

HILO

ENBL

ENBV

COMM

24

VOH1

23

VOL1

22

VPSV

21

20

NC

19

VOL2

18

VOH2

17

14139121110

15 16

GAIN

MODE

COMM

RCLMP

03199-005

Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)

Table 4. 28-Lead TSSOP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LMD2 VCM Bias for CH2 LNA
2 INH2 CH2 LNA Input
3 VPS2 CH2 Supply LNA 5 V
4 LON2 CH2 LNA Inverting Output
5 LOP2 CH2 LNA Noninverting Output
6 COM2 CH2 LNA Ground
7 VIP2 CH2 VGA Noninverting Input
8 VIN2 CH2 VGA Inverting Input
9 VCM2 CH2 Common-Mode Voltage
10 GAIN Gain Control Voltage
11 RCLMP Output Clamping Resistor
12 VOH2 CH2 Noninverting VGA Output
13 VOL2 CH2 Inverting VGA Output
14 COMM VGA Ground (Both Channels)
15 VPSV VGA Supply 5 V (Both Channels)
16 VOL1 CH1 Inverting VGA Output
17 VOH1 CH1 Noninverting VGA Output
18 ENB Enable—VGA/LNA
19 HILO VGA Gain Range Select (HI or LO)
20 VCM1 CH1 Common-Mode Voltage
21 VIN1 CH1 VGA Inverting Input
22 VIP1 CH1 VGA Noninverting Input
23 COM1 CH1 LNA Ground
24 LOP1 CH1 LNA Noninverting Output
25 LON1 CH1 LNA Inverting Output
26 VPS1 CH1 LNA Supply 5 V
27 INH1 CH1 LNA Input
28 LMD1 VCM Bias for CH1 LNA

Table 5. 32-Lead LFCSP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LON1 CH1 LNA Inverting Output
2 VPS1 CH1 LNA Supply 5 V
3 INH1 CH1 LNA Input
4 LMD1 VCM Bias for CH1 LNA
5 LMD2 VCM Bias for CH2 LNA
6 INH2 CH2 LNA Input
7 VPS2 CH2 LNA Supply 5 V
8 LON2 CH2 LNA Inverting Output
9 LOP2 CH2 LNA Noninverting Output
10 COM2 CH2 LNA Ground
11 VIP2 CH2 VGA Noninverting Input
12 VIN2 CH2 VGA Inverting Input
13 VCM2 CH2 Common-Mode Voltage
14 MODE Gain Slope Logic Input
15 GAIN Gain Control Voltage
16 RCLMP Output Clamping Level Input
17 COMM VGA Ground
18 VOH2 CH2 Noninverting VGA Output
19 VOL2 CH2 Inverting VGA Output
20 NC No Connect
21 VPSV VGA Supply 5 V
22 VOL1 CH1 Inverting VGA Output
23 VOH1 CH1 Noninverting VGA Output
24 COMM VGA Ground
25 ENBV VGA Enable
26 ENBL LNA Enable
27 HILO VGA Gain Range Select (HI or LO)
28 VCM1 CH1 Common-Mode Voltage
29 VIN1 CH1 VGA Inverting Input
30 VIP1 CH1 VGA Noninverting Input
31 COM1 CH1 LNA Ground
32 LOP1 CH1 LNA Noninverting Output

Rev. F | Page 9 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

COM2

COM1

INH1

LMD1

COM1X

LON1

LOP1

VIP1

VIN1

VPS1

GAIN12

CLMP12

EN12

EN34

VCM1

VCM2

LMD4

COM4X

58 5764 63 5962 61 60

AD8334

TOP VIEW

(Not to Scale)

VIP4

VIN4

LOP4

LON4

VPS4

2825 26 272017 18 19 21 22 23 24

GAIN34

CLMP34

29 30 31 32

HILO

VCM4

INH2

1

LMD2

LON2

LOP2

VIP2

VIN2

VPS2

VPS3

VIN3

VIP3

LOP3

LON3

LMD3

INH3

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

COM3

COM2X

COM3X

NC = NO CONNECT

PIN 1
INDICATO R

INH4

COM4

Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)

Table 6. 64-Lead LFCSP Pin Function Description (AD8334)

Pin No. Mnemonic Description

1 INH2 CH2 LNA Input
2 LMD2 VCM Bias for CH2 LNA
3 COM2X CH2 LNA Ground Shield
4 LON2 CH2 LNA Feedback Output (for RIZ)
5 LOP2 CH2 LNA Output
6 VIP2 CH2 VGA Positive Input
7 VIN2 CH2 VGA Negative Input
8 VPS2 CH2 LNA Supply 5 V
9 VPS3 CH3 LNA Supply 5 V
10 VIN3 CH3 VGA Negative Input
11 VIP3 CH3 VGA Positive Input
12 LOP3 CH3 LNA Positive Output
13 LON3 CH3 LNA Feedback Output (for RIZ)
14 COM3X CH3 LNA Ground Shield
15 LMD3 VCM Bias for CH3 LNA
16 INH3 CH3 LNA Input
17 COM3 CH3 LNA Ground
18 COM4 CH4 LNA Ground
19 INH4 CH4 LNA Input
20 LMD4 VCM Bias for CH4 LNA
21 COM4X CH4 LNA Ground Shield
22 LON4 CH4 LNA Feedback Output (for RIZ)
23 LOP4 CH4 LNA Positive Output
24 VIP4 CH4 VGA Positive Input
25 VIN4 CH4 VGA Negative Input
26 VPS4 CH4 LNA Supply 5 V
27 GAIN34 Gain Control Voltage for CH3 and CH4
28 CLMP34 Output Clamping Level Input for CH3 and CH4

50 4956 55 5154 53 52

48

COM12

47

VOH1

46

VOL1

45

VPS12

44

VOL2

43

VOH2

42

COM12

41

MODE

40

NC

NC

39

COM34

38

VOH3

37

VOL3

36

VPS34

35

VOL4

34

VOH4

33

COM34

NC

VCM3

03199-006

Rev. F | Page 10 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Pin No. Mnemonic Description

29 HILO Gain Select for Postamp 0 dB or 12 dB
30 VCM4 CH4 Common-Mode Voltage—AC Bypass
31 VCM3 CH3 Common-Mode Voltage—AC Bypass
32 NC No Connect
33 COM34 VGA Ground CH3 and CH4
34 VOH4 CH4 Positive VGA Output
35 VOL4 CH4 Negative VGA Output
36 VPS34 VGA Supply 5 V CH3 and CH4
37 VOL3 CH3 Negative VGA Output
38 VOH3 CH3 Positive VGA Output
39 COM34 VGA Ground CH3 and CH4
40 NC No Connect
41 MODE Gain Control Slope, Logic Input, 0 = Positive
42 COM12 VGA Ground CH1 and CH2
43 VOH2 CH2 Positive VGA Output
44 VOL2 CH2 Negative VGA Output
45 VPS12 CH2 VGA Supply 5 V CH1 and CH2
46 VOL1 CH1 Negative VGA Output
47 VOH1 CH1 Positive VGA Output
48 COM12 VGA Ground CH1 and CH2
49 VCM2 CH2 Common-Mode Voltage—AC Bypass
50 VCM1 CH1 Common-Mode Voltage—AC Bypass
51 EN34 Shared LNA/VGA Enable CH3 and CH4
52 EN12 Shared LNA/VGA Enable CH1 and CH2
53 CLMP12 Output Clamping Level Input CH1 and CH2
54 GAIN12 Gain Control Voltage CH1 and CH2
55 VPS1 CH1 LNA Supply 5 V
56 VIN1 CH1 VGA Negative Input
57 VIP1 CH1 VGA Positive Input
58 LOP1 CH1 LNA Positive Output
59 LON1 CH1 LNA Feedback Output (for RIZ)
60 COM1X CH1 LNA Ground Shield
61 LMD1 VCM Bias for CH1 LNA
62 INH1 CH1 LNA Input
63 COM1 CH1 LNA Ground
64 COM2 CH2 LNA Ground

Rev. F | Page 11 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

60

50

40

30

20

GAIN (dB)

10

0

–10

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 7. Gain vs. V

ASCENDING GAIN MODE
DESCENDI NG GAI N MODE

(WHERE AVAILABLE)

GAIN

HILO = HI

HILO = LO

V

(V)

GAIN

and MODE (MODE Available on AC Package)

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 8. Absolute Gain Error vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 9. Absolute Gain Error vs. V

1MHz

–40°C

10MHz

V

GAIN

30MHz

50MHz

70MHz

V

GAIN

(V)

at Three Temperatures

GAIN

(V)

at Various Frequencies

GAIN

03199-007

+25°C

+85°C

03199-008

03199-009

50

40

30

20

PERCENT OF UNI TS (%)

10

0
–0.5 –0.4 –0. 3 –0 .2 –0.1 0 0.1 0.2 0.3 0. 4 0.5

25

20

15

10

5

0

25

20

15

PERCENT OF UNI TS (%)

10

5

0

Figure 11. Gain Match Histogram for V

50

40

30

20

10

GAIN (dB)

0

–10

–20

100k 1M 10M 100M 500M

Figure 12. Frequency Response for Various Values of V

= ∞, CL = 1 pF, VCM pin floating,

CLMP

SAMPLE SIZE = 80 UNITS
V

= 0.5V

GAIN

Figure 10. Gain Error Histogram

SAMPLE SIZE = 50 UNITS
V

= 0.2V

GAIN

V

= 0.7V

GAIN

–0.17

–0.15

–0.13

–0.11

–0.09

CHANNEL TO CHANNEL G AIN MATCH (d B)

GAIN ERROR (dB)

–0.07

–0.05

–0.03

–0.01

V

= 1V

GAIN

V

= 0.8V

GAIN

V

= 0.6V

GAIN

V

= 0.4V

GAIN

V

= 0.2V

GAIN

V

= 0V

GAIN

FREQUENCY (Hz)

03199-010

03199-011

0.01

0.03

0.05

0.07

0.09

0.11

0.13

0.15

0.17

0.19

0.21

= 0.2 V and 0.7 V

GAIN

03199-012

GAIN

Rev. F | Page 12 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

60

50

40

30

20

GAIN (dB)

10

0

V

V

V

V

V

V

GAIN

GAIN

GAIN

GAIN

GAIN

GAIN

= 1V

= 0.8V

= 0.6V

= 0.4V

= 0.2V

= 0V

0

V

= 1V p-p

OUT

–20

V

= 1.0V

GAIN

V

V

GAIN

GAIN

= 0.7V

= 0.4V

–40

–60

CROSSTALK (d B)

–80

–100

AD8332

AD8334

–10

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 13. Frequency Response for Various Values of V

, HILO = HI

GAIN

03199-013

30

V

= 0.5V

GAIN

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

= RS = 75Ω

R

IN

RIN = RS = 100Ω

= RS = 200Ω

R

IN

R

= RS = 500Ω

IN

R

FREQUENCY (Hz)

= RS = 1kΩ

IN

RIN = RS = 50Ω

03199-014

Figure 14. Frequency Response for Various Matched Source Impedances

30

V

= 0.5V

GAIN

R

=

∞

IZ

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

Figure 15. Frequency Response, Unterm

FREQUENCY (Hz)

inated LNA, R

= 50 Ω

S

03199-015

–120

100k 1M 10M 100M

FREQUENCY (Hz)

03199-016

Figure 16. Channel-to-Channel Crosstalk vs.

Freque

ncy for Various Values of V

50

45

40

35

30

1µF

25

COUPLING

20

GROUP DELAY (ns)

15

10

5

0
100k 1M 10M 100M

0.1µF
COUPLING

FREQUENCY (Hz)

GAIN

03199-017

Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling

20

HI GAIN

10

0

–10

–20

20

LO GAIN

10

OFFSET VOLTAGE (mV)

0

–10

–20

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

V

GAIN

(V)

T = +85°C
T = +25°C
T = –40°C

T = +85°C
T = +25°C
T = –40°C

03199-018

Figure 18. Representative Differential Output Offset Voltage vs.

at Three Temperatures

V

GAIN

Rev. F | Page 13 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

R

IN

R

IZ

= 100Ω,

= 549Ω

50j

–50j

RIN = 50Ω,
R

IZ

R

= 200Ω,

IN

R

= 1.1kΩ

IZ

R

= 200Ω

IN

R

IN

= 270Ω

= 500Ω

= 1kΩ

R

IN

f

= 100kHz

RIN = 50Ω

100j

–100j

IZ

R

= 100Ω

IN

03199-022

35

30

25

20

15

% TOTAL

10

5

0

SAMPLE SIZE = 100

0.2V < V

49.6 50.550.450.350.250.150.049. 949.849.7

< 0.7V

GAIN

GAIN SCALING FACTOR

Figure 19. Gain Scaling Factor Histogram

100

SINGLE ENDE D, PIN VOH O R PIN VOL
R

=

∞

L

10

1

OUTPUT IMPEDANCE (Ω)

03199-019

25j

R

= 6kΩ,

IN

R

=

∞

IZ

0Ω 17Ω

RIN = 75Ω,
R

= 412Ω

IZ

–25j

Figure 22. Smith Chart, S11 vs. Frequency,

0.1

MHz to 200 MHz for Various Values of R

20

VIN = 10mV p-p

15

10

5

0

GAIN (dB)

–5

0.1
100k 100M10M1M

Figure 20. Output Imped

10k

1k

100

INPUT IMPE DANCE (Ω)

RIZ = 6.65kΩ, CSH = 0pF
R

R

10

100k 100M10M1M

IZ

Figure 21. LNA Input Impedance vs.

Freque

FREQUENCY (Hz)

ance vs. Frequency

R

= ∞, CSH = 0pF

IZ

= 3.01kΩ, CSH = 0pF

IZ

= 1.1kΩ, CSH = 1.2pF

R

R
R

FREQUENCY (Hz)

ncy for Various Values of R

= 549Ω, CSH = 8.2pF

IZ

= 412Ω, CSH = 12pF

IZ

= 270Ω, CSH = 22pF

IZ

and CSH

IZ

–10

R

= 75Ω

03199-020

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 23. LNA Frequency Response, Single-Ended,

IN

for Various Values of R

03199-023

IN

20

15

RIZ =

∞

10

5

0

GAIN (dB)

–5

–10

03199-021

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

03199-024

Figure 24. Frequency Response for Unterminated LNA, Single-Ended

Rev. F | Page 14 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

500

f

= 10MHz

400

300

200

100

OUTPUT-REF ERRED NOISE (nV/ Hz)

0

HI GAIN

LO GAIN

0 0.2 0.4 0.6 0.8 1.0

AD8332
AD8334

AD8331

V

GAIN

(V)

Figure 25. Output-Referred Noise vs. V

2.5
RS = 0, RIZ = ∞, V
HILO = L O OR HI

2.0

GAIN

= 1V,

03199-025

GAIN

1.00
RS = 0, RIZ =∞,

V

= 1V, f = 10M Hz

GAIN

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

INPUT-REFERRE D NOISE (n V/ Hz)

0.55

0.50

–50 –30 –10 10 30 50 70 90

TEMPERATURE ( °C)

Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature

10

f = 5MHz, RIZ =∞,

= 1V

V

GAIN

03199-028

1.5

1.0

INPUT-REFERRED NO ISE (nV/ Hz)

0.5
100k 1M 10M 100M

Figure 26. Short-Circuit, Input-R

FREQUENCY (Hz)

eferred Noise vs. Frequency

100

10

1

INPUT-REFERRED NOISE (nV/ Hz)

0.1

0 0.2 0.4 0.6 0.8 1.0

Figure 27. Short-Circuit, Inp

RS = 0, RIZ =∞,
HILO = LO OR HI, f = 10MHz

V

(V)

GAIN

ut-Referred Noise vs. V

GAIN

1

R

THERMAL NOISE

S

INPUT-REFERRE D NOISE (n V/ Hz)

03199-026

0.1
1 10 100 1k

SOURCE RESIST ANCE (Ω)

Figure 29. Input-Referred Noise vs. R

ALONE

03199-029

S

7

INCLUDES NOISE OF VGA

6

5

4

3

NOISE FI GURE (dB)

2

1

03199-027

SIMULATED RESULTS

0

50 100 1k

Figure 30. Noise Figure vs. R

R

= 50Ω

IN

R

= 75Ω

IN

= 100Ω

R

IN

= 200Ω

R

IN

R

=

∞

IZ

SOURCE RESIST ANCE (Ω)

for Various Values of R

S

03199-030

IN

Rev. F | Page 15 of 60

AD8331/AD8332/AD8334

–

–

–

www.BDTIC.com/ADI

35

30

25

20

15

NOISE FI GURE (dB)

10

HILO = LO, RIN = 50Ω

HILO = LO, R

5

HILO = HI, RIN = 50Ω
HILO = HI, R

0

0 0.10.20.30.40.50.60.70.80.91.01.1

30

25

20

15

10

NOISE FI GURE (dB)

5

f = 10MHz, RS = 50Ω

0

10 15 20 25 30 35 40 45 50 55 60

0

G = 30dB,
V

= 1V p-p

OUT

–10

–20

–30

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

1M 10M 100

Figure 33. Harmonic Distortion vs. Frequency

=

∞

IZ

=

∞

Iz

V

(V)

GAIN

Figure 31. Noise Figure vs. V

GAIN (dB)

Figure 32. Noise Figure vs. Gain

HILO = LO , HD3

FREQUENCY (Hz)

f = 10MHz, RS = 50ΩPREAMP LIMITED

GAIN

HILO = LO, R
HILO = LO, R

HILO = HI, RIN = 50Ω
HILO = HI, R

HILO = L O, HD2

HILO = HI, HD2

FB

HILO = HI, HD3

IN

FB

=

= 50Ω

=

∞

∞

30

f = 10MHz,

= 1V p-p

V

OUT

–40

–50

–60

–70

HARMONIC DIST ORTIO N (dBc)

–80

03199-031

–90

0 200018001600140012001000800600400200

HILO = HI , HD2

HILO = HI , HD3

R

LOAD

Figure 34. Harmonic Distortion vs. R

40

f = 10MHz,

= 1V p-p

V

OUT

–50

–60

–70

HARMONIC DIST ORTIO N (dBc)

–80

03199-032

–90

0 10203040

HILO = LO, HD3

HILO = HI, HD2

C

LOAD

Figure 35. Harmonic Distortion vs. C

20

f = 10MHz,
GAIN = 30d B

–40

HILO = LO, HD2

–60

HILO = HI, HD2

–80

HARMONIC DIST ORTIO N (dBc)

03199-033

–100

01234

V

(V p-p)

OUT

(Ω)

(pF)

HILO = L O, HD2

HILO = L O, HD3

03199-034

LOAD

HILO = L O, HD2

HILO = HI, HD3

03199-035

50

LOAD

HILO = LO, HD3

HILO = HI , HD3

03199-036

Figure 36. Harmonic Distortion vs. Differential Output Voltage

Rev. F | Page 16 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

0

V

= 1V p-p

OUT

–20

INPUT RANGE
LIMITED WHEN

–40

HILO = LO

–60

–80

DISTORTION (dBc)

–100

–120

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

HILO = HI, HD3

HILO = L O, HD2

V

(V)

GAIN

Figure 37. Harmonic Distortion vs. V

HILO = L O, HD3

HILO = HI, HD2

, f = 1 MHz

GAIN

0

V

= 1V p-p

OUT

–20

INPUT RANGE
LIMITED WHEN

–40

HILO = LO

–60

HILO = LO, HD2

HILO = L O, HD3

03199-037

0

V

= 1V p-p COMPOSITE (

OUT

G = 30dB

–10

–20

–30

–40

–50

IMD3 (dBc)

–60

–70

–80

–90

1M 10M 100M

f

+

f

)

1

2

FREQUENCY (Hz)

HILO = L O

HILO = HI

Figure 40. IMD3 vs. Frequency

40

10MHz HILO = HI

35

30

25

20

1MHz HILO = HI

1MHz HILO = LO

10MHz HILO = LO

03199-040

–80

DISTORTION (dBc)

HILO = HI , HD3

–100

–120

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

V

GAIN

(V)

Figure 38. Harmonic Distortion vs. V

HILO = HI, HD2

, f = 10 MHz

GAIN

10

0

f = 10MHz

–10

–20

IP1dB COMPRESSION (d Bm)

–30

–40

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

HILO = HI

V

GAIN

Figure 39. IP1dB Compression vs. V

HILO = LO

(V)

GAIN

15

OUTPUT I P3 (dBm)

10

5

V

= 1V p-p COMPOSITE (

03199-038

0

010.90.80.70.60.50.40.30.20.1

OUT

Figure 41. Output Third-Order Intercept vs. V

V

GAIN

f

+

f

)

1

2

(V)

GAIN

03199-041

.0

2mV

100

90

10

0

50mV 10n s

03199-039

3199-042

Figure 42. Small Signal Pulse Response, G = 30 dB,

To

p: Input, Bottom: Output Voltage, HILO = HI or LO

Rev. F | Page 17 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

20mV

100

90

10

0

500mV 10ns

Figure 43. Large Signal Pulse Response, G = 30 dB,

H

ILO = HI or LO, Top: Input, Bottom: Output Voltage

2

G = 30dB

1

INPUT

(V)

0

OUT

V

CL = 0pF
CL = 10pF
CL = 22pF
CL = 47pF

5.0

4.5

4.0

3.5

3.0

2.5

(V p-p)

OUT

2.0

V

1.5

1.0

3199-043

0.5

0

0545403530252015105

4

G = 40dB

3

2

1

INPUT

(V)

0

OUT

V

–1

HILO = HI

HILO = LO

R

(kΩ)

CLMP

Figure 46. Clamp Level vs. R

R

= 48.1kΩ

CLMP

R

= 16.5kΩ

CLMP

R

= 7.15kΩ

CLMP

R

= 2.67kΩ

CLMP

03199-046

0

CLMP

–1

INPUT IS NOT TO SCALE

–2

–50 50403020100–10–20–30–40

TIME (ns)

Figure 44. Large Signal Pulse Response for Various Capacitive Loads,

= 0 pF, 10 pF, 20 pF, 50 pF

C

L

500mV

200mV 400ns

3199-045

Figure 45. Pin GAIN Transient Response,

Top: V

, Bottom: Output Voltage

GAIN

–2

–3

03199-044

–4

–30–20–100 1020304050607080

TIME (ns)

Figure 47. Clamp Level Pulse Response for Four Values of R

03199-047

CLMP

200mV

100

90

10

0

Figure 48. LNA Overdrive Recovery, V

= 0.27 V VGA Output Shown

V

GAIN

100ns

0.05 V p-p to 1 V p-p Burst,

INH

3199-048

Rev. F | Page 18 of 60