Datasheet AD8332 Datasheet (ANALOG DEVICES)

Ultralow Noise VGAs with

VINV

V

www.BDTIC.com/ADI

Preamplifier and Programmable R

FEATURES

Ultralow noise preamplifier (preamp)

Voltage noise = 0.74 nV/√Hz Current noise = 2.5 pA/√Hz

3 dB bandwidth

AD8331: 120 MHz AD8332, AD8334: 100 MHz

Low power

AD8331: 125 mW/channel AD8332, AD8334: 145 mW/channel

Wide gain range with programmable postamp

−4.5 dB to +43.5 dB in LO gain mode

+7.5 dB to +55.5 dB in HI gain mode Low output-referred noise: 48 nV/√Hz typical Active input impedance matching Optimized for 10-bit/12-bit ADCs Selectable output clamping level Single 5 V supply operation AD8332 and AD8334 available in lead frame chip scale package

APPLICATIONS

Ultrasound and sonar time-gain controls High performance automatic gain control (AGC) systems I/Q signal processing High speed, dual ADC drivers

GENERAL DESCRIPTION

The AD8331/AD8332/AD8334 are single-, dual-, and quadchannel, ultralow noise linear-in-dB, variable gain amplifiers (VGAs). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz.

Included in each channel are an ultralow noise preamp (LNA), a

n X-AMP® VGA with 48 dB of gain range, and a selectable gain postamp with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs. Using a single resistor, the LNA input impedance can be adjusted to match a signal source without compromising noise performance.

The 48 dB gain range of the VGA makes these devices suitable fo

r a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching.

IN

AD8331/AD8332/AD8334

FUNCTIONAL BLOCK DIAGRAM

INH

LMD

IPLOPLON

LNA

19dB

VCM BIAS

AD8331/AD8332/AD8334

60

50

40

30

20

GAIN (dB)

10

0

–10

100k 1M 10M 100M 1G

–

48dB

ATTENUATO R

+

VGA BIAS AND

INTERPOLATOR

Figure 1. Signal Path Block Diagram

V

GAIN

V

= 0.8V

GAIN

V

= 0.6V

GAIN

V

= 0.4V

GAIN

V

= 0.2V

GAIN

V

GAIN

FREQUENCY (Hz)

Figure 2. Frequency Response vs. Gain

= 1V

= 0V

V

ENB

CM

MID

3.5dB OR 15.5d B

21dB

GAIN

CONTROL

INTERFACE

GAIN

Differential signal paths result in superb second- and thirdorder distortion performance and low crosstalk.

The low output-referred noise of the VGA is advantageous in dr

iving high speed differential ADCs. The gain of the postamp can be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output can be limited to a user-selected clamping level, pre-venting input overload to a subsequent ADC. An external resistor adjusts the clamping level.

The operating temperature range is −40°C to +85°C. The AD8331 is a

vailable in a 20-lead QSOP package, the AD8332 is available in 28-lead TSSOP and 32-lead LFCSP packages, and the AD8334 is available in a 64-lead LFCSP package.

PA

CLAMP

HI GAIN

MODE

HILO

VOH

VOL

RCLMP

03199-002

03199-001

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

REVISION HISTORY

4/08—Rev. E to Rev. F

Changed R

Changes to Figure 1...........................................................................1

Changes to Table 1, LNA and VGA Characteristics, Output

Offset Voltage, Conditions...............................................................4

Changes to Quiescent Current per Channel and Power Down

Current Parameters...........................................................................6

Changes to Table 2 ............................................................................7

Changes to Table 3, Pin 1 Description ...........................................8

Changes to Table 4, Pin 1 and Pin 28 Descriptions ......................9

Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................9

Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions......10

Changes to Table 6, Pin 61 Description .......................................11

Changes to Typical Performance Characteristics Section,

Default Conditions..........................................................................12

Changes to Figure 25 ......................................................................15

Changes to Figure 39 ......................................................................17

Changes to Figure 55 Through Figure 68 ...................................20

Changes to Theory of Operation, Overview Section .................24

Changes to Low Noise Amplifier Section and Figure 74...........25

Changes to Active Impedance Matching Section, Figure 75,

and Figure 77 ...................................................................................26

Changes to Figure 78 ......................................................................27

Changes to Equation 6, Table 7, Figure 81, and Figure 82.........30

Changes to Figure 83 ......................................................................31

Changes to Figure 88 ......................................................................32

Switched Figure 89 and Figure 90 .................................................33

Changes to Figure 89 ......................................................................33

Changes to Ultrasound TGC Application Section......................34

Incorporated AD8331-EVAL Data Sheet, Rev. A .......................39

Changes to User-Supplied Optional Components Section a

nd Measurement Setup Section...............................................39

Changes to Figure 95..................................................................39

Changes to Figure 97..................................................................41

dded Figure 98..........................................................................42

A

Incorporated AD8332-EVALZ Data Sheet, Rev. D.....................44

I

ncorporated AD8334-EVAL Data Sheet, Rev. 0 ........................49

Updated Outline Dimensions........................................................55

Changes to Ordering Guide...........................................................57

4/06—Rev. D to Rev. E

A

dded AD8334................................................................... Universal

Changes to Figure 1 and Figure 2....................................................1

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................7

Changes to Figure 7 through Figure 9 and Figure 12.................12

Changes to Figure 13, Figure 14, Figure 16, and Figure 18.......13

FB

to R

Throughout .....................................................4

IZ

Changes to Figure 23 and Figure 24 .............................................14

Changes to Figure 25 through Figure 27......................................15

Changes to Figure 31 and Figure 33 through Figure 36 ............16

Changes to Figure 37 through Figure 42......................................17

Changes to Figure 43, Figure 44, and Figure 48..........................18

Changes to Figure 49, Figure 50, and Figure 54..........................19

Inserted Figure 56 and Figure 57..................................................20

Inserted Figure 58, Figure 59, and Figure 61...............................21

Changes to Figure 60......................................................................21

Inserted Figure 63 and Figure 65..................................................22

Changes to Figure 64......................................................................22

Moved Measurement Considerations Section ............................23

Inserted Figure 67 and Figure 68..................................................23

Inserted Figure 70 and Figure 71..................................................24

Change to Figure 72........................................................................24

Changes to Figure 73 and Low Noise Amplifier Section...........25

Changes to Postamplifier Section .................................................28

Changes to Figure 80......................................................................29

Changes to LNA—External Components Section......................30

Changes to Logic Inputs—ENB, MODE, and HILO Section ...31

Changes to Output Decoupling and Overload Sections............32

Changes to Layout, Grounding, and Bypassing Section............33

Changes to Ultrasound TGC Application Section .....................34

Added High Density Quad Layout Section.................................34

Inserted Figure 94 ...........................................................................38

Updated Outline Dimensions........................................................39

Changes to Ordering Guide...........................................................40

3/06—Rev. C to Rev. D

U

pdated Format .................................................................Universal

Changes to Features and General Description..............................1

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................6

Changes to Ordering Guide...........................................................34

11/03—Rev. B to Rev. C

A

ddition of New Part......................................................... Universal

Changes to Figures............................................................. Universal

Updated Outline Dimensions........................................................32

5/03—Rev. A to Rev. B

E

dits to Ordering Guide.................................................................32

Edits to Ultrasound TGC Application Section ...........................25

Added Figure 71, Figure 72, and Figure 73..................................26

Updated Outline Dimensions........................................................31

2/03—Rev. 0 to Rev. A

dits to Ordering Guide.................................................................32

E

Rev. F | Page 3 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

= ∞, CL = 1 pF, VCM pin floating,

CLMP

Table 1.

Parameter Conditions Min Typ Max Unit

1

LNA CHARACTERISTICS

Gain Single-ended input to differential output 19 dB

Input to output (single-ended) 13 dB

Input Voltage Range AC-coupled ±275 mV

Input Resistance RIZ = 280 Ω 50 Ω R R R R

= 412 Ω 75 Ω

IZ

= 562 Ω 100 Ω

IZ

= 1.13 kΩ 200 Ω

IZ

= ∞ 6 kΩ

IZ

Input Capacitance 13 pF

Output Impedance Single-ended, either output 5 Ω

−3 dB Small Signal Bandwidth V

= 0.2 V p-p 130 MHz

OUT

Slew Rate 650 V/µs

Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.74 nV/√Hz

Input Current Noise RIZ = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz

Noise Figure f = 10 MHz, LOP output

Active Termination Match RS = RIN = 50 Ω 3.7 dB Unterminated RS = 50 Ω, RIZ = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2 V

= 0.5 V p-p, single-ended, f = 10 MHz

OUT

HD2 −56 dBc HD3 −70 dBc

Output Short-Circuit Current Pin LON, Pin LOP 165 mA LNA AND VGA CHARACTERISTICS

−3 dB Small Signal Bandwidth V

= 0.2 V p-p

OUT

AD8331 120 MHz AD8332, AD8334 100 MHz

−3 dB Large Signal Bandwidth V

= 2 V p-p

OUT

AD8331 110 MHz AD8332, AD8334 90 MHz

Slew Rate

AD8331 LO gain 300 V/µs HI gain 1200 V/µs AD8332, AD8334 LO gain 275 V/µs

HI gain 1100 V/µs Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.82 nV/√Hz Noise Figure V

= 1.0 V

GAIN

Active Termination Match RS = RIN = 50 Ω, f = 10 MHz, measured 4.15 dB R

= RIN = 200 Ω, f = 5 MHz, simulated 2.0 dB

S

Unterminated RS = 50 Ω, RIZ = ∞, f = 10 MHz, measured 2.5 dB

R

= 200 Ω, RIZ = ∞, f = 5 MHz, simulated 1.0 dB

S

Output-Referred Noise

AD8331 V V AD8332, AD8334 V

V

= 0.5 V, LO gain 48 nV/√Hz

GAIN

= 0.5 V, HI gain 178 nV/√Hz

GAIN

= 0.5 V, LO gain 40 nV/√Hz

GAIN

= 0.5 V, HI gain 150 nV/√Hz

GAIN

Output Impedance, Postamplifier DC to 1 MHz 1 Ω

Rev. F | Page 4 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Parameter Conditions Min Typ Max Unit

1

Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V

Differential 4.5 V p-p

Output Offset Voltage

AD8331 Differential, V

= 0.5 V −50 ±5 +50 mV

GAIN

Common mode −125 −25 +100 mV AD8332, AD8334 Differential, 0.05 V ≤ V

≤ 1.0 V −20 ±5 +20 mV

GAIN

Common mode −125 –25 +100 mV Output Short-Circuit Current 45 mA Harmonic Distortion V

= 0.5 V, V

GAIN

= 1 V p-p, HI gain

OUT

AD8331

HD2 f = 1 MHz −88 dBc HD3 −85 dBc HD2 f = 10 MHz −68 dBc HD3 −65 dBc

AD8332, AD8334

HD2 f = 1 MHz −82 dBc HD3 −85 dBc HD2 f = 10 MHz −62 dBc HD3 −66 dBc

Input 1 dB Compression Point V

= 0.25 V, V

GAIN

= 1 V p-p, f = 1 MHz to 10 MHz 1 dBm

OUT

Two-Tone Intermodulation Distortion (IMD3)

AD8331 V

V

AD8332, AD8334 V

V

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 0.72 V, V

GAIN

= 0.5 V, V

GAIN

= 1 V p-p, f = 1 MHz −80 dBc

OUT

= 1 V p-p, f = 10 MHz −72 dBc

OUT

= 1 V p-p, f = 1 MHz −78 dBc

OUT

= 1 V p-p, f = 10 MHz −74 dBc

OUT

Output Third-Order Intercept

AD8331 V

V

AD8332, AD8334 V

V

Channel-to-Channel Crosstalk (AD8332, AD8334) V Overload Recovery V

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 0.5 V, V

GAIN

= 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns

GAIN

= 1 V p-p, f = 1 MHz 38 dBm

OUT

= 1 V p-p, f = 10 MHz 33 dBm

OUT

= 1 V p-p, f = 1 MHz 35 dBm

OUT

= 1 V p-p, f = 10 MHz 32 dBm

OUT

= 1 V p-p, f = 1 MHz −98 dB

OUT

Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns

ACCURACY

Absolute Gain Error

0.10 V < V

0.95 V < V Gain Law Conformance Channel-to-Channel Gain Matching 0.1 V < V

2

3

0.05 V < V

0.1 V < V

< 0.10 V −1 +0.5 +2 dB

GAIN

< 0.95 V −1 ±0.3 +1 dB

GAIN

< 1.0 V −2 −1 +1 dB

GAIN

< 0.95 V ±0.2 dB

GAIN

< 0.95 V ±0.1 dB

GAIN

GAIN CONTROL INTERFACE (Pin GAIN)

Gain Scaling Factor 0.10 V < V

< 0.95 V 48.5 50 51.5 dB/V

GAIN

Gain Range LO gain −4.5 to +43.5 dB

HI gain 7.5 to 55.5 dB

Input Voltage (V

) Range 0 to 1.0 V

GAIN

Input Impedance 10 MΩ Response Time 48 dB gain change to 90% full scale 500 ns

COMMON-MODE INTERFACE (PIN VCMx)

Input Resistance

4

Current limited to ±1 mA 30 Ω Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV Voltage Range V

= 2.0 V p-p 1.5 to 3.5 V

OUT

Rev. F | Page 5 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Parameter Conditions Min Typ Max Unit

ENABLE INTERFACE

1

(PIN ENB, PIN ENBL, PIN ENBV) Logic Level to Enable Power 2.25 5 V Logic Level to Disable Power 0 1.0 V

Input Resistance Pin ENB 25 kΩ Pin ENBL 40 kΩ Pin ENBV 70 kΩ

Power-Up Response Time V V

= 30 mV p-p 300 µs

INH

= 150 mV p-p 4 ms

INH

HILO GAIN RANGE INTERFACE (PIN HILO)

Logic Level to Select HI Gain Range 2.25 5 V

Logic Level to Select LO Gain Range 0 1.0 V

Input Resistance 50 kΩ OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR

LO GAIN)

Accuracy

HILO = LO R HILO = HI R

= 2.74 kΩ, V

CLMP

= 2.21 kΩ, V

CLMP

= 1 V p-p (clamped) ±50 mV

OUT

= 1 V p-p (clamped) ±75 mV

OUT

MODE INTERFACE (PIN MODE)

Logic Level for Positive Gain Slope 0 1.0 V

Logic Level for Negative Gain Slope 2.25 5 V

Input Resistance 200 kΩ POWER SUPPLY (PIN VPS1, PIN VPS2,

PIN VPSV, PIN VPSL, PIN VPOS)

Supply Voltage 4.5 5.0 5.5 V

Quiescent Current per Channel

AD8331 20 25 mA AD8332 25 27.5 32 mA AD8334 27 29.5 34

Power Dissipation per Channel No signal

AD8331 125 mW AD8332, AD8334 138 mW

Power-Down Current VGA and LNA disabled

AD8331 50 240 400 µA AD8332 50 300 600 µA AD8334 50 600 1200 µA

LNA Current

AD8331 (ENBL) Each channel 7.5 11 15 mA AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA

VGA Current

AD8331 (ENBV) 7.5 14 20 mA AD8332, AD8334 (ENBV) 7.5 17 20 mA

PSRR V

1

All dBm values are referred to 50 Ω.

2

The absolute gain refers to the theoretical gain expression in Equation 1.

3

Best-fit to linear-in-dB curve.

4

The current is limited to ±1 mA typical.

= 0 V, f = 100 kHz −68 dB

GAIN

Rev. F | Page 6 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V Input Voltage (INHx) VS + 200 mV ENB, ENBL, ENBV, HILO Voltage VS + 200 mV GAIN Voltage 2.5 V

Power Dissipation

AR Package1 (AD8332) 0.96 W CP-32 Package (AD8332) 1.97 W RQ Package1 (AD8331) 0.78 W CP-64 Package (AD8334) 0.91 W

Temperature

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C

θJA

AR Package1 (AD8332) 68°C/W CP-32 Package22 (AD8332) 33°C/W RQ Package1 (AD8331) 83°C/W CP-64 Package3 (AD8334) 24.2°C/W

1

Four-layer JEDEC board (2S2P).

2

Exposed pad soldered to board, nine thermal vias in pad—JEDEC, four-layer

board J-STD-51-9.

3

Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, four-layer

board J-STD-51-9.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. F | Page 7 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

LMD

INH

VPSL

LON

LOP

COML

VIP

VIN

MODE

GAIN

1

2

3

4

5

6

(Not to Scale)

7

8

9

10

PIN 1 INDICATO R

AD8331

TOP VIEW

20

19

18

17

16

15

14

13

12

11

COMM

ENBL

ENBV

COMM

VOL

VOH

VPOS

HILO

RCLMP

VCM

03199-003

Figure 3. 20-Lead QSOP Pin Configuration (AD8331)

Table 3. 20-Lead QSOP Pin Function Description (AD8331)

Pin No. Mnemonic Description

1 LMD VCM Bias for the LNA 2 INH LNA Input 3 VPSL LNA 5 V Supply 4 LON LNA Inverting Output 5 LOP LNA Noninverting Output 6 COML LNA Ground 7 VIP VGA Noninverting Input 8 VIN VGA Inverting Input 9 MODE Gain Slope Logic Input 10 GAIN Gain Control Voltage 11 VCM Common-Mode Voltage 12 RCLMP Output Clamping Level 13 HILO Gain Range Select (HI or LO) 14 VPOS VGA 5 V Supply 15 VOH Noninverting VGA Output 16 VOL Inverting VGA Output 17 COMM VGA Ground 18 ENBV VGA Enable 19 ENBL LNA Enable 20 COMM VGA Ground

Rev. F | Page 8 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

1

LMD2

INH2

VPS2

LON2

LOP2

COM2

VIP2

VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

2

3

4

5

6

7

(Not to Scale)

8

9

10

11

12

13

14

PIN 1 INDICATO R

AD8332

TOP VIEW

Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)

28

LMD1

27

INH1

26

VPS1

25

LON1

24

LOP1

23

COM1

22

VIP1

21

VIN1

20

VCM1

19

HILO

18

ENB

17

VOH1

16

VOL1

VPSV

15

03199-004

LON1

VPS1

INH1

LMD1

LMD2

INH2

VPS2

LON2

NC = NO CONNECT

1

2

3

4

5

6

7

8

LOP1

COM1

PIN 1 INDICATO R

LOP2

COM2

VIP1

VIN1

VCM1

29303132 28 252627

AD8332

TOP VIEW

(Not to Scale)

VIP2

VIN2

VCM2

HILO

ENBL

ENBV

COMM

24

VOH1

23

VOL1

22

VPSV

21

20

NC

19

VOL2

18

VOH2

17

14139121110

15 16

GAIN

MODE

COMM

RCLMP

03199-005

Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)

Table 4. 28-Lead TSSOP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LMD2 VCM Bias for CH2 LNA 2 INH2 CH2 LNA Input 3 VPS2 CH2 Supply LNA 5 V 4 LON2 CH2 LNA Inverting Output 5 LOP2 CH2 LNA Noninverting Output 6 COM2 CH2 LNA Ground 7 VIP2 CH2 VGA Noninverting Input 8 VIN2 CH2 VGA Inverting Input 9 VCM2 CH2 Common-Mode Voltage 10 GAIN Gain Control Voltage 11 RCLMP Output Clamping Resistor 12 VOH2 CH2 Noninverting VGA Output 13 VOL2 CH2 Inverting VGA Output 14 COMM VGA Ground (Both Channels) 15 VPSV VGA Supply 5 V (Both Channels) 16 VOL1 CH1 Inverting VGA Output 17 VOH1 CH1 Noninverting VGA Output 18 ENB Enable—VGA/LNA 19 HILO VGA Gain Range Select (HI or LO) 20 VCM1 CH1 Common-Mode Voltage 21 VIN1 CH1 VGA Inverting Input 22 VIP1 CH1 VGA Noninverting Input 23 COM1 CH1 LNA Ground 24 LOP1 CH1 LNA Noninverting Output 25 LON1 CH1 LNA Inverting Output 26 VPS1 CH1 LNA Supply 5 V 27 INH1 CH1 LNA Input 28 LMD1 VCM Bias for CH1 LNA

Table 5. 32-Lead LFCSP Pin Function Description (AD8332)

Pin No. Mnemonic Description

1 LON1 CH1 LNA Inverting Output 2 VPS1 CH1 LNA Supply 5 V 3 INH1 CH1 LNA Input 4 LMD1 VCM Bias for CH1 LNA 5 LMD2 VCM Bias for CH2 LNA 6 INH2 CH2 LNA Input 7 VPS2 CH2 LNA Supply 5 V 8 LON2 CH2 LNA Inverting Output 9 LOP2 CH2 LNA Noninverting Output 10 COM2 CH2 LNA Ground 11 VIP2 CH2 VGA Noninverting Input 12 VIN2 CH2 VGA Inverting Input 13 VCM2 CH2 Common-Mode Voltage 14 MODE Gain Slope Logic Input 15 GAIN Gain Control Voltage 16 RCLMP Output Clamping Level Input 17 COMM VGA Ground 18 VOH2 CH2 Noninverting VGA Output 19 VOL2 CH2 Inverting VGA Output 20 NC No Connect 21 VPSV VGA Supply 5 V 22 VOL1 CH1 Inverting VGA Output 23 VOH1 CH1 Noninverting VGA Output 24 COMM VGA Ground 25 ENBV VGA Enable 26 ENBL LNA Enable 27 HILO VGA Gain Range Select (HI or LO) 28 VCM1 CH1 Common-Mode Voltage 29 VIN1 CH1 VGA Inverting Input 30 VIP1 CH1 VGA Noninverting Input 31 COM1 CH1 LNA Ground 32 LOP1 CH1 LNA Noninverting Output

Rev. F | Page 9 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

COM2

COM1

INH1

LMD1

COM1X

LON1

LOP1

VIP1

VIN1

VPS1

GAIN12

CLMP12

EN12

EN34

VCM1

VCM2

LMD4

COM4X

58 5764 63 5962 61 60

AD8334

TOP VIEW

(Not to Scale)

VIP4

VIN4

LOP4

LON4

VPS4

2825 26 272017 18 19 21 22 23 24

GAIN34

CLMP34

29 30 31 32

HILO

VCM4

INH2

1

LMD2

LON2

LOP2

VIP2

VIN2

VPS2

VPS3

VIN3

VIP3

LOP3

LON3

LMD3

INH3

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

COM3

COM2X

COM3X

NC = NO CONNECT

PIN 1 INDICATO R

INH4

COM4

Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)

Table 6. 64-Lead LFCSP Pin Function Description (AD8334)

Pin No. Mnemonic Description

1 INH2 CH2 LNA Input 2 LMD2 VCM Bias for CH2 LNA 3 COM2X CH2 LNA Ground Shield 4 LON2 CH2 LNA Feedback Output (for RIZ) 5 LOP2 CH2 LNA Output 6 VIP2 CH2 VGA Positive Input 7 VIN2 CH2 VGA Negative Input 8 VPS2 CH2 LNA Supply 5 V 9 VPS3 CH3 LNA Supply 5 V 10 VIN3 CH3 VGA Negative Input 11 VIP3 CH3 VGA Positive Input 12 LOP3 CH3 LNA Positive Output 13 LON3 CH3 LNA Feedback Output (for RIZ) 14 COM3X CH3 LNA Ground Shield 15 LMD3 VCM Bias for CH3 LNA 16 INH3 CH3 LNA Input 17 COM3 CH3 LNA Ground 18 COM4 CH4 LNA Ground 19 INH4 CH4 LNA Input 20 LMD4 VCM Bias for CH4 LNA 21 COM4X CH4 LNA Ground Shield 22 LON4 CH4 LNA Feedback Output (for RIZ) 23 LOP4 CH4 LNA Positive Output 24 VIP4 CH4 VGA Positive Input 25 VIN4 CH4 VGA Negative Input 26 VPS4 CH4 LNA Supply 5 V 27 GAIN34 Gain Control Voltage for CH3 and CH4 28 CLMP34 Output Clamping Level Input for CH3 and CH4

50 4956 55 5154 53 52

48

COM12

47

VOH1

46

VOL1

45

VPS12

44

VOL2

43

VOH2

42

COM12

41

MODE

40

NC

39

COM34

38

VOH3

37

VOL3

36

VPS34

35

VOL4

34

VOH4

33

COM34

NC

VCM3

03199-006

Rev. F | Page 10 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Pin No. Mnemonic Description

29 HILO Gain Select for Postamp 0 dB or 12 dB 30 VCM4 CH4 Common-Mode Voltage—AC Bypass 31 VCM3 CH3 Common-Mode Voltage—AC Bypass 32 NC No Connect 33 COM34 VGA Ground CH3 and CH4 34 VOH4 CH4 Positive VGA Output 35 VOL4 CH4 Negative VGA Output 36 VPS34 VGA Supply 5 V CH3 and CH4 37 VOL3 CH3 Negative VGA Output 38 VOH3 CH3 Positive VGA Output 39 COM34 VGA Ground CH3 and CH4 40 NC No Connect 41 MODE Gain Control Slope, Logic Input, 0 = Positive 42 COM12 VGA Ground CH1 and CH2 43 VOH2 CH2 Positive VGA Output 44 VOL2 CH2 Negative VGA Output 45 VPS12 CH2 VGA Supply 5 V CH1 and CH2 46 VOL1 CH1 Negative VGA Output 47 VOH1 CH1 Positive VGA Output 48 COM12 VGA Ground CH1 and CH2 49 VCM2 CH2 Common-Mode Voltage—AC Bypass 50 VCM1 CH1 Common-Mode Voltage—AC Bypass 51 EN34 Shared LNA/VGA Enable CH3 and CH4 52 EN12 Shared LNA/VGA Enable CH1 and CH2 53 CLMP12 Output Clamping Level Input CH1 and CH2 54 GAIN12 Gain Control Voltage CH1 and CH2 55 VPS1 CH1 LNA Supply 5 V 56 VIN1 CH1 VGA Negative Input 57 VIP1 CH1 VGA Positive Input 58 LOP1 CH1 LNA Positive Output 59 LON1 CH1 LNA Feedback Output (for RIZ) 60 COM1X CH1 LNA Ground Shield 61 LMD1 VCM Bias for CH1 LNA 62 INH1 CH1 LNA Input 63 COM1 CH1 LNA Ground 64 COM2 CH2 LNA Ground

Rev. F | Page 11 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, R

−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

60

50

40

30

20

GAIN (dB)

10

0

–10

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 7. Gain vs. V

ASCENDING GAIN MODE DESCENDI NG GAI N MODE

(WHERE AVAILABLE)

GAIN

HILO = HI

HILO = LO

V

(V)

GAIN

and MODE (MODE Available on AC Package)

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 8. Absolute Gain Error vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

0 0.2 0.4 0.6 0.8 1.0 1.1

Figure 9. Absolute Gain Error vs. V

1MHz

–40°C

10MHz

V

GAIN

30MHz

50MHz

70MHz

V

GAIN

(V)

at Three Temperatures

GAIN

(V)

at Various Frequencies

GAIN

03199-007

+25°C

+85°C

03199-008

03199-009

50

40

30

20

PERCENT OF UNI TS (%)

10

0 –0.5 –0.4 –0. 3 –0 .2 –0.1 0 0.1 0.2 0.3 0. 4 0.5

25

20

15

10

5

0

25

20

15

PERCENT OF UNI TS (%)

10

5

0

Figure 11. Gain Match Histogram for V

50

40

30

20

10

GAIN (dB)

0

–10

–20

100k 1M 10M 100M 500M

Figure 12. Frequency Response for Various Values of V

= ∞, CL = 1 pF, VCM pin floating,

CLMP

SAMPLE SIZE = 80 UNITS V

= 0.5V

GAIN

Figure 10. Gain Error Histogram

SAMPLE SIZE = 50 UNITS V

= 0.2V

GAIN

V

= 0.7V

GAIN

–0.17

–0.15

–0.13

–0.11

–0.09

CHANNEL TO CHANNEL G AIN MATCH (d B)

GAIN ERROR (dB)

–0.07

–0.05

–0.03

–0.01

V

= 1V

GAIN

V

= 0.8V

GAIN

V

= 0.6V

GAIN

V

= 0.4V

GAIN

V

= 0.2V

GAIN

V

= 0V

GAIN

FREQUENCY (Hz)

03199-010

03199-011

0.01

0.03

0.05

0.07

0.09

0.11

0.13

0.15

0.17

0.19

0.21

= 0.2 V and 0.7 V

GAIN

03199-012

GAIN

Rev. F | Page 12 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

60

50

40

30

20

GAIN (dB)

10

0

V

GAIN

= 1V

= 0.8V

= 0.6V

= 0.4V

= 0.2V

= 0V

0

V

= 1V p-p

OUT

–20

V

= 1.0V

GAIN

V

GAIN

= 0.7V

= 0.4V

–40

–60

CROSSTALK (d B)

–80

–100

AD8332

AD8334

–10

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 13. Frequency Response for Various Values of V

, HILO = HI

GAIN

03199-013

30

V

= 0.5V

GAIN

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

= RS = 75Ω

R

IN

RIN = RS = 100Ω

= RS = 200Ω

R

IN

R

= RS = 500Ω

IN

R

FREQUENCY (Hz)

= RS = 1kΩ

IN

RIN = RS = 50Ω

03199-014

Figure 14. Frequency Response for Various Matched Source Impedances

30

V

= 0.5V

GAIN

R

=

∞

IZ

20

10

0

GAIN (dB)

–10

–20

–30

100k 1M 10M 100M 500M

Figure 15. Frequency Response, Unterm

FREQUENCY (Hz)

inated LNA, R

= 50 Ω

S

03199-015

–120

100k 1M 10M 100M

FREQUENCY (Hz)

03199-016

Figure 16. Channel-to-Channel Crosstalk vs.

Freque

ncy for Various Values of V

50

45

40

35

30

1µF

25

COUPLING

20

GROUP DELAY (ns)

15

10

5

0 100k 1M 10M 100M

0.1µF COUPLING

FREQUENCY (Hz)

GAIN

03199-017

Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling

20

HI GAIN

10

0

–10

–20

20

LO GAIN

10

OFFSET VOLTAGE (mV)

0

–10

–20

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

V

GAIN

(V)

T = +85°C T = +25°C T = –40°C

03199-018

Figure 18. Representative Differential Output Offset Voltage vs.

at Three Temperatures

V

GAIN

Rev. F | Page 13 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

R

IN

R

IZ

= 100Ω,

= 549Ω

50j

–50j

RIN = 50Ω, R

IZ

R

= 200Ω,

IN

R

= 1.1kΩ

IZ

R

= 200Ω

IN

R

IN

= 270Ω

= 500Ω

= 1kΩ

R

IN

f

= 100kHz

RIN = 50Ω

100j

–100j

IZ

R

= 100Ω

IN

03199-022

35

30

25

20

15

% TOTAL

10

5

0

SAMPLE SIZE = 100

0.2V < V

49.6 50.550.450.350.250.150.049. 949.849.7

< 0.7V

GAIN

GAIN SCALING FACTOR

Figure 19. Gain Scaling Factor Histogram

100

SINGLE ENDE D, PIN VOH O R PIN VOL R

=

∞

L

10

1

OUTPUT IMPEDANCE (Ω)

03199-019

25j

R

= 6kΩ,

IN

R

=

∞

IZ

0Ω 17Ω

RIN = 75Ω, R

= 412Ω

IZ

–25j

Figure 22. Smith Chart, S11 vs. Frequency,

0.1

MHz to 200 MHz for Various Values of R

20

VIN = 10mV p-p

15

10

5

0

GAIN (dB)

–5

0.1 100k 100M10M1M

Figure 20. Output Imped

10k

1k

100

INPUT IMPE DANCE (Ω)

RIZ = 6.65kΩ, CSH = 0pF R

R

10

100k 100M10M1M

IZ

Figure 21. LNA Input Impedance vs.

Freque

FREQUENCY (Hz)

ance vs. Frequency

R

= ∞, CSH = 0pF

IZ

= 3.01kΩ, CSH = 0pF

IZ

= 1.1kΩ, CSH = 1.2pF

R

R R

FREQUENCY (Hz)

ncy for Various Values of R

= 549Ω, CSH = 8.2pF

IZ

= 412Ω, CSH = 12pF

IZ

= 270Ω, CSH = 22pF

IZ

and CSH

IZ

–10

R

= 75Ω

03199-020

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

Figure 23. LNA Frequency Response, Single-Ended,

IN

for Various Values of R

03199-023

IN

20

15

RIZ =

∞

10

5

0

GAIN (dB)

–5

–10

03199-021

–15

100k 1M 10M 100M 500M

FREQUENCY (Hz)

03199-024

Figure 24. Frequency Response for Unterminated LNA, Single-Ended

Rev. F | Page 14 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

500

f

= 10MHz

400

300

200

100

OUTPUT-REF ERRED NOISE (nV/ Hz)

0

HI GAIN

LO GAIN

0 0.2 0.4 0.6 0.8 1.0

AD8332 AD8334

AD8331

V

GAIN

(V)

Figure 25. Output-Referred Noise vs. V

2.5 RS = 0, RIZ = ∞, V HILO = L O OR HI

2.0

GAIN

= 1V,

03199-025

GAIN

1.00 RS = 0, RIZ =∞,

V

= 1V, f = 10M Hz

GAIN

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

INPUT-REFERRE D NOISE (n V/ Hz)

0.55

0.50

–50 –30 –10 10 30 50 70 90

TEMPERATURE ( °C)

Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature

10

f = 5MHz, RIZ =∞,

= 1V

V

GAIN

03199-028

1.5

1.0

INPUT-REFERRED NO ISE (nV/ Hz)

0.5 100k 1M 10M 100M

Figure 26. Short-Circuit, Input-R

FREQUENCY (Hz)

eferred Noise vs. Frequency

100

10

1

INPUT-REFERRED NOISE (nV/ Hz)

0.1

0 0.2 0.4 0.6 0.8 1.0

Figure 27. Short-Circuit, Inp

RS = 0, RIZ =∞, HILO = LO OR HI, f = 10MHz

V

(V)

GAIN

ut-Referred Noise vs. V

GAIN

1

R

THERMAL NOISE

S

INPUT-REFERRE D NOISE (n V/ Hz)

03199-026

0.1 1 10 100 1k

SOURCE RESIST ANCE (Ω)

Figure 29. Input-Referred Noise vs. R

ALONE

03199-029

S

7

INCLUDES NOISE OF VGA

6

5

4

3

NOISE FI GURE (dB)

2

1

03199-027

SIMULATED RESULTS

0

50 100 1k

Figure 30. Noise Figure vs. R

R

= 50Ω

IN

R

= 75Ω

IN

= 100Ω

R

IN

= 200Ω

R

IN

R

=

∞

IZ

SOURCE RESIST ANCE (Ω)

for Various Values of R

S

03199-030

IN

Rev. F | Page 15 of 60

AD8331/AD8332/AD8334

–

www.BDTIC.com/ADI

35

30

25

20

15

NOISE FI GURE (dB)

10

HILO = LO, RIN = 50Ω

HILO = LO, R

5

HILO = HI, RIN = 50Ω HILO = HI, R

0

0 0.10.20.30.40.50.60.70.80.91.01.1

30

25

20

15

10

NOISE FI GURE (dB)

5

f = 10MHz, RS = 50Ω

0

10 15 20 25 30 35 40 45 50 55 60

0

G = 30dB, V

= 1V p-p

OUT

–10

–20

–30

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

1M 10M 100

Figure 33. Harmonic Distortion vs. Frequency

=

∞

IZ

=

∞

Iz

V

(V)

GAIN

Figure 31. Noise Figure vs. V

GAIN (dB)

Figure 32. Noise Figure vs. Gain

HILO = LO , HD3

FREQUENCY (Hz)

f = 10MHz, RS = 50ΩPREAMP LIMITED

GAIN

HILO = LO, R HILO = LO, R

HILO = HI, RIN = 50Ω HILO = HI, R

HILO = L O, HD2

HILO = HI, HD2

FB

HILO = HI, HD3

IN

FB

=

= 50Ω

=

∞

30

f = 10MHz,

= 1V p-p

V

OUT

–40

–50

–60

–70

HARMONIC DIST ORTIO N (dBc)

–80

03199-031

–90

0 200018001600140012001000800600400200

HILO = HI , HD2

HILO = HI , HD3

R

LOAD

Figure 34. Harmonic Distortion vs. R

40

f = 10MHz,

= 1V p-p

V

OUT

–50

–60

–70

HARMONIC DIST ORTIO N (dBc)

–80

03199-032

–90

0 10203040

HILO = LO, HD3

HILO = HI, HD2

C

LOAD

Figure 35. Harmonic Distortion vs. C

20

f = 10MHz, GAIN = 30d B

–40

HILO = LO, HD2

–60

HILO = HI, HD2

–80

HARMONIC DIST ORTIO N (dBc)

03199-033

–100

01234

V

(V p-p)

OUT

(Ω)

(pF)

HILO = L O, HD2

HILO = L O, HD3

03199-034

LOAD

HILO = L O, HD2

HILO = HI, HD3

03199-035

50

LOAD

HILO = LO, HD3

HILO = HI , HD3

03199-036

Figure 36. Harmonic Distortion vs. Differential Output Voltage

Rev. F | Page 16 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

0

V

= 1V p-p

OUT

–20

INPUT RANGE LIMITED WHEN

–40

HILO = LO

–60

–80

DISTORTION (dBc)

–100

–120

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

HILO = HI, HD3

HILO = L O, HD2

V

(V)

GAIN

Figure 37. Harmonic Distortion vs. V

HILO = L O, HD3

HILO = HI, HD2

, f = 1 MHz

GAIN

0

V

= 1V p-p

OUT

–20

INPUT RANGE LIMITED WHEN

–40

HILO = LO

–60

HILO = LO, HD2

HILO = L O, HD3

03199-037

0

V

= 1V p-p COMPOSITE (

OUT

G = 30dB

–10

–20

–30

–40

–50

IMD3 (dBc)

–60

–70

–80

–90

1M 10M 100M

f

+

f

)

1

2

FREQUENCY (Hz)

HILO = L O

HILO = HI

Figure 40. IMD3 vs. Frequency

40

10MHz HILO = HI

35

30

25

20

1MHz HILO = HI

1MHz HILO = LO

10MHz HILO = LO

03199-040

–80

DISTORTION (dBc)

HILO = HI , HD3

–100

–120

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

V

GAIN

(V)

Figure 38. Harmonic Distortion vs. V

HILO = HI, HD2

, f = 10 MHz

GAIN

10

0

f = 10MHz

–10

–20

IP1dB COMPRESSION (d Bm)

–30

–40

0 0.1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1. 0

HILO = HI

V

GAIN

Figure 39. IP1dB Compression vs. V

HILO = LO

(V)

GAIN

15

OUTPUT I P3 (dBm)

10

5

V

= 1V p-p COMPOSITE (

03199-038

0

010.90.80.70.60.50.40.30.20.1

OUT

Figure 41. Output Third-Order Intercept vs. V

V

GAIN

f

+

f

)

1

2

(V)

GAIN

03199-041

.0

2mV

100

90

10

0

50mV 10n s

03199-039

3199-042

Figure 42. Small Signal Pulse Response, G = 30 dB,

To

p: Input, Bottom: Output Voltage, HILO = HI or LO

Rev. F | Page 17 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

20mV

100

90

10

0

500mV 10ns

Figure 43. Large Signal Pulse Response, G = 30 dB,

H

ILO = HI or LO, Top: Input, Bottom: Output Voltage

2

G = 30dB

1

INPUT

(V)

0

OUT

V

CL = 0pF CL = 10pF CL = 22pF CL = 47pF

5.0

4.5

4.0

3.5

3.0

2.5

(V p-p)

OUT

2.0

V

1.5

1.0

3199-043

0.5

0

0545403530252015105

4

G = 40dB

3

2

1

INPUT

(V)

0

OUT

V

–1

HILO = HI

HILO = LO

R

(kΩ)

CLMP

Figure 46. Clamp Level vs. R

R

= 48.1kΩ

CLMP

R

= 16.5kΩ

CLMP

R

= 7.15kΩ

CLMP

R

= 2.67kΩ

CLMP

03199-046

0

CLMP

–1

INPUT IS NOT TO SCALE

–2

–50 50403020100–10–20–30–40

TIME (ns)

Figure 44. Large Signal Pulse Response for Various Capacitive Loads,

= 0 pF, 10 pF, 20 pF, 50 pF

C

L

500mV

200mV 400ns

3199-045

Figure 45. Pin GAIN Transient Response,

Top: V

, Bottom: Output Voltage

GAIN

–2

–3

03199-044

–4

–30–20–100 1020304050607080

TIME (ns)

Figure 47. Clamp Level Pulse Response for Four Values of R

03199-047

CLMP

200mV

100

90

10

0

Figure 48. LNA Overdrive Recovery, V

= 0.27 V VGA Output Shown

V

GAIN

100ns

0.05 V p-p to 1 V p-p Burst,

INH

3199-048

Rev. F | Page 18 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

1V

100

90

10

0

Figure 49. VGA Overdrive Recovery, V

= 1 V VGA Output Shown Attenuated by 24 dB

V

GAIN

1V

100

90

10

0

Figure 50. VGA Overdrive Recovery, V

= 1 V VGA Output Shown Attenuated by 24 dB

V

GAIN

2V

200mV 1ms

Figure 51. Enable Response, Top: V

100ns

4 mV p-p to 70 mV p-p Burst,

INH

100ns

4 mV p-p to 275 mV p-p Burst,

INH

, Bottom: V

ENB

OUT

, V

= 30 mV p-p

INH

2V

3199-049

1V 1ms

3199-052

Figure 52. Enable Response, Large Signal,

, Bottom: V

Top: V

ENB

0

–10

–20

–30

–40

PSRR (dB)

–50

–60

–70

3199-050

–80

100k 1M 10M 100M

VPSV, V

GAIN

, V

= 150 mV p-p

OUT

INH

VPS1, V

= 0.5V

FREQUENCY (Hz)

GAIN

VPS1, V

= 0.5V

GAIN

= 0V

03199-053

Figure 53. PSRR vs. Frequency (No Bypass Capacitor)

140

V

= 0.5V

GAIN

130

120

110

100

90

80

70

60

50

40

QUIESCENT S UPPLY CURRENT (mA)

3199-051

30

20

–40 100806040200–20

AD8334

AD8332

AD8331

TEMPERATURE ( °C)

03199-054

Figure 54. Quiescent Supply Current vs. Temperature

Rev. F | Page 19 of 60

AD8331/AD8332/AD8334

*

R

www.BDTIC.com/ADI

TEST CIRCUITS

MEASUREMENT CONSIDERATIONS

Figure 55 through Figure 68 show typical measurement configurations and proper interface values for measurements with 50 Ω conditions.

Short-circuit input noise measurements are made as shown in Figure 62. The input-referred noise level is determined by

FB*

120nH

22pF

FERRITE BEAD

Figure 55. Test Circuit—Gain and Ban

NETWORK ANALYZE

0.1µF

50Ω50Ω

18nF

270Ω

0.1µF

INH

DUT

0.1µF

LMD

NETWORK ANALYZER

di

viding the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels because a 50 Ω load is driven directly. The generator is removed when noise measurements are made.

INOUT

237Ω

28Ω

237Ω

28Ω

dwidth Measurements

1:1

3199-055

50Ω50Ω

INOUT

10kΩ

18nF

0.1µF

237Ω

FB*

120nH

22pF

0.1µF INH

LMD

0.1µF

NETWORK ANALYZ ER

0.1µF INH

LMD

0.1µF

DUT

VGN

0.1µF

28Ω

237Ω

28Ω

1:1

03199-056

r Various Matched Source Impedances

50Ω50Ω

INOUT

0.1µF

237Ω

DUT

0.1µF

VGN

28Ω

237Ω

28Ω

nse for Unterminated LNA, R

1:1

03199-057

= 50 Ω

S

10kΩ

*FERRITE BEAD

Figure 56. Test Circuit—Frequency Response fo

FB*

120nH

*FERRITE BEAD

Figure 57. Test Circuit—Frequency Respo

Rev. F | Page 20 of 60

AD8331/AD8332/AD8334

K

*

www.BDTIC.com/ADI

FB*

120nH

22pF

*FERRITE BEAD

NETWORK ANALYZ ER

18nF

0.1µF OR

1µF

INH

0.1µF

10kΩ

LNA

LMD

50Ω50Ω

0.1µF OR 1µF

INOUT

0.1µF

237Ω

0.1µF

237Ω

28Ω

1:1

03199-058

VGA

Figure 58. Test Circuit—Group Delay vs. Frequency for Two Values of AC Coupling

18nF

INH

270Ω

DUT

LMD

0.1µF

237Ω

28Ω

1:1

50Ω

03199-059

NETWORK ANALYZER

50Ω

120nH

OUT

*FERRITE BEAD

Figure 59. Test Circuit—LNA Input I

FB*

0.1µF

22pF

mpedance vs. Frequency in Standard and Smith Chart (S11) Formats

NETWORK ANALYZER

50Ω50Ω

INOUT

0.1µF

237Ω

28Ω

1:1

03199-060

FB*

120nH

*FERRITE BEAD

22pF

0.1µF INH

0.1µF

Figure 60. Test Circuit—Frequen

0.1µF

VGALNA

LMD

0.1µF

cy Response for Unterminated LNA, Single-Ended

NETWOR

ANALYZER

18nF

FB*

22pF

0.1µF INH

LMD

120nH

FERRITE BEAD

Figure 61. Test Circuit—Short-Ci

270Ω

DUT

0.1µF

237Ω

0.1µF

1:1

28Ω

rcuit, Input-Referred Noise

50Ω

IN

03199-061

Rev. F | Page 21 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

A

49.9Ω

50Ω

SIGNAL G ENERATOR

TO MEASURE G AIN

DISCONNECT F OR

NOISE MEASUREMENT

0.1µF

1Ω

FERRITE

BEAD

120nH

22pF

GAIN

INH

LMD

DUT

0.1µF

B

IN

1:1

SPECTRUM

ANALYZER

50Ω

03199-062

Figure 62. Test Circuit—Noise Figure

SPECTRUM

ANALYZER

50Ω

IN

03199-063

50Ω

LPF

SIGNAL GENERATOR

–6dB

0.1µF

22pF

18nF

AD8332

INH

270Ω

LMD

0.1µF

DUT

0.1µF

1kΩ

28Ω

1:1

–6dB

Figure 63. Test Circuit—Harmonic Distortion vs. Load Resistance

SPECTRUM

IN

ANALYZER

50Ω

03199-064

50Ω

LPF

SIGNAL GENERATOR

–6dB

0.1µF

22pF

18nF

AD8332

LMD

270Ω

DUT

0.1µF

237Ω

–6dB

28Ω

1:1

28Ω

Figure 64. Test Circuit—Harmonic Distortion vs. Load Capacitance

SPECTRUM

50Ω

–6dB

+22dB

–6dB

+22dB

SIGNAL

GENERATORS

COMBINER

–6dB

FB*

120nH

*FERRITE BEAD

22pF

0.1µF

18nF

INH

LMD

274Ω

DUT

0.1µF

237Ω

28Ω

1:1

237Ω

28Ω

–6dB

ANALYZER

INPUT

50Ω

03199-065

Figure 65.Test Circuit—IMD3 vs. Frequency

Rev. F | Page 22 of 60

AD8331/AD8332/AD8334

E

www.BDTIC.com/ADI

18nF

FB*

120nH

22pF

50Ω

*FERRITE BEAD

0.1µF

270Ω

INH

DUT

LMD

0.1µF

237Ω

28Ω

237Ω

28Ω

OSCILLO SCOPE

50Ω

IN

1:1

3199-066

Figure 66. Test Circuit—Pulse Response Measurements

18nF

FB*

120nH

22pF

50Ω

RF SIGNAL GENERATOR

*FERRITE BEAD

0.1µF

270Ω

INH

LMD

0.1µF

DUT

TO PIN GAIN OR PIN ENxx

0.1µF

255Ω

Figure 67. Test Circuit—Gain and Enable Transient Response

NETWO RK

ANALYZER

PROBE

OSCILLOSCOP

DIFF

PULSE

GENERATOR

CH1 CH2

9.5dB

50Ω

03199-067

FB*

120nH

22pF

50Ω

RF SIGNAL GENERATOR

*FERRITE BEAD

0.1µF

TO POWER

18nF

270Ω

INH

0.1µF

PINS

LMD

50Ω

0.1µF

DUT

0.1µF

255Ω

50Ω

INOUT

DIFF

PROBE

PROBE POWER

03199-068

Figure 68. Test Circuit—PSRR vs. Frequency

Rev. F | Page 23 of 60

AD8331/AD8332/AD8334

VINV

V

www.BDTIC.com/ADI

THEORY OF OPERATION

OVERVIEW

The AD8331/AD8332/AD8334 operate in the same way. Figure 69, Figure 70, and Figure 71 are functional block diagrams of

e three devices

th

INH

LMD

INH1

LMD1

LMD2

INH2

+

–

LNA

VCM

BIAS

IPLOPLON

–

ATTENUAT OR

+

VGA BIAS AND

INTERPOLATOR

–48dB

CM

V

MID

AD8331

ENBL

ENBV GAIN

Figure 69. AD8331 Functional Block Diagram

LON1 LOP1

+19dB

LNA 1

LNA 2

VCM BIAS

IP1

IN1

–

+

–

ATTENUATOR

–48dB

VGA BIAS AND

INTERPOLAT OR

ATTENUATOR

–48dB

AD8332

LON2 LO P2

VIP2

VIN2

ENB

Figure 70. AD8332 Functional Block Diagram

GAIN INT

CM1

V

MID

21dB

GAIN

INT

21dB

V

MID

VCM2

3.5dB/

15.5dB

PA21dB

CLAMP

3.5dB/

15.5dB

PA1

CLAMP

HILO

VOH

VOL

RCLMP

MODE

HILO

VOH1

VOL1

GAIN

VOH1

PA2

VOL1

RCLMP

LON1 LOP1VIP1VIN1 EN12

INH1

LMD1

LMD2

INH2

LON2

LOP2

VIP2

VIN2

MODE

VIN3

VIP3

03199-069

LOP3

LON3

INH3

LMD3

LMD4

INH4

LNA 1

LNA 2

LNA 3

LNA 4

VCM BIAS

VCM

BIAS

–

ATTENUATO R

–48dB

+

VGA BIAS AND

INTERPO LATOR

+

ATTENUATO R

–48dB

–

GAIN UP/

DOWN

–

ATTENUATO R

–48dB

+

VGA BIAS AND

INTERPO LATOR

+

ATTENUATO R

–48dB

–

AD8334

CM1

V

MID1

V

MID2

V

MID3

V

MID4

VCM4EN34VIN4VIP4LON4 LOP4

21dB

GAIN

INT

21dB

GAIN

INT

21dB

CLAMP

PA1

PA2

PA3

PA4

CLAMP

CLMP12

VOH1

VOL1

GAIN12

HILO VOL2

VOH2

VCM2

VCM3

VOH3

VOL3

GAIN34

VOL4

VOH4

CLMP34

03199-071

Figure 71. AD8334 Functional Block Diagram

Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain postamp with adjustable output voltage limiting. Figure 72 shows a simplified block diagram with external

03199-070

co

mponents.

INH

PREAMPLIFIER

19dB

LNA

LMD LOP

VCM BIAS

LON

VIN

SIGNAL PATH

48dB

ATTENUATOR

VIP

AND

BIAS

INTERPOLATOR

V

VCM

MID

POSTAMP

3.5dB/15.5dB

21dB

GAIN

INTERFACE

HILO

VOH

VOL

CLAMP

RCLMP

Figure 72. Simplified Block Diagram

Rev. F | Page 24 of 60

GAIN

03199-072

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

The linear-in-dB gain-control interface is trimmed for slope and absolute accuracy. The gain range is 48 dB, extending from

−4.5 dB to +43.5 dB in LO gain and +7.5 dB to +55.5 dB in HI gain mode. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V. Equation 1 and Equation 2 are the expressions for gain.

GAIN (dB) = 50 (dB/V) × V

− 6.5 dB, (HILO = LO) (1)

GAIN

or GAIN (dB) = 50 (dB/V) × V

+ 5.5 dB, (HILO = HI) (2)

GAIN

The ideal gain characteristics are shown in Figure 73.

60

50

40

30

HILO = HI

LOW NOISE AMPLIFIER (LNA)

Good noise performance in the AD8331/AD8332/AD8334 relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input matching.

A simplified schematic of the LNA is shown in Figure 74. INH

s capacitively coupled to the source. A bias generator

i establishes dc input bias voltages of 3.25 V and centers the output common-mode levels at 2.5 V. A capacitor C the same value as the input coupling capacitor C connected from the LMD pin to ground.

C

IZ

LOP

2.5V 2.5V

VPOS

R

IZ

LON

INH

LMD

) is

VGA

TO

(can be

20

GAIN (dB)

10

0

–10

0 0.2 0.4 0.6 0.8 1.0 1.1

ASCENDING GAIN MODE DESCENDING GAIN MODE

(WHERE AVAILABLE)

Figure 73. Ideal Gain Control Characteristics

HILO = LO

V

(V)

GAIN

03199-073

The gain slope is negative with MODE pulled high (where available), as follows:

GAIN (dB) = −50 (dB/V) × V

+ 45.5 dB, (HILO = LO) (3)

GAIN

or GAIN (dB) = −50 (dB/V) × V

+ 57.5 dB, (HILO = HI) (4)

GAIN

The LNA converts a single-ended input to a differential output w

ith a voltage gain of 19 dB. If only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain for a net gain range of −27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion.

The final stage is a logic programmable amplifier with gains of

3.5 dB o

r 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit ADC applications, in terms of output-referred noise and absolute gain range. Output voltage limiting can be programmed by the user.

I

C

INH

C

R

S

SH

Figure 74. Simplified LN

–a

3.25V 3.25V Q1 Q2

I

0

VCM

I

BIAS

A Schematic

I

0

–a

LMD

C

LMD

0

03199-074

The LNA supports differential output voltages as high as 5 V p-p, with positive and negative excursions of ±1.25 V, about a common-mode voltage of 2.5 V. Because the differential gain magnitude is 9, the maximum input signal before saturation is ±275 mV or +550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection.

Low value feedback resistors and the current-driving capability o

f the output stage allow the LNA to achieve a low input-referred voltage noise of 0.74 nV/√Hz. This is achieved with a current consumption of only 11 mA per channel (55 mW). On-chip resistor matching results in precise single-ended gains of 4.5× (9× differential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion.

Rev. F | Page 25 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

Active Impedance Matching

The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance, R

, is given in Equation 5, where A is the single-

IN

ended gain of 4.5, and 6 kΩ is the unterminated input impedance.

R

=

IN

C

is needed in series with RIZ because the dc levels at Pin LON

IZ

A

+

1

=

kΩ6

and Pin INH are unequal. Expressions for choosing R of R

and for choosing CIZ are found in the Applications

IN

Information section. C

and the ferrite bead enhance stability at

SH

R

×

kΩ6

IZIZ

(5)

R

+

kΩ33

IZ

in terms

IZ

higher frequencies, where the loop gain is diminished, and prevent peaking. Frequency response plots of the LNA are shown in

Figure 23 and Figure 24. The bandwidth is approximately

130 MH

z for matched input impedances of 50 Ω to 200 Ω and declines at higher source impedances. The unterminated bandwidth (when R

= ∞) is approximately 80 MHz.

IZ

Each output can drive external loads as low as 100 Ω in addition

o the 100 Ω input impedance of the VGA (200 Ω differential).

t Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a singleended driver for auxiliary circuits, such as those used for Doppler ultrasound imaging. Pin LON drives R

. Alternatively,

IZ

a differential external circuit can be driven from the two outputs in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications Information section should be carefully observed.

The impedance at each LNA output is 5 Ω. A 0.4 dB reduction

pen-circuit gain results when driving the VGA, and a 0.8 dB

in o reduction results with an additional 100 Ω load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 Ω on either side, a compensating load is recommended on the opposite output.

LNA Noise

The input-referred voltage noise sets an important limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain), including the VGA noise. The open-circuit current noise is

2.5 pA/√Hz. These measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in

Figure 75. Figure 76 and Figure 77 show simulations extracted from these r

esults and the 4.1 dB noise figure (NF) measurement with the

input actively matched to a 50 Ω source. Unterminated (R

=

IZ

∞) operation exhibits the lowest equivalent input noise and noise figure.

esistance, rising at low R

r compared to the source noise, and again at high R

Figure 76 shows the noise figure vs. source

, where the LNA voltage noise is large

S

due to

S

current noise. The VGA input-referred voltage noise of 2.7 nV/√Hz is included in all of the curves.

+

V

IN

–

+

V

IN

–

ACTIVE IMP EDANCE MATCH - RS = R

+

V

IN

–

Figure 75. Input Configurations

7

6

5

4

3

NOISE FI GURE (dB)

2

1

SIMULATION

0

50 100 1k

Figure 76. Noise Figure vs. R

Active Match, and Unterminated Inputs

7

INCLUDES NOISE OF VGA

6

5

4

3

NOISE FI GURE (dB)

2

1

(SIMULATED RESULTS)

0

50 100 1k

Figure 77. Noise Figure vs. R

UNTERMINATED

R

IN

R

S

RESISTIVE TERMINAT ION

R

IN

R

S

R

S

R

IN

R

S

R

IZ

RIN=

1 + 4.5

INCLUDES NOISE OF VGA

RESISTIVE TERMINAT ION

R

= 50Ω

IN

= 75Ω

R

IN

= 100Ω

R

IN

R

= 200Ω

IN

=

R

IZ

for Various Fixed Values of RIN, Actively Matched

S

= RIN)

(R

S

ACTIVE IM PEDANCE MATCH

UNTERMINATED

RS (Ω)

∞

RS (Ω)

V

IZ

V

for Resistive,

S

OUT

IN

OUT

03199-075

03199-076

03199-077

Rev. F | Page 26 of 60

AD8331/AD8332/AD8334

200Ω

www.BDTIC.com/ADI

The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 76 shows their relative NF performance. In this graph,

he input impedance is swept with R

t

to preserve the match at

S

each point. The noise figures for a source impedance of 50  are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200  are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.

Figure 77 is a plot of NF vs. R

for various values of RIN, which is

S

helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of 1.0 nV/√Hz, combined with a VGA with

3.75 nV/√Hz, yields a noise figure degradation of approximately

1.5 dB (for most input impedances), significantly worse than the AD8331/AD8332/AD8334 performance.

The equivalent input noise of the LNA is the same for singleen

ded and differential output applications. The LNA noise figure improves to 3.5 dB at 50 Ω without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recommended for stability purposes when driving external circuits on a separate board (see the lo

w noise applications, a ferrite bead is even more desirable.

Applications Information section). In

VARIABLE GAIN AMPLIFIER

The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 2.7 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 78.

GAIN

VIP

VIN

g

m

6dB

R

GAIN INTERPOLATOR

(BOTH CHANNELS)

2R

Figure 78. Simplified VGA S

48dB

chematic

POSTAMP

+

–

POSTAMP

03199-078

X-AMP VGA

The input of the VGA is a differential R-2R ladder attenuator network with 6 dB steps per stage and a net input impedance of 200 Ω differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the center tap connection of the ladder to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground.

The signal level at successive stages in the input attenuator fal

ls from 0 dB to −48 dB in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to

−48 dB. This circuit technique results in excellent linear-in-dB gain law conformance and low distortion levels and deviates ±0.2 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply.

The X-AMP inputs are part of a gain-of-12 feedback amplifier

t completes the VGA. Its bandwidth is 150 MHz. The input

tha stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across gain setting (see

Figure 12 and Figure 13).

Gain Control

Position along the VGA attenuator is controlled by a singleended analog control voltage, V

, with an input range of

GAIN

40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of V

beyond the control

GAIN

range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. Gain can be calculated using Equation 1 and Equation 2.

Gain accuracy is very good because both the scaling factor and

bsolute gain are factory trimmed. The overall accuracy relative

a to the theoretical gain expression is ±1 dB for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically ±0.2 dB. Gain matching between channels is better than 0.1 dB ( s

hows gain errors in the center of the control range). When

V

< 0.1 or > 0.95, gain errors are slightly greater.

GAIN

Figure 11

Rev. F | Page 27 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

The gain slope can be inverted, as shown in Figure 73 (except for the AD8332 AR models). The gain drops with a slope of

−50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin to HI gain mode.

Gain control response time is less than 750 ns to settle within 10%

f the final value for a change from minimum to maximum gain.

o

VGA Noise

In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC.

Output and input-referred noise as a function of V in Figure 25 and Figure 27 for the short-circuited input condit

ions. The input noise voltage is simply equal to the output noise

divided by the measured gain at each point in the control range. The output-referred noise is flat over most of the gain range

ecause it is dominated by the fixed output-referred noise of the

b VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and the noise of the source prevail. The inputreferred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small.

At lower gains, the input-referred noise, and thus noise figure, in

creases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC.

With its low output-referred noise levels, these devices ideally

ive low voltage ADCs. The converter noise floor drops 12 dB

dr for every two bits of resolution and drops at lower input fullscale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications Information section.

The preceding noise performance discussion applies to a dif

ferential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage because the contribution of its bias noise is designed to cancel in the differential signal. A transformer can be used with single-ended applications when low noise is desired.

are plotted

GAIN

Gain control noise is a concern in very low noise applications.

mal noise in the gain control interface can modulate the

Ther channel gain. The resultant noise is proportional to the output signal level and usually only evident when a large signal is present. Its effect is observable only in LO gain mode where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN input. An external RC filter can be used to remove V

source noise. The filter bandwidth should be

GAIN

sufficient to accommodate the desired control bandwidth.

Common-Mode Biasing

An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection because the VCM network makes a number of important connections internally, including the center tap of the VGA differential input attenuator, the feedback network of the VGA fixed gain amplifier, and the feedback network of the postamp in both gain settings. For best results, use a 1 nF capacitor and a 0.1 µF capacitor in parallel, with the 1 nF capacitor nearest to the VCM pin. Separate VCM pins are provided for each channel. For dc coupling to a 3 V ADC, the output common-mode voltage is adjusted to 1.5 V by biasing the VCM pin.

POSTAMPLIFIER

The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB (×6), set by the HILO logic pin. Figure 79 is a simplified block

agram.

di

Gm2

+

VOH

Gm1

F2

VCM

–

Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI gain mode and 300 V/µs in LO gain mode. The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel.

F1

Gm2

Gm1

Figure 79. Postamplifier Block Diagram

VOL

3199-079

Rev. F | Page 28 of 60

AD8331/AD8332/AD8334

V

www.BDTIC.com/ADI

Noise

The topology of the postamp provides constant input-referred n

oise with the two gain settings and variable output-referred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the output signal levels and noise floor appropriately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range.

Although the quantization noise floor of an ADC depends on a n

umber of factors, the 48 nV/√Hz and 178 nV/√Hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional technique, described in the

Applications Information section, can extend the noise floor

ev

en lower for possible use with 14-bit ADCs.

Output Clamping

Outputs are internally limited to a level of 4.5 V p-p differential when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resistor from R

to ground. Tab le 8 shows a list of recommended

CLMP

resistor values.

Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels, and the user should adjust the clamp resistor accordingly. For additional information, see the

Applications Information section.

The accuracy of the clamping levels is approximately ±5% in LO

r HI mode. Figure 80 illustrates the output characteristics for a

o fe

w values of R

5.0

4.5

4.0

3.5

3.0

(V)

OL

2.5

,

OH

2.0

V

1.5

1.0

0.5

0

–3 –2 – 1 0 1 2 3

.

CLMP

R

=

∞

CLMP

8.8kΩ

3.5kΩ

R

= 1.86kΩ

CLMP

3.5kΩ

8.8kΩ

R

=

∞

CLMP

V

(V)

INH

Figure 80. Output Clamping Characteristics

03199-080

Rev. F | Page 29 of 60

AD8331/AD8332/AD8334

V

A

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

LNA—EXTERNAL COMPONENTS

The LMD pin (connected to the bias circuitry) must be bypassed to ground and signal sourced to the INH pin, which is capacitively coupled using 2.2 nF to 0.1 F capacitors (see Figure 81).

The unterminated input impedance of the LNA is 6 k. The

er can synthesize any LNA input resistance between 50  and

us 6 k. R Table 7.

Table 7. LNA External Component Values for Common Source Impe

RIN (Ω) RIZ (Nearest STD 1% Value, Ω) CSH (pF)

50 280 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k None 6 k

When active input termination is used, a decoupling capacitor (C the LNA.

The shunt input capacitor, C frequencies where the active termination match is lost due to the gain roll-off of the LNA at high frequencies. The value of C capacitor is required. Suggested values for C 200 Ω are shown in Table 7 .

When a long trace to Pin INH is unavoidable, or if both LNA o with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or equivalent). Other values can prove useful.

Figure 82 shows the interconnection details of the LNA output. C inputs is required because of the differences in their dc levels and the need to eliminate the offset of the LNA. Capacitor values of 0.1 µF are recommended. There is a 0.4 dB loss in gain between the LNA output and the VGA input due to the 5 Ω output resistance. Additional loading at the LOP and LON outputs affects LNA gain.

is calculated according to Equation 6 or selected from

IZ

)

(

kΩ33 ×

R

IN

=

R

IZ

–kΩ6

(6)

()

R

IN

dances

∞

) is required to isolate the input and output bias voltages of

IS

, reduces gain peaking at higher

SH

diminishes as RIN increases to 500 Ω, at which point no

SH

for 50 Ω ≤ RIN ≤

SH

None

utputs drive external circuits, a small ferrite bead (FB) in series

apacitive coupling between the LNA outputs and the VGA

C

LMD

0.1µF

1

LMD2

2

INH2

+5V

3

VPS2

4

LON2

5

LOP2

6

COM2

7

10

11

12

13

14

8

9

VIP2

VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

*SEE TEXT

GAIN

1nF0.1µF

1nF

1nF0.1µF

Figure 81. Basic Connections for a Ty

3.25V

C

SH

LNA

3.25V

FB

28

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

27

26

25

24

23

22

21

20

19

18

17

16

15

1nF

C

*

C

IZ

*

R

IZ

1nF

LNA OUT

0.1µF

5V

1nF

5V

*

VGA OUT

*

VGA OUT

0.1µF

pical Channel (AD8332 Shown)

LN

DECOUPLING

R

RESISTO R

IZ

2.5V

5Ω

LON

LOP

5Ω

VCM

LNA

DECOUPLING

RESISTO R

VIP

VIN

*

SH

0.1µF

5V

50Ω

0.1µF

5V

0.1µF

TO EXT

CIRCUIT

100Ω

TO EXT

CIRCUIT

LNA

SOURCE

Figure 82. Interconnections of the LNA and VGA

Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is routed to a remote PC board, it tolerates a load capacitance up to 100 pF with the addition of a 49.9 Ω series resistor or ferrite 75 Ω/100 MHz bead.

03199-081

03199-082

Rev. F | Page 30 of 60

AD8331/AD8332/AD8334

–

www.BDTIC.com/ADI

Gain Input

The GAIN pin is common to both channels of the AD8332. The input impedance is nominally 10 MΩ, and a bypass capacitor from 100 pF to 1 nF is recommended.

Parallel connected devices can be driven by a common voltage

ource or DAC. Decoupling should take into account any

s bandwidth considerations of the drive waveform, using the total distributed capacitance.

If gain control noise in LO gain mode becomes a factor, maint

aining ≤15 nV/√Hz noise at the GAIN pin ensures satisfactory noise performance. Internal noise prevails below 15 nV/√Hz at the GAIN pin. Gain control noise is negligible in HI gain mode.

VCM Input

The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH defaults to 2.5 V dc. With output ac-coupled applications, the VCM pin is unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. The VGA outputs can be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and

3.5 V can be realized at Pin VOH and Pin VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board.

The voltage on the VCM pin is sourced by an internal buffer wi

th an output impedance of 30 Ω and a ±2 mA default output current (see Figure 83). If the VCM pin is driven from an ext

ernal source, its output impedance should be <<30 Ω, and its current drive capability should be >>2 mA. If the VCM pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a common-mode voltage other than 2.5 V is used, a voltage-limiting resistor, R

, is needed to protect against

CLMP

overload.

INTERNAL

2mA MAX

AC GROUNDING FO R INTERNAL CIRCUI TRY

CIRCUITRY

30Ω

Figure 83. VCM Interface

VCM

100pF

RO << 30Ω

0.1µF

NEW V

CM

03199-083

Logic Inputs—ENB, MODE, and HILO

The input impedance of all enable pins is nominally 25 kΩ and can be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. The enable pin, ENB, powers down the VGA; when pulled low, the VGA output voltages are near ground. Multiple devices can be driven from a common source. Consult

ation about circuit functions controlled by the enable pins.

m

Table 3, Ta ble 4, Tab le 5 , and Table 6 for infor-

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It is ei

ther connected to ground or pulled up to 5 V, depending on

the desired gain range and output noise.

Optional Output Voltage Limiting

The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground (see

or a list of several voltage levels and corresponding resistor

f

Table 8

values). Unconnected, the default limiting level is 4.5 V p-p. Note that third harmonic distortion increases as waveform

plitudes approach clipping. For lowest distortion, the clamp

am level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution is determined experimentally. a

s a function of the limiting level for a 2 V p-p output signal.

Figure 84 shows third harmonic distortion

A wider limiting level is desirable in HI gain mode.

20

V

= 0.75V

GAIN

–30

–40

–50

HD3 (dBc)

–60

–70

–80

1.52.02.53.0 4.03.5 4.5 5.0

Figure 84. HD3 vs. Clamping Level for

CLAMP LIMIT LEVEL (V p-p)

HILO = LO

HILO = HI

03199-084

2 V p-p Differential Input

Table 8. Clamp Resistor Values

Clamp Resistor Value (kΩ)

Clamp Level (V p-p)

HILO = LO HILO = HI

0.5 1.21

1.0 2.74 2.21

1.5 4.75

2.0 7.5

2.5 11

3.0 16.9

3.5 26.7

4.0 49.9

4.02

6.49

9.53

14.7

23.2

39.2

4.4 100 73.2

Output Decoupling

When driving capacitive loads greater than about 10 pF, or long circuit connections on other boards, an output network of resistors and/or ferrite beads can be useful to ensure stability. These components can be incorporated into a Nyquist filter such as the one shown in val

ue is 84.5 Ω. For example, all the evaluation boards for this

Figure 81. In Figure 81, the resistor

series incorporate 100  in parallel with a 120 nH bead. Lower value resistors are permissible for applications with nearby loads

Rev. F | Page 31 of 60

AD8331/AD8332/AD8334

X

www.BDTIC.com/ADI

or with gains less than 40 dB. The exact values of these components can be selected empirically.

An antialiasing noise filter is typically used with an ADC. Filter r

equirements are application dependent.

When the ADC resides on a separate board, the majority of f

ilter components should be placed nearby to suppress noise picked up between boards and to mitigate charge kickback from the ADC inputs. Any series resistance beyond that required for output stability should be placed on the ADC board. sh

ows a second-order, low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC.

OPTIONAL

BACKPLANE

84.5Ω

0.1µF

1.5µH

158Ω

18pF

Figure 85. 20 MHz Second-Order, Low-Pass Filter

DRIVING ADCs

The output drive accommodates a wide range of ADCs. The noise floor requirements of the VGA depend on a number of application factors, including bit resolution, sampling rate, fullscale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range can be adjusted by selecting HI or LO gain mode.

The relative noise and distortion performance of the two gain m

odes can be compared in Figure 25 and Figure 31 through Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is s

uited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC fullscale voltages as high as 4 V p-p. Because distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 36), it is possible to lower the output-referred noise even

urther by using a resistive attenuator (or transformer) at the

f output. The circuit in Figure 86 has an output full-scale range of 2 V p-p

, a gain range of −10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit ADC applications.

4V p-p DIFF,

48nV/ Hz

VOH

VOL

Figure 86. Adjusting the Noise Floor for 14-Bit ADCs

187Ω

2:1

187Ω

2V p-p DIFF,

24nV/ Hz

374Ω

LPF

AD6644

OVERLOAD

These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced.

ADC

Figure 85

ADC

03199-085

03199-086

Signals larger than ±275 mV at the LNA input are clipped to 5 V p-p dif s

hows the response to a 1 V p-p input burst. The symmetric

ferential prior to the input of the VGA. Figure 48

overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as ±2.5 V without triggering the slow-settling ESD input protection diodes.

Both stages of the VGA are susceptible to overload. Postamp-

ier limiting is more common and results in the clean-limited

lif output characteristics found in

es. The graph in Figure 87 summarizes the combinations of

cas

put signal and gain that lead to the different types of overload.

in

43.5

GAIN (dB)

–4.5

OVERLOAD

1m

POSTAMP

INPUT AMP LITUDE (V)

15mV

LO GAIN

MODE

-AMP

OVERLOAD

25mV

0.2750.110m

Figure 49. Recovery is fast in all

POSTAMP

OVERLOAD

56.5

29dB

24.5dB

GAIN (dB)

LNA OVERLOAD

7.5

1

1m 0.2750.110m 1

OVERLOAD

4mV

25mV

HI GAIN

MODE

INPUT AMPLITUDE (V)

-AMP

41dB

24.5dB

LNA OVERLOAD

Figure 87. Overload Gain and Signal Conditions

The clamp interface mentioned in the Output Clamping section controls the maximum output swing of the postamp and its overload response . When the clamp feature is not used, the output level defaults to approximately 4.5 V p-p differential centered at 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of R

should be

CLMP

selected for graceful overload. A value of 8.3 kΩ or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode). This limits the output swing to just above 2 V p-p differential.

OPTIONAL INPUT OVERLOAD PROTECTION

Applications in which high transients are applied to the LNA input can benefit from the use of clamp diodes. A pair of backto-back Schottky diodes can reduce these transients to manageable levels.

Figure 88 illustrates how such a diode-protection scheme

n be connected.

ca

OPTIONAL SCHOTT KY OVERLOAD

CLAMP

231

BAS40-04

0.1µF

FB

C

R

SH

C

SH

2

3

4

INH

VPSL

LON

IZ

R

IZ

Figure 88. Input Overload Clamping

COMM

ENBL

20

19

03199-088

03199-087

Rev. F | Page 32 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

When selecting overload protection, the important parameters are forward and reverse voltages and t BAS40-04 series shown in Figure 88 has a τ

(or τrr). The Infineon

rr

of 100 ps and a VF

rr

of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs.

LAYOUT, GROUNDING, AND BYPASSING

Due to their excellent high frequency characteristics, these devices are sensitive to their PCB environments. Realizing expected performance requires attention to detail critical to good high speed board design.

A multilayer board with power and ground planes is recomm

ended with blank areas in the signal layers filled with ground plane. Be certain that the power and ground pins provided for robust power distribution to the device are connected. Decouple the power supply pins with surface-mount capacitors as close as possible to each pin to minimize impedance paths to ground. Decouple the LNA power pins from the VGA supply using ferrite beads. Together with the capacitors, ferrite beads eliminate undesired high frequencies without reducing the headroom. Use a larger value capacitor for every 10 chips to 20 chips to decouple residual low frequency noise. To minimize voltage drops, use a 5 V regulator for the VGA array.

Several critical LNA areas require special care. The LON and

output traces must be as short as possible before connecting

LOP to the coupling capacitors connected to Pin VIN and Pin VIP. R

must be placed near the LON pin as well. Resistors must be

IZ

placed as close as possible to the VGA output pins, VOL and VOH, to mitigate loading effects of connecting traces. Values are discussed in the Output Decoupling section.

Signal traces must be short and direct to avoid parasitic effects. W

herever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance.

MULTIPLE INPUT MATCHING

Matching of multiple sources with dissimilar impedances can be accomplished as shown in Figure 89. A relay and low supply volt

age analog switch can be used to select between multiple sources and their associated feedback resistors. An ADG736 d

ual SPDT switch is shown in this example; however, multiple

switches are also available and users are referred to the

evices Selection Guide for switches and multiplexers.

D

Analog

ADG736

1.13kΩ

SELECT R

IZ

280Ω

LON

5Ω

LOP

5Ω

03199-090

200Ω

50Ω

0.1µF

18nF

INH

LMD

AD8332

LNA

Figure 89. Accommodating Multiple Sources

DISABLING THE LNA

Where accessible, connection of the LNA enable pin to ground powers down the LNA, resulting in a current reduction of about half. In this mode, the LNA input and output pins can be left unconnected; however, the power must be connected to all the supply pins for the disabling circuit to function.

lustrates the connections using AD8331 as an example.

il

20

COMM

19

ENBL

18

ENBV

17

COMM

16

VOL

15

VOH

14

VPOS +5V

13

HILO

12

RCLMP

+5V

0.1µF

VIN

0.1µF

MODE

NC

1

2

3

4

5

6

7

8

9

LMD

AD8331

INH

VPSL

LON

LOP

COML

VIP

VIN

MODE

+5V

VOUT

Figure 90

HILO

R

CLMP

GAIN

10

Figure 90. Disabling the LNA

Rev. F | Page 33 of 60

GAIN

VCM

11

VCM

03199-089

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

ULTRASOUND TGC APPLICATION

The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications because it provides the means for echolocation of reflected ultrasound energy.

Figure 91 through Figure 93 are schematics of a dual, fully dif

ferential system using the AD8332 and the AD9238 12-bit

h

igh speed ADC with conversion speeds as high as 65 MSPS.

HIGH DENSITY QUAD LAYOUT

The AD8334 is the ideal solution for applications with limited board space. Figure 94 represents four channels routed to and

ay from this very compact quad VGA. Note that none of the

aw signal paths crosses and that all four channels are spaced apart to eliminate crosstalk.

In this example, all of the components shown are Size 0402;

owever, the same layout is executable at the expense of slightly

h more board area. The sketch also assumes that both sides of the printed circuit board are available for components and that the bypass and power supply decoupling circuitry is located on the wiring side of the board.

Rev. F | Page 34 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

TP3

(RED)

TP4

L19 SAT

L20 SAT

+5V

120nH FB

FILTER

C67 SAT

+

C46 1µF

L7

+5VGA

L6

+5VLNA

JP13

L17

SAT

JP12

L18

SAT

TB1 +5V

(BLACK)

TB2

GND

OPTIONAL 4-POLE LOW-PASS

VIN+B

C66 SAT

–B

V

IN

CFB2

18nF

RFB2

274Ω

C51

0.1µF

VCM1

TP2 GAIN

TP7 GND

R3

(R

CLMP

JP8

DC2H

C54

0.1µF

C55

0.1µF

JP7

DC2L

E

)

S3

IN2

C50

0.1µF

L12 120nH FB

22pF

0.1µF

C83 1nF

C69

0.1µF

120nH FB

TP5

C80

+5VLNA

C41

C53

0.1µF

C48

0.1µF

R27

100Ω

L11

L10

R26

100Ω

0.1µF

C68 1nF

C49

JP5

IN2

C74 1nF

C78

1nF

AD8332ARU

1

LMD2

2

INH2

3

VPS2

4

LON2

5

LOP2

6

COM2

7

VIP2

8

VIN2

9

VCM2

10

GAIN

11

RCLMP

12

VOH2

13

VOL2

14

COMM

+5VGA

C45

0.1µF

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

C85 1nF

28

27

26

+5VLNA

25

24

23

22

21

20

C77

1nF

19

+5VGA

18

17

16

15

C70

0.1µF

JP6

IN1

ENABLE JP16 DISABLE

120nH FB

120nF FB

22pF

C42

0.1µF

C43

0.1µF

R24

100Ω

L9

L8

R25

100Ω

C79

VCM1

120nH FB

CFB1 18nF

RFB1 274Ω

C59

0.1µF

C58

0.1µF

JP10

L13

+5VGA

HI GAIN JP10 LO GAIN

JP9

C56

TP6

C60

0.1µF

OPTIONAL 4-POLE LOW-PASS

JP17

L1

SAT

L14

SAT

FILTER

C64

SAT

S1

E

L15 SAT

L16

SAT

IN1

VIN+A

C65 SAT

VIN–A

03199-091

Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238

Rev. F | Page 35 of 60

AD8331/AD8332/AD8334

V

www.BDTIC.com/ADI

ADP3339AKC-3.3

+5V

312

OUT

IN

S2

EXT CLOCK

R17

49.9Ω

+3.3VCLK

C86

0.1µF

V

DD

20MHz

GND

SG-636PCE

OUT

TAB

OUT

2

R1

L5

120nH FB

L4

120nH FB

L3

120nH FB

L2

120nH FB

C31

0.1µF

C30

0.1µF

C29

0.1µF

C1

0.1µF

VIN+_A

V

–_A

IN

C35

0.1µF

C36

0.1µF

R12

1.5kΩ

R4

1.5kΩ

C33

10µF

6.3V

+

R5

33Ω

R6

33Ω

C17

0.1µF

GND

C44 1µF

+

VREF

R20

4.7kΩ

U5

74VHC04

U5

10µF

6.3V

1.5kΩ1. 5kΩ

ADCLK

8965

C34

C20

0.1µF

JP11JP3

4.7kΩ

TP 12

TP 13

JP1

33Ω

R41

1

R8

R7

DATA

CLK

C39

10µF

C16

0.1µF

2

C38

0.1µF

C37

0.1µF

VIN–_B

V

+_B

+3.3VCLK

JP4

3

2

EXT

1

INT

R18 499Ω

R16 5kΩ

R19 499Ω

C63

0.1µF

C47

+

10µF

6.3V

14

OE

3

IN

ADCLK

U5

74VHC04

4312

U5

74VHC04

U6

U5

74VHC04

1213

SPARES

U5

74VHC04

1011

C2

10µF

6.3V

C40

0.1µF

TP9

C32

0.1µF

C62

18pF

C19 1nF

R9 0Ω

3

+3.3VADDIG

C61

18pF

C18 1nF

+

C15 1nF

+3.3VAVDD

+

C52

10nF

C12 10µF

6.3V

C57

10nF

DNC

D0_B

D1_B

D2_B

D3_B

D4_B

D5_B

C26

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

C22

0.1µF

AGND

VIN+_A

VIN–_A

AGND

AVDD

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD

AGND

VIN–_B

VIN+_B

AGND

AVDD

CLK_B

DCS

DFS

PDWN_B

OEB_B

DNC

D0_B

D1_B

D2_B

DRGND

DRVDD

D3_B

D4_B

D5_B

C24 1nF

C21 1nF

AVDD

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

OTR_A

D11_A (MSB)

D10_A

D9_A

D8_A

DRGND

DRVDD

D7_A

D6_A

D5_A

D4_A

U1 A/D CONVERTER AD9238

D3_A

D2_A

D1_A

D0_A

DNC

DRVDD

DRGND

OTR_B

D11_B (MSB)

D10_B

D9_B

D8_B

D7_B

D6_B

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

ADCLK

R10 0Ω

4.7kΩ

R15 0Ω

R11 100Ω

JP2

SHARED

REF

Y

R14

+3.3VADDIG

OTR_A

D11_A

D10_A

D9_A

D8_A

C23

0.1µF

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

C13 1nF

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

N

+3.3VADDIG

C25 1nF

C14

0.1µF

C11

+

10µF

6.3V

03199-092

Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238

Rev. F | Page 36 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

OTR_A

D11_A

D10_A

D9_A

D8_A

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DATACLKA

22 × 4

1

RP 9

2

3

4

1

22 × 4

RP 10

2

3

4

1

22 × 4

RP 11

2

3

4

1

22 × 4

RP 12

2

3

4

1

G1

74VHC541

19

G2

2

8

A1

7

3

A2

6

4

A3

5

A4

8

6

A5

7

A6

6

8

A7

5

9

A8

1

G1

74VHC541

19

G2

8

2

A1

3

7

A2

6

4

A3

5

A4

8

6

A5

7

A6

8

6

A7

5

9

A8

U10

U7

VCC

GND

VCC

GND

20

+

10

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

C3

0.1µF

C28 10µF

6.3V

+3.3VDVDD

20

10

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

C8

0.1µF

C10

0.1µF

+

C76 10µF

6.3V

R40 22Ω

22 × 4

18

RP 1

7

2

6

3

54

18

22 × 4

RP2

7

2

6

3

54

18

22 × 4

RP 3

7

2

6

3

54

18

22 × 4

RP 4

7

2

6

3

54

2

4

6

8

10

12

14

HEADER UP MALE NO SHROUD

16

18

20

22

24

26 25

28 27

30

34

36

38

40

SAM080UPM

1

3

5

7

9

11

13

15

17

19

21

23

29

3132

33

35

37

39

+3.3VDVDD

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

D5_B

D4_B

D3_B

D2_B

D1_B

D0_B

DNC

19

8

1

22 × 4

RP 13

7

2

6

3

5

4

22 × 4

8

1

RP 14

7

2

6

3

5

4

18

22 × 4

RP 15

19

7

2

6

3

5

4

22 × 4

8

1

RP 16

7

2

6

3

5

4

DATACLK

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

G1

74VHC541

G2

A1

A2

A3

A4

A5

A6

A7

A8

G1

74VHC541

G2

A1

A2

A3

A4

A5

A6

A7

A8

20

U2

VCC

10

GND

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

+3.3VDVDD

20

VCC

U3

10

GND

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

++

C7

0.1µFC90.1µF

C4

0.1µFC50.1µFC60.1µF

C27 10µF

6.3V

+

C75 10µF

6.3V

22 × 4

18

RP 5

2

3

22 × 4

1

RP 6

2

3

18

22 × 4

RP 7

2

3

18

22 × 4

RP 8

2

3

R39

22Ω

7

6

54

8

7

6

54

7

6

54

7

6

54

42

44

46

48 47

52

54 53

56 55

58

60

62

64

66

68

70

72

74

76

78

80

SAM080UPM

41

43

45

4950

51

HEADER UP MALE NO SHROUD

57

59

61

63

65

67

69

71

73

75

77

79

03199-093

Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238

Rev. F | Page 37 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

CH3 LNA INPUT

CH4 LNA INPUT

16

INH3

COM3

COM4

INH4

20

LMD4

21

COM4X

22 23 24

LON4

LOP4

VIP4

VIN4

VPS4

GAIN34

2825 26 2717 18 19

CLMP34

29

HILO

30 31 32

VCM4

VCM3

COM34

NC

CH2 LNA INPUT

CH1 LNA INPUT

15

14

13912

LON3

COM3X

LMD3

VOH4

VPS34

VOL4

11

10

VIN3

VIP3

LOP3

COM34

VOH3

VOL3

VPS3

NC

LOCATED ON WIRING S IDE

8

7

6

514

LOP2

VIP2

VIN2

VPS2

POWER SUPPLY DECOUPLI NG

AD8334

COM12

MODE

VOH2

VOL2

3

2

INH2

LMD2

COM2X

LON2

COM1X

GAIN12

CLMP12

VPS12

VOL1

COM12

VOH1

COM2

COM1

INH1

LMD1

LON1

LOP1

VIP1

VIN1

VPS1

EN12

EN34

VCM1

VCM2

64

58 575962 61 6063

50 4956 55 5154 53 52

47

46

CH1 DIFFERENT IAL

OUTPUT

03199-094

35

36

37

34

33

CH4 DIFFERENT IAL

OUTPUT

384239

CH3 DIFFERENT IAL

OUTPUT

40

41

43

CH2 DIFFERENT IAL

OUTPUT

45

44

Figure 94. Compact Signal Path and Board Layout for the AD8334

Rev. F | Page 38 of 60

48

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8331 EVALUATION BOARD

GENERAL DESCRIPTION

The AD8331 evaluation board is a platform for testing and evaluating the AD8331 variable gain amplifier (VGA). The board is provided completely assembled and tested; the user simply connects an input signal, V supply. The AD8331-EVALZ is lead free and RoHS compliant.

USER-SUPPLIED OPTIONAL COMPONENTS

As shown in the schematic in Figure 96, the board provides for optional components. The components shown in black are for typical operation, and the components shown in gray are installed at the user’s discretion.

As shipped, the LNA input impedance of the AD8331-EVALZ is c

onfigured for 50  to accommodate most signal generators and network analyzers. Input impedances up to 6 kΩ are realized by changing the values of RFB and CSH. Refer to the Theory of Operation section for details on this circuit feature.

e Tab le 9 for typical values of input impedance and corres-

Se

onding components.

p

Table 9. LNA External Component Values for Common Source Impe

RIN (Ω) RFB (Ω, Nearest 1% Value) CSH (pF)

50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k None 6 k ∞ None

The board is designed for Size 0603 surface-mount components. Back-to-back diodes can be installed at Location D3 if desired.

To evaluate the LNA as a standalone amplifier, install optional

MA connectors LON and LOP and capacitors C1 and C2;

S typical values are 0.1 µF or smaller. At R4 and R8, 0  resistors are installed unless capacitive loads larger than 10 pF are connected to the SMA connectors LON and LOP (such as coaxial cables). In that event, small value resistors (68  to 100 ) must be installed at R4 and R8 to preserve the stability of the amplifier.

A resistor can be inserted at RCLMP if output clamping is desir

ed. Refer to Table 8 for appropriate values.

dances

sources, and a 5 V power

GAIN

Figure 95. AD8331-EVALZ Top View

MEASUREMENT SETUP

The basic board connection for measuring bandwidth is shown in Figure 97. A 5 V, 100 mA minimum power supply and a low

oise, voltage reference supply for GAIN are required. Table 10

n lis

ts jumpers, and Figure 97 shows their functions and positions.

The preferred signal detection method is a differential probe co

nnected to VO, as shown in Figure 97. Single-ended loads can

e connected using the board edge SMA connector, VOH. Be sure

b to take into account the 25.8 dB attenuation incurred when using the board in this manner. For connection to an ADC, the 270  series resistors can be replaced with 0  or other appropriate values.

Table 10. Jumper Functions

Jumper Function

ENBL Enables the LNA when inserted in the top position ENBV Enables the VGA when inserted in the top position W5, W6 Connects the AD8331 outputs to the SMA connectors Mode

HI_LO Top, HI gain; bottom, LO gain (shown in HI gain position)

Bottom, gain increases with V

GAIN

with V

; top, gain decreases

GAIN

03199-195

BOARD LAYOUT

The evaluation board circuitry uses four conductor layers. The two inner layers are grounded, and all interconnecting circuitry is located on the outer layers. Figure 99 to Figure 102 illustrate t

he copper patterns. Table 11 provides a parts list.

Rev. F | Page 39 of 60

AD8331/AD8332/AD8334

V

www.BDTIC.com/ADI

AD8331 EVALUATION BOARD SCHEMATICS

+5

GND

GND2GND1 GND3 GND4

CLMD

+C3

0.1µF

10µF

INH

231

L1

120nH FB

D2 PROBE

LON

LOP

+5V

R4

R8

C

INH

0.1µF

CSH

22pF

120nH FB

C1

LO

C2

W1

MODE

L2

C16

0.1µF

10V

0.1µF

+5V DOWN

UP

CFB

0.018µF

RFB 274Ω

0.1µF

C14

C6

1

LMD

2

INH

DUT

AD8331ARQ

3

VPS

4

LON

5

LOP

6

COML

7

VIP

8

VIN

9

MODE CLMP

20

COMM

+5V

EN

LNA

19

ENBL

18

ENBV

17

COMM

120nH FB

16

VOL

100Ω

15

VOH

120nH FB

14

VPOS +5V

13

HILO

12

L3

R44

R43

L4

+5V

C35

0.1µF

HI

HI_LO

LO

VGA

DIS

W5

VO

W6

C32

0.1µF

RCLMP

+5V

EN

DIS

C24

0.1µF

C26

0.1µF

L5

120nH FB

R16

237Ω

R20

237Ω

1:1

T1

VOH

10

GAIN

NOTES

1. COMPONENTS IN GREY ARE OPTIO NAL AND USER SUPPLIED.

C34 1nF

GAIN

VCM

11

C18

0.1µF

Figure 96. Schematic of the AD8331 Evaluation Board

VCM

03199-196

Rev. F | Page 40 of 60

AD8331/AD8332/AD8334

A

www.BDTIC.com/ADI

DP 8200 PREC ISION VOL TAGE REF EREN CE

(FOR VGAIN)

NALYZER

4395

GND

ENABLE

SELECT UP OR

DOW N GA IN

SLOPE

ENABLE

LNA

VGA

HI/LO GAIN

SELECT GA IN

Figure 97. AD8331—Typical Board Test Connections

1103 T EKPRO BE

POW ER SUPPL Y

POWER SUPPLY

+5 V

GND

DIFFERENTIAL PROBE TO VO PINS

INSER T JUM PERS W5 A ND W6 TO USE OUTPUT TRANSFORMER AND VOH SMA

E3631 A

03199-197

Rev. F | Page 41 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8331 EVALUATION BOARD PCB LAYERS

Figure 98. AD8331-EVALZ Assembly

03199-201

03199-198

Figure 101. Internal Layer Ground

03199-199

Figure 99. Primary Side

Figure 100. Second

Copper

ary Side Copper

Figure 102. Power Plane

03199-200

Figure 103. Top Silkscreen

03199-202

03199-203

Rev. F | Page 42 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8331 BILL OF MATERIALS

Table 11.

Manufacturer

Qty Reference Designator Description Manufacturer

5 L1, L2, L3, L4, L5 Ferrite bead, 120 nH, 0603 inductor Murata BLM18BA750SN1D 1 RFB SM, 274 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF2740V 2 R16, R20 SM, 237 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF2370V 2 R43, R44 SM, 100 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF1000V 1 CFB 0.018 F, 10%, X7R, 0603 capacitor Panasonic ECJ-1VB1E183K 10

C6, C14, C16, C18, C24,

C26, C32, C35, C 1 C34 1000 pF, 50 V, 0603 capacitor Panasonic ECJ-1VB2A102K 1 C3 10 F, 10 V tantalum capacitor Nichicon F931A106MAA 6

HI_LO (HI), MODE (UP), ENBL (EN),

NBV (EN), W5, W6

E 1 CSH 22 pF, 50 V, 0603 capacitor Panasonic ECJ-1VC1H220J 1 T1 RF, 0.015 MHz to 300 MHz transformer Mini-Circuits T1-6T KK81 4 Four corners of the board

1 DUT Integrated circuit, variable gain amplifier Analog Devices AD8331ARQZ 3 VO, W5, W6 2-pin header/connector FCI 4 ENBL, ENBV, HI_LO, MODE fixed 3-pin header/connector Molex 22-11-2032 2 INH, VOH SMA, right angle PC mount/connector Amphenol 901-143-6RFX 1 +5 V 0.125” diameter, red loop test point Components Corp. TP-104-01-02 5 GND, GND1, GND2, GND3, GND4 0.125” diameter, black loop test point Components Corp. TP-104-01-00 1 VCM fixed 0.125” diameter, purple loop test point Components Corp. TP-104-01-07

1

FCI = Framatome Connectors International

, CLMD

INH

0.1 µF, 50 V, 0603 capacitor Kemet C0603C104K4RAC

Mini-jump jumper/shunt FCI

Bumper used as feet, mounted on wiring side of the boar

d

1

3M SJ-67A11

1

P

art Number

65474-001

69157-102

Rev. F | Page 43 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8332 EVALUATION BOARD

GENERAL DESCRIPTION

The AD8332-EVALZ is a platform for the testing and evaluation of the AD8332 variable gain amplifier (VGA). The board is shipped assembled and tested, and users need only connect the signal and VGAIN sources to a single 5 V power supply.

graph of the component side of the board, and Figure 105

photo

hows the schematic. The AD8332-EVALZ is lead free and

s RoHS compliant.

Figure 104 is a

Table 12. LNA External Component Values for Common Source Impe

RIN (Ω) R

50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k None 6 k

SMA connectors, S2, S3, S6, and S7, are provided for access to the LNA outputs or the VGA inputs. If the LNA is used alone,

0.1 μF coupling capacitors can be installed at the C5, C9, C23, and C24 locations. Resistors of 68 Ω to 100 Ω may be required if the load capacitances, as seen by the LNA outputs, are larger than approximately 10 pF.

A resistor can be inserted at RCLMP if output clamping is desired. T

he peak-to-peak clamping level is adjusted by installing one of

the standard 1% resistor values listed in A high frequency differential probe connected to the 2-pin headers,

Ox, is the preferred method to observe a waveform at the

V VGA output. A typical setup is shown in

d loads can be connected directly via the board edge SMA

ende connectors. Note that the AD8332 output amplifier is buffered with 237 Ω resistors; therefore, be sure to compensate for attenuation if low impedances are connected to the output SMAs.

dances

, R

FB1

∞

(Ω Std 1% Value) C

FB2

, C

(pF)

SH1

SH2

None

Table 8 .

Figure 106. Single-

03199-095

Figure 104. AD8332-EVALZ Top View

USER-SUPPLIED OPTIONAL COMPONENTS

The board is built and tested using the components shown in black in Figure 105. Provisions are made for optional compon-

nts (shown in gray) that can be installed for testing at user

e discretion. The default LNA input impedance is 50 Ω to match various signal generators and network analyzers. Input impedances up to 6 kΩ are realized by changing the values of RFBx and CSHx. For reference,

lues and corresponding adjustments. The board is designed

va for Size 0603 surface-mount components.

Table 1 2 lists the common input impedance

MEASUREMENT SETUP

The basic board connections for measuring bandwidth are shown in Figure 106. A 5 V, 100 mA (minimum) power supply

equired, and a low noise voltage reference supply is required

is r for VGAIN.

BOARD LAYOUT

The evaluation board circuitry uses four conductor layers. The two inner layers are power and ground planes, and all interconnecting circuitry is located on the outer layers. Figure 108 to

Figure 111 illustrate the copper patterns.

Rev. F | Page 44 of 60

AD8331/AD8332/AD8334

V

www.BDTIC.com/ADI

EVALUATION BOARD SCHEMATICS

+5

GND GND4GND3GND2GND1

VOH2

+

C25

10µF

LNA2

T2 1:1

L1

120nH FB

L8

120nH FB

+5V

C9

C5

R13

237Ω

R14

237Ω

R10

R12

0.1µF

+5VLNA

C11

C12

S6

LON2

S7

LOP2

COMPONENTS IN GRAY ARE OPTIONAL AND USER SUPPLI ED.

C4

0.1µF

CAL2

W8

TP3

CLAMP

RCLMP

W12

VO2

W13

0.1µF

C16

0.1µF

W6

CSH2 22pF

C6

VCM2

GAIN

0.1µF

1nF

120nH FB

R7

100Ω

R8

100Ω

120nH FB

1

LMD2

2

INH2

3

VPS2

AD8332ARUZ

4

LON2

5

LOP2

6

COM2

7

VIP2

8

VIN2

9

VCM2

10

GAIN

11

RCLMP

12

VOH2

13

VOL2

14 15

COMM

0.1µF

CFB2

18nF

RFB2

274Ω

C14

0.1µF

C8

C20

0.1µF

L3

L4

C2

C10

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

C22

0.1µF

28

27

26

25

24

23

22

21

20

19

18

17

16

C1

0.1µF

CFB1 18nF

RFB1

274Ω

C13

0.1µF

C17

0.1µF

W5

L6

120nH FB

R5

100Ω

R6

100Ω

L5

120nH FB

L7

CSH1

22pF

+5V

HI

LO

W4

C7

0.1µF

C15

0.1µF

VCM1

W9

+5V

ENABLE

DISABLE

W7 VO1

+5V

0.1µF

CAL1

R11

W10

W11

C3

120nH FB

+5VLNA

R9

C19

0.1µF

C18

0.1µF

C23

C24

L2

LNA1

S2

LON1

S3

LOP1

R15

237Ω

R16

237Ω

1:1

T1

VOH1

3199-096

Figure 105. Schematic of the AD8332 Evaluation Board

Rev. F | Page 45 of 60

AD8331/AD8332/AD8334

K

www.BDTIC.com/ADI

SUPPLY FOR

VGAIN

NETWOR

ANALYZER

1103 TEKPROBE POWER SUPPLY

DIFFERENTIAL

PROBE

Figure 106. AD8332—Typical Board Test Connections

03199-097

Rev. F | Page 46 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8332 EVALUATION BOARD PCB LAYERS

03199-101

Figure 107. AD8332-EVALZ Assembly

03199-098

Figure 110. Ground Plane

Figure 108. Primary Side C

Figure 109. Second

ary Side Copper

opper

03199-099

03199-100

Rev. F | Page 47 of 60

Figure 111. Power Plane

Figure 112. Component Side Silkscreen

3199-102

03199-103

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8332 BILL OF MATERIALS

Table 13.

Manufacturer

Qty Reference Designator Description Manufacturer

8 L1, L2, L3, L4, L5, L6, L7, L8 Ferrite Bead, 120 nH, 0603 inductor Murata BLM18BA750SN1D 2 RFB1, RFB2 SM, 274 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF2740V 4 R13, R14, R15, R16 SM, 237 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF2370V 4 R5, R6, R7, R8 SM, 100 Ω, 1%, 1/10 W, 0603 resistor Panasonic ERJ-3EKF1000V 2 CFB1, CFB2 SM, 18 nF, 10%, 50 V, 0603 capacitor Panasonic ECJ-1VB1E183K 18

1 C8 SM, 1 nF, 50 V, 0603 capacitor Panasonic ECJ-1VB2A102K 2 CSH1, CSH2 SM, 22 pF, 50 V, 0603 capacitor Panasonic ECJ-1VC1H220J 1 C25 SM, 10 µF, 10 V Tantalum capacitor Nichicon F931A106MAA 2 T1, T2 RF, 0.015 MHz to 300 MHz transformer Mini-Circuits T1-6T KK81 6 W6VO2, W7VO1, W10, W11, W12, W13 2-pin header/connector Molex 22-10-2021 2 W4, W5 3-pin header/connector Molex 22-10-2031 4 LNA1, LNA2, VOH1, VOH2 SMA, right angle PC mount/connector Amphenol 901-143-6RFX 4 VCM1, VCM2, GAIN, CLAMP 0.125” diameter purple loop test point Components Corp. TP104-01-07 1 +5 V 0.125” red loop test point Components Corp. TP104-01-02 5 GND, GND1, GND2, GND3, GND4 0.125” black loop test point Components Corp. TP104-01-00 1 DUT

C1, C2, C3, C4, C6, C7, C10, C11, C12, C13,

C15, C16, C17, C18, C19, C20, C22

C14,

SM, 0.1 µF, 10%, 0603 capacitor Kemet C0603C104K4RAC

Integrated circuit, dual channel variable gain amplifier

Analog Devices AD8332ARUZ

P

art Number

Rev. F | Page 48 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8334 EVALUATION BOARD

GENERAL DESCRIPTION

The AD8334-EVALZ is a platform for the testing and evaluation of the AD8334 variable gain amplifier (VGA). The board is shipped assembled and tested, and users need only connect the

signal and VGAIN sources and a single 5 V power supply. Figure 113 is a photograph of the board. The AD8334-EVALZ is

ad free and RoHS compliant.

le

Figure 113. AD8334-EVALZ Top View

Rev. F | Page 49 of 60

03199-104

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

CONFIGURING THE INPUT IMPEDANCE

The board is built and tested using the components shown in black in Figure 114. Provisions are made for optional

omponents (shown in gray) that can be installed at user

c discretion. As shipped, the input impedances of the low noise amplifiers (LNAs) are configured for 50 Ω to match the output impedances of most signal generators and network analyzers. Input impedances up to 6 kΩ can be realized by changing the values of the feedback resistors, R capacitors, C6, C8, C10, and C12. For reference, Ta ble 14 lists st

andard values of 1% resistors for some typical values of input impedance. Of course, if the user has determined that the source impedance falls between these values, the feedback resistor value can be calculated accordingly. Note that the board is designed to accept standard surface-mount, size 0603 components.

Table 14. LNA External Component Values for Common Source Impe

RIN (Ω) R

50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k No capacitor 6 k No resistor No capacitor

dances

, R

FB1

FB2

, R

FB3

, R

FB1

(Ω, ±1%) C6, C8, C10, C12 (pF)

FB4

FB2, RFB3

, R

FB4

, and shunt

east effect on the performance of the device of any detection

l method tried. The probe can also be used for monitoring input signals at IN1, IN2, IN3, or IN4. It can be used for probing other circuit nodes; however, be aware that the 200 kΩ input impedance can affect certain circuits.

Differential-to-single-ended transformers are provided for

gle-ended output connections. Note that series resistors are

sin provided to protect against accidental output overload should a 50 Ω load be connected to the connector. Of course, the effect of these resistors is to limit the bandwidth. If the load connected to the SMA is >500 Ω, the 237 Ω series resistors, RX1, RX2, RX3, RX4, RX5, RX6, RX7, and RX8, can be replaced with 0 Ω values.

Driving the VGA from an External Source or Using the LNA to Drive an External Load

Appropriate components can be installed if the user wants to drive the VGA directly from an external source or to evaluate the LNA output. If the LNA is used to drive off-board loads or cables, small value series resistors (47 Ω to 100 Ω) are recommended for LNA decoupling. These can be installed in the R10, R11, R14, R15, R18, R19, R22, and R23 spaces.

Provisions are made for surface-mount SMA connectors that

n be used for driving from either direction. If the LNA is not

ca used, it is recommended that the capacitors, C16, C17, C21, C22, C26, C27, C31, and C32, be carefully removed to avoid driving the outputs of the LNAs.

Using the Clamp Circuit

The board is shipped with no resistors installed in the spaces provided for clamp-circuit operation. Note that each pair of channels shares a clamp resistor. If the output clamping is desired, the resistors are installed in R49 and R50. The peak-topeak clamping level is application dependent.

Viewing Signals

The preferred signal detector is a high impedance differential probe, such as the Tektronix P6247, 1 GHz differential probe, connected to the 2-pin headers (VO1, VO2, VO3, or VO4), as shown in

Figure 116. The low capacitance of this probe has the

Figure 114. AD8334-EVALZ Assembly

MEASUREMENT SETUP

The basic board connections for measuring bandwidth are shown in Figure 116. A 5 V, 200 mA (minimum) power supply is r

equired, and a low noise voltage reference supply is required

for VGAIN.

BOARD LAYOUT

The evaluation board circuitry uses four conductor layers. The two inner layers are ground, and all interconnecting circuitry is located on the outer layers. Figure 117 to Figure 120 illustrate t

he copper patterns, and Tabl e 15 lists the evaluation board

pa

rts.

03199-105

Rev. F | Page 50 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

EVALUATION BOARD SCHEMATICS

IN3

2

22 pF

C10

0.1µF C3

IN4

2

0.1µF

L8

120nH

LON4

1

R22

CB7

LO4

1

0.1µF

LOP4

NOTES:

1. COMPONENTS IN GRAY ARE OPTIO NAL USER SUPPLIED.

2. IN1 TO IN4 ARE OPEN HO LES TO BE USED TO ANCHO R A SCOPE PROBE.

3. NC = NO CONNECT .

R23

CB8

1

+5V

22 pF

C11

CFB4

18nF

274Ω

RFB4

0.1µF

C32

12 0 nH

L4

GAIN34

R50

1

HI

J12

LO

+5V

120nH

100Ω

L17

0.1µF

237Ω

R43

100Ω

RX8

J8

C51

RX7

J7

0.1µF C49

237Ω

R41

T4VO 4

VOH4

03199-106

C31

120nH

COM3

C12

COM4

INH4

20

LMD4

C4

0.1µF

COM4X

LON4

23

LOP4

24

VIP 4

25 26 2717 18 19 21 22

VIN4

0.1µF

VPS 4

C13

GAIN34

1nF

C80

28 29

0.1µF

CLMP34

C55

HILO

30 3 1 3 2

VCM4

C64

0.1µF

VCM 3

3

NC

C62

0.1µF

L16

C77

0.1µF 120nH

+5V

LON3

INH3

1

120nH

L6

R19

0.1µF C9

1

CFB3

18 nF

RFB3

274

Ω

15

16

14

LM D 3

INH3

COM34

VO H4

34

33

13912

LO N3

CO M3 X

VP S34

VOL4

35

36

LOP3

+5 V

CB 6

1

CB 5

1

C27

120nH

0.1µF C71

0.1µF C26

11

10

VPS 3

VIP3

VIN3

LO3

R18

1

0.1µF

LO P3

CO MM 34

VO H3

VOL3

37

384239

NC

40

3

U

120nH

100Ω

RX6

L15

L34

J6

0.1µF C46

237Ω

R38

T3VO 3

120nH

100Ω

RX5

J5

0.1µF C44

237Ω

R36

VOH3

Figure 115.Schematic of the AD8334 Evaluation Board

LOP2

+5 V

1

120nH

L2

L3

0.1µF C69

R15

0.1µF

8

7

VPS 2

6

VIP2

VIN2

AD8334

CB 4

1

C22

C21

1

LO2

LO P2

1

514

LON2

1

CB 3

1

R14

1

RFB2

274Ω

0.1µF

C2

3

CO M2 X

LO N2

IN2

LM D 2

2

INH2

120nH

0.1µF

CF B2

18 nF

22 pF

C8

INH2

COM2

COM1

INH1

LMD1

COM1X

LON1

LOP1

VIP 1

VIN1

VPS1

GAIN12

CLMP12

10 µF

C14

+

L7

+5V

C7

64

22 pF

63

C6

0.1 µF

C1

5962 61 60

IN1

2

0.1µF C5

CFB1

18 nF

R1 0

274Ω

RFB1

1

R11

58

0.1µF C16

57

0.1µF

1nF

C82

0.1µF

C67

12

C53

1

0.1µF C17

12 0 nH

L1

R4 9

GAIN

1

EN12

GND1 GND2 GND3 GND6GND5GND4

12 0 nH

L5

INH1

CB 1

LON1

1

LO1

1

LOP1

1

CB2

1

+5V

EN12

D

C57

E

+5V

E

D

EN34

120nH

100Ω

L10

RX2

120nH

100Ω

RX1

L9

EN34

COM12

MO DE

41

D

+5V

J11

120nH

L14

L13

VO H2

VOL2

434645

44

10 0Ω

RX4

VP SV2

VO H1

VOL1

47

120nH

100Ω

RX3

COM12

L11

VCM 1

VCM 2

48

50 4 956 55 5154 53 52

0.1µF

C59

0.1µF

0.1µF C75

120nH FB

J4

0.1µF C41

237Ω

R33

J3

0.1µF C39

237Ω

R31

T2VO 2

+5V

L12

J2

0.1µF C36

237Ω

R28

J1

0.1µF C34

23 7Ω

R26

T1VO 1

VOH1

VOH2

Rev. F | Page 51 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

PRECISION VOLTAGE

REFERENCE (FO R VGAIN)

GAIN

CONTROL

VOLTAGE

GND

NETWORK ANALYZER

SIGNAL

INPUT

PROBE POWER SUPPLY

DIFFERENTIAL

PROBE

+5V

POWER SUPPLY

GND

03199-107

Figure 116. AD8334—Typical Board Test Connections (One Channel Shown)

Rev. F | Page 52 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

AD8334 EVALUATION BOARD PCB LAYERS

03199-108

03199-110

Figure 117. Component Side Copper

03199-109

Figure 118. Wiring Side Copper

Figure 119. Inner Layer 1

Figure 120. Inner Layer 2

03199-111

Rev. F | Page 53 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

03199-112

Figure 121. Component Side Silkscreen

AD8334 BILL OF MATERIALS

Table 15.

Qty Reference Designator Description Manufacturer

1 +5 V 0.125” diameter, red loop test point Components Corp. TP-104-01-02 6 GND1 to GND6 0.125” diameter, black loop test point Components Corp. TP-104-01-00 2 GAIN12, GAIN34 0.125” diameter, purple loop test point Components Corp. TP-104-01-07 36

4 C6, C8, C10, C12 22 pF, 5%, 50 V, 0603 capacitor Panasonic ECJ-1VC1H220J 2 C80, C82 1 nF, 10%, 100 V, 0603 capacitor Panasonic ECJ-1VB2A102K 4 CFB1, CFB2, CFB3, CFB4 18 nF, 0603 capacitor Panasonic ECJ-1VB1E183K 12 J1, J2, J3, J4, J5, J6, J7, J8, VO1, VO2, VO3, VO4 0.1” 2-pin header FCI 69157-102 8 INHI1 to INHI4, VOH1 to VOH4 SMA, right angle PC mount/connector Amphenol 901-143-6RFX 18

8 R26, R28, R31, R33, R36, R38, R41, R43 237 Ω, 1%, 1/10W, 0603 resistor Panasonic ERJ-3EKF2370V 4 RFB1, RFB2, RFB3, RFB4 274 Ω, 1%, 1/10W, 0603 resistor Panasonic ERJ-3EKF2740V 8 RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8 100 Ω, 1%, 1/10W, 0603 resistor Panasonic ERJ-3EKF1000V 4 EN12, EN34, J11, J12 0.1” 3-pin header/connector Molex 22-10-2031 4 T1, T2, T3, T4 RF, 0.015 MHz to 300 MHz transformer Mini-Circuits T1-6T KK81 1 U1 Integrated circuit, quad VGA Analog Devices AD8334ACPZ 4 Four corners

12

1 C14 10 μF, 10 V, A size tantalum capacitor Nichicon F931A106MAA

1

C1, C2, C3, C4, C5, C7, C9, C11, C13, C16, C17, C21, C22, C26, C27, C31, C32, C34, C36, C39, C41, C44, C46, C49, C51, C53, C55, C57, C59, C62, C64, C67, C69, C71, C75, C77

L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, L17, L34

J1 to J8, J11 (up), J12 (high), EN12 (lower position), EN34 (lower position)

FCI = Framatome Connectors International

0.1 μF, 16 V, 0603 capacitor Kemet C0603C104K4RAC

Ferrite bead, 120 nH, 0603 inductor Murata BLM18BA750SN1D

Bumper foot, mounted to wiring side of the board

Mini-jump jumper/shunt FCI

Manufacturer Part Number

3M SJ-67A11

1

65474-001

Rev. F | Page 54 of 60

AD8331/AD8332/AD8334

C

Y

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

9.80

9.70

9.60

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8° 0°

0.75

0.60

0.45

141

Figure 122. 28-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-28)

Dimensions shown in millimeters

0.345 (8.76)

0.341 (8.66)

0.337 (8.55)

20

1

11

10

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

0.065 (1.65)

0.049 (1.25)

0.010 (0.25)

0.004 (0.10)

COPLANARITY

0.004 (0.10)

0.069 (1.75)

0.053 (1.35)

SEATING

0.025 (0.64) BSC

CONTROLLING DIMENSIO NS ARE IN I NCHES ; M ILLIMETERS DIMENSIO NS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.012 (0.30)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MO-137-AD

PLANE

0.010 (0.25)

0.006 (0.15)

8° 0°

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

0.041 (1.04) REF

012808-A

Figure 123. 20-Lead Shrink Small Outline Package (QSOP)

(RQ-20)

Dimensions shown in Inches and (millimeters

Rev. F | Page 55 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

5.00

BSC SQ

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

3.50 REF

PIN 1

32

1

8

9

INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

THE EXPOSE D PAD I S NOT CONNECTED INTERNALL Y . FOR INCREASE D RE LIABILI TY OF THE SOL DER JO INTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOM ME NDE D THAT THE PAD BE SOLDERED TO THE GROUND PLANE.

0.60 MAX

0.50

4.75

BSC SQ

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD- 2

BSC

0.50

0.40

0.30

COPLANARITY

Figure 124. 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

041806-A

1.00

0.85

0.80

SEATING

PLANE

12° MAX

9.00

BSC SQ

PIN 1 INDICATOR

VIEW

TOP

49

48

33

32

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

7.50 REF

0.80 MAX

0.65 TYP

0.50 BSC

0.60 MAX

8.75

BSC SQ

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

*

COMPLIANT TO JEDEC S TANDARDS MO-220-VM MD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 125. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

0.30

0.25

0.18

64

17

PIN 1 INDICATOR

1

*

4.85

4.70 SQ

4.55

16

THE EXPOSED PAD IS NOT CONNECTED INTERNALL Y. F O R INCRE ASE D REL I ABI L I TY OF THE S OLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMM E NDED THAT THE PAD BE SOLDERED TO THE GROUND PL ANE .

063006-B

Rev. F | Page 56 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8331ARQ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQ-REEL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQ-REEL7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ1 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ-RL1 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ-R71 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331-EVALZ1 Evaluation Board with AD8331ARQ AD8332ACP-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACP-REEL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACP-REEL7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-R21 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-R71 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-RL1 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ARU –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARU-REEL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARU-REEL7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ1 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ-R71 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ-RL1 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332-EVALZ1 Evaluation Board with AD8332ARU AD8334ACPZ1 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334ACPZ-REEL1 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334ACPZ-REEL71 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334-EVALZ1 Evaluation Board with AD8334ACP

1

Z = RoHS Compliant Part.

Rev. F | Page 57 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

NOTES

Rev. F | Page 58 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

NOTES

Rev. F | Page 59 of 60

AD8331/AD8332/AD8334

www.BDTIC.com/ADI

NOTES

Rev. F | Page 60 of 60

Datasheet AD8332 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

MEASUREMENT CONSIDERATIONS

THEORY OF OPERATION

OVERVIEW

LOW NOISE AMPLIFIER (LNA)

Active Impedance Matching

LNA Noise

VARIABLE GAIN AMPLIFIER

X-AMP VGA

Gain Control

VGA Noise

Common-Mode Biasing

POSTAMPLIFIER

Noise

Output Clamping

APPLICATIONS INFORMATION

LNA—EXTERNAL COMPONENTS

Gain Input

VCM Input

Logic Inputs—ENB, MODE, and HILO

Optional Output Voltage Limiting

Output Decoupling

DRIVING ADCs

OVERLOAD

OPTIONAL INPUT OVERLOAD PROTECTION

LAYOUT, GROUNDING, AND BYPASSING

MULTIPLE INPUT MATCHING

DISABLING THE LNA

ULTRASOUND TGC APPLICATION

HIGH DENSITY QUAD LAYOUT

AD8331 EVALUATION BOARD

GENERAL DESCRIPTION

USER-SUPPLIED OPTIONAL COMPONENTS

MEASUREMENT SETUP

BOARD LAYOUT

AD8331 EVALUATION BOARD SCHEMATICS

AD8331 EVALUATION BOARD PCB LAYERS

AD8331 BILL OF MATERIALS

AD8332 EVALUATION BOARD

GENERAL DESCRIPTION

USER-SUPPLIED OPTIONAL COMPONENTS

MEASUREMENT SETUP

BOARD LAYOUT

EVALUATION BOARD SCHEMATICS

AD8332 EVALUATION BOARD PCB LAYERS

AD8332 BILL OF MATERIALS

AD8334 EVALUATION BOARD

GENERAL DESCRIPTION

CONFIGURING THE INPUT IMPEDANCE

Driving the VGA from an External Source or Using the LNA to Drive an External Load

Using the Clamp Circuit

Viewing Signals

MEASUREMENT SETUP

BOARD LAYOUT

EVALUATION BOARD SCHEMATICS

AD8334 EVALUATION BOARD PCB LAYERS

AD8334 BILL OF MATERIALS

OUTLINE DIMENSIONS

ORDERING GUIDE