Analog Devices AD8331 2 c Datasheet

Ultralow Noise VGAs with

FEATURES

Ultralow noise preamplifier

Voltage noise = 0.74 nV/√Hz

Current noise = 2.5 pA/√Hz
3 dB bandwidth: 120 MHz
Low power: 125 mW/channel
Wide gain range with programmable postamp

–4.5 dB to +43.5 dB

+7.5 dB to +55.5 dB
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
Available in space-saving chip scale package

APPLICATIONS

Ultrasound and sonar time-gain control
High performance AGC systems
I/Q signal processing
High speed dual ADC driver

GENERAL DESCRIPTION

The AD8331/AD8332 are single- and dual-channel ultralow
noise, linear-in-dB, variable gain amplifiers. Although optimized
for ultrasound systems, they are usable as low noise variable
gain elements at frequencies up to 120 MHz.

Each channel consists of an ultralow noise preamplifier (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamplifier with adjustable output limiting. The LNA gain is
19 dB with a single-ended input and differential outputs capable
of accurate, programmable active input impedance matching by
selecting an external feedback resistor. Active impedance
control optimizes noise performance for applications that
benefit from input matching.

The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching. Differential
signal paths lead to superb second and third order distortion
performance and low crosstalk.

Preamplifier and Programmable R

IN

AD8331/AD8332

FUNCTIONAL BLOCK DIAGRAM

VPSV

VIN1VIP1LOP1LON1

[(–48 to 0) + 21] dB

–

+

+

–

VIN2VIP2LOP2LON2

COMM

VGA 1

BIAS AND

INTERPOLATOR

VGA 2

ENB

V

MID

VPS1

COM1

INH1

LMD1

LMD2

INH2

VPS2

COM2

25 24 22 21 15 20 9 19

26

23

+19dB

+

27

LNA 1
–

28

BIAS

(V

)

MID

1

–

LNA 2

+

2

3

6

4 5 7 8 14 18 11

Figure 1. AD8332 Shown 28-Lead TSSOP

50

40

30

)

20

B
d

(
N

I

10

A
G

0

–10

–20

100k

V

= 1V

GAIN

0.8V

0.6V

0.4V

0.2V

0V

1M 1G100M10M

FREQUENCY (Hz)

Figure 2. Frequency Response vs. Gain

The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier may
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output may be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.

The operating temperature range is –40°C to +85°. The
AD8331 is available in a 20-lead QSOP package, and the
AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They
require a single 5 V supply, and the quiescent power
consumption is 125 mW/ch. A power-down (enable) pin is
provided.

3.5dB/15.5dB

POST
AMP1

POST
AMP2

CLAMP

RCLMP

GAIN

INT

HILOVCM2VCM1

VOH1

17

16

VOL1

10

GAIN

13

VOL2

12

VOH2

03199-B-001

03199-C-002

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8331/AD8332

TABLE OF CONTENTS

REVISION HISTORY.................................................................. 2

AD8331, AD8332—Specifications.................................................. 3

Absolute Maximum Ratings............................................................ 6

ESD CAUTION ............................................................................ 6

AD8331, AD8332—Typical Performance Characteristics .......... 7

Test Circuits..................................................................................... 15

Theory of Operation...................................................................... 17

Overview...................................................................................... 17

Low Noise Amplifier (LNA)...................................................... 17

Variable Gain Amplifier............................................................. 19

Postamplifier............................................................................... 21

Applications..................................................................................... 22

LNA – External Components................................................... 22

Driving ADCs ............................................................................. 24

Overload...................................................................................... 24

Optional Input Overload Protection. ...................................... 25

Layout, Grounding, And Bypassing......................................... 25

Multiple Input Matching........................................................... 25

Disabling the LNA...................................................................... 25

Measurement Considerations................................................... 26

Ultrasound TGC Application ................................................... 26

Pin Configuration and Function Descriptions........................... 30

AD8331........................................................................................ 30

AD8332........................................................................................ 31

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

Revision C

11/03—Data Sheet Changed from REV. B to REV. C

Addition of New Part...........................................................Universal

Changes to Figures ...............................................................Universal

Updated Outline Dimensions..........................................................32

5/03—Data Sheet Changed from REV. A to REV. B

Edits to Ordering Guide....................................................................32

Edits to Ultrasound TGC Application section................................25

Added Figure 71, Figure 72, and Figure 73......................................26

Updated Outline Dimensions............................................................31

2/03—Data Sheet Changed from REV. 0 to REV. A

Edits to Ordering Guide.....................................................................32

Rev. C | Page 2 of 32

AD8331/AD8332

AD8331, AD8332—SPECIFICATIONS

Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R

pin floating, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

V

CM

Parameter Conditions Min Typ Max Unit

LNA CHARACTERISTICS

Gain

Single-Ended Input
to Differential Output

Input to Output (Single-Ended) 13 dB

Input Voltage Range AC-Coupled ±275 mV

R

Input Resistance

280 Ω 50 Ω

FB =

R

= 412 Ω 75 Ω

FB

R

562 Ω 100 Ω

FB =

R

1.13 kΩ 200 Ω

FB =

R

∞ 6 kΩ

FB =

Input Capacitance 13 pF
Output Impedance Single-Ended, Either Output 5 Ω
–3 dB Small Signal Bandwidth V

= 0.2 V p-p 130 MHz

OUT

Slew Rate 650 V/µs
Input Voltage Noise

= 0 Ω, HI or LO Gain,

R

S

= ∞, f = 5 MHz

R

FB

Input Current Noise RFB = ∞, HI or LO Gain, f = 5 MHz 2.5 pA/√Hz
Noise Figure f = 10 MHz, LOP Output

Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RFB = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2

HD2 –56 dBc
HD3

= 0.5 V p-p,

V

OUT

Single-Ended, f = 10 MHz

Output Short-Circuit Current Pins LON, LOP 165 mA

LNA + VGA CHARACTERISTICS

–3 dB Small Signal Bandwidth V
–3 dB Large Signal Bandwidth V

= 0.2 V p-p 120 MHz

OUT

= 2 V p-p 110 MHz

OUT

LO Gain 300 V/µs Slew Rate
HI Gain 1200 V/µs

Input Voltage Noise

Noise Figure V

Active Termination Match

= 0 Ω, HI or LO Gain,

R

S

R

= ∞, f = 5 MHz

FB

= 1.0 V

GAIN

RS = RIN = 50 Ω,
f = 10 MHz, Measured

R

= RIN = 200 Ω,

S

f = 5 MHz, Simulated

Unterminated

RS = 50 Ω, RFB = ∞,
f = 10 MHz, Measured

R

= 200 Ω, RFB = ∞,

S

f = 5 MHz, Simulated
V

= 0.5 V, LO Gain 48 nV/√Hz Output-Referred Noise

GAIN

V

= 0.5 V, HI Gain 178 nV/√Hz

GAIN

Output Impedance, Postamplifier DC to 1 MHz 1 Ω
Output Signal Range, Postamplifier

≥ 500 Ω,

R

L

Unclamped, Either Pin

Differential 4.5 V p-p

Output Offset Voltage

Differential –50 ±5 +50 mV

V

GAIN

= 0.5 V

Common-Mode

Output Short-Circuit Current 45 mA

= ∞, CL = 1 pF,

CLMP

19 dB

0.74 nV/√Hz

–70 dBc

0.82 nV/√Hz

4.15 dB

2.0 dB

2.5 dB

1.0 dB

V

± 1.125 V

CM

–125 –25 +100 mV

Rev. C | Page 3 of 32

AD8331/AD8332

Parameter Conditions Min Typ Max Unit

Harmonic Distortion V

HD2 –88 dBc
HD3
HD2 –68 dBc

HD3
Input 1 dB Compression Point V
Two-Tone Intermodulation

Distortion (IMD3)

Channel-to-Channel Crosstalk
(AD8332)
Overload Recovery

Group Delay Variation 5 MHz < f < 50 MHz, Full Gain Range ±2 ns

ACCURACY

Absolute Gain Error2

Gain Law Conformance3 0.1 V < V
Channel-to-Channel Gain Matching 0.1 V < V

GAIN CONTROL INTERFACE
(Pin GAIN)

Gain Scaling Factor 0.10 V < V

Input Voltage (V

) Range 0 to 1.0 V

GAIN

Input Impedance 10 MΩ
Response Time 48 dB Gain Change to 90% Full Scale 750 ns

COMMON-MODE INTERFACE
(Pin VCMn)

Input Resistance Current Limited to ±1 mA 30 Ω
Output CM Offset Voltage VCM = 2.5 V –125 –25 +100 mV
Voltage Range

= 0.5 V, V

GAIN

f = 1 MHz

f = 10 MHz

= 0.25 V, V

GAIN

V

= 0.72 V, V

GAIN

= 0.5 V, V

V

GAIN

V

= 0.5 V, V

GAIN

V

= 0.5 V, V

GAIN

V

= 0.5 V, V

GAIN

= 1.0 V,

V

GAIN

= 50 mV p-p/1 V p-p,

V

IN

= 1 V p-p

OUT

–85 dBc

–65 dBc

= 1 V p-p, f = 1 MHz–10 MHz 7 dBm1

OUT

= 1 V p-p, f = 1 MHz –80 dBc

OUT

= 1 V p-p, f = 10 MHz –72 dBc

OUT

= 1 V p-p, f = 1 MHz 38 dBm Output Third Order Intercept

OUT

= 1 V p-p, f = 10 MHz 33 dBm

OUT

= 1 V p-p, f = 1 MHz –84 dB

OUT

5 ns

f = 10 MHz

0.05 V < V

0.10 V < V

0.95 V < V

< 0.10 V –1 +0.5 +2 dB

GAIN

< 0.95 V –1 ±0.3 +1 dB

GAIN

< 1.0 V –2 –1 +1 dB

GAIN

< 0.95 V ±0.2 dB

GAIN

< 0.95 V ±0.1 dB

GAIN

< 0.95 V 50 dB/V

GAIN

LO Gain –4.5 to +43.5 dB Gain Range
HI Gain +7.5 to +55.5 dB

V

= 2.0 V p-p 1.5 to 3.5 V

OUT

ENABLE INTERFACE
(Pins ENB, ENBL, ENBV)

Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Input Resistance

Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ
V

= 30 mV p-p 300 µs Power-Up Response Time

INH

V

= 150 mV p-p 4 ms

INH

HILO GAIN RANGE INTERFACE
(Pin HILO)

Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50 kΩ

1

All dBm values are referred to 50 Ω, unless otherwise noted.

2

Conformance to theoretical gain expression (see Equation 1).

3

Conformance to best fit dB linear curve.

Rev. C | Page 4 of 32

AD8331/AD8332

Parameter Conditions Min Typ Max Unit

OUTPUT CLAMP INTERFACE
(Pin RCLMP; HI or LO Gain)

Accuracy

HILO = LO R
HILO = HI R

MODE INTERFACE
(Pin MODE)

Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200 kΩ

POWER SUPPLY
(Pins VPS1, VPS2, VPSV, VPSL, VPOS)

Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel 25 mA
Power Dissipation per channel No Signal 125 mW
Disable Current
AD8332 (VGA and LNA) 300 600 µA
AD8331 (VGA and LNA) 240 400 µA
AD8332 (ENBL) Each Channel 12 mA
AD8332 (ENBV) Each Channel 13 mA
AD8331 (ENBL) 11 mA
AD8331 (ENBV) 14 mA
PSRR V

= 2.74 kΩ, V

CLMP

= 2.21 kΩ, V

CLMP

= 1 V p-p (Clamped) ±50 mV

OUT

= 1 V p-p (Clamped) ±75 mV

OUT

= 0, f = 100 kHz –68 dB

GAIN

Rev. C | Page 5 of 32

AD8331/AD8332

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings

Parameter Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHn) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V

Power Dissipation

RU-28 Package (AD8332)4 0.96 W
CP-32 Package (AD8332)5 1.97 W
RQ-20 Package (AD8331)4 0.78 W

Temperature

Operating Temperature –40°C to +85°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

θJA

RU-28 Package (AD8332)4 68°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 83°C/W

θJC

RU-28 Package (AD8332)4 14°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 n/a

4

Four-Layer JEDEC Board (2S2P).

5

Exposed pad soldered to board, nine thermal vias in pad — JEDEC 4-Layer

Board J-STD-51-9.

Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 6 of 32

AD8331/AD8332

AD8331, AD8332—TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R
–4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.

60

50

40

)

30

B
d

(
N

I
A

20

G

10

0

MODE = LO

HILO = HI

HILO = LO

MODE = HI
(AC PACKAGE
ONLY)

50

SAMPLE SIZE = 80 UNITS
V

GAIN

40

S
T

30

I
N
U

F
O

%

20

10

= ∞, CL = 1 pF, VCM = 2.5 V,

CLMP

= 0.5V

–10

0 0.2

Figure 3. Gain vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

00.2

and MODE (MODE Available on AC Package)

GAIN

–40°C

Figure 4. Absolute Gain Error vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

1MHz

30MHz

0 0.2

Figure 5. Absolute Gain Error vs. V

0.60.4 1.00.8 1.1

V

(V)

GAIN

+25°C

+85°C

0.60.4

V

(V)

GAIN

at Three Temperatures

GAIN

10MHz

70MHz

0.60.4

V

(V)

GAIN

at Various Frequencies

GAIN

1.00.8 1.1

1.00.8 1.1

03199-C-003

03199-C-004

03199-C-005

0

–0.1

GAIN ERROR (dB)

Figure 6. Gain Error Histogram

25

SAMPLE SIZE = 50 UNITS

20

= 0.2V

V

GAIN

15
10

5
0

25

% OF UNITS

V

= 0.7V

GAIN

20
15
10

5
0

–0.05

–0.03

–0.01

0.01

–0.11

–0.17

–0.15

–0.13

–0.09

–0.07

CHANNEL-TO-CHANNEL GAIN MATCH(dB)

Figure 7. Gain Match Histogram for V

)
B
d

(
N

I
A
G

–10

–20

50

40

30

20

10

0

100k

V

= 1V

GAIN

0.8V

0.6V

0.4V

0.2V

0V

1M 1G100M10M

FREQUENCY (Hz)

0.03

0.05

0.07

GAIN

0.09

= 0.2 V and 0.7 V

Figure 8. Frequency Response for Various Values of V

0.11

0.13

0.15

0.40–0.3 –0.2 0.1–0.4–0.5 0.30.2 0.5

0.21

0.19

0.17

GAIN

03199-C-006

03199-C-007

03199-C-008

Rev. C | Page 7 of 32

AD8331/AD8332

GAIN (dB)

60

50

40

30

20

10

0

–10

V

GAIN

0.8V

0.2V

1M 1G100k 100M10M

= 1V

0.6V

0.4V

0V

FREQUENCY (Hz)

03199-C-009

0

V

= 1 V p-p

OUT

–10

–20

–30

)
B
d

(

–40

K
L
A
T
S

–50

S

V

= 1V

–60

–70

–80

–90

GAIN

0.9V

0.7V

0.5V

1M100k 100M10M

FREQUENCY (Hz)

0.4V

03199-C-012

O
R
C

Figure 9. Frequency Response for Various Values of V

30

V

=0.5V

GAIN

20

10

0

–10

GAIN (dB)

–20

–30

–40

100k

RIN=RS=50Ω,75Ω,100Ω

RIN=RS=1kΩ

RIN=RS= 500Ω

R

=200Ω

IN=RS

1M 1G

FREQUENCY (Hz)

, HILO = HI

GAIN

100M10M

03199-C-010

Figure 10. Frequency Response for Various Matched Source Impedances

30

V

= 0.5V

GAIN

R

= ∞

FB

20

10

)

0

B
d

(
N

I
A

–10

G

–20

–30

–40

1M 1G100k 100M10M

FREQUENCY (Hz)

Figure 11. Frequency Response, Untermin ated, R

= 50 Ω

S

03199-C-011

Figure 12. Channel-to-Channel Crosstalk vs.

Frequency for Various Values of V

50

1µF
COUPLING

0.1µF
COUPLING

1M100k 100M10M

FREQUENCY(Hz)

45

40

35

30

25
20

GROUP DELAY (ns)

15

10

5

0

GAIN

Figure 13. Group Delay vs. Frequ ency

OFFSET VOLTAGE (mV)

–10

–20

–10

–20

20

10

0

20

10

0

HI GAIN

T=+25°C

LO GAIN

T = –40°C

T = –40°C

T = –40°C

T=+85°C

V

(V)

GAIN

T=+25°C

T=+25°C

T = –40°C

T=+85°C

T=+85°C

Figure 14. Representative Differential Output Offset Voltage vs. V

Temperatures

1.10.40.20 0.30.1 0.90.70.5 0.80.6 1.0

at Three

GAIN

03199-C-013

03199-C-014

Rev. C | Page 8 of 32

AD8331/AD8332

35

SAMPLE SIZE = 100

0.2V < V

30

GAIN

< 0.7V

25

20

15

% TOTAL

10

5

0

GAIN SCALING FACTOR

Figure 15. Gain Scaling Factor Histogram

100

SINGLE ENDED, PIN VOH OR VOL
R

= ∞

L

)

Ω

(

10

E
C
N
A
D
E
P
M

I
T

U
P

1

T
U
O

25j

RIN = 75Ω,

= 412

Ω

R

FB

RIN = 100Ω,

= 549

Ω

R

FB

17

–25j

Ω

RIN = 200Ω,

= 1.1k

R

FB

0

Ω

03199-B-015

50.5

50.449.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3

Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz

20

15

10

5

)
B
d

(

0

N

I
A
G

–5

50j

R

= 50

IN

RFB = 270

Ω

RIN = 6kΩ,

=

∞

R

FB

–50j

for Va rious Values of R

RIN = 1k

Ω

RIN = 500

Ω

Ω

,

Ω

FB

100j

f = 100kHz

–100j

RIN = 50Ω, 75Ω,
AND 100

Ω

RIN = 200

RIN = 200

03199-B-018

Ω

Ω

0.1
100k 1M

10k

)

Ω

(

1k

E
C
N
A
D
E
P
M

I
T

U

100

P
N

I

10

FREQUENCY (Hz)

10M 100M

Figure 16. Output Impedance vs. Frequency

RFB = ∞, CSH = 0pF

R

= 6.65kΩ, CSH = 0pF

FB

= 3.01kΩ, CSH = 0pF

R

FB

= 1.1kΩ, CSH = 1.2pF

R

FB

R

= 549Ω, CSH = 8.2pF

FB

R

= 412Ω, CSH = 12pF

FB

R

= 270Ω, CSH = 22pF

FB

1M100k 100M10M

FREQUENCY (Hz)

Figure 17. LNA Input Impedance vs. Frequency for

Various Values of R

and CSH

FB

03199-C-016

03199-C-017

–10

–15

–20

100k

10M

FREQUENCY (Hz)

100M1M

1G

Figure 19. LNA Frequency Response,

IN

100M1M

1G

)
B
d

(
N

I
A
G

–10

–15

–20

20

15

10

–5

100k

5

0

Single-Ended, for Various Values of R

RFB = ∞

10M

FREQUENCY (Hz)

Figure 20. LNA Frequency Response, Unterminated, Single-Ended

03199-C-019

03199-C-020

Rev. C | Page 9 of 32

AD8331/AD8332

500

)

z
H

400

/
V
n

(
E

S

I

300

O
N

D
E
R
R
E

200

F
E
R

­T
U
P
T

100

U
O

1.6

1.4

)

1.2

z
H
/
V

1.0

n

(
E

S

I

0.8

O
N

T
U

0.6

P
N

I

0.4

0.2

100

f = 10MHz

HILO = HI

HILO = LO

0

0 0.4

0.2 0.8
V

GAIN

(V)

Figure 21. Output-Referred Noise vs. V

RS = 0, RFB = ∞, V
HILO = LO OR HI

0

= 1V

GAIN

1M 10M

FREQUENCY (Hz)

Figure 22. Short-Circuit Input-Referred Noise vs. Frequency

RS = 0, RFB = ∞,
HILO = LO OR HI, f = 10MHz

GAIN

1.00
RS = 0, RFB = ∞,

0.95

V

= 1V, f = 10MHz

GAIN

0.90

)

0.85

z
H
/

0.80

V
n

(
E

0.75

S

I
O
N

0.70

T
U
P

0.65

N

I

0.60

0.55

03199-C-021

1.00.6

03199-C-022

100M100k

0.50

10–30–50 –10 705030

TEMPERATURE (°C)

Figure 24. Short-Circuit Input-Referred Noise vs. Temperature

10

f = 5MHz, R

)

z
H
/
V
n

(
E

S

I

1.0

O
N

T
U
P
N

I

0.1
110

7

6

=∞, V

FB

RS = THERMAL NOISE ALONE

= 1V

GAIN

SOURCE RESISTANCE (

100 1k

Ω

Figure 25. Input-Referred Noise vs. R

INCLUDES NOISE OF VGA

)

S

90

03199-C-025

03199-C-024

)

z
H

10

/
V
n

(
E

S

I
O
N
T
U
P

1

N

I

0.1
0 0.4

0.2 0.8
V

GAIN

(V)

Figure 23. Short-Circuit Input-Referred Noise vs. V

GAIN

03199-C-023

1.00.6

Rev. C | Page 10 of 32

5

)
B
d

(
E

4

R
U
G

I
F

3

E
S

I
O
N

2

1

0

R

IN

SIMULATION

10050 1k

Figure 26. Noise Figure vs. R

= 50Ω

75Ω
100Ω
200Ω

R

= ∞

FB

SOURCE RESISTANCE (Ω)

for Variou s Value s of RIN

S

03199-C-026

AD8331/AD8332

50

f = 10MHz, R

45

40

35

)
B
d

(

30

E
R
U

25

G

I
F

E

20

S

I

HILO = LO, R

O
N

15

10

5

0

0 0.2

0.1 0.50.3 0.90.7

= 50Ω

S

HILO = LO, RIN= 50Ω

= ∞

FB

HILO = HI, R

Figure 27. Noise Figure vs. V

30

25

)
B

20

d

(
E

R
U

15

G

I
F

E
S

I
O

10

N

5

HILO = LO, R

= ∞

FB

HILO = HI, R

= ∞

FB

HILO = HI, RIN= 50Ω

0.60.4

V

(V)

GAIN

HILO = HI, R

HILO = LO, R

IN

= 50Ω

03199-C-027

1.00.8 1.1

GAIN

= ∞

FB

= 50Ω

IN

–30

f = 10MHz

= 1V p-p

V

OUT

–40

)
c
B
d

–50

(
N

O

I
T
R

–60

O
T
S

I
D

–70

C

I
N
O
M

–80

R
A
H

–90

–100

HILO = LO,
HD3

HILO = HI,
HD2

200 8000 600400 1.0k 2.0k1.8k1.6k1.4k1.2k

Figure 30. Harmonic Distortion vs. R

–40

f = 10MHz

= 1V p-p

V

OUT

–50

)
c
B
d

(
N

–60

O

I
T
R

O
T

–70

S

I
D

C

I
N

–80

O
M
R
A
H

–90

HILO = LO,
HD3

HILO = HI,

HD3

HILO = LO,
HD2

R

LOAD

(Ω)

HILO = HI,
HD3

HILO = HI,
HD2

HILO = LO,
HD2

03199-C-030

LOAD

f = 10MHz, R

0

10 20

15 30 5040

S

= 50Ω

3525

GAIN (dB)

Figure 28. Noise Figure vs. Gain

0

G = 30dB

–10

V

=1V

OUT

P-P

–20
–30

–40

HARMONIC DISTORTION (dBc)

–100

–50

–60

–70

–80
–90

HILO = LO,
HD2

HILO = HI,
HD2

FREQUENCY(Hz)

Figure 29. Harmonic Distortion vs. Frequency

HILO = LO,
HD3

HILO = HI,
HD3

5545 60

100M1M 10M

03199-C-028

03199-C-029

–100

–40

–50

)
c
B
d

(
N

–60

O

I
T
R

O
T

–70

S

I
D

C

I
N

–80

O
M
R
A
H

–90

–100

10 40 5003020

C

LOAD

Figure 31. Harmonic Distortion vs. C

f = 10MHz
GAIN = 30 dB

HILO = LO,
HD3

14032

V

(V p-p)

OUT

(pF)

HILO = HI,
HD3

HILO = HI,
HD2

LOAD

HILO = LO,
HD2

Figure 32. Harmonic Distortion vs. Differential Output Voltage

03199-C-031

03199-C-032

Rev. C | Page 11 of 32

AD8331/AD8332

0

V

= 1V p-p

OUT

–20

INPUT RANGE
LIMITED WHEN
HILO = LO

–40

–60

–80

DISTORTION (dBc)

–100

–120

DISTORTION (dBc)

–100

–120

)
m

B
d

(
R

E
W
O

P
T

U
P
N

I

HILO = HI,

HD3

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Figure 33. Harmonic Distortion vs. V

0

= 1V p-p

V

OUT

–20

INPUT RANG E

–40

–60

–80

LIMITED WHEN

HILO = LO

HILO = HI,

HD2

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0

Figure 34. Harmonic Distortion vs. V

10

5

f = 10MHz

0

–5

–10

–15

–20

–25

–30

0 0.30.1

HILO = HI

Figure 35. Input 1 dB Compression vs. V

HILO = LO,

HD2

V

HILO = HI,

HD3

V

0.40.2
V

(V)

GAIN

HILO = LO,

HD2

(V)

GAIN

(V)

GAIN

HILO = LO,

HD3

GAIN

GAIN

HILO = HI,

HD2

, f = 1 MHz

HILO = LO,

HD3

, f = 10 MHz

HILO = LO

GAIN

0.90.70.5 0.80.6 1.0

03199-C-033

03199-C-034

03199-C-035

0

V

= 1V p-p COMPOSITE (f1+ f2)

OUT

G = 30dB

–10

–20

–30

)

c
B

–40

d

(
3
D

–50

M

I

–60

–70

–80

–90

1M

10M

FREQUENCY (Hz)

Figure 36. IMD3 vs. Frequen cy

40

HILO = HI,

1MHz

35

)
m

B
d

(
3

P

I
T

U
P
T
U
O

30

HILO = HI,

25

10MHz

20

15

= 1V p-p COMPOSITE (f1 + f2)

V

OUT

10

5

0

0.1 0.40 0.30.2

HILO = LO,

10MHz

V

GAIN

HILO = LO,

1MHz

(V)

Figure 37. Output Third Order Intercept vs. V

2mV

100

90

10

0

50mV

Figure 38. Small Signal Pulse Response, G = 30 dB,

Top: Input, Bottom: Output Voltage, HILO = HI or LO

10ns

GAIN

03199-C-036

100M

03199-C-037

1.00.90.80.70.60.5

03199-C-038

Rev. C | Page 12 of 32

AD8331/AD8332

5

20mV

100

90

10

0

500mV

Figure 39. Large Signal Pulse Response, G = 30 dB,

HILO = HI or LO, Top: Input, Bottom: Output Voltage

(V)

V

OUT

2

G = 30dB

1

INPUT

0

–1

C

C

= 50pF

L

= 0pF

L

10ns

03199-C-039

4

)
p

3

­p

V

(

T
U
O

V

2

1

0

010 3020 5040

HILO = HI

HILO = LO

R

CLMP

(kΩ)

Figure 42. Clamp Level vs. R

4

G = 40dB

3

2

1

)
V

(

T

0

U
O

V

–1

–2

R

= 48.1kΩ R

CLMP

R

= 7.15kΩ R

CLMP

CLMP

CLMP

= 2.67kΩ

03199-C-042

CLMP

= 16.5kΩ

INPUT IS NOT TO SCALE

–2

10–10–30 0–20

TIME (ns)

Figure 40. Large Signal Pulse Response for

Various Capacitive Loads, C

500mV

200mV

Figure 41. Pin GAIN Transient Response,

, Bottom: Output Voltage

Top : V

GAIN

604020 5030–40

= 0 pF, 10 pF, 20 pF, 50 pF

L

400ns

8070

03199-B-041

03199-C-040

–3

–4

–10 200

10

TIME (ns)

Figure 43. Clamp Level Pulse Response

200mV

100

90

10

0

Figure 44. LNA Overdrive Recovery, V

1 V p-p Burst, V

= 0.27 V, VGA Output Shown

GAIN

30

100ns

0.05 V p-p to

INH

6040 50

03199-B-044

03199-C-043

Rev. C | Page 13 of 32

AD8331/AD8332

50mV

100

90

10

0

Figure 45. VGA Overdrive Recovery, V

V

= 1 V, VGA Output Shown Attenuated 24 dB

GAIN

50mV

100
90

10

0

Figure 46. VGA Overdrive Recovery, V

V

= 1 V, VGA Output Shown Attenuated 24 dB

GAIN

2V

100ns

4 mV p-p to 70 mV p-p Burst,

INH

100ns

4 mV p-p to 275 mV p-p Burst,

INH

2V

1V

03199-B-045

1ms

03199-B-048

Figure 48. Enable Response, Large Signal,

, Bottom: V

Top : V

ENB

0

–10

–20

VPSV, V

–30

)
B
d

(

–40

R
R
S
P

–50

–60

–70

–80

03199-B-046

= 0.5V

GAIN

1M100k 100M10M

, V

= 150 mV p-p

OUT

INH

VPS1, V

FREQUENCY (Hz)

= 0.5V

GAIN

VPS1, V

GAIN

= 0V

03199-C-049

Figure 49. PSRR v s. Frequency (No By pass Capacito r)

60

= 0.5V

V

GAIN

55

50

45

AD8332

200mV

Figure 47. Enable Response, Top: V

, Bottom: V

ENB

OUT

, V

1ms

= 30 mV p-p

INH

03199-B-047

Rev. C | Page 14 of 32

40

35

30

QUIESCENT SUPPLY CURRENT (mA)

25

20

–40

–20

TEMPERATURE (°C)

AD8331

400

20

Figure 50. Quiescent Supply Current vs. Temperature

1008060

03199-C-050

AD8331/AD8332

TEST CIRCUITS

NETWORK ANALYZER

50Ω50Ω

INOUT

1.8nF

270Ω

FB*

22pF

0.1µF

0.1µF

INH

LMD

120nH

*FERRITE BEAD

Figure 51. Gain and Bandwidth Measurements

1.8nF

270Ω

DUT

0.1µF

0.1µF

237Ω

237Ω

28Ω

28Ω

1:1

03199-C-051

OSCILLOSCOPE

50Ω

120nH

50Ω

FB*

49Ω

0.1µF

22pF

*FERRITE BEAD

LMD

0.1µF

Figure 52. Transient Measurements

ABG

FB*

0.1µF

120nH

1Ω

22pF

Figure 53. Used for Noise Measurements

INH

0.1µF

INH

LMD

DUT

0.1µF

0.1µF

DUT

237Ω

237Ω

28Ω

28Ω

0.1µF

0.1µF

1:1

IN

1:1

*FERRITE BEAD

50Ω

IN

SPECTRUM
ANALYZER

50Ω

03199-C-052

03199-C-053

Rev. C | Page 15 of 32

AD8331/AD8332

1.8nF

270Ω

DUT

0.1µF

0.1µF

237Ω

28Ω

237Ω

28Ω

FB*

120nH

22pF

50Ω

*FERRITE BEAD

0.1µF

0.1µF

INH

LMD

1:1

SPECTRUM
ANALYZER

50Ω

IN

03199-C-054

Figure 54. Distortion

NETWORK ANALYZER

FB*

120nH

0.1µF

22pF

*FERRITE BEAD

50Ω

1.8nF

INH

LMD

0.1µF

270Ω

DUT

50Ω

0.1µF

0.1µF

INOUT

50Ω

237Ω

50Ω

03199-C-055

237Ω

28Ω

28Ω

1:1

Figure 55. S11 Measurements

Rev. C | Page 16 of 32

AD8331/AD8332

(

)

(

(

)

(

(

)

(

)

THEORY OF OPERATION

OVERVIEW

The following discussion applies to all part numbers. Figure 56
and Figure 1 are functional block diagrams of the AD8331 and
AD8332, respectively.

GAIN

INT

17

COMM

VIN

8

7

AD8331

∆

G = –48dB to 0dB

BIAS AND

INTERPOLATOR

19

ENBL

VPOS

VCM

14

11

V

VGA

+21dB

18

ENBV RCLMP

HILO

19

3.5dB/

15.5dB

MID

15

POST
AMP1

CLAMP

12

VOH

VOL

16

9

MODE

03199-C-056

LON LOP VIP

4 5

3

VPSL

6

COML

2

INH

LMD

GAIN

LNA

1

LNA
BIAS

)

(V

MID

10

20

COMM

Figure 56. Functional Block Diagram — AD8331

Each channel contains an LNA that provides user-adjustable
input impedance termination, a differential X-AMP VGA, and a
programmable gain postamplifier with adjustable output
voltage limiting. Figure 57 shows a simplified block diagram.

60

50

40

30

MODE = LO

20

GAIN (dB)

10

0

–10

00.2

MODE = HI

(WHERE AVAILABLE)

HILO = HI

HILO = LO

0.60.4

V

(V)

GAIN

Figure 58. Gain Control Characteristics

When MODE is set high, (where available):

GAIN

or

GAIN

03199-C-058

1.00.8 1.1

3=,545+×50–=)( LOHILOdB.VVdBdBGAIN

()

()

()

4=,557+×50–=)( HIHILOdB.VVdBdBGAIN

()

VIN

VIP

GAIN

*SHARED BETWEEN CHANNELS

X-AMP VGA POSTAMP

[(–48 to 0) + 21] dB

A

B

A

N

I

S

D

N

R

I

T

O

E

L

A

P

T

O

R

*

VCM

V

MID

3.5dB/15.5dB

VOH

VOL

RCLMP

CLAMP*

HILO

LMD

PREAMPLIFIER

+INH

–

BIAS
(V

)

MID

LON

19dB

LNA

LOP

INTERFACE*

GAIN

Figure 57. Simplified Block Diagram

The linear-in-dB gain control interface is trimmed for slope and
absolute accuracy. The overall gain range is 48 dB, extending
from –4.5 dB to +43.5 dB or from +7.5 dB to +55.5 dB,
depending on the setting of the HILO pin. The slope of the gain
control interface is 50 dB/V, and the gain control range is 40 mV
to 1 V, leading to the following expressions for gain:

GAIN

()

=×=

)

1,56 50)( LOHILOdB.–VVdBdBGAIN

or

GAIN

()

=+×=

)

2,55 50)( HIHILOdB.VVdBdBGAIN

The gain characteristics are shown in Figure 58.

The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. When only one output is used, the
gain is 13 dB. The inverting output is used for active input
impedance termination. Each of the LNA outputs is capacitively
coupled to a VGA input. The VGA consists of an attenuator
with a range of 48 dB followed by an amplifier with 21 dB of
gain, for a net gain range of –27 dB to +21 dB. The X-AMP
gain-interpolation technique results in low gain error and
uniform bandwidth, and differential signal paths minimize

03199-B-057

distortion.

The final stage is a logic programmable amplifier with gains of

3.5 dB or 15.5 dB. The LO and HI gain modes are optimized
for 12-bit and 10-bit A/D converter applications, in terms of
output-referred noise and absolute gain range. Output voltage
limiting may be programmed by the user.

LOW NOISE AMPLIFIER (LNA)

Good noise performance relies on a proprietary ultralow noise
preamplifier at the beginning of the signal chain, which
minimizes the noise contribution in the following VGA. Active
impedance control optimizes noise performance for
applications that benefit from input matching.

Rev. C | Page 17 of 32

AD8331/AD8332

A simplified schematic of the LNA is shown in Figure 59. INH
is capacitively coupled to the source. An on-chip bias generator
centers the output dc levels at 2.5 V and the input voltages at

3.25 V. A capacitor C
capacitor C

is connected from the LMD pin to ground.

INH

of the same value as the input coupling

LMD

C

FB

R

FB

LOP

VPOS

LON

is needed in series with RFB, since the dc levels at Pins LON

C

FB

and INH are unequal. Expressions for choosing R
R

and for choosing CFB are found in the Applications section.

IN

C

and the ferrite bead enhance stability at higher frequencies

SH

in terms of

FB

where the loop gain declines and prevents peaking. Frequency
response plots of the LNA are shown in Figure 19 and Figure 20.
The bandwidth is approximately 130 MHz for matched input
impedances of 50 Ω to 200 Ω and declines at higher source
impedances. The unterminated bandwidth (R

= ∞) is

FB

approximately 80 MHz.

I

C

INH

R

S

INH

C

SH

Figure 59. Simplified LNA Schematic

Q1

I

I

0

0

Q2

I

0

0

LMD

C

LMD

The LNA supports differential output voltages as high as
5 V p-p with positive and negative excursions of ±1.25 V, about
a common-mode voltage of 2.5 V. Since the differential gain
magnitude is 9, the maximum input signal before saturation is
± 275 mV or 550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Since the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD
protection.

Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input­referred voltage noise of 0.74 nV/√Hz. This is achieved with a
modest current consumption of 10 mA per channel (50 mW).
On-chip resistor matching results in precise gains of 4.5 per side
(9 differential), critical for accurate impedance control. The use
of a fully differential topology and negative feedback minimizes
distortion. Low HD2 is particularly important in second
harmonic ultrasound imaging applications. Differential
signaling enables smaller swings at each output, further
reducing third order distortion.

Active Impedance Matching

The LNA supports active impedance matching through an
external shunt feedback resistor from Pin LON to Pin INH. The
input resistance R

is given by Equation 5, where A is the

IN

single-ended gain of 4.5, and 6 kΩ is the unterminated input
impedance.

Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a single­ended driver for auxiliary circuits, such as those used for
Doppler mode ultrasound imaging, and Pin LON drives R

.

FB

Alternatively, a differential external circuit can be driven from

03199-C-059

the two outputs, in addition to the active feedback termination.
In both cases, important stability considerations discussed in
the Applications section should be carefully observed.

The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open-circuit gain results when driving the VGA, and 0.8 dB
with an additional 100 Ω load at the output. The differential
gain of the LNA is 6 dB higher. If the load is less than 200 Ω on
either side, a compensating load is recommended on the
opposite output.

LNA Noise

The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of the
LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open-circuit current noise is

2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in Figure 60.
Figure 61 and Figure 62 are simulations extracted from these
results, and the 4.1 dB NF measurement with the input actively
matched to a 50 Ω source. Unterminated (R

= ∞) operation

FB

exhibits the lowest equivalent input noise and noise figure.
Figure 61 shows the noise figure versus source resistance, rising
at low R
source noise, and again at high R

, where the LNA voltage noise is large compared to the

S

due to current noise. The

S

VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in
all of the curves.

×Ω6

R

R

FB

=

IN

+1

A

=Ω6

k

Rk

FB

+Ω33

Rk

5

()

FB

Rev. C | Page 18 of 32

AD8331/AD8332

V

IN

V

IN

ACTIVE IMPEDANCE MATCH –RS = R

V

IN

UNTERMINATED

R

S

+
–

RESISTIVE TERMINATION

R

S

+
–

R

S

+
–

RIN=

Figure 60. Input Configurations

7

6

5

)
B
d

(
E

4

R
U
G

I
F

3

E
S

I
O
N

2

1

SIMULATION

0

10050 1k

Figure 61. Noise Figure vs. R

Active Matched, and Unterminated Inputs

7

INCLUDES NOISE OF VGA

6

5

4

IGURE (dB)

3

NOISE F

2

1

SIMULATION

0

10050 1k

Figure 62. Noise Figure vs. R

R

IN

V

OUT

R

IN

R

IN

1 + 4.5

R

S

R

R

FB

V

OUT

FB

IN

V

OUT

03199-C-060

INCLUDES NOISE OF VGA

RESISTIVE TERMINATION

ACTIVE IMPEDANCE MATCH

= RIN)

(R

S

UNTERMINATED

R

(Ω)

S

for Resistive,

S

RIN = 50

Ω

70

Ω

100

Ω

200

Ω

RFB =

∞

RS(Ω)

for Various Fixed Values of RIN, Actively Matched

S

03199-C-061

03199-C-081

The primary purpose of input impedance matching is to
improve the system transient response. With resistive
termination, the input noise increases due to the thermal noise
of the matching resistor and the increased contribution of the
LNA’s input voltage noise generator. With active impedance
matching, however, the contributions of both are smaller than
they would be for resistive termination by a factor of 1/(1 +

LNA Gain). Figure 61 shows their relative noise figure (NF)

performance. In this graph, the input impedance has been swept
with R

to preserve the match at each point. The noise figures

S

for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB,
respectively, for the resistive, active, and unterminated
configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB,
and 1.0 dB, respectively.

Figure 62 is a plot of the NF versus R

for various values of RIN,

S

which is helpful for design purposes. The plateau in the NF for
actively matched inputs mitigates source impedance variations.
For comparison purposes, a preamp with a gain of 19 dB and
noise spectral density of a 1.0 nV/√Hz, combined with a VGA
with 3.75 nV/√Hz, would yield a noise figure degradation of
approximately 1.5 dB (for most input impedances), significantly
worse than the AD8332 performance.

The equivalent input noise of the LNA is the same for single­ended and differential output applications. The LNA noise
figure improves to 3.5 dB at 50 Ω without VGA noise, but this
is exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually
recommended for stability purposes, when driving external
circuits on a separate board (see the Applications section). In
low noise applications, a ferrite bead is even more desirable.

VARIABLE GAIN AMPLIFIER

The differential X-AMP VGA provides precise input
attenuation and interpolation. It has a low input-referred noise
of 2.7 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in Figure 63.

GAIN

g

VIP

VIN

GAIN INTERPOLATOR

m

6dB

R

(BOTH CHANNELS)

48dB

2R

Figure 63. Simplified VGA Schematic

POST-AMP

POST-AMP

03199-C-063

Rev. C | Page 19 of 32

AD8331/AD8332

X-AMP VGA

The input of the VGA is a differential R-2R ladder attenuator
network, with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and
isolate their common-mode voltage. The VGA inputs are biased
through the ladder’s center tap connection to VCM, which is
typically set to 2.5 V and is bypassed externally to provide a
clean ac ground.

The signal level at successive stages in the input attenuator falls
from 0 dB to –48 dB, in 6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps merge
to provide a smooth attenuation range from 0 dB to –48 dB. This
circuit technique results in excellent, linear-in-dB gain law
conformance and low distortion levels and deviates ±0.2 dB or less
from ideal. The gain slope is monotonic with respect to the control
voltage and is stable with variations in process, temperature, and
supply.

The X-AMP inputs are part of a gain-of-12 feedback amplifier,
which completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and
ensure excellent frequency response uniformity across gain
setting (see Figure 8 and Figure 9).

Gain Control

Position along the VGA attenuator is controlled by a single­ended analog control voltage, V
to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V
(20 mV/dB). Values of V

GAIN

minimum or maximum gain values. Both channels of the
AD8332 are controlled from a single gain interface to preserve
matching. Gain can be calculated using Equations 1 and 2.

Gain accuracy is very good since both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is ±1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple, trim
errors, and tester limits. The gain error relative to a best-fit line for
a given set of conditions is typically ±0.2 dB. Gain matching
between channels is better than 0.1 dB (see Figure 7, which shows
gain errors in the center of the control range). When V
or > 0.95, gain errors are slightly greater.

The gain slope may be inverted, as shown in Figure 58 (avail­able in most versions). The gain drops with a slope of
–50 dB/V across the gain control range from maximum to
minimum gain. This slope is useful in applications, such as
automatic gain control, where the control voltage is
proportional to the measured output signal amplitude. The
inverse gain mode is selected by setting the MODE pin HI.

, with an input range of 40 mV

GAIN

beyond the control range saturate to

< 0.1

GAIN

Gain control response time is less than 750 ns to settle within
10% of the final value for a change from minimum to max­imum gain.

VGA Noise

In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum
resolvable input signal, the output-referred noise, which
depends primarily on the VGA, limits the maximum
instantaneous dynamic range that can be processed at any one
particular gain control voltage. This limit is set in accordance
with the quantization noise floor of the ADC.

Output and input-referred noise as a function of V

GAIN

are
plotted in Figure 21 and Figure 23 for the short-circuited input
condition. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.

The output-referred noise is flat over most of the gain range,
since it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and source prevail. The input-referred noise
reaches its minimum value near the maximum gain control
voltage, where the input-referred contribution of the VGA
becomes very small.

At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, since the input capacity
increases with it. The contribution of the ADC noise floor has
the same dependence as well. The important relationship is
the magnitude of the VGA output noise floor relative to that
of the ADC.

With its low output-referred noise levels, these devices ideally
drive low-voltage ADCs. The converter noise floor drops 12 dB
for every 2 bits of resolution and drops at lower input full-scale
voltages and higher sampling rates. ADC quantization noise is
discussed in the Applications section.

The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage, since the
contribution of its bias noise is designed to cancel in the
differential signal. A transformer can be used with single-ended
applications when low noise is desired.

Rev. C | Page 20 of 32

AD8331/AD8332

Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is
present. Its effect is observable only in LO gain mode, where the
noise floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter may
be used to remove V

source noise. The filter bandwidth

GAIN

should be sufficient to accommodate the desired control
bandwidth.

Common-Mode Biasing

An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection, since the
VCM network makes a number of important connections
internally, including the center tap of the VGA’s differential
input attenuator, the feedback network of the VGA’s fixed gain
amplifier, and the feedback network of the postamplifier in both
gain settings. For best results, use a 1 nF and a 0.1 µF capacitor
in parallel, with the 1 nF nearest to Pin VCM. Separate VCM
pins are provided for each channel. For dc-coupling to a 3 V
ADC, the output common-mode voltage is adjusted to 1.5 V by
biasing the VCM pin.

POSTAMPLIFIER

The final stage has a selectable gain of 3.5 dB or 15.5 dB, set by
the logic Pin HILO. These correspond to linear gains of 1.5 or 6.
A simplified block diagram of the postamplifier is shown in
Figure 64.

Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI
gain mode and 300 V/µs in LO gain mode. The feedback
networks for HI and LO gain modes are factory trimmed to
adjust the absolute gains of each channel.

Noise

The topology of the postamplifier provides constant input­referred noise with the two gain settings and variable output­referred noise. The output-referred noise in HI gain mode
increases (with gain) by four. This setting is recommended
when driving converters with higher noise floors. The extra gain
boosts the output signal levels and noise floor appropriately.
When driving circuits with lower input noise floors, the LO gain
mode optimizes the output dynamic range.

Gm2

+

VOH

Gm1

F2

VCM

–

F1

Gm2

Gm1

Figure 64. Postamplifier Block Diagram

VOL

03199-B-064

Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and
10-bit converters, respectively. An additional technique,
described in the Applications section, can extend the noise floor
even lower for possible use with 14-bit ADCs.

Output Clamping

Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a
resistor from R

to ground. Table shows a list of

CLMP

recommended resistor values.

Output clamping can be used for ADC input overload
protection, if needed, or postamp overload protection when
operating from a lower common-mode level, such as 1.5 V. The
user should be aware that distortion products increase as output
levels approach the clamping levels and should adjust the clamp
resistor accordingly. Also, see the Applications section.

The accuracy of the clamping levels is approximately ±5% in LO
or HI mode. Figure 65 illustrates the output characteristics for a
few values of R

5.0

4.5

4.0

3.5

3.0

(V)

OL

2.5

, V

OH

2.0

V

1.5

1.0

0.5

0

–3 –2

.

CLMP

R

=

∞

CLMP

8.8k

Ω

3.5k

Ω

R

= 1.86k

CLMP

Figure 65. Output Clamping Characteristics

Ω

0–1

V

(V)

INH

213

03199-C-065

Rev. C | Page 21 of 32

AD8331/AD8332

APPLICATIONS

LNA – EXTERNAL COMPONENTS

The LMD pin (connected to the bias circuitry) must be
bypassed to ground, and signal source to the INH pin
capacitively coupled using 2.2 nF to 0.1 μF capacitors (see
Figure 66).

The unterminated input impedance of the LNA is 6 kΩ. The
user may synthesize any LNA input resistance between 50 Ω
and 6 kΩ. R
from Table .

Table 3. LNA External Component Values
for Common Source Impedances

R

(Ω) R

IN

50 280 22
75 412 12
100 562 8
200 1.13k 1.2
500 3.01k None
6k

When active input termination is used, a 0.1 µF capacitor (C
required to isolate the input and output bias voltages of the LNA.

The shunt input capacitor, C
frequencies where the active termination match is lost due to
the HF gain roll-off of the LNA. Suggested values are shown in
Table ; for unterminated applications, reduce the capacitor value
by half.

When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values may prove useful.

Figure 67 shows the interconnection details of the LNA output.
Capacitive coupling between LNA outputs and the VGA inputs
is required because of differences in their dc levels and to
eliminate the offset of the LNA. Capacitor values of 0.1 µF are
recommended. There is 0.4 dB loss in gain between the LNA
output and the VGA input due to the 5 Ω output resistance.
Additional loading at the LOP and LON outputs will affect
LNA gain.

is calculated according to Equation 6 or selected

FB

×Ω33

Rk

()

IN

=

R

FB

(Nearest STD 1% Value, Ω) C

FB

–Ω6

Rk

()

6

()

IN

∞

, reduces gain peaking at higher

SH

(pF)

SH

None

FB

) is

C

0.1µF

V

GAIN

1nF

0.1µF

1nF

1nF

+5V

LMD

0.1µF

1

LMD2

2

INH2

3

VPS2

4

LON2

5

LOP2

6

COM2

7

VIP2

8

VIN2

9

VCM2

10

GAIN

11

RCLMP

12

VOH2

13

VOL2

14

COMM

*

SEE TEXT

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1nF

FB

C

*

SH

1nF

C

*

FB

R

*

FB

LNA OUT

0.1µF

1nF

VGA OUT

VGA OUT

0.1µF

0.1µF

5V

5V

5V

*
*

0.1µF

5V

0.1 F

LNA

SOURCE

Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)

TO EXT

CIRCUIT

VIP

VCM

VIN

50Ω

50Ω

100Ω

100Ω

TO EXT

CIRCUIT

5Ω

LON

LNA

C

SH

LOP

5Ω

Figure 67. Interconnections of the LNA and VGA

Both LNA outputs are available for driving external circuits. Pin
LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it will tolerate a load capacitance
up to 100 pF with the addition of a 49.9 Ω series resistor or
ferrite 75 Ω/100 MHz bead.

03199-C-066

03199-C-067

Rev. C | Page 22 of 32

AD8331/AD8332

Gain Input

Pin GAIN is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ and a bypass capacitor
from 100 pF to1 nF is recommended.

Parallel connected devices may be driven by a common voltage
source or DAC. Decoupling should take into account any
bandwidth considerations of the drive waveform, using the total
distributed capacitance.

If gain control noise in LO gain mode becomes a factor,
maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure
satisfactory noise performance. Internal noise prevails below
15 nV/√Hz at the GAIN pin. Gain control noise is negligible in
HI gain mode.

VCM Input

The common-mode voltage of Pins VCM, VOL, and VOH
defaults to 2.5 Vdc. With output ac-coupled applications, the
VCM pin will be unterminated; however, it must still be
bypassed in close proximity for ac grounding of internal
circuitry. The VGA outputs may be dc connected to a
differential load, such as an ADC. Common-mode output
voltage levels between 1.5 V and 3.5 V may be realized at Pins
VOH and VOL by applying the desired voltage at Pin VCM.
DC-coupled operation is not recommended when driving loads
on a separate PC board.

The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see Figure 68). If the VCM pin is driven from an
external source, its output impedance should be <<30 Ω and its
current drive capability should be >>2 mA. If the VCM pins of
several devices are connected in parallel, the external buffer
should be capable of overcoming their collective output
currents. When a common-mode voltage other than 2.5 V is
used, a voltage-limiting resistor, R

, is needed to protect

CLMP

against overload.

INTERNAL

2mA MAX

AC GROUNDING FOR
INTERNAL CIRCUITRY

CIRCUITRY

V

CM

30Ω

100pF

Figure 68. VCM Interface

RO << 30Ω

0.1µF

NEW V

CM

03199-B-068

Logic Inputs—ENB, MODE, and HILO

The input impedance of all enable pins is nominally 25 kΩ and
may be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pins perform
a power-down function, when disabled, the VGA outputs are
near ground. Multiple devices may be driven from a common
source. Consult the pin-function tables for circuit functions
controlled by the enable pins.

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.

Optional Output Voltage Limiting

The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground, and Table
lists several voltage levels and the corresponding resistor value.
Unconnected, the default limiting level is 4.5 V p-p.

Note that third harmonic distortion will increase as waveform
amplitudes approach clipping. For lowest distortion, the clamp
level should be set higher than the converter input span. A
clamp level of 1.5 V p-p is recommended for a 1 V p-p linear
output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a

0.5 V p-p operation. The best solution will be determined
experimentally. Figure 69 shows third harmonic distortion
as a function of the limiting level for a 2 V p-p output signal.
A wider limiting level is desirable in HI gain mode.

–20

V

= 0.75V

GAIN

–30

–40

)
c
B
d

(

–50

3
D
H

–60

–70

–80

Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input

2.0 3.51.5 3.02.5 4.0 4.5
CLAMP LIMIT LEVEL (V p-p)

HILO = LO

HILO = HI

5.0

03199-C-069

Rev. C | Page 23 of 32

AD8331/AD8332

Table 4. Clamp Resistor Values

Clamp Resistor Value (kΩ) Clamp Level

(V p-p)

0.5 1.21

1.0 2.74 2.21

1.5 4.75 4.02

2.0 7.5 6.49

2.5 11 9.53

3.0 16.9 14.7

3.5 26.7 23.2

4.0 49.9 39.2

4.4 100 73.2

Output Filtering and Series Resistor Requirements

To ensure stability at the high end of the gain control range,
series resistors or ferrite beads are recommended for the
outputs when driving large capacitive loads, or circuits on other
boards,. These components can be part of the external
noise filter.

Recommended resistor values are 84.5 Ω for LO gain mode and
100 Ω for HI gain mode (see Figure 66) and are placed near
Pins VOH and VOL. Lower value resistors are permissible for
applications with nearby loads or with gains less than 40 dB.
Lower values are best selected empirically.

An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.

When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and mitigates charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 70
shows a second order low-pass filter with a bandwidth of
20 MHz. The capacitor is chosen in conjunction with the 10 pF
input capacitance of the ADC.

0

84.5Ω

0

Figure 70. 20 MHz Second-Order Low-Pass Filter

HILO = LO HILO = HI

OPTIONAL

BACKPLANE

.

1

µ

F

.

1

µ

F

1

.

5

µ

H

158Ω

158Ω84.5Ω

1

.

5

µ

H

18pF

ADC

The relative noise and distortion performance of the two gain
modes can be compared in Figure 21 and Figure 27 through
Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full­scale voltages as high as 4 V p-p. Since distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 32), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 71 has an output full-scale range of
2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.

HZ

187Ω

2:1

187Ω

2V p-p DIFF,
24n V/

HZ

374Ω

LPF

ADC

AD6644

03199-C-071

4V p-p DIFF,
48n V/

VOH

VOL

Figure 71. Adjusting the Noise Floor for 14-Bit ADCs

OVERLOAD

These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.

Signals larger than ±275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 44
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.

Both stages of the VGA are susceptible to overload. Postamp
limiting is more common and results in the clean-limited
output characteristics found in Figure 45. Under more extreme
conditions, the X-AMP will overload, causing the minor glitches
evident in Figure 46. Recovery is fast in all cases. The graph in
Figure 72 summarizes the combinations of input signal and
gain that lead to the different types of overload.

DRIVING ADCS

The output drive will accommodate a wide range of ADCs. The
noise floor requirements of the VGA will depend on a number
of application factors, including bit resolution, sampling rate,
full-scale voltage, and the bandwidth of the noise/antialias filter.
The output noise floor and gain range can be adjusted by
selecting HI or LO gain mode.

Rev. C | Page 24 of 32

AD8331/AD8332

43.5

–4.5

OVERLOAD

)
B
d

(
IN

A
G

1m

POSTAMP

X-AMP

OVERLOAD

15mV

25mV

LO GAIN

MODE

INPUT AMPLITUDE (V)

POSTAMP

OVERLOAD

4mV

56.5

29dB

)

24.5dB

B
d

(

D
A
O
L
R
E
V

O
A
N
L

.2750.110m

IN
A
G

7.5

1

1m 0.2750.110m 1

X-AMP

OVERLOAD

25mV

HI GAIN

MODE

INPUT AMPLITUDE (V)

41dB

24.5dB

D
A
O
L
R
E
V

O
A
N
L

Figure 72. Overload Gain and Signal Conditions

The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When no R

resistor is provided, this level defaults

CLMP

to near 4.5 V p-p differential to protect outputs centered at a

2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of R

should be chosen for

CLMP

graceful overload. A value of 8.3 kΩ or less is recommended for

1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p diff.

OPTIONAL INPUT OVERLOAD PROTECTION.

Applications in which high transients are applied to the LNA
input may benefit from the use of clamp diodes. A pair of back­to-back Schottky diodes can reduce these transients to
manageable levels. Figure 73 illustrates how such a diode­protection scheme may be connected.

LAYOUT, GROUNDING, AND BYPASSING

Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.

A multilayer board with power and ground plane is
recommended, and unused area in the signal layers should be
filled with ground. The multiple power and ground pins provide
robust power distribution to the device and must all be
connected. The power supply pins should each be with multiple

03199-C-072

values of high frequency ceramic chip capacitors to maintain
low impedance paths to ground over a wide frequency range.
These should have capacitance values of 0.01 μF to 0.1 μF in
parallel with 100 pF to 1 nF, and be placed as close as possible to
the pins. The LNA power pins should be decoupled from the
VGA using ferrite beads. Together with the decoupling
capacitors, ferrite beads help eliminate undesired high
frequencies without reducing the headroom, as do small value
resistors.

Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before
connecting to the coupling capacitors connected to Pins VIN
and VIP. R

must be placed nearby the LON pin as well.

FB

Resistors must be placed as close as possible to the VGA output
pins VOL and VOH to mitigate loading effects of connecting
traces. Values are discussed in the section entitled Output
Filtering and Series Resistor
Requirements.

OPTIONAL
SCHOTTKY
OVERLOAD

CLAMP

231

BAS40-04

0.1µF

FB

C

R

SH

C

R

SH

2

FB

3

FB

4

INH

VPS

LON

COMM

ENBL

20

19

03199-C-072

Figure 73. Input Overload Clamping

When selecting overload protection, the important parameters
are forward and reverse voltages and t
BAS40 series shown in Figure 73 has a τ

(or τrr.). The Infineon

rr

of 100 ps and VF of

rr

310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.

Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.

MULTIPLE INPUT MATCHING

Matching of multiple sources with dissimilar impedances can
be accomplished as shown in the circuit of Figure 75. A relay
and low supply voltage analog switch may be used to select
between multiple sources and their associated feedback
resistors. An ADG736 dual SPDT switch is shown in this
example; however, multiple switches are also available and users
are referred to the Analog Devices Selection Guide for switches
and multiplexers.

DISABLING THE LNA

Where accessible, connection of the LNA enable pin to ground
will power down the LNA, resulting in a current reduction of
about half. In this mode, the LNA input and output pins may be
left unconnected, however the power must be connected to all
the supply pins for the disabling circuit to function. Figure 74
illustrates the connections using an AD8331 as an example.

Rev. C | Page 25 of 32

AD8331/AD8332

+5V

NC

NC

C

FB

0.018µF

1

LMD

AD8331

2

INH

3

VPS

COMM

ENBL

ENBV

20

MEASUREMENT CONSIDERATIONS

Figure 51 through Figure 55 show typical measurement

19

configurations and proper interface values for measurements
with 50 Ω conditions.

18

+5V

Short-circuit input noise measurements are made using
Figure 53. The input-referred noise level is determined by
dividing the output noise by the numerical gain between Point
A and Point B and accounting for the noise floor of the
spectrum analyzer. The gain should be measured at each

NC

4

LON

COMM

17

frequency of interest and with low signal levels since a 50 Ω

NC

5

LOP

6

COML

VOL

VOH

16

VOUT

15

load is driven directly. The generator is removed when noise
measurements are made.

ULTRASOUND TGC APPLICATION

The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key

0.1µF

VIN

0.1µF

7

VIP

8

VIN

14

VPOS +5V

13

HILO

HILO

subsystem in such applications, since it provides the means for
echolocation of reflected ultrasound energy.

Figure 76 through Figure 78 are schematics of a dual, fully
differential system using the AD8332 and AD9238 12-bit high
speed ADC with conversion speeds as high as 65 MSPS. In this
example, the VGA outputs are dc-coupled, using the reference

MODE

9

MODE

CLMP

12

R

CLMP

output of the ADC and a level shifter to center the common­mode output voltage to match that of the converter. Consult the
data sheet of the converter to determine whether external CMV

GAIN

10

GAIN

VCM

11

VCM

biasing is required. AC coupling is recommended if the CMV
of the VGA and ADC are widely disparate.

03199-C-074

Figure 74. Disabling the LNA

200Ω

50Ω

0.1µF

ADG736

SELECTR

18nF

INH

LMD

AD8332

1.13kΩ

FB

280Ω

LON

5Ω

LNA

LOP

5Ω

03199-C-075

Using the circuit shown, and a high speed ADC FIFO
evaluation kit connected to a laptop PC, an FFT can be
performed on the AD8332. With the on-board clock of 20 MHz,
and minimal low-pass filtering, and both channels driven with a
1 MHz filtered sine wave, the THD is –75 dB, noise floor –93 dB
and HD2 –83 dB.

Figure 75. Accommodating Multiple Sources

Rev. C | Page 26 of 32

AD8331/AD8332

V

TP3

+5V

(RED)
TB1
+5V

TP4

(BLACK)

TB2

GND

VREF

R23
2kΩ

OPTIONAL 4-POLE LOW-PASS

VIN+B

C66
SAT

–B

IN

L19

SAT

L20

SAT

3

2

+

L7

120nH FB

L6

120nH FB

7

4

C71 1nF

R22

1kΩ

FILTER

C67
SAT

C46
1µF

AD8541

6

VCM

L17

SAT

L18

SAT

+5VGA

+5VLNA

0.1µF

VCM1

JP13

JP14

JP12

CFB2

18nF

RFB2

274Ω

C51

0.1µF

TP2 GAIN

TP7 GND

R3

(R

CLMP

JP8

DC2H

C54

0.1µF

C55

0.1µF

JP7

DC2L

S3

E

)

IN2

C50

0.1µF

L12
120nH FB

C80

22PF

+5VLNA

C41

0.1µF

C83
1nF

C69

0.1µF

100Ω

120nH FB

120nH FB

TP5

0.1µF

C48

0.1µF

R27

L11

L10

R26

100Ω

C53

0.1µF

C68
1nF

C49

JP5

IN2

C74
1nF

C78
1nF

AD8332ARU

1

LMD2

2

INH2

3

VPS2

4

LON2

5

LOP2

6

COM2

7

VIP2

8

VIN2

9

VCM2

10

GAIN

11

CLMP

12

VOH2

13

VOL2

14

COM

+5VGA

C45

0.1µF

LMD1

INH1

VPS1

LON1

LOP1

COM1

VIP1

VIN1

VCM1

HILO

ENB

VOH1

VOL1

VPSV

C85

1nF

28

27

26

+5VLNA

25

24

23

22

21

20

C77
1nF

19

+5VGA

18

17

16

15

C70

0.1µF

JP6

IN1

ENABLE

JP16

DISABLE

120nH FB

120nF FB

22 PF

C42

0.1µF

C43

0.1µF

R24

100Ω

L9

L8

R25

100Ω

C79

VCM1

120nH FB

CFB1
18nF

RFB1
274Ω

C59

0.1µF

0.1µF

0.1µF

L13

+5VGA

HI GAIN

JP10
LO GAIN

JP9

C58

C56

JP10

TP6

C60

0.1µF

OPTIONAL 4-POLE LOW-PASS

L1

SAT

JP17

L14

SAT

FILTER

SAT

C64
SAT

SAT

E

L15

L16

S1

IN1

VIN+A

C65
SAT

VIN–A

03199-C-076

Figure 76. Schematic, TGC, VGA Section

Rev. C | Page 27 of 32

AD8331/AD8332

ADP3339AKC-3.3

+5V

312

IN

OUT

OUT
TAB

S2

EXT CLOCK

R17

49.9Ω

+3.3VCLK

C86

0.1µF

V

DD

20MHz

GND

SG-636PCE

OUT

2

VR1

OE

U6

GND

+

14

3

C44

1µF

+

C63

0.1µF

C47
10µF

6.3V

120nH FB

120nH FB

120nH FB

120nH FB

+3.3VCLK

3

JP 4

2

EXT

1

INT

L5

L4

L3

L2

R18
499Ω

R16
5kΩ

R19
499Ω

+3.3VCLK

C31

0.1µ

F

+3.3VADDIG

C30

0.1µ

F

+3.3VAVDD

C29

0.1µ

F

+3.3VDVDD

C1

0.1

µ

F

U5

74VHC04

U5

74VHC04

SPARES

10µF

R5

R20

R4

1.5kΩ

C33

10µF

6.3V

+

C34

10µF

6.3V

1.5kΩ1.5kΩ

0.1µF

33Ω

R6

33Ω

R8

33Ω

R7

33Ω

C20

JP 11JP 3

R41

4.7kΩ

C17

0.1µF

10µF

0.1µF

C39

C16

0.1µF

C32

0.1µF

C19
1nF

VIN+_A

V

IN

VREF

VIN–B

V

–_A

1.5kΩ

C35

0.1µF

C36

0.1µF

C38

0.1µF

C37

0.1µF

+B

IN

R12

4.7kΩ

ADCLK

ADCLK

74VHC04

4312

U5

74VHC04

U5

74VHC04

11

U5

74VHC04

TP 12

U5

TP 13

DATA

CLK

JP 1

3

1

2

8965

1213

10

Figure 77. Converter Schematic

+3.3VAVDD

C2

+

6.3V

C61

18pF

C18
1nF

C40

TP 9

+

C12
10µF

6.3V

C15
1nF

C62

18pF

R9

0Ω

+3.3VADDIG

C52

10nF

C57

10nF

DNC

DNC

D0_B

D1_B

D2_B

D3_B

D4_B

D5_B

0.1µF

C26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

C22

0.1µF

AGND

VIN+_A

VIN –_A

AGND

AVDD

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD

AGND

VIN –_B

VIN+_B

AGND

AVDD

CLK_B

DCS

DFS

PDWN_B

OEB_B

DNC

DNC

D0_B

D1_B

D2_B

DRGND

DRVDD

D3_B

D4_B

D5_B

C24
1nF

C21
1nF

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

OTRA_A

D11_A(MSB)

D10_A

DRGND

DRVDD

U1 A/D CONVERTER AD9238

DRVDD

DRGND

OTRB_B

D11_B(MSB)

D10_B

AVDD

D9_A

D8_A

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

D9_B

D8_B

D7_B

D6_B

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

ADCLK

R10
0Ω

4.7kΩ

R15
0Ω

R11
100Ω

JP 2

SHARED

REF

Y

R14

+3.3VADDIG

OTR_A

D11_A

D10_A

D9_A

D8_A

C23

0.1µF

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

C13
1nF

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

N

+3.3VADDIG

C25
1nF

C14

0.1µF

C11

+

10µF

6.3V

03199-C-077

Rev. C | Page 28 of 32

AD8331/AD8332

VCC
GND

Y1
Y2
Y3

Y4
Y5
Y6
Y7

Y8

20

10

C3

0.1µF

18
17
16

15
14
13
12

11

+

+3.3VDVDD

C28
10µF

6.3V

+3.3VDVDD

20

U7

VCC
GND

Y1
Y2

Y3
Y4
Y5
Y6

Y7
Y8

10

C8

0.1µF

18
17

16
15
14
13

12
11

C10

0.1µF

+

C76
10µF

6.3V

OTR_A

D11_A

D10_A

D9_A
D8_A
D7_A

D6_A

D5_A
D4_A

D3_A
D2_A
D1_A
D0_A

DNC
DNC

DATACLKA

22× 4

18

RP 9

7

2

6

3

54

18

22× 4

RP 10

7

2

6

3

54

8

22 × 4

1

RP 11

7

2

6

3

54

18

22× 4

RP 12

7

2

6

3

54

19

19

1

2
3
4

5
6
7
8

9

1

2
3

4
5
6
7
8

9

G1

74VHC541

G2
A1
A2
A3

A4
A5
A6
A7

A8

G1

74VHC541

G2
A1
A2

A3
A4
A5
A6

A7
A8

U10

R40
22Ω

22× 4

18

RP 1

7

2

6

3

54

22× 4

18

RP2

7

2

6

3

54

18

22× 4

RP 3

7

2

6

3

54

18

22× 4

RP 4

7

2

6

3

54

2
4
6
8

10
12
14
16

18
20
22
24

26 25
28 27
30

34
36
38
40

SAM080UPM

1
3
5
7

9
11
13
15

17
19
21
23

29
3132
33

35
37
39

OTR_B

D11_B
D10_B

D9_B
D8_B
D7_B

D6_B
D5_B

D4_B

D3_B
D2_B
D1_B
D0_B

DNC

DNC

18

22× 4

RP 13

7

2

6

3

54

22× 4

18

RP 14

7

2

6

3

54

18

22× 4

RP 15

7

2

6

3

54

22× 4

18

RP 16

7

2

6

3

54

DATACLK

19

19

1

2
3

4
5
6
7

8
9

1

2

3
4
5
6
7

8
9

G1

74VHC541

G2
A1

A2
A3
A4
A5

A6
A7
A8

G1

74VHC541

G2
A1

A2
A3
A4
A5

A6
A7
A8

U2

U3

20

VCC

10

GND

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

+3.3VDVDD

20

VCC

10

GND

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

+3.3VDVDD

++

C7

0.1µFC90.1µF

C4

0.1µFC50.1µFC60.1µF

C27
10µF

6.3V

+

C75
10µF

6.3V

Figure 78. Interface Schematic

22× 4

18

RP 5

7

2

6

3

54

22× 4

8

1

RP 6

7

2

6

3

54

22× 4

18

RP 7

7

2

6

3

54

18

22× 4

RP 8

7

2

6

3

54

R39
22Ω

42
44

46

48 47

52
54 53

HEADER UP MALE NO SHROUDHEADER UP MALE NO SHROUD

56 55

58
60
62
64

66

68

70

72

74
76
78
80

SAM080UPM

41
43
45

4950
51

57
59
61
63

65
67
69
71

73
75
77
79

03199-B-078

Rev. C | Page 29 of 32

AD8331/AD8332

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8331

PIN 1

1

LMD

INH

VPSL

LON
LOP

COML

VIP
VIN

MODE

GAIN

IDENTIFIER

2
3
4
5

(Not to Scale)

6
7
8
9

10

AD8331

TOP VIEW

Figure 79. 20-Lead QSOP

Table 5. 20–Lead QSOP (RQ PACKAGE)

Pin No. Name Description

1 LMD LNA Signal Ground
2 INH LNA Input
3 VPSL LNA 5V Supply
4 LON LNA Inverting Output
5 LOP LNA Noninverting Output
6 COML LNA Ground
7 VIP VGA Noninverting Input
8 VIN VGA Inverting Input
9 MODE Gain Slope Logic Input
10 GAIN Gain Control Voltage
11 VCM Common-Mode Voltage
12 CLMP Output Clamping Level
13 HILO Gain Range Select (HI or LO)
14 VPOS VGA 5 V Supply
15 VOH Noninverting VGA Output
16 VOL Inverting VGA Output
17 COMM VGA Ground
18 ENBV VGA Enable
19 ENBL LNA Enable
20 COMM VGA Ground

20
19
18
17
16
15
14
13
12
11

COMM
ENBL
ENBV
COMM
VOL
VOH
VPOS
HILO
RCLMP
VCM

03199-C-079

Rev. C | Page 30 of 32

AD8331/AD8332

AD8332

PIN 1

1

LMD2

INH2

VPS2

LON2

LOP2

COM2

VIP2
VIN2

VCM2

GAIN

RCLMP

VOH2

VOL2

COMM

IDENTIFIER

2
3
4
5
6

(Not to Scale)

7
8

9
10
11
12
13
14

AD8332

TOP VIEW

Figure 80. 28-Lead TSSOP

Table 6. 28–Lead TSSOP (AR PACKAGE)

Pin No. Name Description

1 LMD2 CH2 LNA Signal Ground
2 INH2 CH2 LNA Input
3 VPS2 CH2 Supply LNA 5 V
4 LON2 CH2 LNA Inverting Output
5 LOP2 CH2 LNA Noninverting Output
6 COM2 CH2 LNA Ground
7 VIP2 CH2 VGA Noninverting Input
8 VIN2 CH2 VGA Inverting Input
9 VCM2 CH2 Common-Mode Voltage
10 GAIN Gain Control Voltage
11 RCLMP Output Clamping Resistor
12 VOH2 CH2 Noninverting VGA Output
13 VOL2 CH2 Inverting VGA Output
14 COMM VGA Ground (Both Channels)
15 VPSV VGA Supply 5 V (Both Channels)
16 VOL1 CH1 Inverting VGA Output
17 VOH1 CH1 Noninverting VGA Output
18 ENB Enable—VGA/LNA
19 HILO VGA Gain Range Select (HI or LO)
20 VCM1 CH1 Common-Mode Voltage
21 VIN1 CH1 VGA Inverting Input
22 VIP1 CH1 VGA Noninverting Input
23 COM1 CH1 LNA Ground
24 LOP1 CH1 LNA Noninverting Output
25 LON1 CH1 LNA Inverting Output
26 VPS1 CH1 LNA Supply 5 V
27 INH1 CH1 LNA Input
28 LMD1 CH1 LNA Signal Ground

28

LMD1

27

INH1

26

VPS1

25

LON1

24

LOP1

23

COM1

22

VIP1

21

VIN1

20

VCM1

19

HILO

18

ENB

17

VOH1

16

VOL1

15

VPSV

03199-B-081

Table 7. 32–Lead LFCSP (AC PACKAGE)

LON1

VPS1

INH1

LMD1

LMD2

INH2
VPS2
LON2

VIP1

VIN1

VCM1

COM1

LOP1

1
2
3
4
5
6
7
8

LOP2

3132

PIN 1
INDICATOR

(Not to Scale)

10

COM2

2930

28

AD8332

TOP VIEW

1211

VIP2

VIN2

HILO

ENBL

252627

14139

15 16

GAIN

VCM2

MODE

Figure 81. 32-Lead LFCSP

ENBV

24
23
22
21
20
19
18
17

RCLMP

COMM

VOH1
VOL1
VPSV
NC
VOL2
VOH2
COMM

03199-C-082

Pin No. Name Description

1 LON1 CH1 LNA Inverting Output
2 VPS1 CH1 LNA Supply 5 V
3 INH1 CH1 LNA Input
4 LMD1 CH1 LNA Signal Ground
5 LMD2 CH2 LNA Signal Ground
6 INH2 CH2 LNA Input
7 VPS2 CH2 LNA Supply 5 V
8 LON2 CH2 LNA Inverting Output
9 LOP2 CH2 LNA Noninverting Output
10 COM2 CH2 LNA Ground
11 VIP2 CH2 VGA Noninverting Input
12 VIN2 CH2 VGA Inverting Input
13 VCM2 CH2 Common-Mode Voltage
14 MODE Gain Slope Logic Input
15 GAIN Gain Control Voltage
16 RCLMP Output Clamping Level Input
17 COMM VGA Ground
18 VOH2 CH2 Noninverting VGA Output
19 VOL2 CH2 Inverting VGA Output
20 NC Not Connected
21 VPSV VGA Supply 5 V
22 VOL1 CH1 Inverting VGA Output
23 VOH1 CH1 Noninverting VGA Output
24 COMM VGA Ground
25 ENBV VGA Enable
26 ENBL LNA Enable
27 HILO VGA Gain Range Select (HI or LO)
28 VCM1 CH1 Common-Mode Voltage
29 VIN1 CH1 VGA Inverting Input
30 VIP1 CH1 VGA Noninverting Input
31 COM1 CH1 LNA Ground
32 LOP1 CH1 LNA Noninverting Output

Rev. C | Page 31 of 32

AD8331/AD8332

C

Y

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

Figure 82. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)

Dimensions shown in millimeters

5.00

BSC SQ

PIN 1

1.00

0.85

0.80

12° MAX

SEATING
PLANE

INDICATOR

TOP

VIEW

4.75

BSC SQ

0.80 MAX

0.65 TYP

0.30

0.20 REF

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 83. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32)

Dimensions shown in millimeters

1.20 MAX

SEATING

PLANE

0.60 MAX

0.05 MAX

0.02 NOM

15

4.50

4.40

4.30

141

0.20

0.09

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

6.40 BSC

0.60 MAX

25

24

17

16

BOTTOM

VIEW

8°
0°

32

1

8

9

3.50 REF

0.75

0.60

0.45

PIN 1
INDICATOR

3.25

3.10 SQ

2.95

0.25MIN

0.341
BSC

20 11

1

PIN 1

0.065

0.049

0.010

0.004

OPLANARIT

0.004
COMPLIANT TO JEDEC STANDARDS MO-137AD

Figure 84. 20 Lead Shrink Outline [QSOP] (RQ-20)

0.025
BSC

0.012

0.008

0.069

0.053

10

SEATING
PLANE

0.154
BSC

0.236
BSC

0.010

0.006

8°
0°

0.050

0.016

Dimensions shown in millimeters

ORDERING GUIDE

AD8331/AD8332
Models

AD8331ARQ –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331ARQ-REEL –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331ARQ-REEL7 –40°C to +85°C Shrink Small Outline Package 150 mil Body, 25 mil pitch RQ-20
AD8331-EVAL Evaluation Board with AD8331ARQ
AD8332ARU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL7 –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ACP-REEL –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-32
AD8332ACP-REEL7 –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-32
AD8332-EVAL Evaluation Board with AD8332ARU

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C03199-0-11/03(C)

Temperature Range Package Description

Rev. C | Page 32 of 32

Package Outline