Analog Devices AD8331 2 c Datasheet

Ultralow Noise VGAs with

FEATURES

Ultralow noise preamplifier

Voltage noise = 0.74 nV/√Hz

Current noise = 2.5 pA/√Hz
3 dB bandwidth: 120 MHz
Low power: 125 mW/channel
Wide gain range with programmable postamp

–4.5 dB to +43.5 dB

+7.5 dB to +55.5 dB
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
Available in space-saving chip scale package

APPLICATIONS

Ultrasound and sonar time-gain control
High performance AGC systems
I/Q signal processing
High speed dual ADC driver

GENERAL DESCRIPTION

The AD8331/AD8332 are single- and dual-channel ultralow
noise, linear-in-dB, variable gain amplifiers. Although optimized
for ultrasound systems, they are usable as low noise variable
gain elements at frequencies up to 120 MHz.

Each channel consists of an ultralow noise preamplifier (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamplifier with adjustable output limiting. The LNA gain is
19 dB with a single-ended input and differential outputs capable
of accurate, programmable active input impedance matching by
selecting an external feedback resistor. Active impedance
control optimizes noise performance for applications that
benefit from input matching.

The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching. Differential
signal paths lead to superb second and third order distortion
performance and low crosstalk.

Preamplifier and Programmable R

IN

AD8331/AD8332

FUNCTIONAL BLOCK DIAGRAM

VPSV

VIN1VIP1LOP1LON1

[(–48 to 0) + 21] dB

–

+

+

–

VIN2VIP2LOP2LON2

COMM

VGA 1

BIAS AND

INTERPOLATOR

VGA 2

ENB

V

MID

VPS1

COM1

INH1

LMD1

LMD2

INH2

VPS2

COM2

25 24 22 21 15 20 9 19

26

23

+19dB

+

27

LNA 1
–

28

BIAS

(V

)

MID

1

–

LNA 2

+

2

3

6

4 5 7 8 14 18 11

Figure 1. AD8332 Shown 28-Lead TSSOP

50

40

30

)

20

B
d

(
N

I

10

A
G

0

–10

–20

100k

V

= 1V

GAIN

0.8V

0.6V

0.4V

0.2V

0V

1M 1G100M10M

FREQUENCY (Hz)

Figure 2. Frequency Response vs. Gain

The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier may
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output may be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.

The operating temperature range is –40°C to +85°. The
AD8331 is available in a 20-lead QSOP package, and the
AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They
require a single 5 V supply, and the quiescent power
consumption is 125 mW/ch. A power-down (enable) pin is
provided.

3.5dB/15.5dB

POST
AMP1

POST
AMP2

CLAMP

RCLMP

GAIN

INT

HILOVCM2VCM1

VOH1

17

16

VOL1

10

GAIN

13

VOL2

12

VOH2

03199-B-001

03199-C-002

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8331/AD8332

TABLE OF CONTENTS

REVISION HISTORY.................................................................. 2

AD8331, AD8332—Specifications.................................................. 3

Absolute Maximum Ratings............................................................ 6

ESD CAUTION ............................................................................ 6

AD8331, AD8332—Typical Performance Characteristics .......... 7

Test Circuits..................................................................................... 15

Theory of Operation...................................................................... 17

Overview...................................................................................... 17

Low Noise Amplifier (LNA)...................................................... 17

Variable Gain Amplifier............................................................. 19

Postamplifier............................................................................... 21

Applications..................................................................................... 22

LNA – External Components................................................... 22

Driving ADCs ............................................................................. 24

Overload...................................................................................... 24

Optional Input Overload Protection. ...................................... 25

Layout, Grounding, And Bypassing......................................... 25

Multiple Input Matching........................................................... 25

Disabling the LNA...................................................................... 25

Measurement Considerations................................................... 26

Ultrasound TGC Application ................................................... 26

Pin Configuration and Function Descriptions........................... 30

AD8331........................................................................................ 30

AD8332........................................................................................ 31

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

Revision C

11/03—Data Sheet Changed from REV. B to REV. C

Addition of New Part...........................................................Universal

Changes to Figures ...............................................................Universal

Updated Outline Dimensions..........................................................32

5/03—Data Sheet Changed from REV. A to REV. B

Edits to Ordering Guide....................................................................32

Edits to Ultrasound TGC Application section................................25

Added Figure 71, Figure 72, and Figure 73......................................26

Updated Outline Dimensions............................................................31

2/03—Data Sheet Changed from REV. 0 to REV. A

Edits to Ordering Guide.....................................................................32

Rev. C | Page 2 of 32

AD8331/AD8332

AD8331, AD8332—SPECIFICATIONS

Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R

pin floating, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

V

CM

Parameter Conditions Min Typ Max Unit

LNA CHARACTERISTICS

Gain

Single-Ended Input
to Differential Output

Input to Output (Single-Ended) 13 dB

Input Voltage Range AC-Coupled ±275 mV

R

Input Resistance

280 Ω 50 Ω

FB =

R

= 412 Ω 75 Ω

FB

R

562 Ω 100 Ω

FB =

R

1.13 kΩ 200 Ω

FB =

R

∞ 6 kΩ

FB =

Input Capacitance 13 pF
Output Impedance Single-Ended, Either Output 5 Ω
–3 dB Small Signal Bandwidth V

= 0.2 V p-p 130 MHz

OUT

Slew Rate 650 V/µs
Input Voltage Noise

= 0 Ω, HI or LO Gain,

R

S

= ∞, f = 5 MHz

R

FB

Input Current Noise RFB = ∞, HI or LO Gain, f = 5 MHz 2.5 pA/√Hz
Noise Figure f = 10 MHz, LOP Output

Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RFB = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2

HD2 –56 dBc
HD3

= 0.5 V p-p,

V

OUT

Single-Ended, f = 10 MHz

Output Short-Circuit Current Pins LON, LOP 165 mA

LNA + VGA CHARACTERISTICS

–3 dB Small Signal Bandwidth V
–3 dB Large Signal Bandwidth V

= 0.2 V p-p 120 MHz

OUT

= 2 V p-p 110 MHz

OUT

LO Gain 300 V/µs Slew Rate
HI Gain 1200 V/µs

Input Voltage Noise

Noise Figure V

Active Termination Match

= 0 Ω, HI or LO Gain,

R

S

R

= ∞, f = 5 MHz

FB

= 1.0 V

GAIN

RS = RIN = 50 Ω,
f = 10 MHz, Measured

R

= RIN = 200 Ω,

S

f = 5 MHz, Simulated

Unterminated

RS = 50 Ω, RFB = ∞,
f = 10 MHz, Measured

R

= 200 Ω, RFB = ∞,

S

f = 5 MHz, Simulated
V

= 0.5 V, LO Gain 48 nV/√Hz Output-Referred Noise

GAIN

V

= 0.5 V, HI Gain 178 nV/√Hz

GAIN

Output Impedance, Postamplifier DC to 1 MHz 1 Ω
Output Signal Range, Postamplifier

≥ 500 Ω,

R

L

Unclamped, Either Pin

Differential 4.5 V p-p

Output Offset Voltage

Differential –50 ±5 +50 mV

V

GAIN

= 0.5 V

Common-Mode

Output Short-Circuit Current 45 mA

= ∞, CL = 1 pF,

CLMP

19 dB

0.74 nV/√Hz

–70 dBc

0.82 nV/√Hz

4.15 dB

2.0 dB

2.5 dB

1.0 dB

V

± 1.125 V

CM

–125 –25 +100 mV

Rev. C | Page 3 of 32

AD8331/AD8332

Parameter Conditions Min Typ Max Unit

Harmonic Distortion V

HD2 –88 dBc
HD3
HD2 –68 dBc

HD3
Input 1 dB Compression Point V
Two-Tone Intermodulation

Distortion (IMD3)

Channel-to-Channel Crosstalk
(AD8332)
Overload Recovery

Group Delay Variation 5 MHz < f < 50 MHz, Full Gain Range ±2 ns

ACCURACY

Absolute Gain Error2

Gain Law Conformance3 0.1 V < V
Channel-to-Channel Gain Matching 0.1 V < V

GAIN CONTROL INTERFACE
(Pin GAIN)

Gain Scaling Factor 0.10 V < V

Input Voltage (V

) Range 0 to 1.0 V

GAIN

Input Impedance 10 MΩ
Response Time 48 dB Gain Change to 90% Full Scale 750 ns

COMMON-MODE INTERFACE
(Pin VCMn)

Input Resistance Current Limited to ±1 mA 30 Ω
Output CM Offset Voltage VCM = 2.5 V –125 –25 +100 mV
Voltage Range

= 0.5 V, V

GAIN

f = 1 MHz

f = 10 MHz

= 0.25 V, V

GAIN

V

= 0.72 V, V

GAIN

= 0.5 V, V

V

GAIN

V

= 0.5 V, V

GAIN

V

= 0.5 V, V

GAIN

V

= 0.5 V, V

GAIN

= 1.0 V,

V

GAIN

= 50 mV p-p/1 V p-p,

V

IN

= 1 V p-p

OUT

–85 dBc

–65 dBc

= 1 V p-p, f = 1 MHz–10 MHz 7 dBm1

OUT

= 1 V p-p, f = 1 MHz –80 dBc

OUT

= 1 V p-p, f = 10 MHz –72 dBc

OUT

= 1 V p-p, f = 1 MHz 38 dBm Output Third Order Intercept

OUT

= 1 V p-p, f = 10 MHz 33 dBm

OUT

= 1 V p-p, f = 1 MHz –84 dB

OUT

5 ns

f = 10 MHz

0.05 V < V

0.10 V < V

0.95 V < V

< 0.10 V –1 +0.5 +2 dB

GAIN

< 0.95 V –1 ±0.3 +1 dB

GAIN

< 1.0 V –2 –1 +1 dB

GAIN

< 0.95 V ±0.2 dB

GAIN

< 0.95 V ±0.1 dB

GAIN

< 0.95 V 50 dB/V

GAIN

LO Gain –4.5 to +43.5 dB Gain Range
HI Gain +7.5 to +55.5 dB

V

= 2.0 V p-p 1.5 to 3.5 V

OUT

ENABLE INTERFACE
(Pins ENB, ENBL, ENBV)

Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Input Resistance

Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ
V

= 30 mV p-p 300 µs Power-Up Response Time

INH

V

= 150 mV p-p 4 ms

INH

HILO GAIN RANGE INTERFACE
(Pin HILO)

Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50 kΩ

1

All dBm values are referred to 50 Ω, unless otherwise noted.

2

Conformance to theoretical gain expression (see Equation 1).

3

Conformance to best fit dB linear curve.

Rev. C | Page 4 of 32

AD8331/AD8332

Parameter Conditions Min Typ Max Unit

OUTPUT CLAMP INTERFACE
(Pin RCLMP; HI or LO Gain)

Accuracy

HILO = LO R
HILO = HI R

MODE INTERFACE
(Pin MODE)

Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200 kΩ

POWER SUPPLY
(Pins VPS1, VPS2, VPSV, VPSL, VPOS)

Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel 25 mA
Power Dissipation per channel No Signal 125 mW
Disable Current
AD8332 (VGA and LNA) 300 600 µA
AD8331 (VGA and LNA) 240 400 µA
AD8332 (ENBL) Each Channel 12 mA
AD8332 (ENBV) Each Channel 13 mA
AD8331 (ENBL) 11 mA
AD8331 (ENBV) 14 mA
PSRR V

= 2.74 kΩ, V

CLMP

= 2.21 kΩ, V

CLMP

= 1 V p-p (Clamped) ±50 mV

OUT

= 1 V p-p (Clamped) ±75 mV

OUT

= 0, f = 100 kHz –68 dB

GAIN

Rev. C | Page 5 of 32

AD8331/AD8332

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings

Parameter Rating

Voltage

Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHn) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V

Power Dissipation

RU-28 Package (AD8332)4 0.96 W
CP-32 Package (AD8332)5 1.97 W
RQ-20 Package (AD8331)4 0.78 W

Temperature

Operating Temperature –40°C to +85°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

θJA

RU-28 Package (AD8332)4 68°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 83°C/W

θJC

RU-28 Package (AD8332)4 14°C/W
CP-32 Package (AD8332)5 33°C/W
RQ-20 Package (AD8331)4 n/a

4

Four-Layer JEDEC Board (2S2P).

5

Exposed pad soldered to board, nine thermal vias in pad — JEDEC 4-Layer

Board J-STD-51-9.

Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 6 of 32

AD8331/AD8332

AD8331, AD8332—TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, R
–4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.

60

50

40

)

30

B
d

(
N

I
A

20

G

10

0

MODE = LO

HILO = HI

HILO = LO

MODE = HI
(AC PACKAGE
ONLY)

50

SAMPLE SIZE = 80 UNITS
V

GAIN

40

S
T

30

I
N
U

F
O

%

20

10

= ∞, CL = 1 pF, VCM = 2.5 V,

CLMP

= 0.5V

–10

0 0.2

Figure 3. Gain vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

00.2

and MODE (MODE Available on AC Package)

GAIN

–40°C

Figure 4. Absolute Gain Error vs. V

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

–1.5

–2.0

1MHz

30MHz

0 0.2

Figure 5. Absolute Gain Error vs. V

0.60.4 1.00.8 1.1

V

(V)

GAIN

+25°C

+85°C

0.60.4

V

(V)

GAIN

at Three Temperatures

GAIN

10MHz

70MHz

0.60.4

V

(V)

GAIN

at Various Frequencies

GAIN

1.00.8 1.1

1.00.8 1.1

03199-C-003

03199-C-004

03199-C-005

0

–0.1

GAIN ERROR (dB)

Figure 6. Gain Error Histogram

25

SAMPLE SIZE = 50 UNITS

20

= 0.2V

V

GAIN

15
10

5
0

25

% OF UNITS

V

= 0.7V

GAIN

20
15
10

5
0

–0.05

–0.03

–0.01

0.01

–0.11

–0.17

–0.15

–0.13

–0.09

–0.07

CHANNEL-TO-CHANNEL GAIN MATCH(dB)

Figure 7. Gain Match Histogram for V

)
B
d

(
N

I
A
G

–10

–20

50

40

30

20

10

0

100k

V

= 1V

GAIN

0.8V

0.6V

0.4V

0.2V

0V

1M 1G100M10M

FREQUENCY (Hz)

0.03

0.05

0.07

GAIN

0.09

= 0.2 V and 0.7 V

Figure 8. Frequency Response for Various Values of V

0.11

0.13

0.15

0.40–0.3 –0.2 0.1–0.4–0.5 0.30.2 0.5

0.21

0.19

0.17

GAIN

03199-C-006

03199-C-007

03199-C-008

Rev. C | Page 7 of 32

AD8331/AD8332

GAIN (dB)

60

50

40

30

20

10

0

–10

V

GAIN

0.8V

0.2V

1M 1G100k 100M10M

= 1V

0.6V

0.4V

0V

FREQUENCY (Hz)

03199-C-009

0

V

= 1 V p-p

OUT

–10

–20

–30

)
B
d

(

–40

K
L
A
T
S

–50

S

V

= 1V

–60

–70

–80

–90

GAIN

0.9V

0.7V

0.5V

1M100k 100M10M

FREQUENCY (Hz)

0.4V

03199-C-012

O
R
C

Figure 9. Frequency Response for Various Values of V

30

V

=0.5V

GAIN

20

10

0

–10

GAIN (dB)

–20

–30

–40

100k

RIN=RS=50Ω,75Ω,100Ω

RIN=RS=1kΩ

RIN=RS= 500Ω

R

=200Ω

IN=RS

1M 1G

FREQUENCY (Hz)

, HILO = HI

GAIN

100M10M

03199-C-010

Figure 10. Frequency Response for Various Matched Source Impedances

30

V

= 0.5V

GAIN

R

= ∞

FB

20

10

)

0

B
d

(
N

I
A

–10

G

–20

–30

–40

1M 1G100k 100M10M

FREQUENCY (Hz)

Figure 11. Frequency Response, Untermin ated, R

= 50 Ω

S

03199-C-011

Figure 12. Channel-to-Channel Crosstalk vs.

Frequency for Various Values of V

50

1µF
COUPLING

0.1µF
COUPLING

1M100k 100M10M

FREQUENCY(Hz)

45

40

35

30

25
20

GROUP DELAY (ns)

15

10

5

0

GAIN

Figure 13. Group Delay vs. Frequ ency

OFFSET VOLTAGE (mV)

–10

–20

–10

–20

20

10

0

20

10

0

HI GAIN

T=+25°C

LO GAIN

T = –40°C

T = –40°C

T = –40°C

T=+85°C

V

(V)

GAIN

T=+25°C

T=+25°C

T = –40°C

T=+85°C

T=+85°C

Figure 14. Representative Differential Output Offset Voltage vs. V

Temperatures

1.10.40.20 0.30.1 0.90.70.5 0.80.6 1.0

at Three

GAIN

03199-C-013

03199-C-014

Rev. C | Page 8 of 32

AD8331/AD8332

35

SAMPLE SIZE = 100

0.2V < V

30

GAIN

< 0.7V

25

20

15

% TOTAL

10

5

0

GAIN SCALING FACTOR

Figure 15. Gain Scaling Factor Histogram

100

SINGLE ENDED, PIN VOH OR VOL
R

= ∞

L

)

Ω

(

10

E
C
N
A
D
E
P
M

I
T

U
P

1

T
U
O

25j

RIN = 75Ω,

= 412

Ω

R

FB

RIN = 100Ω,

= 549

Ω

R

FB

17

–25j

Ω

RIN = 200Ω,

= 1.1k

R

FB

0

Ω

03199-B-015

50.5

50.449.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3

Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz

20

15

10

5

)
B
d

(

0

N

I
A
G

–5

50j

R

= 50

IN

RFB = 270

Ω

RIN = 6kΩ,

=

∞

R

FB

–50j

for Va rious Values of R

RIN = 1k

Ω

RIN = 500

Ω

Ω

,

Ω

FB

100j

f = 100kHz

–100j

RIN = 50Ω, 75Ω,
AND 100

Ω

RIN = 200

RIN = 200

03199-B-018

Ω

Ω

0.1
100k 1M

10k

)

Ω

(

1k

E
C
N
A
D
E
P
M

I
T

U

100

P
N

I

10

FREQUENCY (Hz)

10M 100M

Figure 16. Output Impedance vs. Frequency

RFB = ∞, CSH = 0pF

R

= 6.65kΩ, CSH = 0pF

FB

= 3.01kΩ, CSH = 0pF

R

FB

= 1.1kΩ, CSH = 1.2pF

R

FB

R

= 549Ω, CSH = 8.2pF

FB

R

= 412Ω, CSH = 12pF

FB

R

= 270Ω, CSH = 22pF

FB

1M100k 100M10M

FREQUENCY (Hz)

Figure 17. LNA Input Impedance vs. Frequency for

Various Values of R

and CSH

FB

03199-C-016

03199-C-017

–10

–15

–20

100k

10M

FREQUENCY (Hz)

100M1M

1G

Figure 19. LNA Frequency Response,

IN

100M1M

1G

)
B
d

(
N

I
A
G

–10

–15

–20

20

15

10

–5

100k

5

0

Single-Ended, for Various Values of R

RFB = ∞

10M

FREQUENCY (Hz)

Figure 20. LNA Frequency Response, Unterminated, Single-Ended

03199-C-019

03199-C-020

Rev. C | Page 9 of 32

AD8331/AD8332

500

)

z
H

400

/
V
n

(
E

S

I

300

O
N

D
E
R
R
E

200

F
E
R

­T
U
P
T

100

U
O

1.6

1.4

)

1.2

z
H
/
V

1.0

n

(
E

S

I

0.8

O
N

T
U

0.6

P
N

I

0.4

0.2

100

f = 10MHz

HILO = HI

HILO = LO

0

0 0.4

0.2 0.8
V

GAIN

(V)

Figure 21. Output-Referred Noise vs. V

RS = 0, RFB = ∞, V
HILO = LO OR HI

0

= 1V

GAIN

1M 10M

FREQUENCY (Hz)

Figure 22. Short-Circuit Input-Referred Noise vs. Frequency

RS = 0, RFB = ∞,
HILO = LO OR HI, f = 10MHz

GAIN

1.00
RS = 0, RFB = ∞,

0.95

V

= 1V, f = 10MHz

GAIN

0.90

)

0.85

z
H
/

0.80

V
n

(
E

0.75

S

I
O
N

0.70

T
U
P

0.65

N

I

0.60

0.55

03199-C-021

1.00.6

03199-C-022

100M100k

0.50

10–30–50 –10 705030

TEMPERATURE (°C)

Figure 24. Short-Circuit Input-Referred Noise vs. Temperature

10

f = 5MHz, R

)

z
H
/
V
n

(
E

S

I

1.0

O
N

T
U
P
N

I

0.1
110

7

6

=∞, V

FB

RS = THERMAL NOISE ALONE

= 1V

GAIN

SOURCE RESISTANCE (

100 1k

Ω

Figure 25. Input-Referred Noise vs. R

INCLUDES NOISE OF VGA

)

S

90

03199-C-025

03199-C-024

)

z
H

10

/
V
n

(
E

S

I
O
N
T
U
P

1

N

I

0.1
0 0.4

0.2 0.8
V

GAIN

(V)

Figure 23. Short-Circuit Input-Referred Noise vs. V

GAIN

03199-C-023

1.00.6

Rev. C | Page 10 of 32

5

)
B
d

(
E

4

R
U
G

I
F

3

E
S

I
O
N

2

1

0

R

IN

SIMULATION

10050 1k

Figure 26. Noise Figure vs. R

= 50Ω

75Ω
100Ω
200Ω

R

= ∞

FB

SOURCE RESISTANCE (Ω)

for Variou s Value s of RIN

S

03199-C-026