Analog Devices AD8324 Datasheet

3.3 V Upstream

FEATURES

Supports DOCSIS 2.0 and Euro-DOCSIS standards for reverse path transmission systems Gain programmable in 1 dB steps over a 59 dB range Low distortion at 61 dBmV output: –59 dBc SFDR at 21 MHz –54 dBc SFDR at 65 MHz Output noise level @ minimum gain 1.3 nV/√Hz Maintains 75 Ω output impedance in TX-enable and Transmit-disable condition Upper bandwidth: 100 MHz (full gain range)

3.3 V supply operation Supports SPI® interfaces

APPLICATIONS

DOCSIS 2.0 and Euro-DOCSIS cable modems CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers

Cable Line Driver

AD8324

FUNCTIONAL BLOCK DIAGRAM

BYP

DIFF =

OUT+

OUT–

RAMP

04339-0-001

IN+

DIFF OR SINGLE INPUT AMP

IN–

ZIN(SINGLE) = 550Ω Z

(DIFF) = 1100Ω

AD8324

GND DATEN DATACLK

VERNIER

ATTENUATION

CORE

DECODE

DATA LATCH

SHIFT

OUTPUT

STAGE

OUT

75Ω

POWER-

DOWN LOGIC

SLEEP

TXEN

Figure 1. Functional Block Diagram

–40

GENERAL DESCRIPTION

The AD83241 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8324 ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications. The gain of the AD8324 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB.

The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 transformer.

Distortion performance of –54 dBc is achieved with an output level up to 61 dBmV at 65 MHz bandwidth.

This device has a sleep mode function that reduces the quiescent current to 30 µA and a full power-down function that reduces power-down current to 2.5 mA.

The AD8324 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8324 operates from a single 3.3 V supply.

= 61dBmV @ DEC 60

–50

–60

DISTORTION (dBc)

–70

–80

515

OUT

THIRD HARMONIC

25 35 45 55 65

FREQUENCY (MHz)

Figure 2. Worst Harmonic Distortion vs. Frequency

Patent pending.

= 61dBmV @ DEC 60

OUT

SECOND HARMONIC

04339-0-002

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD8324

TABLE OF CONTENTS

Specifications..................................................................................... 3

Power Saving Features ............................................................... 12

Logic Inputs (TTL/CMOS Compatible Logic)......................... 4

Timing Requirements.................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Functional Descriptions ........................6

Typical Performance Characteristics............................................. 7

Applications..................................................................................... 10

General Applications.................................................................. 10

Circuit Description..................................................................... 10

Gain Programming for the AD8324........................................ 10

Input Bias, Impedance, and Termination ................................10

Output Bias, Impedance, and Termination............................. 10

Power Supply............................................................................... 11

Signal Integrity Layout Considerations................................... 11

Initial Power-Up .........................................................................11

Distortion, Adjacent Channel Power, and DOCSIS............... 12

Utilizing Diplex Filters............................................................... 12

Noise and DOCSIS..................................................................... 12

Evaluation Board Features and Operation.............................. 13

Differential Signal Source.......................................................... 13

Differential Signal from Single-Ended Source....................... 13

Single-Ended Source.................................................................. 13

Overshoot on PC Printer Ports ................................................ 14

Installing Visual Basic Control Software................................. 14

Running AD8324 Software ....................................................... 14

Controlling Gain/Attenuation of the AD8324...................... 14

Transmit Enable and Sleep Mode............................................. 14

Memory Functions..................................................................... 14

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

RAMP Pin and BYP Pin Features ............................................11

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 16

AD8324

SPECIFICATIONS

Table 1. TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1 transformer

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Specified AC Voltage Output = 61 dBmV, Max Gain 27.5 dBmV Input Resistance Single-Ended Input 550 Ω

Differential Input 1100 Ω

Input Capacitance 2 pF

GAIN CONTROL INTERFACE

Voltage Gain Range 58 59.0 60 dB

Max Gain Gain Code = 60 Dec 32.5 33.5 34.5 dB

Min Gain Gain Code = 1 Dec –26.5 –25.5 –24.5 dB Output Step Size Output Step Size Temperature Coefficient TA = –40°C to +85°C ±0.004 dB/°C

OUTPUT CHARACTERISTICS

Bandwidth (–3 dB) All Gain Codes (1–60 Decimal Codes) 100 MHz Bandwidth Roll-Off f = 65 MHz 1.7 dB 1 dB Compression Point3 Max Gain, f = 10 MHz, Output Referred 19.6 21 dBm

Min Gain, f = 10 MHz, Input Referred 2.1 3.7 dBm

Output Noise2

Max Gain f = 10 MHz 157 166 nV/√Hz

Min Gain f = 10 MHz 1.3 1.5 nV/√Hz

Transmit Disable f = 10 MHz 1.1 1.2 nV/√Hz Noise Figure2

Max Gain f = 10 MHz 15.5 16.0 dB Differential Output Impedance TX Enable and TX Disable 75 ± 30%4 Ω

OVERALL PERFORMANCE

Second-Order Harmonic Distortion

f = 33 MHz, V f = 65 MHz, V

Third-Order Harmonic Distortion

f = 65 MHz, V

2, 6

ACPR Isolation (Transmit Disable)2 Max Gain, f = 65 MHz –75 –70 dB

POWER CONTROL

TX Enable Settling Time Max Gain, VIN = 0 2.5 µs TX Disable Settling Time Max Gain, VIN = 0 3.8 µs Output Switching Transients3 Equivalent Output = 31 dBmV 2.5 6 mV p-p

Equivalent Output = 61 dBmV 27 71 mV p-p

Output Settling

Due to Gain Change Min to Max Gain 60 ns

Due to Input Step Change Max Gain, VIN = 27.5 dBmV 30 ns

POWER SUPPLY

Operating Range 3.13 3.3 3.47 V Quiescent Current Max Gain 195 207 235 mA

Min Gain 25 39 50 mA Transmit Disable (TXEN = 0) 1 2.5 4 mA

OPERATING TEMPERATURE RANGE LFCSP –40 +85 °C QSOP –25 +70 °C

at the device output.

0.6 1.0 1.4 dB/LSB

5, 3

= 61 dBmV @ Max Gain –66 –60 dBc

OUT

= 61 dBmV @ Max Gain –58 –53 dBc

OUT

f = 21 MHz, V

= 61 dBmV @ Max Gain –59 –57.5 dBc

OUT

= 61 dBmV @ Max Gain –54 –52.5 dBc

OUT

–61 –58 dBc

SLEEP

Mode (Power-Down)

30 500 µA

Rev. 0 | Page 3 of 16

AD8324

TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.

Guaranteed by design and characterization to ±6 sigma for TA = 25°C.

Guaranteed by design and characterization to ±3 sigma for TA = 25°C.

Measured through a 1:1 transformer.

Specification is worst case over all gain codes.

VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.

LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)

Table 2.

DATEN

, CLK, SDATA, TXEN,

Parameter Min Typ Max Unit

Logic 1 Voltage 2.1 Logic 0 Voltage 0

Logic 1 Current (V Logic 0 Current (V

= 3.3 V), CLK, SDATA,

INH

= 0 V), CLK, SDATA,

INL

= 3.3 V), TXEN 50

INH

= 0 V), TXEN −250

INL

= 3.3 V),

INH

= 0 V),

INL

SLEEP

TIMING REQUIREMENTS

Table 3. VCC = 3.3 V, tR = tF = 4 ns, f

Parameter Min Typ Max Unit

Clock Pulse Width (tWH) 16.0 Clock Period (tC) 32.0 Setup Time SDATA vs. Clock (tDS) 5.0

DATEN

vs. Clock (tES)

vs. Clock (tEH)

VALID DATA WORD G1

MSB . . . LSB

VUH

Setup Time Hold Time SDATA vs. Clock (tDH) 5.0

Hold Time Input Rise and Fall Times, SDATA,

SDATA

CLK

SLEEP

, VCC = 3.3 V, unless otherwise noted

DATEN

= 8 MHz, unless otherwise noted

CLK

DATEN

, Clock (tR, tF)

VALID DATA WORD G2

3.3 V

0.8 V 20 nA

−100 nA 190 µA

−30 µA 190 µA

−30 µA

ns ns ns ns ns ns

−600

−250

15.0

3.0 10 ns

VALID DATA BIT

SDAT

MSB MSB-1 MSB-2

DATEN

TXEN

NALO

OUTPUT

8 CLOCK CYCLES

SIGNAL AMPLITUDE (p-p)

GAIN TRANSFER (G1) GAIN TRANSFER (G2)

OFF

04339-0-0030

CLK

Figure 4. SDATA Timng

04339-0-004

Figure 3. Serial Interface Ti ming

Rev. 0 | Page 4 of 16

AD8324

ABSOLUTE MAXIMUM RATINGS

Table 4. AD8324 Stress Ratings

Parameter Rating

Supply Voltage VCC 3.63 V Input Voltage

VIN+, VIN– 1.5 V p-p

DATEN

, SDATA, CLK,

Internal Power Dissipation

QSOP, LFCSP 776 mW

Operating Temperature Range

LFCSP –40°C to +85°C

QSOP –25°C to +70°C Storage Temperature Range –65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C

SLEEP

, TXEN

–0.5 V to +3.63 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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