ANALOG DEVICES AD8315 Service Manual

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FEATURES

Complete RF detector/controller function >50 dB range at 0.9 GHz (−49 dBm to +2 dBm, re 50 Ω) Accurate scaling from 0.1 GHz to 2.5 GHz Temperature-stable linear-in-dB response Log slope of 23 mV/dB, intercept at −60 dBm at 0.9 GHz True integration function in control loop Low power: 20 mW at 2.7 V, 38 mW at 5 V Power-down to 10.8 μW

APPLICATIONS

Single, dual, and triple band mobile handset (GSM, DCS, EDGE) Transmitter power control

GENERAL DESCRIPTION

The AD8315 is a complete low cost subsystem for the precise control of RF power amplifiers operating in the frequency range

0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB. It is intended for use in cellular handsets and other batteryoperated wireless devices. The log amp technique provides a much wider measurement range and better accuracy than controllers using diode detectors. In particular, its temperature stability is excellent over a specified range of −30°C to +85°C.

50 dB GSM PA Controller

AD8315

Its high sensitivity allows control at low signal levels, thus reducing the amount of power that needs to be coupled to the detector.

For convenience, the signal is internally ac-coupled. This high-pass coupling, with a corner at approximately 0.016 GHz, determines the lowest operating frequency. Therefore, the source can be dc grounded.

The AD8315 provides a voltage output, VAPC, that has the voltage range and current drive to directly connect to most handset power amplifiers’ gain control pin. VAPC can swing from 250 mV above ground to within 200 mV below the supply voltage. Load currents of up to 6 mA can be supported.

The setpoint control input is applied to the VSET pin and has an operating range of 0.25 V to 1.4 V. The associated circuit determines the slope and intercept of the linear-in-dB measurement system; these are nominally 23 mV/dB and

−60 dBm for a 50 Ω termination (−73 dBV) at 0.9 GHz. Further simplifying the application of the AD8315, the input resistance of the setpoint interface is over 100 MΩ, and the bias current is typically 0.5 µA.

The AD8315 is available in MSOP and LFCSP packages and consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered down, the sleep current is 4 µA.

FUNCTIONAL BLOCK DIAGRAM

VPOS

ENBL

DET

RFIN

OMM

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

10dB

LOW NOISE

GAIN BIAS

DET

OFFSET COMP’N

10dB

LOW NOISE

BAND GAP

REFERENCE

DET DET DET

10dB 10dB

INTERCEPT

POSITIONING

Figure 1.

OUTPUT ENABLE

DELAY

V-I

VAP C

FLTR

VSET

23mV/dB 250mV TO

1.4V = 50dB

01520-001

×1.35

HI-Z

LOW NOISE (25nV/√Hz) RAIL-TO-RAIL BUFFER

AD8315

TABLE OF CONTENTS

Features .............................................................................................. 1

Practical Loop ............................................................................. 15

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 12

Basic Theory................................................................................ 12

Controller-Mode Log Amps ..................................................... 13

Control Loop Dynamics............................................................ 13

REVISION HISTORY

6/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Ordering Guide.......................................................... 23

1/03—Rev. 0 to Rev. B

Edits to Product Description Section ............................................ 1

Edit to Functional Block Diagram ................................................. 1

Edits to Specifications...................................................................... 2

Edits to Absolute Maximum Ratings ............................................. 3

Ordering Guide Updated................................................................. 3

TPC 9 Replaced with New Figure .................................................. 5

Edits to TPC 27................................................................................. 8

Edit to Figure 1.................................................................................. 9

Edit to Figure 3................................................................................ 10

Edit to Equation 9........................................................................... 10

Edit to Equation 10......................................................................... 10

A Note About Power Equivalency ........................................... 16

Basic Connections...................................................................... 16

Range on VSET and RFIN ........................................................ 17

Transi e n t Resp o n se .................................................................... 17

Mobile Handset Power Control Example ............................... 18

Enable and Power-On................................................................ 19

Input Coupling Options ............................................................ 19

Using the Chip Scale Package................................................... 20

Evaluation Board ........................................................................ 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Edit to Equation 11......................................................................... 10

Edits to Example section ............................................................... 10

Edit to Basic Connections Section ............................................... 12

Edits to Input Coupling Options Section.................................... 14

Table III Becomes Table II............................................................. 15

Table II Recommended Components Deleted ........................... 15

Using the Chip-Scale Package Section Added............................ 15

Edits to Evaluation Board Section................................................ 15

Figure 12 Title Edited..................................................................... 16

Figure 13 Title Edited..................................................................... 16

8-Lead Chip Scale Package (CP-8) Added .................................. 17

Updated Outline Dimensions....................................................... 17

10/99—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD8315

SPECIFICATIONS

VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV

Equivalent dBm Range −44 +2 dBm Logarithmic Slope Logarithmic Intercept

Equivalent dBm Level −66 −57 −51 dBm

RF INPUT INTERFACE Pin RFIN

Input Resistance Input Capacitance

OUTPUT Pin VAPC

Minimum Output Voltage V ENBL low 0.02 V Maximum Output Voltage RL ≥ 800 Ω 2.45 2.6 V vs. Temperature General Limit 2.7 V ≤ V Output Current Drive Source/Sink 5/200 mA/μA Output Buffer Noise 25 nV√Hz Output Noise RF input = 2 GHz, 0 dBm, f Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz Slew Rate 10% to 90%, 1.2 V step (V Response Time FLTR = open, see Figure 26 150 ns

SETPOINT INTERFACE Pin VSET

Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V Logarithmic Scale Factor 43.5 dB/V Input Resistance 100 kΩ Slew Rate 16 V/μs

ENABLE INTERFACE Pin ENBL

Logic Level to Enable Power 1.8 V Input Current when Enable

High Logic Level to Disable Power 0.8 V Enable Time

Disable Time

Power-On/Enable Time

To meet all specifications 0.1 2.5 GHz

0.1 GH 21.5 24 25.5 mV/dB

0.1 GHz −79 −70 −64 dBV

0.1 GHz 2.8 kΩ

0.1 GHz 0.9 pF

≤ 200 mV, ENBL high 0.25 0.27 0.3 V

SET

85°C, V

= 3 V, I

POS

≤ 5.5 V, RL = ∞ V

POS

= 6 mA 2.54 V

OUT

= 100 kHz, C

NOISE

), open loop

SET

= 220 pF 130 nV/√Hz

FLT

− 0.1 V

POS

13 V/μs

POS

20 μA

Time from ENBL high to V

≤ 200 mV, refer to Figure 23

SET

Time from ENBL low to V

≤ 200 mV, refer to Figure 23

SET

within 1% of final value,

APC

within 1% of final value,

APC

Time from VPOS/ENBL high to V V

≤ 200 mV, refer to Figure 28

SET

Time from VPOS/ENBL low to V

≤ 200 mV, refer to Figure 28

SET

within 1% of final value,

APC

within 1% of final value,

APC

4 5 μs

8 9 μs

2 3 μs

100 200 ns

Rev. C | Page 3 of 24

AD8315

Parameter Conditions Min Typ Max Unit

POWER INTERFACE Pin VPOS

Supply Voltage 2.7 5.5 V Quiescent Current ENBL high 8.5 10.7 mA

Over Temperature −30°C ≤ TA ≤ +85°C 12.9 mA

Disable Current

Over Temperature −30°C ≤ TA ≤ +85°C 13 μA

Operation down to 0.02 GHz is possible.

Mean and standard deviation specifications are available in Table 2

See Figure 11 for plot of input impedance vs. frequency.

This parameter is guaranteed but not tested in production. Limit is −3 sigma from the mean.

Response time in a closed-loop system depends on the filter capacitor (C

This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the 6 sigma value.

Table 2. Typical Specifications at Selected Frequencies at 25°C (Mean and Sigma)

Frequency (GHz) Mean Sigma Mean Sigma Mean Sigma Mean Sigma

0.1 23.8 0.3 −70.1 1.8 −57.7 1.3 −10.6 0.8

0.9 23.2 0.4 −72.6 1.8 −61.0 1.3 −11.2 0.8

1.9 22.2 0.3 −73.8 1.6 −62.9 0.9 −18.5 1.7

2.5 22.3 0.4 −75.6 1.5 −64.0 1.1 −20.0 1.7

ENBL low 4 10 μA

) used and the response of the variable gain element.

FLT

±1 dB Dynamic Range

Slope (mV/dB) Intercept (dBV)

Low Point (dBV) High Point (dBV)

Rev. C | Page 4 of 24

AD8315

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage VPOS 5.5 V Temporary Overvoltage VPOS

(100 cycles, 2 sec duration, ENBL Low) 6.3 V

VAPC, VSET, ENBL 0 V, V RFIN 17 dBm

Equivalent Voltage 1.6 V rms

Internal Power Dissipation 60 mW θJA (MSOP) 200°C/W θJA (LFCSP, Paddle Soldered) 80°C/W θJA (LFCSP, Paddle Not Soldered) 200°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec)

MSOP 300°C LFCSP 240°C

POS

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 5 of 24

AD8315

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RFIN

ENBL

VSET

(Not to Scale)

FLTR

NC = NO CONNECT

AD8315

TOP VIEW

VPOS

VAP C

COMM

01520-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 RFIN RF Input. 2 ENBL Connect to VPOS for Normal Operation Connect Pin to Ground for Disable Mode. 3 VSET Setpoint Input. Nominal input range 0.25 V to 1.4 V. 4 FLTR Integrator Capacitor. Connect between FLTR and COMM. 5 COMM Device Common (Ground). 6 NC No Connection. 7 VAPC Output. Control voltage for gain control element. 8 VPOS Positive Supply Voltage: 2.7 V to 5.5 V.

Rev. C | Page 6 of 24

AD8315

R R

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–20

–30

0.1GHz

–40

0.9GHz

–50

RF INPUT AMPLITUDE (dBV)

–60

–70

–80

0.2

1.9GHz

0.4 0.6 0.8 1.0 1.2 1.4 V

SET

2.5GHz

(V)

Figure 3. Input Amplitude vs. V

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLITUDE (d BV)

–50

–60

–70

0.1

+85°C

+25°C

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–30°C

ERROR AT +85°C AND –30°C BASED ON DEVIATIO N FROM SLOPE AND INTE RCEPT AT +25°C

(V)

SET

Figure 4. Input Amplitude and Log Conformance vs. V

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLIT UDE (dBV)

–50

–60

–70

0.1

0.3 0. 5 0.7 0.9 1.1 1.3 1.5

–30°C

+85°C

+25°C

ERROR AT +85°C AND –30° C BASED ON DEVIAT ION FRO M SLOPE AND I NTERCEPT AT +25°C

(V)

SET

+25°C

–30°C

+25°C

–30°C

+85°C

at 0.1 GHz

SET

+85°C

–7

–17

–27

–37

–47

–57

–67

–1

–2

–3

–4

RF INPU T AMPL ITUDE (dBm)

1520-003

ERROR (dB)

–1

–2

–3

–4

01520-004

ERROR (dB)

01520-005

0.1GHz

1.9GHz

OR (dB)

–1

–2

–3

–4

0.2

(V)

SET

Figure 6. Log Conformance vs. V

(+3dBm)

RF INPUT

(–47dBm)

–10

–20

–30

–40

AMPLITUDE ( dBV)

–50

+25°C

–60

+85°C

–70

0.1

0.30.50.70.91.11.31.5

+85°C

–30°C

+25°C

ERROR AT +85°C AND –30° C BASED ON DEVIATI ON FROM SLOPE AND INTERCEPT AT +25°C

–30°C

(V)

SET

Figure 7. Input Amplitude and Log Conformance vs. V

(+3dBm)

–10

–30°C

+85°C

ERROR AT +85°C AND –30°C BASED ON DEVIATION F ROM SLOPE AND INTERCEPT AT +25°C

(V)

SET

RF INPUT

(–47dBm)

–20

–30

–40

AMPLITUDE (dBV)

–50

–60

–70

+25°C

–30°C

+85°C

0.1

0.3 0.5 0.7 0.9 1.1 1.3 1.5

2.5GHz

SET

0.9GHz

at 1.9 GHz

SET

1.60.4 0.6 0.8 1.0 1.2 1.4

01520-006

–1

–2

–3

–4

ERROR (dB)

–1

–2

–3

–4

ERROR (dB)

01520-007

01520-008

Figure 5. Input Amplitude and Log Conformance vs. V

at 0.9 GHz

SET

Figure 8. Input Amplitude and Log Conformance vs. V

at 2.5 GHz

SET

Rev. C | Page 7 of 24

AD8315

(

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

+85°C

ERROR AT +85°C AND –30° C BASED ON DEVIATION FROM SLOPE AND INT ERCEPT AT +25°C

–60

RF INPUT AMPL ITUDE (dBV)

Figure 9. Distribution of Error at Temperature After Ambient Normalization vs.

–30°C

0–70

(+3dBm)(–47dBm)

01520-009

Figure 12. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz

ERROR (dB)

–1

–2

ERROR AT +85°C AND –30°C

–3

BASED ON DEVIAT ION FROM SLOPE AND INTERCEPT AT +25°C

–4

–80 –50 –40 –30 –20 –10

–70

RF INPUT AMPL ITUDE (dBV)

Figure 10. Distribution of Error at Temperature After Ambient Normalization vs.

+85°C

–30°C

0–60

(+3dBm)(–47dBm)

01520-010

Figure 13. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz

3000

2700

2400

2100

1800

X (LFCSP)

1500

1200

RESISTANCE (Ω)

900

600

300

FREQUENCY (GHz )

0.1

0.9

1.9

2.5

X (MSOP)

R (LFCSP)

R (MSOP)

0.5 1.0 1.5 2. 0 FREQUENCY (GHz)

MSOP

R –

2900 –

700 – 130 – 170 –

jXΩ j1900 j240 j80 j70

CHIP SCAL E (L FCSP)

R –

2700 –

730 – 460 – 440 –

–200

–400

jXΩ

–600

j1500 j220

–800

j130 j110

–1000

–1200

REACTANCE (Ω)

–1400

–1600

–1800

–2000

1520-011

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz

ERROR (dB)

–1

–2

–3

–4

–80 –50 –40 –30 –20 –10

Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz

SUPPLY CURRENT

1.3

Figure 11. Input Impedance

–30°C

ERROR AT +85°C AND –30°C BASED ON DEVIAT ION FROM SLOPE AND I NTERCEPT AT +25°C

–70

ERROR AT +85°C AND –30°C BASED ON DEVIAT ION FROM SLOPE AND INTERCEPT AT +25°C

–70

RF INPUT AMPLITUDE (d BV)

–30°C

RF INPUT AMPLITUDE (d BV)

DECREASING

ENBL

1.4 1.5 1.6 1.7

ENBL

(V)

Figure 14. Supply Current vs. V

+85°C

INCREASING V

ENBL

0–60

(+3dBm)(–47dBm)

01520-012

0–60

01520-013

01520-014

Rev. C | Page 8 of 24

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