ANALOG DEVICES AD8314 Service Manual

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100 MHz to 2.7 GHz, 45 dB

FEATURES

Complete RF detector/controller function
Typical range:−58 dBV to −13 dBV

−45 dBm to 0 dBm, re 50 Ω
Frequency response from 100 MHz to 2.7 GHz
Temperature-stable linear-in-dB response

Accurate to 2.7 GHz
Rapid response: 70 ns to a 10 dB step
Low power: 12 mW at 2.7 V
Power down to 20 μA

APPLICATIONS

Cellular handsets (TDMA, CDMA , GSM)
RSSI and TSSI for wireless terminal devices
Transmitter power measurement and control

GENERAL DESCRIPTION

The AD8314 is a complete low cost subsystem for the
measurement and control of RF signals in the frequency range
of 100 MHz to 2.7 GHz, with a typical dynamic range of 45 dB,
intended for use in a wide variety of cellular handsets and other
wireless devices. It provides a wider dynamic range and better
accuracy than possible using discrete diode detectors. In
particular, its temperature stability is excellent over the full
operating range of −40°C to +85°C.

Its high sensitivity allows control at low power levels, thus
reducing the amount of power that needs to be coupled to the
detector. It is essentially a voltage-responding device, with a
typical signal range of 1.25 mV to 224 mV rms or –58 dBV to

−13 dBV. This is equivalent to −45 dBm to 0 dBm, re 50 Ω.

FUNCTIONAL BLOCK DIAGRAM

RF Detector/Controller

AD8314

For convenience, the signal is internally ac-coupled, using a
5 pF capacitor to a load of 3 kΩ in shunt with 2 pF. This high­pass coupling, with a corner at approximately 16 MHz,
determines the lowest operating frequency. Therefore, the
source can be dc grounded.

The AD8314 provides two voltage outputs. The first, V_UP,
increases from close to ground to about 1.2 V as the input signal
level increases from 1.25 mV to 224 mV. This output is intended
for use in measurement mode. Consult the
for information on this mode. A capacitor can be connected
between the V_UP and FLTR pins when it is desirable to
increase the time interval over which averaging of the input
waveform occurs.

The second output, V_DN, is an inversion of V_UP but with
twice the slope and offset by a fixed amount. This output starts
at about 2.25 V (provided the supply voltage is ≥3.3 V) for the
minimum input and falls to a value close to ground at the
maximum input. This output is intended for analog control
loop applications. A setpoint voltage is applied to VSET, and
V_DN is then used to control a VGA or power amplifier. Here
again, an external filter capacitor can be added to extend the
averaging time. Consult the

Applications section for

information on this mode.

The AD8314 is available in 8-lead MSOP and 8-lead LFCSP
packages and consumes 4.5 mA from a 2.7 V to 5.5 V supply.
When powered down, the typical sleep current is 20 µA.

Applications section

FLTR

+

10dB

DETDET

BAND GAP

REFERENCE

DETDETDET

RFIN

OFFSET

COMPENSATION

COMM

PADDLE)

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

10dB10dB 10dB

AD8314

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

V-I

–

I-V

–

X2

+

VPOS

ENBL

VSET

V_UP

V_DN

01086-001

AD8314

TABLE OF CONTENTS

Features .............................................................................................. 1

dBV vs. dBm ............................................................................... 13

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions............................ 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 10

Inverted Output .......................................................................... 11

Applications..................................................................................... 12

Basic Connections...................................................................... 12

Transfer Function in Terms of Slope and Intercept ............... 12

Filter Capacitor ........................................................................... 13

Operating in Controller Mode ................................................. 13

Power-On and Enable Glitch.................................................... 14

Input Coupling Options ............................................................ 14

Increasing the Logarithmic Slope in Measurement Mode ... 15

Effect of Waveform Type on Intercept .................................... 15

Mobile Handset Power Control Examples.............................. 16

Operation at 2.7 GHz................................................................. 18

Using the LFCSP Package.......................................................... 18

Evaluation Board ........................................................................ 18

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

5/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to General Description .................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Inserted Figure 3; Renumbered Sequentially................................ 5

Changes to Figure 4, Figure 5, Figure 6, Figure 7,

and Figure 8 ...................................................................................... 6

Changes to Figure 9, Figure 10, and Figure 12 ............................. 7

Changes to Figure 37...................................................................... 14

Changes to Table 5.......................................................................... 15

Changes to Figure 39...................................................................... 16

Changes to Table 7.......................................................................... 19

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 20

3/02—Rev. 0 to Rev. A

Edit to Product Description.............................................................1

Edit to Specifications.........................................................................2

Edit to Ordering Guide ....................................................................3

Edit to TPC 1......................................................................................4

New Section (Operation at 2.7 GHz) Added.............................. 14

Addition of New Figures 14 and 15 ............................................. 14

Changes to Evaluation Board Section.......................................... 14

Addition of Chip Scale Package.................................................... 16

Rev. B | Page 2 of 20

AD8314

SPECIFICATIONS

VS = 3 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION

Frequency Range
Input Voltage Range Internally ac-coupled 1.25 224 mV rms

Equivalent Power Range 52.3 Ω external termination −45 0 dBm
Logarithmic Slope Main output, V_UP, 100 MHz2 18.85 21.3 23.35 mV/dB
Logarithmic Intercept Main output, V_UP, 100 MHz −68 −62 −56 dBV

Equivalent dBm Level 52.3 Ω external termination −55 −49 −43 dBm

INPUT INTERFACE Pin RFIN

DC Resistance to COMM 100 kΩ
Inband Input Resistance f = 0.1 GHz 3 kΩ
Input Capacitance f = 0.1 GHz 2 pF

MAIN OUTPUT Pin V_UP

Voltage Range V_UP connected to VSET 0.01 1.2 V
Minimum Output Voltage No signal at RFIN, RL ≥ 10 kΩ 0.01 0.02 0.05 V
Maximum Output Voltage3 RL ≥ 10 kΩ 1.9 2 V

General Limit 2.7 V ≤ VS ≤ 5.5 V VS − 1.1 VS − 1 V
Available Output Current Sourcing/sinking 1/0.5 2/1 mA
Response Time 10% to 90%, 10 dB step 70 ns
Residual RF (at 2f) f = 0.1 GHz (worst condition) 100 μV

INVERTED OUTPUT Pin V_DN

Gain Referred to V_UP VDN = 2.25 V − 2 × VUP −2
Minimum Output Voltage VS ≥ 3.3 V 0.01 0.05 0.1 V
Maximum Output Voltage VS ≥ 3.3 V4 2.1 2.2 2.5 V
Available Output Current Sourcing/sinking 4/100 6/200 mA/μA
Output-Referred Noise RF input = 2 GHz, –33 dBV, f
Response Time 10% to 90%, 10 dB input step 70 ns
Full-Scale Settling Time −40 dBm to 0 dBm input step to 95% 150 ns

SETPOINT INPUT Pin VSET

Voltage Range Corresponding to central 40 dB 0.15 1.2 V
Input Resistance 7 10 kΩ
Logarithmic Scale Factor f = 0.900 GHz 20.7 mV/dB

f = 1.900 GHz 19.7 mV/dB
ENABLE INTERFACE Pin ENBL

Logic Level to Enable Power HI condition, −40°C ≤ TA ≤ +85°C 1.6 V

Input Current when HI 2.7 V at ENBL, −40°C ≤ TA ≤ +85°C 20 300 μA
Logic Level to Disable Power LO condition, −40°C ≤ TA ≤ +85°C −0.5 +0.8 V

POWER INTERFACE Pin VPOS

Supply Voltage 2.7 3.0 5.5 V
Quiescent Current 3.0 4.5 5.7 mA

Overtemperature −40°C ≤ TA ≤ +85°C 2.7 4.4 6.6 mA
Total Supply Current when Disabled 20 95 μA

Overtemperature −40°C ≤ TA ≤ +85°C 40 μA

1

For a discussion on operation at higher frequencies, see Applications section.

2

Mean and standard deviation specifications are available in Table 4.

3

Increased output possible when using an attenuator between V_UP and VSET to raise the slope.

4

Refer to Figure 22 for details.

1

To meet all specifications 0.1 2.5 GHz

= 10 kHz 1.05 μV/√Hz

NOISE

V

POS

Rev. B | Page 3 of 20

AD8314

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Value

Supply Voltage VPOS 5.5 V
V_UP, V_DN, VSET, ENBL 0 V, VPOS
Input Voltage 1.6 V rms
Equivalent Power 17 dBm
Internal Power Dissipation 200 mW
θJA (MSOP) 200°C/W
θJA (LFCSP, Paddle Soldered) 80°C/W
θJA (LFCSP, Paddle Not Soldered) 200°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec)

8-Lead MSOP 300°C
8-Lead LFCSP 240°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 4 of 20

AD8314

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RFIN

ENBL

VSET

FLTR

1

AD8314

2

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

VPOS

V_DN

V_UP

COMM

01086-002

Figure 2. RM-8 Pin Configuration

1RFIN

2ENBL

AD8314

TOP VIEW

3VSET

(Not to Scale)

4FLTR

Figure 3. CP-8-1 Pin Configuration

8VPOS

7V_DN

5V_UP

5COMM

01086-003

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 RFIN RF Input.
2 ENBL Connect Pin to VS for Normal Operation. Connect pin to ground for disable mode.
3 VSET Setpoint Input for Operation in Controller Mode. To operate in detector mode connect VSET to V_UP.
4 FLTR

Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between

FLTR and V_UP.
5 COMM Device Common (Ground)
6 V_UP Logarithmic Output. Output voltage increases with increasing input amplitude.
7 V_DN Inversion of V_UP, Governed by: V_DN = 2.25 V − 2 × VUP.
8 VPOS Positive Supply Voltage (VS), 2.7 V to 5.5 V.

Rev. B | Page 5 of 20

AD8314

TYPICAL PERFORMANCE CHARACTERISTICS

1.2

1.0

0.8

(V)

0.6

UP

V

0.4

0.2

0.1GHz

0.9GHz

1.9GHz

2.5GHz

4

3

2

1

0

ERROR (dB)

–1

–2

–3

1.9GHz

2.5GHz

0.1GHz

0.9GHz

0

–75 –5

–65 –55 –45 –35 – 25 –15

INPUT AMPLI TUDE (dBV)(–52dBm) (–2dBm)

Figure 4. V

vs. Input Amplitude

UP

1.2

1.0

+25°C

0.8

–40°C

(V)

0.6

UP

V

0.4

0.2

0

–70 0

–60 – 50 –40 –30 –20 –10

Figure 5. V

UP

+85°C

+25°C

SLOPE AND INTERCEPT
NORMALIZE D AT +25°C AND

APPLIED T O –40°C AND +85°C

INPUT AMPLI TUDE (dBV)(–47dBm) (+3dBm)

and Log Conformance vs. Input Amplitude at 0.1 GHz;

−40°C, +25°C, and +85°C

1.2

1.0

0.8

(V)

0.6

UP

–40°C

V

0.4

+25°C

+85°C

–40°C

–4

01086-004

–60 –50 –40 –30 –20 –10

–70 0

INPUT AMPLITUDE (dBV)(–47dBm) (+ 3dBm)

01086-007

Figure 7. Log Conformance vs. Input Amplitude

3

2

1

0

ERROR (dB)

–1

–2

–3

01086-005

1.2

1.0

0.8

(V)

0.6

UP

V

0.4

0.2

0

–70 0

Figure 8. V

+85°C

+25°C

–40°C

SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED T O –40°C AND +85° C

–60 –50 –40 –30 – 20 –10

INPUT AMPLI TUDE (dBV)(–47dBm) (+3dBm)

and Log Conformance vs. Input Amplitude at 1.9 GHz;

UP

3

2

1

0

ERROR (dB)

–1

–2

–3

01086-008

−40°C, +25°C, and +85°C

3

2

1

0

ERROR (dB)

–1

1.2

1.0

0.8

(V)

0.6

UP

V

0.4

+85°C

+25°C

–40°C

+85°C

3

2

1

0

ERROR (dB)

–1

0.2

0

–70 0

–60 – 50 –40 –30 –20 –10

Figure 6. V

UP

SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLI ED TO –40°C AND +85° C

INPUT AMPLI TUDE (dBV)(–47dBm) (+3dBm)

and Log Conformance vs. Input Amplitude at 0.9 GHz;

−40°C, +25°C, and +85°C

–2

–3

01086-006

Rev. B | Page 6 of 20

0.2

0

–70 0

Figure 9. V

SLOPE AND INT ERCEPT
NORMALIZED AT +25°C AND
APPLIED T O –40°C AND +85° C

–60 – 50 –40 –30 –20 –10

INPUT AMPLI TUDE (dBV)(–47dBm) (+3dBm)

and Log Conformance vs. Input Amplitude at 2.5 GHz;

UP

−40°C, +25°C, and +85°C

–2

–3

01086-009