ANALOG DEVICES AD8307 Service Manual
Low Cost, DC to 500 MHz, 92 dB
www.BDTIC.com/ADI
FEATURES
Complete multistage logarithmic amplifier
92 dB dynamic range: –75 dBm to +17 dBm
to –90 dBm using matching network
Single supply of 2.7 V minimum at 7.5 mA typical
DC to 500 MHz operation, ±1 dB linearity
Slope of 25 mV/dB, intercept of −84 dBm
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 150 A sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers (to 120 dB)
Signal level determination down to 20 Hz
True decibel ac mode for multimeters
Logarithmic Amplifier
AD8307
FUNCTIONAL BLOCK DIAGRAM
AD8307
7
+INP
INP
8
1.1kΩ
INM
1
–INP
2
COM
BAND GAP REFERENCE
7.5mA
3
NINE DETECTO R CELLS
AND BIASING
SIX 14.3dB 900MHz
AMPLIFI ER STAGES
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
Figure 1.
MIRROR
2µA
/dB
2
COM
12.5kΩ
6
ENBVPS
5
INT
OUT
4
3
OFS
1082-001
GENERAL DESCRIPTION
The AD8307 is the first logarithmic amplifier made available in
an 8-lead (SOIC_N) package. It is a complete 500 MHz monolithic
demodulating logarithmic amplifier based on the progressive
compression (successive detection) technique, providing a
dynamic range of 92 dB to ±3 dB law-conformance and 88 dB
to a tight ±1 dB error bound at all frequencies up to 100 MHz.
It is extremely stable and easy to use, requiring no significant
external components. A single-supply voltage of 2.7 V to 5.5 V
at 7.5 mA is needed, corresponding to an unprecedented power
consumption of only 22.5 mW at 3 V. A fast acting CMOScompatible control pin can disable the AD8307 to a standby
current of less than 150 A.
Each of the cascaded amplifier/limiter cells has a small signal
gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz. The input
is fully differential and at a moderately high impedance (1.1 k
in parallel with about 1.4 pF). The AD8307 provides a basic
dynamic range extending from approximately −75 dBm (where
dBm refers to a 50 source, that is, a sine amplitude of about
±56 V) up to +17 dBm (a sine amplitude of ±2.2 V). A simple
input matching network can lower this range to –88 dBm to
+3 dBm. The logarithmic linearity is typically within ±0.3 dB up
to 100 MHz over the central portion of this range, and degrades
only slightly at 500 MHz. There is no minimum frequency limit.
The AD8307 can be used at audio frequencies of 20 Hz or lower.
The output is a voltage scaled 25 mV/dB, generated by a current
of nominally 2 µA/dB through an internal 12.5 kΩ resistor. This
voltage varies from 0.25 V at an input of −74 dBm (that is, the
ac intercept is at −84 dBm, a 20 µV rms sine input), up to 2.5 V
for an input of +16 dBm. This slope and intercept can be trimmed
using external adjustments. Using a 2.7 V supply, the output
scaling can be lowered, for example to 15 mV/dB, to permit
utilization of the full dynamic range.
The AD8307 exhibits excellent supply insensitivity and temperature
stability of the scaling parameters. The unique combination of
low cost, small size, low power consumption, high accuracy and
stability, very high dynamic range, and a frequency range
encompassing audio through IF to UHF makes this product
useful in numerous applications requiring the reduction of a
signal to its decibel equivalent.
The AD8307 operates over the industrial temperature range of
−40°C to +85°C, and is available in 8-lead SOIC and 8-lead
PDIP packages.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1997–2008 Analog Devices, Inc. All rights reserved.
AD8307
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Log Amp Theory .............................................................................. 9
Progressive Compression .......................................................... 10
Demodulating Log Amps .......................................................... 11
Intercept Calibration .................................................................. 12
Offset Control ............................................................................. 12
Extension of Range ..................................................................... 13
Interfaces .......................................................................................... 14
Enable Interface .......................................................................... 14
Input Interface ............................................................................ 14
Offset Interface ........................................................................... 15
Output Interface ......................................................................... 15
Theory of Operation ...................................................................... 17
Basic Connections ...................................................................... 17
Input Matching ........................................................................... 18
Narrow-Band Matching ............................................................ 18
Slope and Intercept Adjustments ............................................. 19
Applications Information .............................................................. 20
Buffered Output .......................................................................... 20
Four-Pole Filter ........................................................................... 20
1 µW to 1 kW 50 Power Meter ............................................. 21
Measurement System with 120 dB Dynamic Range .............. 21
Operation at Low Frequencies .................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/08—Rev. C to Rev. D
Deleted DC-Coupled Applications Section ................................ 22
Deleted Operation Above 500 MHz Section .............................. 23
Updated Outline Dimensions ....................................................... 23
10/06—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Offset Interface ........................................................... 15
Changes to Output Interface ......................................................... 15
Updated captions to Outline Dimensions ................................... 24
Changes to Ordering Guide .......................................................... 24
6/03—Rev. A to Rev. B
Renumbered TPCs and Figures ........................................ Universal
Changes to Ordering Guide ............................................................ 3
Changes to Figure 24 ...................................................................... 17
Deleted Evaluation Board Information ....................................... 18
Updated Outline Dimensions ....................................................... 19
Rev. D | Page 2 of 24
AD8307
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SPECIFICATIONS
VS = 5 V, TA = 25°C, RL ≥ 1 M, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
GENERAL CHARACTERISTICS
Input Range (±3 dB Error) From noise floor to maximum input 92 dB
Input Range (±1 dB Error) From noise floor to maximum input 88 dB
Logarithmic Conformance f ≤ 100 MHz, central 80 dB ±0.3 ±1 dB
f = 500 MHz, central 75 dB ±0.5 dB
Logarithmic Slope Unadjusted1 23 25 27 mV/dB
vs. Temperature 23 27 mV/dB
Logarithmic Intercept Sine amplitude, unadjusted2 20 μV
Equivalent sine power in 50 Ω −87 −84 −77 dBm
vs. Temperature −88 −76 dBm
Input Noise Spectral Density Inputs shorted 1.5 nV/√Hz
Operating Noise Floor R
Output Resistance Pin 4 to ground 10 12.5 15 kΩ
Internal Load Capacitance 3.5 pF
Response Time Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF 400 ns
Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF 500 ns
Upper Usable Frequency 500 MHz
Lower Usable Frequency AC-coupled input 10 Hz
AMPLIFIER CELL CHARACTERISTICS
Cell Bandwidth −3 dB 900 MHz
Cell Gain 14.3 dB
INPUT CHARACTERISTICS
DC Common-Mode Voltage AC-coupled input 3.2 V
Common-Mode Range Either input (small signal) −0.3 +1.6 VS − 1 V
DC Input Offset Voltage3 R
Drift 0.8 μV/°C
Incremental Input Resistance Differential 1.1 kΩ
Input Capacitance Either pin to ground 1.4 pF
Bias Current Either input 10 25 μA
POWER INTERFACES
Supply Voltage 2.7 5.5 V
Supply Current V
Disabled V
1
This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB.
2
This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.
3
Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the
Applications Information section.
= 50 Ω/2 −78 dBm
SOURCE
≤ 50 Ω 50 500 μV
SOURCE
≥ 2 V 8 10 mA
ENB
≤ 1 V 150 750 μA
ENB
Rev. D | Page 3 of 24
AD8307
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Ratings
Supply 7.5 V
Input Voltage (Pin 1 and Pin 8) V
Storage Temperature Range (N, R) −65°C to +125°C
Ambient Temperature Range, Rated
Performance Industrial, AD8307AN,
AD8307AR
Lead Temperature Range
(Soldering, 10 sec)
SUPPLY
−40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
can cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect
device reliability.
ESD CAUTION
Rev. D | Page 4 of 24
AD8307
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INM
1
COM
2
AD8307
3
OFS
OUT
TOP VIEW
(Not to Scale)
4
Figure 2. Pin Configuration
INP
8
VPS
7
ENB
6
INT
5
01082-002
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 INM Signal Input Minus Polarity. Normally at V
POS
/2.
2 COM Common Pin (Usually Grounded).
3 OFS Offset Adjustment. External capacitor connection.
4 OUT Logarithmic (RSSI) Output Voltage. R
= 12.5 kΩ.
OUT
5 INT Intercept Adjustment, ±3 dB. (See the Slope and Intercept Adjustments section.)
6 ENB CMOS-Compatible Chip Enable. Active when high.
7 VPS Positive Supply: 2.7 V to 5.5 V.
8 INP
Signal Input Plus Polarity. Normally at V
/2. Due to the symmetrical nature of the response, there is no special
POS
significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ.
Rev. D | Page 5 of 24
AD8307
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TYPICAL PERFORMANCE CHARACTERISTICS
8
3
7
6
5
4
3
SUPPLY CURRENT (mA)
2
1
0
1.0
1.1
1.2
1.3
1.4
1.5
V
(V)
ENB
Figure 3. Supply Current vs. V
8
7
6
5
4
3
SUPPLY CURRENT (mA)
2
1
0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
V
(V)
ENB
Figure 4. Supply Current vs. V
1.6
ENB
ENB
1.7
(5 V)
(3 V)
1.8
1.9
1.8 1.9 2.0
2.0
2
1
TEMPERATURE E RROR @ +85°C
0
ERROR (dB)
–1
TEMPERATURE ERROR @ –40°C
–2
01082-003
–3
TEMPERATURE E RROR @ +25°C
INPUT LEVEL (dBm)
01082-006
200–20–40–60–80
Figure 6. Log Conformance vs. Input Level (dBm) at −40°C, +25°C, and +85°C
3
2
INPUT FREQUENCY 100MHz
(V)
OUT
V
1
01082-004
0
Figure 7. V
vs. Input Level (dBm) at Various Frequencies
OUT
INPUT FREQUENCY 10MHz
INPUT FREQUENCY 300MHz
INPUT FREQUENCY 500MHz
INPUT LEVEL (dBm)
01082-007
200–20–40–60–80
3
2
1
0
ERROR (dB)
–1
–2
–3
INPUT FREQUENCY = 300MHz
INPUT FREQUENCY = 100MHz
INPUT LEVEL (dBm)
01082-005
200–20–40–60–80
Figure 5. Log Conformance vs. Input Level (dBm), 100 MHz and 300 MHz
1.5
1.0
0.5
0
ERROR (dB)
–0.5
–1.0
–1.5
CFO VALUE = 0.01µF
CFO VALUE = 1µF
CFO VALUE = 0.1µF
INPUT LEVEL (dBm)
Figure 8. Log Conformance vs. CFO Values at 1 kHz Input Frequency
Rev. D | Page 6 of 24
01082-008
200–20–40–60–80
AD8307
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3.0
2.5
10MHz, INT = –96.52dBm
INT PIN = 3.0V
3
100MHz
2
2.0
(V)
1.5
OUT
V
1.0
0.5
Figure 9. V
3.0
2.5
2.0
(V)
1.5
OUT
V
1.0
0.5
INT P
= 4.0V
IN
10MHz, INT = –87.71dBm
NO CONNECT ON I NT
10MHz, INT = –82.90dBm
0
INPUT LEVEL (dBm)
vs. Input Level at 5 V Supply; Showing Intercept Adjustment
OUT
INT = 1.0V , INT = –86dBm
INT NO CONNECT, INT = –71dBm
0
INT VOLTAGE
INT VOLTAGE
INT VOLTAGE
INT = 2.0V , INT = –78dBm
INPUT LEVEL (dBm)
0–20 –10 10–40–60–80 –70 –50 –30
1
+INPUT
0
ERROR (d B)
–1
–2
01082-009
200–20 –10 10–40–60–80 –70 –50 –30
–3
–INPUT
INPUT LEVEL (dBm)
01082-012
200–20–40–60–80
Figure 12. Log Conformance vs. Input Level at 100 MHz Showing
Response to Alternative Inputs
3
2
1
0
ERROR (dB)
–1
100MHz
–2
01082-010
–3
500MHz
INPUT LEVEL (dBm)
01082-013
10–10–30–50–70–90
Figure 10. V
2.5
2.0
1.5
(V)
OUT
V
1.0
0.5
Figure 11. V
vs. Input Level at 3 V Supply Using AD820 as Buffer,
OUT
Gain = +2; Showing Intercept Adjustment
100MHz @ –40°C
100MHz @ +25°C
100MHz @ +85°C
0
INPUT LEVEL (dBm)
vs. Input Level at Three Temperatures (−40°C, +25°C, +85°C)
OUT
01082-011
200–20–40–60–80
Rev. D | Page 7 of 24
Figure 13. Log Conformance vs. Input Level at 100 MHz and 500 MHz;
Input Driven Differentially Using Transformer
3
2
1
0
100MHz
ERROR (dB)
–1
–2
–3
INPUT LEVEL (dBm)
500MHz
10MHz
100–10–20 20–30–40–50–60–70
Figure 14. Log Conformance vs. Input Level at 3 V Supply
Using AD820 as Buffer, Gain = +2
01082-014
AD8307
G
V
V
V
T
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CH1 200mV
V
OUT
CH 1
2
CH1 500mV
CH1
OU
ND
V
OUT
CH 1
V
ENB
CH 2
GND
CH2 2.00V
Figure 15. Power-Up Response Time
CH1 200mV
CH2 2.00V
Figure 16. Power-Down Response Time
500ns
500ns
V
ENB
CH 2
01082-015
CH1 GND
INPUT
SIGNAL
CH2
CH2 1.00V
Figure 18. V
CH1 500mV
2.5V
INPUT
SIGNAL
CH2
CH1 GND
1082-016
CH2 1.00V
Rise Time
OUT
200ns
200ns
CH2
GND
01082-018
CH2
GND
V
OUT
CH1
1082-019
Figure 19. Large Signal Response Time
HP8648B
SIGNAL
GENERATOR
RF OUT
1nF
INP VPS ENB INT
52.3Ω
INM COM OFS OUT
1nF
NC = NO CONNECT
PS = 5.0V
0.1µF
8765
NC
AD8307
234
1
NC
TEK P6139A
10x PROBE
HP8112A
PULSE
GENERATOR
OUT
SYNCH OUT
TEK744A
SCOPE
TRIG
Figure 17. Test Setup for Power-Up/Power-Down Response Time
HP8648B
SIGNAL
GENERATOR
PULSE
MODULATION
MODE
RF OUT
01082-017
10MHz REF CLK
PULSE MODE IN
VPS = 5.0V
1nF
52.3Ω
1nF
NC = NO CONNECT
0.1µF
8765
INP VPS ENB INT
AD8307
INM COM OFS OUT
234
1
NC
Figure 20. Test Setup for V
EXT TRIG
OUT
NC
TEK P6204
FET PROBE
Pulse Response
OUT
HP8112A
PULSE
GENERATOR
TEK744A
SCOPE
TRIG
OUT
TRIG
01082-020
Rev. D | Page 8 of 24
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