Analog Devices AD8305 a Datasheet

100 dB Range (10 nA to 1 mA)

Logarithmic Converter

FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Measures Current over 5 Decades

Law Conformance 0.1 dB from 10 nA to 1 mA
Single- or Dual-Supply Operation (3 V to 12 V Total)
Full Log-Ratio Capabilities
Nominal Slope of 10 mV/dB (200 mV/Decade)
Nominal Intercept of 1 nA (Set by External Resistor)

Optional Adjustment of Slope and Intercept
Complete and Temperature Stable
Rapid Response Time for a Given Current Level
Miniature 16-Lead Chip Scale Package

(LFCSP 3 mm ⴛ 3 mm)
Low Power: ~5 mA Quiescent Current

APPLICATIONS
Optical Power Measurement
Wide Range Baseband Logarithmic Compression
Measurement of Current and Voltage Ratios
Optical Absorbance Measurement

GENERAL DESCRIPTION

The AD8305 is an inexpensive microminiature logarithmic
converter optimized for determining optical power in fiber optic
systems. It uses an advanced implementation of a classic trans­linear (junction based) technique to provide a large dynamic
range in a versatile and easily used form. A single-supply voltage of
between 3 V and 12 V is adequate; dual supplies may optionally
be used. The low quiescent current (typically 5 mA) permits use
in battery-operated applications.

The input current, I

, of 10 nA to 1 mA applied to the INPT

PD

pin is the collector current of an optimally scaled NPN transis­tor, which converts this current to a voltage (V

) with a precise

BE

logarithmic relationship. A second such converter is used to
handle the reference current (I

) applied to pin IREF. These

REF

input nodes are biased slightly above ground (0.5 V). This is gen­erally acceptable for photodiode applications where the anode
does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating I

. The output of the loga-

REF

rithmic front end is available at Pin VLOG.

The basic logarithmic slope at this output is nominally 200 mV/
decade (10 mV/dB). Thus, a 100 dB range corresponds to an
output change of 1 V. When this voltage (or the buffer output)
is applied to an ADC that permits an external reference voltage
to be employed, the AD8305’s voltage reference output of 2.5 V
at Pin VREF can be used to improve the scaling accuracy. Suit­able ADCs include the AD7810 (serial 10-bit), AD7823 (serial

*Protected by U.S. Patent No. 4,604,532 and 5,519,308; other patents pending.

AD8305

*

FUNCTIONAL BLOCK DIAGRAM

SCAL

451⍀

COMM

10

BFIN

I

PD

( )

1nA

VOUT

VLOG

200k⍀

V

BIAS

VRDZ

VREF

IREF

I

PD

INPT

VSUM

0.5V

0.5V

20k⍀

COMM

Q2

Q1

VNEG

80k⍀

V

P

VPOS

GENERATOR

2.5V

V

BE2

TEMPERATURE

–
+

COMPENSATION

V

BE1

BIAS

14.2k⍀

6.69k⍀

COMM

0.20 log

I

LOG

8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of
the logarithmic slope can be provided using a simple external
resistor network.

The logarithmic intercept (also known as the reference current)
is nominally positioned at 1 nA by the use of the externally
generated current, I

, of 10 mA, provided by a 200 kW resistor

REF

connected between VREF, at 2.5 V, and the reference input
IREF, at 0.5 V. The intercept can be adjusted over a wide range
by varying this resistor. The AD8305 can also operate in a log­ratio mode, with the numerator current applied to INPT and
the denominator current applied to IREF.

A buffer amplifier is provided for driving a substantial load, for
use in raising the basic slope of 10 mV/dB to higher values, as a
precision comparator (threshold detector), or in implementing
low-pass filters. Its rail-to-rail output stage can swing to within
100 mV of the positive and negative supply rails, and its peak
current sourcing capacity is 25 mA.

It is a fundamental aspect of translinear logarithmic converters
that the small signal bandwidth falls as the current level dimin­ishes, and the low frequency noise-spectral density increases. At
the 10 nA level, the bandwidth of the AD8305 is about 50 kHz,
and increases in proportion to I

up to a maximum value of

PD

about 15 MHz. Using the buffer amplifier, the increase in noise
level at low currents can be addressed by using it to realize low­pass filters of up to three poles.

The AD8305 is available in a 16-lead LFCSP package and is
specified for operation from –40∞C to +85∞C.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8305–SPECIFICATIONS

(VP = 5 V, VN = 0 V, TA = 25C, R
otherwise noted.)

= 200 k, and VRDZ connected to VREF, unless

REF

Parameter Conditions Min Typ Max Unit

INPUT INTERFACE Pin 4, INPT, Pin 3, IREF

Specified Current Range, I

PD

Flows toward INPT Pin 10 n 1 m A
Input Current Min/Max Limits Flows toward INPT Pin 10 m A
Reference Current, I

, Range Flows toward IREF Pin 10 n 1 m A

REF

Summing Node Voltage Internally Preset; May be Altered by User 0.46 0.5 0.54 V
Temperature Drift –40∞C < T
Input Offset Voltage V

INPT

< +85∞C 0.015 mV/∞C

A

– V

SUM

, V

IREF

– V

SUM

–20 +20 mV

LOGARITHMIC OUTPUT Pin 9, VLOG

Logarithmic Slope 190 200 210 mV/dec

–40∞C < T
Logarithmic Intercept

1

–40∞C < T
Law Conformance Error 10 nA < I
Wideband Noise
Small Signal Bandwidth

2

2

IPD > 1 mA 0.7 mV÷Hz

IPD > 1 mA 0.7 MHz

< +85∞C 185 215 mV/dec

A

0.3 1 1.7 nA

< +85∞C 0.1 2.5 nA

A

< 1 mA 0.1 0.4 dB

PD

Maximum Output Voltage 1.7 V
Minimum Output Voltage Limited by V

= 0 V 0.01 V

N

Output Resistance 4.375 5 5.625 kW

REFERENCE OUTPUT Pin 2, VREF

Voltage wrt Ground 2.435 2.5 2.565 V

–40∞C < T

< +85∞C 2.4 2.6 V

A

Maximum Output Current Sourcing (Grounded Load) 20 mA
Incremental Output Resistance Load Current < 10 mA 2 W

OUTPUT BUFFER Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT

Input Offset Voltage –20 +20 mV
Input Bias Current Flowing out of Pin 10 or 11 0.4 mA
Incremental Input Resistance 35 MW
Output Range R

= 1 kW to ground VP – 0.1 V

L

Incremental Output Resistance Load Current < 10 mA 0.5 W
Peak Source/Sink Current 25 mA
Small Signal Bandwidth GAIN = 1 15 MHz
Slew Rate 0.2 V to 4.8 V Output Swing 15 V/ms

POWER SUPPLY Pin 8, VPOS; Pin 6 and Pin 7, VNEG

Positive Supply Voltage (V

– VN) £ 12 V 3 5 12 V

P

Quiescent Current 5.4 6.5 mA
Negative Supply Voltage (Optional)

NOTES

1

Other values of logarithmic intercept can be achieved by adjusting R

2

Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.

(VP – VN) £ 12 V –5.5 0 V

.

REF

REV. A–2–

AD8305

ABSOLUTE MAXIMUM RATINGS

1

ORDERING GUIDE

Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30∞C/W

␪

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C

Model Range Description Option

AD8305ACP –40∞C to +85∞C 16-Lead LFCSP CP-16
AD8305ACP-REEL7 7" Tape and Reel
AD8305-EVAL Evaluation Board

Temperature Package Package

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

With package die paddle soldered to thermal pad containing nine vias connected
to inner and bottom layers.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

16 COMM

15 COMM

14 COMM

13 COMM

VRDZ 1

VREF 2

IREF 3

INPT 4

PIN 1
INDICATOR

AD8305

TOP VIEW

VNEG 6

VSUM 5

VPOS 8

VNEG 7

12 VOUT

11 SCAL

10 BFIN

9 VLOG

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 VRDZ Top of a Resistive Divider Network that Offsets V

to Position the Intercept. Normally connected

LOG

to VREF; may also be connected to ground when bipolar outputs are to be provided.

2 VREF Reference Output Voltage of 2.5 V.

3IREF Accepts (Sinks) Reference Current, I

REF.

4INPT Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo

current flows into INPT.

5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and I

REF

node potential.

6, 7 VNEG

Optional Negative Supply, VN. (This pin is usually grounded; for details of usage, see the Applications section).

8 VPOS Positive Supply, (VP – VN ) £ 12 V.

9 VLOG Output of the Logarithmic Front End.

10 BFIN Buffer Amplifier Noninverting Input.

11 SCAL Buffer Amplifier Inverting Input.

12 VOUT Buffer Output.

13–16 COMM Analog Ground.

REV. A

–3–

AD8305–Typical Performance Characteristics

(VP = 5 V, VN = 0 V, R
otherwise noted.)

= 200 k, TA = 25C, unless

REF

1.6

TA = –40C, 0C, +25C, +70C, +85C

= 0V

V

1.4

N

1.2

1.0

– V

0.8

LOG

V

0.6

0.4

0.2

0

1n

TPC 1. V

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

1n

TPC 2. V

–40C

+25C

+85C

10n 100n 1 10 100 1m 10m

vs. I

LOG

10n 100n 1 10 100 1m 10m

LOG

–40C

vs. I

PD

+25C
+85C

REF

0C

+70C

IPD – A

for Multiple Temperatures

T

= –40C, 0C, +25C, +70C, +85C

A

VN = 0V

0C

+70C

I

– A

REF

for Multiple Temperatures

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

–2.0

–40C

1n

10n 100n 1 10 100 1m 10m

TPC 4. Law Conformance Error vs. IPD (at I

TA = –40C, 0C, +25C, +70C, +85C
V

= 0V

N

+85C

0C

+25C

I

PD

+70C

– A

REF

for Multiple Temperatures, Normalized to 25

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

–2.0

10n 100n 1 10 100 1m 10m

1n

TPC 5. Law Conformance Error vs. I

T

= –40C, 0C, +25C, +70C, +85C

A

VN = 0V

+70C

+25C

I

– A

REF

+85C

0C

–40C

(at IPD = 10 mA)

REF

for Multiple Temperatures, Normalized to 25

= 10 mA)

∞

C

∞

C

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

TPC 3. V

10nA

100nA

1A

10A

100A

1mA

1n

10n 100n 1 10 100 1m 10m

vs. IPD for Multiple Values of I

LOG

IPD – A

(Decade Steps from 10 nA to 1 mA)

REF

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

1n

100A 1mA

10A

1A

10nA

100nA

10n 100n 1 10 100 1m 10m

IPD – A

TPC 6. Law Conformance Error vs. IPD for Multiple
Values of I

(Decade Steps from 10 nA to 1 mA)

REF

REV. A–4–

AD8305

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

1n

TPC 7. V

1A

100nA

10nA

10n 100n 1 10 100 1m 10m

vs. I

LOG

I

– A

REF

for Multiple Values of I

REF

1mA

100A

10A

PD

(Decade Steps from 10 nA to 1 mA)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

1n

10n 100n 1 10 100 1m 10m

+3V, 0V

+5V, 0V

+9V, 0V

+3V, –0.5V

+5V, –5V

+12V, 0V

IPD – A

TPC 8. Law Conformance Error vs. IPD for Various
Supply Conditions (see Annotations)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

100A

1n

10n 100n 1 10 100 1m 10m

10A

1mA

I

REF

10nA

– A

TPC 10. Law Conformance Error vs. I

100nA

REF

1A

for Multiple

Values of IPD (Decade Steps from 10 nA to 1 mA)

1.4

1.2

1.0

0.8

– V

OUT

0.6

V

0.4

0.2

0

TPC 11. Pulse Response – IPD to V

100A TO 1mA: T-RISE = <1s,
T- F A LL = < 1s

10A TO 10A: T-RISE = <1s,
T- F A LL = < 1s

1A TO 10 A: T-RISE = 1s,
T- F A LL = 5s

100nA TO 1A: T- R I SE = 5s,
T- F A LL = 20s

10nA TO 100nA: T-RISE = 20s,
T- F A LL = 30s

TIME – s

OUT

160140120100806040200–20

(G = 1)

180

– mV

– V

V

REV. A

INPT

–0.1

SUM

–0.2

–0.3

–0.4

0.4

0.3

0.2

0.1

0

1n

10n 100n 1 10 100 1m 10m

TPC 9. V

INPT

IPD – A

– V

SUM

vs. I

PD

–5–

1.6

– V

V

OUT

1.4

1.2

1.0

0.8

0.6

0.4

0.2

10nA TO 100nA: T-RISE = 30s,
T- F A LL = 20s

100nA TO 1A: T- R I SE = 30s,
T- F A LL = 5s

1A TO 10A: T-RISE = 5s,
T- F A LL = < 1s

10A TO 100A: T-RISE = 1s,
T- F A LL = < 1s

100A TO 1mA: T-RISE = < 1s,
T- F A LL = < 1s

0

TIME – s

TPC 12. Pulse Response – I

REF

to V

OUT

160140120100806040200–20

(G = 1)

180

AD8305

OUT

V

–10

–20

–30

–40

–50

10

0

100

1k 10k 100k 1M 10M 100M

10nA

100nA

1mA

1A

FREQUENCY – Hz

10A

100A

TPC 13. Small Signal AC Response (5% Sine
Modulation), from I
Decade Steps from 10 nA to 1 mA, I

10

0

–10

–20

–30

NORMALIZED RESPONSE – dB

–40

–50

100

1k 10k 100k 1M 10M 100M

to V

PD

OUT

100nA

10nA

1mA

1A

FREQUENCY – Hz

(G = 1) for IPD in

= 10 mA

REF

10A

100A

TPC 14. Small Signal AC Response (5% Sine
Modulation), from I

REF

to V

(G = 1) for I

OUT

REF

in

Decade Steps from 10 nA to 1 mA, IPD = 10 mA

3

0

–3

–6

NORMALIZED RESPONSE – dB

–9

–12

10k 100k 1M 10M 100M

AV = 5

A

= 2.5

V

FREQUENCY – Hz

= 1

A

V

= 2

A

V

TPC 16. Small Signal AC Response of the Buffer for
Various Closed-Loop Gains (R

2.0

1.5

1.0

0.5

0

DRIFT – mV

–0.5

OS

V

–1.0

–1.5

–2.0

MEAN + 3

MEAN – 3

TEMPERATURE – C

= 1 kW CL < 2 pF)

L

90806040200–20 10–10 30 50 70–30–40

TPC 17. Buffer Input Offset Drift vs. Temperature

␴

to Either Side of Mean)

(3

100

10nA

10

100nA

1

Vrms/ Hz

0.1

0.01
100

1k 10k 100k 1M 10M

TPC 15. Spot Noise Spectral Density at V

1A

100A

FREQUENCY – Hz

10A

OUT

(G = 1) vs. Frequency for IPD in Decade Steps from
10 nA to 1 mA

6

5

4

3

mVrms

2

1

0

100n 1 10 100 1m 10m

10n

IPD – A

TPC 18. Total Wideband Noise Voltage
at V

vs. IPD (G = 1)

OUT

REV. A–6–