Analog Devices AD8305 a Datasheet

100 dB Range (10 nA to 1 mA)

Logarithmic Converter

FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Measures Current over 5 Decades

Law Conformance 0.1 dB from 10 nA to 1 mA
Single- or Dual-Supply Operation (3 V to 12 V Total)
Full Log-Ratio Capabilities
Nominal Slope of 10 mV/dB (200 mV/Decade)
Nominal Intercept of 1 nA (Set by External Resistor)

Optional Adjustment of Slope and Intercept
Complete and Temperature Stable
Rapid Response Time for a Given Current Level
Miniature 16-Lead Chip Scale Package

(LFCSP 3 mm ⴛ 3 mm)
Low Power: ~5 mA Quiescent Current

APPLICATIONS
Optical Power Measurement
Wide Range Baseband Logarithmic Compression
Measurement of Current and Voltage Ratios
Optical Absorbance Measurement

GENERAL DESCRIPTION

The AD8305 is an inexpensive microminiature logarithmic
converter optimized for determining optical power in fiber optic
systems. It uses an advanced implementation of a classic trans­linear (junction based) technique to provide a large dynamic
range in a versatile and easily used form. A single-supply voltage of
between 3 V and 12 V is adequate; dual supplies may optionally
be used. The low quiescent current (typically 5 mA) permits use
in battery-operated applications.

The input current, I

, of 10 nA to 1 mA applied to the INPT

PD

pin is the collector current of an optimally scaled NPN transis­tor, which converts this current to a voltage (V

) with a precise

BE

logarithmic relationship. A second such converter is used to
handle the reference current (I

) applied to pin IREF. These

REF

input nodes are biased slightly above ground (0.5 V). This is gen­erally acceptable for photodiode applications where the anode
does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating I

. The output of the loga-

REF

rithmic front end is available at Pin VLOG.

The basic logarithmic slope at this output is nominally 200 mV/
decade (10 mV/dB). Thus, a 100 dB range corresponds to an
output change of 1 V. When this voltage (or the buffer output)
is applied to an ADC that permits an external reference voltage
to be employed, the AD8305’s voltage reference output of 2.5 V
at Pin VREF can be used to improve the scaling accuracy. Suit­able ADCs include the AD7810 (serial 10-bit), AD7823 (serial

*Protected by U.S. Patent No. 4,604,532 and 5,519,308; other patents pending.

AD8305

*

FUNCTIONAL BLOCK DIAGRAM

SCAL

451⍀

COMM

10

BFIN

I

PD

( )

1nA

VOUT

VLOG

200k⍀

V

BIAS

VRDZ

VREF

IREF

I

PD

INPT

VSUM

0.5V

0.5V

20k⍀

COMM

Q2

Q1

VNEG

80k⍀

V

P

VPOS

GENERATOR

2.5V

V

BE2

TEMPERATURE

–
+

COMPENSATION

V

BE1

BIAS

14.2k⍀

6.69k⍀

COMM

0.20 log

I

LOG

8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of
the logarithmic slope can be provided using a simple external
resistor network.

The logarithmic intercept (also known as the reference current)
is nominally positioned at 1 nA by the use of the externally
generated current, I

, of 10 mA, provided by a 200 kW resistor

REF

connected between VREF, at 2.5 V, and the reference input
IREF, at 0.5 V. The intercept can be adjusted over a wide range
by varying this resistor. The AD8305 can also operate in a log­ratio mode, with the numerator current applied to INPT and
the denominator current applied to IREF.

A buffer amplifier is provided for driving a substantial load, for
use in raising the basic slope of 10 mV/dB to higher values, as a
precision comparator (threshold detector), or in implementing
low-pass filters. Its rail-to-rail output stage can swing to within
100 mV of the positive and negative supply rails, and its peak
current sourcing capacity is 25 mA.

It is a fundamental aspect of translinear logarithmic converters
that the small signal bandwidth falls as the current level dimin­ishes, and the low frequency noise-spectral density increases. At
the 10 nA level, the bandwidth of the AD8305 is about 50 kHz,
and increases in proportion to I

up to a maximum value of

PD

about 15 MHz. Using the buffer amplifier, the increase in noise
level at low currents can be addressed by using it to realize low­pass filters of up to three poles.

The AD8305 is available in a 16-lead LFCSP package and is
specified for operation from –40∞C to +85∞C.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8305–SPECIFICATIONS

(VP = 5 V, VN = 0 V, TA = 25C, R
otherwise noted.)

= 200 k, and VRDZ connected to VREF, unless

REF

Parameter Conditions Min Typ Max Unit

INPUT INTERFACE Pin 4, INPT, Pin 3, IREF

Specified Current Range, I

PD

Flows toward INPT Pin 10 n 1 m A
Input Current Min/Max Limits Flows toward INPT Pin 10 m A
Reference Current, I

, Range Flows toward IREF Pin 10 n 1 m A

REF

Summing Node Voltage Internally Preset; May be Altered by User 0.46 0.5 0.54 V
Temperature Drift –40∞C < T
Input Offset Voltage V

INPT

< +85∞C 0.015 mV/∞C

A

– V

SUM

, V

IREF

– V

SUM

–20 +20 mV

LOGARITHMIC OUTPUT Pin 9, VLOG

Logarithmic Slope 190 200 210 mV/dec

–40∞C < T
Logarithmic Intercept

1

–40∞C < T
Law Conformance Error 10 nA < I
Wideband Noise
Small Signal Bandwidth

2

2

IPD > 1 mA 0.7 mV÷Hz

IPD > 1 mA 0.7 MHz

< +85∞C 185 215 mV/dec

A

0.3 1 1.7 nA

< +85∞C 0.1 2.5 nA

A

< 1 mA 0.1 0.4 dB

PD

Maximum Output Voltage 1.7 V
Minimum Output Voltage Limited by V

= 0 V 0.01 V

N

Output Resistance 4.375 5 5.625 kW

REFERENCE OUTPUT Pin 2, VREF

Voltage wrt Ground 2.435 2.5 2.565 V

–40∞C < T

< +85∞C 2.4 2.6 V

A

Maximum Output Current Sourcing (Grounded Load) 20 mA
Incremental Output Resistance Load Current < 10 mA 2 W

OUTPUT BUFFER Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT

Input Offset Voltage –20 +20 mV
Input Bias Current Flowing out of Pin 10 or 11 0.4 mA
Incremental Input Resistance 35 MW
Output Range R

= 1 kW to ground VP – 0.1 V

L

Incremental Output Resistance Load Current < 10 mA 0.5 W
Peak Source/Sink Current 25 mA
Small Signal Bandwidth GAIN = 1 15 MHz
Slew Rate 0.2 V to 4.8 V Output Swing 15 V/ms

POWER SUPPLY Pin 8, VPOS; Pin 6 and Pin 7, VNEG

Positive Supply Voltage (V

– VN) £ 12 V 3 5 12 V

P

Quiescent Current 5.4 6.5 mA
Negative Supply Voltage (Optional)

NOTES

1

Other values of logarithmic intercept can be achieved by adjusting R

2

Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.

(VP – VN) £ 12 V –5.5 0 V

.

REF

REV. A–2–

AD8305

ABSOLUTE MAXIMUM RATINGS

1

ORDERING GUIDE

Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30∞C/W

␪

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C

Model Range Description Option

AD8305ACP –40∞C to +85∞C 16-Lead LFCSP CP-16
AD8305ACP-REEL7 7" Tape and Reel
AD8305-EVAL Evaluation Board

Temperature Package Package

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

With package die paddle soldered to thermal pad containing nine vias connected
to inner and bottom layers.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

16 COMM

15 COMM

14 COMM

13 COMM

VRDZ 1

VREF 2

IREF 3

INPT 4

PIN 1
INDICATOR

AD8305

TOP VIEW

VNEG 6

VSUM 5

VPOS 8

VNEG 7

12 VOUT

11 SCAL

10 BFIN

9 VLOG

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 VRDZ Top of a Resistive Divider Network that Offsets V

to Position the Intercept. Normally connected

LOG

to VREF; may also be connected to ground when bipolar outputs are to be provided.

2 VREF Reference Output Voltage of 2.5 V.

3IREF Accepts (Sinks) Reference Current, I

REF.

4INPT Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo

current flows into INPT.

5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and I

REF

node potential.

6, 7 VNEG

Optional Negative Supply, VN. (This pin is usually grounded; for details of usage, see the Applications section).

8 VPOS Positive Supply, (VP – VN ) £ 12 V.

9 VLOG Output of the Logarithmic Front End.

10 BFIN Buffer Amplifier Noninverting Input.

11 SCAL Buffer Amplifier Inverting Input.

12 VOUT Buffer Output.

13–16 COMM Analog Ground.

REV. A

–3–

AD8305–Typical Performance Characteristics

(VP = 5 V, VN = 0 V, R
otherwise noted.)

= 200 k, TA = 25C, unless

REF

1.6

TA = –40C, 0C, +25C, +70C, +85C

= 0V

V

1.4

N

1.2

1.0

– V

0.8

LOG

V

0.6

0.4

0.2

0

1n

TPC 1. V

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

1n

TPC 2. V

–40C

+25C

+85C

10n 100n 1 10 100 1m 10m

vs. I

LOG

10n 100n 1 10 100 1m 10m

LOG

–40C

vs. I

PD

+25C
+85C

REF

0C

+70C

IPD – A

for Multiple Temperatures

T

= –40C, 0C, +25C, +70C, +85C

A

VN = 0V

0C

+70C

I

– A

REF

for Multiple Temperatures

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

–2.0

–40C

1n

10n 100n 1 10 100 1m 10m

TPC 4. Law Conformance Error vs. IPD (at I

TA = –40C, 0C, +25C, +70C, +85C
V

= 0V

N

+85C

0C

+25C

I

PD

+70C

– A

REF

for Multiple Temperatures, Normalized to 25

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

–2.0

10n 100n 1 10 100 1m 10m

1n

TPC 5. Law Conformance Error vs. I

T

= –40C, 0C, +25C, +70C, +85C

A

VN = 0V

+70C

+25C

I

– A

REF

+85C

0C

–40C

(at IPD = 10 mA)

REF

for Multiple Temperatures, Normalized to 25

= 10 mA)

∞

C

∞

C

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

TPC 3. V

10nA

100nA

1A

10A

100A

1mA

1n

10n 100n 1 10 100 1m 10m

vs. IPD for Multiple Values of I

LOG

IPD – A

(Decade Steps from 10 nA to 1 mA)

REF

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

1n

100A 1mA

10A

1A

10nA

100nA

10n 100n 1 10 100 1m 10m

IPD – A

TPC 6. Law Conformance Error vs. IPD for Multiple
Values of I

(Decade Steps from 10 nA to 1 mA)

REF

REV. A–4–

AD8305

1.8

1.6

1.4

1.2

1.0

– V

LOG

0.8

V

0.6

0.4

0.2

0

1n

TPC 7. V

1A

100nA

10nA

10n 100n 1 10 100 1m 10m

vs. I

LOG

I

– A

REF

for Multiple Values of I

REF

1mA

100A

10A

PD

(Decade Steps from 10 nA to 1 mA)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

1n

10n 100n 1 10 100 1m 10m

+3V, 0V

+5V, 0V

+9V, 0V

+3V, –0.5V

+5V, –5V

+12V, 0V

IPD – A

TPC 8. Law Conformance Error vs. IPD for Various
Supply Conditions (see Annotations)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR – dB(10mV/dB)

–0.3

–0.4

–0.5

100A

1n

10n 100n 1 10 100 1m 10m

10A

1mA

I

REF

10nA

– A

TPC 10. Law Conformance Error vs. I

100nA

REF

1A

for Multiple

Values of IPD (Decade Steps from 10 nA to 1 mA)

1.4

1.2

1.0

0.8

– V

OUT

0.6

V

0.4

0.2

0

TPC 11. Pulse Response – IPD to V

100A TO 1mA: T-RISE = <1s,
T- F A LL = < 1s

10A TO 10A: T-RISE = <1s,
T- F A LL = < 1s

1A TO 10 A: T-RISE = 1s,
T- F A LL = 5s

100nA TO 1A: T- R I SE = 5s,
T- F A LL = 20s

10nA TO 100nA: T-RISE = 20s,
T- F A LL = 30s

TIME – s

OUT

160140120100806040200–20

(G = 1)

180

– mV

– V

V

REV. A

INPT

–0.1

SUM

–0.2

–0.3

–0.4

0.4

0.3

0.2

0.1

0

1n

10n 100n 1 10 100 1m 10m

TPC 9. V

INPT

IPD – A

– V

SUM

vs. I

PD

–5–

1.6

– V

V

OUT

1.4

1.2

1.0

0.8

0.6

0.4

0.2

10nA TO 100nA: T-RISE = 30s,
T- F A LL = 20s

100nA TO 1A: T- R I SE = 30s,
T- F A LL = 5s

1A TO 10A: T-RISE = 5s,
T- F A LL = < 1s

10A TO 100A: T-RISE = 1s,
T- F A LL = < 1s

100A TO 1mA: T-RISE = < 1s,
T- F A LL = < 1s

0

TIME – s

TPC 12. Pulse Response – I

REF

to V

OUT

160140120100806040200–20

(G = 1)

180

AD8305

OUT

V

–10

–20

–30

–40

–50

10

0

100

1k 10k 100k 1M 10M 100M

10nA

100nA

1mA

1A

FREQUENCY – Hz

10A

100A

TPC 13. Small Signal AC Response (5% Sine
Modulation), from I
Decade Steps from 10 nA to 1 mA, I

10

0

–10

–20

–30

NORMALIZED RESPONSE – dB

–40

–50

100

1k 10k 100k 1M 10M 100M

to V

PD

OUT

100nA

10nA

1mA

1A

FREQUENCY – Hz

(G = 1) for IPD in

= 10 mA

REF

10A

100A

TPC 14. Small Signal AC Response (5% Sine
Modulation), from I

REF

to V

(G = 1) for I

OUT

REF

in

Decade Steps from 10 nA to 1 mA, IPD = 10 mA

3

0

–3

–6

NORMALIZED RESPONSE – dB

–9

–12

10k 100k 1M 10M 100M

AV = 5

A

= 2.5

V

FREQUENCY – Hz

= 1

A

V

= 2

A

V

TPC 16. Small Signal AC Response of the Buffer for
Various Closed-Loop Gains (R

2.0

1.5

1.0

0.5

0

DRIFT – mV

–0.5

OS

V

–1.0

–1.5

–2.0

MEAN + 3

MEAN – 3

TEMPERATURE – C

= 1 kW CL < 2 pF)

L

90806040200–20 10–10 30 50 70–30–40

TPC 17. Buffer Input Offset Drift vs. Temperature

␴

to Either Side of Mean)

(3

100

10nA

10

100nA

1

Vrms/ Hz

0.1

0.01
100

1k 10k 100k 1M 10M

TPC 15. Spot Noise Spectral Density at V

1A

100A

FREQUENCY – Hz

10A

OUT

(G = 1) vs. Frequency for IPD in Decade Steps from
10 nA to 1 mA

6

5

4

3

mVrms

2

1

0

100n 1 10 100 1m 10m

10n

IPD – A

TPC 18. Total Wideband Noise Voltage
at V

vs. IPD (G = 1)

OUT

REV. A–6–

AD8305

TEMPERATURE – C

20

V

REF

DRIFT – mV

15

10

5

0

–5

–10

–15

90806040200–20 10–10 30 50 70–30–40

–20

MEAN + 3

MEAN – 3

–25

TEMPERATURE – C

5

V

INPT

DRIFT – mV

4

3

2

1

0

–1

–2

90806040200–20 10–10 30 50 70–30–40

–3

MEAN + 3

MEAN – 3

–4

–5

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

–2.0

1n

10n 100n 1 10 100 1m 10m

MEAN + 3

MEAN – 3

– A

I

PD

TA = 25C

TPC 19. Law Conformance Error Distribution
(3␴ to Either Side of Mean)

2.0

1.5

1.0

0.5

0

–0.5

ERROR – dB(10mV/dB)

–1.0

–1.5

MEAN + 3 @ 70C

MEAN  3 @ 0C

MEAN – 3 @ 70C

TA = 0C, 70C

TPC 22. V

REF

Side of Mean)

20

15

10

5

0

–5

 DRIFT – mV

–10

–15

Drift vs. Temperature (3␴ to Either

MEAN + 3

MEAN – 3

ERROR – dB(10mV/dB)

REV. A

–2.0

1n 10n 100n 1 10 100 1m 10m

IPD – A

TPC 20. Law Conformance Error Distribution
(3␴ to Either Side of Mean)

4

3

2

1

0

–1

–2

–3

–4

1n

MEAN + 3 @ –40C

MEAN

3 @ +85C

MEAN – 3 @ –40C

10n 100n 1 10 100 1m 10m

IPD – A

T

= –40C, +85C

A

TPC 21. Law Conformance Error Distribution
(3␴ to Either Side of Mean)

–7–

–20

TEMPERATURE – C

TPC 23. V

REF

– V

Drift vs. Temperature

IREF

(3␴ to Either Side of Mean)

TPC 24. V

Drift vs. Temperature (3␴ to Either

INPT

Side of Mean)

90806040200–20 10–10 30 50 70–30–40

AD8305

10

8

6

4

2

0

–2

–4

 Vy DRIFT – mV/dec

–6

–8

–10

MEAN + 3

MEAN – 3

90806040200–20 10–10 30 50 70–30–40

TEMPERATURE – C

TPC 25. Slope Drift vs. Temperature (3␴ to Either
Side of Mean of 200 mV/decade)

350

250

150

50

MEAN + 3

4000

3500

3000

2500

2000

COUNT

1500

1000

500

0

0.4

0.6 0.8 1.0 1.2 1.4 1.6
INTERCEPT – nA

TPC 28. Distribution of Logarithmic Intercept (Nominally
1 nA when R

7000

6000

5000

4000

= 200 kW ± 0.1%) Sample >22,000

REF

–50

 Iz DRIFT – pA

–150

–250

–350

MEAN – 3

TEMPERATURE – C

TPC 26. Intercept Drift vs. Temperature (3␴ to
Either Side of Mean of 1 nA)

6000

5000

4000

3000

COUNT

2000

1000

0

190 195 200 205 210

SLOPE – mV/dec

COUNT

3000

2000

1000

90806040200–20 10–10 30 50 70–30–40

85

TPC 29. Distribution of V

0

2.44

6000

5000

4000

3000

COUNT

2000

1000

0
–0.015

2.46 2.48 2.50 2.52 2.54 2.56

–0.010 –0.005 0.0 0.005 0.010 0.015

V

– V

REF

(RL = 100 kW) Sample >22,000

REF

V

– V

INPT

VOLTA G E – V

SUM

TPC 27. Distribution of Logarithmic Slope
(Nominally 200 mV/decade) Sample >22,000

TPC 30. Distribution of Offset Voltage (V
Sample >22,000

INPT

– V

SUM

REV. A–8–

)

AD8305

GENERAL STRUCTURE

The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will
also be useful in many nonoptical applications. These notes
explain the structure of this unique style of translinear log amp.
Figure 1 is a simplified schematic showing the key elements.

PHOTODIODE

INPUT CURRENT

I

PD

INPT

0.5V

Q1

VNEG (NORMALLY GROUNDED)

BIAS

GENERATOR

2.5V

80k

20k

0.5V

VSUM

V

VREF

COMM

BE1

IREF

0.5V

Q2

I

REF

V

V

V

BE1

BE2

VRDZ

BE2

TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T  K

44A/dec

14.2k

6.69k

451

COMM

VLOG

Figure 1. Simplified Schematic

The photodiode current IPD is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current I
Equation 1. A finite positive value of V

to a corresponding logarithmic voltage, as shown in

PD

is needed to bias

SUM

the collector of Q1 for the usual case of a single-supply voltage.
This is internally set to 0.5 V, that is, one fifth of the reference
voltage of 2.5 V appearing on Pin VREF. The resistance at the
VSUM pin is nominally 16 kW; this voltage is not intended as
a general bias source.

The AD8305 also supports the use of an optional negative supply
voltage, V

, at Pin VNEG. When VN is –0.5 V or more negative,

N

VSUM may be connected to ground; thus INPT and IREF
assume this potential. This allows operation as a voltage-input
logarithmic converter by the inclusion of a series resistor at either
or both inputs. Note that the resistor setting I

will need to be

REF

adjusted to maintain the intercept value. It should also be noted
that the collector-emitter voltages of Q1 and Q2 are now the full

, and effects due to self-heating will cause errors at large

V

N

input currents.

The input dependent V

of a second transistor, Q2, operating at I

V

BE2

of Q1 is compared with the reference

BE1

. This is gener-

REF

ated externally, to a recommended value of 10 mA. However,
other values over a several-decade range can be used with a
slight degradation in law conformance (TPC 1).

Theory

The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:

VkTqII

=

//In

BE C S

where IC is its collector current, IS is a scaling current, typically

–17

only 10

A, and kT/q is the thermal voltage, proportional to

()

(1)

absolute temperature (PTAT) and is 25.85 mV at 300 K. The
current, I

, is never precisely defined and exhibits an even stron-

S

ger temperature dependence, varying by a factor of roughly a

billion between –35∞C and +85∞C. Thus, to make use of the
BJT as an accurate logarithmic element, both of these tempera­ture dependencies must be eliminated.

The difference between the base-emitter voltages of a matched pair
of BJTs, one operating at the photodiode current I
operating at a reference current I

VV kTqIIkTqII

–//–//

=

In In

BE1 BE2

=
=

() ( )

kT q I I

In 10

() ( )

mV I I T K

. log /

59 5 300

, can be written as:

REF

CS REF S

/ log /

PD REF

10

()

PD REF

10

and the second

PD

(2)

=

()

The uncertain and temperature dependent saturation current IS,
which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference voltage
is processed by what is essentially an analog divider. Effectively, it
puts a variable under Equation 2. The output of this process,
which also involves a conversion from voltage-mode to current­mode, is an intermediate, temperature-corrected current:

II II

=

log /

LOG Y PD REF

()

10

(3)

where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, I
independent slope of 44 mA/decade, for all values of I

is 44 mA, resulting in a temperature-

Y

and I

PD

REF

.
This current is subsequently converted back to a voltage-mode
output, V

It is apparent that this output should be zero for I

, scaled 200 mV/decade.

LOG

PD

= I

REF

, and
would need to swing negative for smaller values of input current.
To avoid this, I
value of I

PD

would need to be as small as the smallest

REF

. However, it is impractical to use such a small refer-

ence current as 1 nA. Accordingly, an offset voltage is added to

to shift it upward by 0.8 V when Pin VRDZ is directly

V

LOG

connected to VREF. This has the effect of moving the intercept
to the left by four decades, from 10 mA to 1 nA:

II II

=

LOG Y PD INTC

where I

INTC

log /

10

is the operational value of the intercept current. To

()

(4)

disable this offset, Pin VRDZ should be grounded, then the
intercept I

INTC

a negative V

is simply I

, a negative supply of sufficient value is required

LOG

. Since values of IPD < I

REF

INTC

result in

to accommodate this situation (discussed later).

The voltage V

is generated by applying I

LOG

to an internal

LOG

resistance of 4.55 kW, formed by the parallel combination of a

6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ
pin. When the VLOG pin is unloaded and the intercept reposi­tioning is disabled by grounding VRDZ, the output current I

LOG

generates a voltage at the VLOG pin of:

VI

=¥

LOG LOG

=¥ ¥
=

455

.k

W

AI

44 4 55

VI

Y REF

.k log /

Wm I

log /

I

()

10

PD

()

10

PD

REF

(5)

where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive
loading on VLOG will lower this slope and also result in an
overall scaling uncertainty due to the variability of the on-chip
resistors. Consequently, this practice is not recommended.

V

may also swing below ground when dual supplies (VP and

LOG

) are used. When VN = –0.5 V or larger, the input pins INPT

V

N

and IREF may now be positioned at ground level by simply
grounding VSUM.

REV. A

–9–

AD8305

Managing Intercept and Slope

When using a single supply, VRDZ should be directly connected
to VREF to allow operation over the entire five-decade input
current range. As noted previously, this introduces an accurate
offset voltage of 0.8 V at the VLOG pin, equivalent to four decades,
resulting in a logarithmic transfer function that can be written as:

VV II

=¥

LOG Y PD REF

where I

INTC

log /

VII

log /

=

YPDINTC

= I

REF

Thus, the effective intercept current I
thousandth of I

REF

recommended value of I

The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged, in view of the fact that the
on-chip resistors will not ratio correctly to the added resistance.
Also, it is rare that one would want to lower the basic slope of
10 mV/dB; if this is needed, it should be effected at the low
impedance output of the buffer, which is provided to avoid such
miscalibration and also allow higher slopes to be used.

The AD8305 buffer is essentially an uncommitted op amp with
rail-to-rail output swing, good load-driving capabilities and a
unity-gain bandwidth of >12 MHz. In addition to allowing the
introduction of gain, using standard feedback networks and
thereby increasing the slope voltage V
to implement multipole low-pass filters, threshold detectors,
and a variety of other functions. Further details of these can be
found in the AD8304 data sheet.

Response Time and Noise Considerations

The response time and output noise of the AD8305 are funda­mentally a function of the signal current I
the bandwidth is proportional to I
output low frequency voltage-noise spectral-density is a function
of IPD (TPC 15) and also increases for small values of I
Details of the noise and bandwidth performance of translinear
log amps can be found in the AD8304 Data Sheet.

APPLICATIONS

The AD8305 is easy to use in optical supervisory systems and in
similar situations where a wide ranging current is to be converted
to its logarithmic equivalent, which is represented in decibel
terms. Basic connections for measuring a single-current input are
shown in Figure 2, which also includes various nonessential com­ponents, as will be explained.

4

10

()

10

()

10

4

/10

is only one ten-

INTC

(6)

, corresponding to 1 nA when using the

= 10 mA.

REF

, the buffer can be used

Y

. For small currents,

PD

, as shown in TPC 13.

PD

REF

The

.

I

451

COMM

10

VOUT

SCAL

BFIN

PD

( )

1nA

12k

8k

VLOG

C

FLT

10nF

200k

V

BIAS

1k

I

PD

1nF

VRDZ

VREF

IREF

1k

1nF

INPT

VSUM

1nF

0.5V

0.5V

20k

COMM

Q2

Q1

VNEG

80k

+5V

VPOS

GENERATOR

2.5V

V

BE2

–

TEMPERATURE

+

COMPENSATION

V

BE1

BIAS

14.2k

6.69k

COMM

I

LOG

0.5 log

Figure 2. Basic Connections for Fixed Intercept Use

The 2 V difference in voltage between the VREF and INPT pins
in conjunction with the external 200 kW resistor R
reference current I

of 10 mA into Pin IREF. Connecting pin

REF

provide a

REF

VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively
lowering the intercept current I
it at 1 nA. A wide range of other values for I

by a factor of 104 to position

INTC

, from under

REF

100 nA to over 1 mA, may be used. The effect of such changes
is shown in TPC 3.

Any temperature variation in R

must be taken into account

REF

when estimating the stability of the intercept. Also, the overall
noise will increase when using very low values of I

. In fixed-

REF

intercept applications, there is little benefit in using a large
reference current, since this only compresses the low current
end of the dynamic range when operated from a single supply,
here shown as 5 V. The capacitor between VSUM and ground
is recommended to minimize the noise on this node and to help
provide a clean reference current.

Since the basic scaling at VLOG is 0.2 V/decade, and thus a swing
of 4 V at the buffer output would correspond to 20 decades, it will
often be useful to raise the slope to make better use of the rail­to-rail voltage range. For illustrative purposes, the circuit in
Figure 2 provides an overall slope of 0.5 V/decade (25 mV/dB).
Thus, using I
to 1.4 V at I

PD

= 10 mA, V

REF

= 1 mA while the buffer output runs from 0.5 V to

runs from 0.2 V at IPD = 10 nA

LOG

3.5 V, corresponding to a dynamic range of 120 dB (electrical,
that is, 60 dB optical power).

The optional capacitor from VLOG to ground forms a single-pole
low-pass filter in combination with the 4.55 kW resistance at this
pin. For example, using a C

of 10 nF, the –3 dB corner

FLT

frequency is 3.5 kHz. Such filtering is useful in minimizing the
output noise, particularly when I

is small. Multipole filters are

PD

more effective in reducing the total noise; examples are provided
in the AD8304 data sheet.

REV. A–10–

AD8305

The dynamic response of this overall input system is influenced by
the external RC networks connected from the two inputs (INPT,
IREF) to ground. These are required to stabilize the input systems
over the full current range. The bandwidth changes with the
input current due to the widely varying pole frequency. The RC
network adds a zero to the input system to ensure stability over the
full range of input current levels. The network values shown in
Figure 2 will usually suffice, but some experimentation may be
necessary when the photodiode capacitance is high.

Although the two current inputs are similar, some care is needed
to operate the reference input at extremes of current (<100 nA)
and temperature (<0∞C). Modifying the RC network to 4.7 nF
and 2 kW will allow operation to –40∞C at 10 nA. By inspecting
the transient response to perturbations in I

at representative

REF

current levels, the capacitor value can be adjusted to provide fast
rise and fall times with acceptable settling. To fine tune the net­work zero, the resistor value should be adjusted.

CALIBRATION

The AD8305 has a nominal slope and intercept of 200 mV/decade
and 1 nA, respectively. These values are untrimmed and the
slope alone may vary as much as 7.5% over temperature. For
this reason, it is recommended that a simple calibration be done
to achieve increased accuracy.

1.4

1.2

1.0

0.8

– V

LOG

0.6

V

0.4

0.2

0

1n 10n 100n 1 10 100 1m 10m

UNCALIBRATED ERROR

MEASURED OUTPUT

CALIBRATED ERROR

IDEAL OUTPUT

IPD – A

4

3

2

1

0

–1

ERROR – dB(10mV/dB)

–2

–3

Figure 3. Using Two-Point Calibration to Increase
Measurement Accuracy

Figure 3 shows the improvement in accuracy when using a two­point calibration method. To perform this calibration, apply two
known currents, I
10 nA and 1 mA. Measure the resulting output, V

and I2, in the linear operating range between

1

and V2,

1

respectively, and calculate the slope m and intercept b.

mVV I I=

bV m I=¥

–/log – log

()()()

12 101 102

– log

1101

[]

()

(7)

(8)

The same calibration could be performed with two known opti­cal powers, P

and P2. This allows for calibration of the entire

1

measurement system while providing a simplified relationship
between the incident optical power and V

mVV PP=

bV mP=¥

–/–

()()

12 12

–

11

LOG

voltage.

(9)

(10)

The Uncalibrated Error line in Figure 3 was generated assuming
that the slope of the measured output was 200 mV/decade when
in fact it was actually 194 mV/decade. Correcting for this dis­crepancy decreased measurement error up to 3 dB.

USING A NEGATIVE SUPPLY

Most applications of the AD8305 require only a single supply of

3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 4.

I

VOUT

SCAL

BFIN

451

COMM

F

SIGMAX

10

( )

PD

1nA

12k

8k

VLOG

C

FLT

10nF

RREF
200k

V

BIAS

1k

1nF

I

PD

+
V

–

R

VRDZ

VREF

IREF

1k

1nF

INPT

VSUM

F

S

V

5V

VPOS

BIAS

2.5V

V

BE2

–

TEMPERATURE

+

COMPENSATION

V

BE1

£ –0.5V

V

NEG

C1

GENERATOR

80k

20k

0.5V

SIG

SIG

= IPD + I

COMM

Q2

Q1

VNEG

REF

0.5V

Iq + I

I

N

14.2k

6.69k

COMM

RS £

I

LOG

Iq + I

0.5 log

VN – V

Figure 4. Negative Supply Application

The use of a negative supply, VN, allows the summing node to
be placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When

= –0.5 V, the VCE of Q1 and Q2 will be the same as for

V

NEG

the default case when VSUM is grounded. This bias need not
be accurate, and a poorly defined source can be used. The
source does however need to be able to support the quiescent
current as well as the INPT and IREF signal current. For example,
it may be convenient to utilize a forward-biased junction voltage
of about 0.7 V or a Schottky barrier voltage of a little over 0.5 V.
The effect of supply on the dynamic range and accuracy can be
seen in TPC 8.

With the summing node at ground, the AD8305 may now be
used as a voltage-input log amp at either the numerator input,
INPT, or the denominator input, IREF, by inserting a suitably
scaled resistor from the voltage source to the relevant pin. The
overall accuracy for small input voltages is limited by the voltage
offset at the inputs of the JFET op amps.

The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of I

. However, the voltage V

PD

remains

LOG

referenced to the ACOM pin, and while it does not swing nega­tive for default operating conditions, it is free to do so. Thus,
adding a resistor from VLOG to the negative supply lowers
all values of VLOG, which raises the intercept. The disadvan­tage of this method is that the slope is reduced by the shunting
of the external resistor, and the poorly defined ratio of on­chip and off-chip resistances causes errors in both the slope
and the intercept.

REV. A

–11–

AD8305

REFERENCE
DETECTOR

+5V

SIGNAL
DETECTOR

+5V

Q2

Q1

80k

2.5 V

VPOS

GENERATOR

V

BE2

–

TEMPERATURE

+

COMPENSATION

V

BE1

BIAS

14.2k

6.69k

COMM

I

LOG

VOUT

451

VLOG

COMM

SCAL

BFIN

44.2k

28.0k

33nF

12.1k

18nF

0.5 log

10

( )

I

I

REF

PD

+ 2

VRDZ

SIG

REF

1k

1k

1nF

VREF

1nF

VSUM

IREF

I

REF

I

PD

INPT

0.5V

20k

COMM

0.5V

VNEG

P

P

Figure 5. Optical Absorbance Measurement

LOG-RATIO APPLICATIONS

It is often desirable to determine the ratio of two currents, for
example, in absorbance measurements. These are commonly used
to assess the attenuation of a passive optical component, such as
an optical filter or variable optical attenuator. In these situations,
a reference detector is used to measure the incident power enter­ing the component. The exiting power is then measured using a
second detector and the ratio is calculated to determine the
attenuation factor. Since the AD8305 is fundamentally a ratiometric
device, having nearly identical logging systems for both numerator
and denominator (I

and I

PD

, respectively), it can greatly

REF

simplify such measurements.

Figure 5 illustrates the AD8305’s log-ratio capabilities in optical
absorbance measurements. Here a reference detector diode is used
to provide the reference current, I

, proportional to the optical

REF

reference power level. A second detector measures the transmitted
signal power, proportional to I

. The AD8305 calculates the

PD

logarithm of the ratio of these two currents, as shown in
Equation 11, and which is reformulated in power terms in
Equation 12. Both of these equations include the internal factor
of 10,000 introduced by the output offset applied to V

LOG

via pin
VRDZ. If the true (nonoffset) log ratio shown in Equation 4 is
preferred, VRDZ should be grounded to remove the offset. As
already noted, the use of a negative supply at Pin VNEG will
allow both V

and the buffer output to swing below ground,

LOG

and also allow the input pins INPT and IREF to be set to
ground potential. Thus, the AD8305 may also be used to deter­mine the log ratio of two voltages.

Figure 5 also illustrates how a second order Sallen-Key low-pass
filter can be realized using two external capacitors and one
resistor. Here, the corner frequency is set to 1 kHz and the filter
Q is chosen to provide an optimally flat (overshoot-free) pulse
response. To scale this frequency either up or down, simply
scale the capacitors by the appropriate factor. Note that one of
the resistors needed to realize this filter is the output resistance
of 4.55 kW present at Pin VLOG. While this will not ratio

exactly to the external resistor, which may slightly alter the Q of
the filter, the effect on pulse response will be negligible for most
purposes. Note that the gain of the buffer (⫻2.5) is an integral
part of this illustrative filter design; in general, the filter may be
redesigned for other closed-loop gains.

The transfer characteristics can be expressed in terms of optical
power. If we assume that the two detectors have equal responsivities,
the relationship is

VV PP

=¥

05 10

OUT SIG REF

. log /

4

()

10

(11)

Using the identity log10(AB) = log10A + log10B and defining the

/ P

attenuation as –10 ⫻ log

10(PSIG

), the overall transfer char-

REF

acteristic can be written as

VmVdB

=¥250– a

OUT

where

a= ¥– log ( )10

PP

10

SIG REF

(12)

Figure 6 illustrates the linear-in-dB relationship between the
absorbance and the output of the circuit in Figure 5.

2.5

2.0

1.5

– V

LOG

V

1.0

0.5

0

0505

10 15 20 25 30 35 40 45

ATTENUATION – dB

Figure 6. Example of an Absorbance Transfer Function

REV. A–12–

AD8305

VSUM

VNEG VPOSVREF

IREF

INPT

VOUT

BFIN

VLOG

TRIAX CONNECTORS
(SIGNAL – INPT AND IREF
GUARD – VSUM
SHIELD – GROUND)

AD8305

CHARACTERIZATION

BOARD

KEITHLEY 236

KEITHLEY 236

DC MATRIX/DC SUPPLIES/DMM

AD8305

12

11

10

9

5 6 7 8

COMM COMM COMM COMM

16 15 14 13

1

2

3

4

VSUM VNEG VNEG VPOS

VRDZ

VREF

IREF

INPT

VOUT

SCAL

BFIN

VLOG

0.1F

OUTPUT

AD8138

EVALUATION

BOARD

A

B

+IN

BNC-T

INPUT R INPUT A INPUT B

HP 3577A

NETWORK ANALYZER

+V

S

AD8138

PROVIDES DC OFFSET

REVERSING THE INPUT POLARITY

Some applications may require interfacing to a circuit that
sources current rather than sinks current, such as connecting to
the cathode side of a photodiode. Figure 7 shows the use of a
current mirror circuit. This allows for simultaneous monitoring
of the optical power at the cathode, and a data recovery path
using a transimpedance amplifier at the anode. The modified
Wilson mirror provides a current gain very close to unity and a
high output resistance. Figure 8 shows measured transfer function
and law conformance performance of the AD8305 in conjunc­tion with this current mirror interface.

5V

MAT03

MAT03

I

PD

0.1F

1k

1nF

TIA

2.5V

200k

1nF

I

IN⬇IPD

10nA TO 1mA

1

2

0V

3

0V

4

DATA PATH

16 15 14 13

COMM COMM COMM COMM

VRDZ

VREF

AD8305

IREF

INPT

VSUM VNEG VNEG VPOS

5 6 7 8

0.1F

VOUT

SCAL

BFIN

VLOG

5V

V
log

OUT

= 0.2 

10 (IPD

OUTPUT

12

11

10

9

/1nA)

Figure 7. Wilson Current Mirror for Cathode Interfacing

1.6

1.4

1.00

0.75

These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GW to ground would subtract

0.5 nA from the input, which amounts to an error of –0.44 dB for
a source current of 10 nA. Additionally, the very high output
resistance at the input pins and the long cables commonly needed
during characterization allow 60 Hz and RF emissions to introduce
substantial measurement errors. Careful guarding techniques
are essential to reduce the pickup of these spurious signals.

Figure 9. Primary Characterization Setup

The primary characterization setup shown in Figure 9 is used to
measure V

, the static (dc) performance, logarithmic conform-

REF

ance, slope and intercept, the voltages appearing at pins VSUM,
INPT and IREF, and the buffer offset and V

drift with temper-

REF

ature. To ensure stable operation over the full current range of

and temperature extremes, filter components of C1 = 4.7 nF

I

REF

and R13 = 2 kW are used at pin to IREF ground. In some cases,
a fixed resistor between pins VREF and IREF was used in place
of a precision current source. For the dynamic tests, including
noise and bandwidth measurements, more specialized setups
are required.

CHARACTERIZATION METHODS

During the characterization of the AD8305, the device was
treated as a precision current-input logarithmic converter, since
it is not practical for several reasons to generate accurate photo­currents by illuminating a photodiode. The test currents were
generated either by using well calibrated current sources, such
as the Keithley 236, or by using a high value resistor from a
voltage source to the input pin. Great care is needed when using
very small input currents. For example, the triax output connec­tion from the current generator was used with the guard tied to
VSUM. The input trace on the PC board was guarded by con­necting adjacent traces to VSUM.

REV. A

1.2

1.0

– V

0.8

LOG

V

0.6

0.4
+3V

+5V

0.2

0

1n 10n 100n 1 10 100 1m 10m

5V

IPD – A

+5V

+3V

5V

Figure 8. Log Output and Error Using Current
Mirror with Various Supplies

0.50

0.25

0

–0.25

ERROR – dB(10mV/dB)

–0.50

–0.75

–1.00

Figure 10. Configuration for Buffer Amplifier
Bandwidth Measurement

Figure 10 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes

–13–

AD8305

provisions to offset V
ments over the full range of I

at the buffer input, allowing measure-

LOG

using a single supply. The network

PD

analyzer input impedances were set to 1 MW.

HP 3577A

NETWORK ANALYZER

AD8138

+IN

EVALUATION

BOARD

OUTPUT

POWER

SPLITTER

INPUT R INPUT A INPUT B

1

2

R2

1nF

B

A

1k

1nF

R1

1k

3

4

16 15 14 13

COMM COMM COMM COMM

VRDZ

VREF

AD8305

IREF

INPT

VSUM VNEG VNEG VPOS

5 6 7 8

VOUT

SCAL

BFIN

VLOG

0.1F

12

11

10

9

+V

S

Figure 11. Configuration for Logarithmic
Amplifier Bandwidth Measurement

The setup shown in Figure 11 was used for frequency response
measurements of the logarithmic amplifier section. The AD8138
output is offset to 1.5 V dc and modulated to a depth of 5% at
frequency. R1 is chosen (over a wide range of values up to

1.0 GW) to provide I

. The buffer was used to deload VLOG

PD

from the measurement system.

HP 89410A

SOURCE

TRIGGER CHANNEL 1 CHANNEL 2

The configuration in Figure 12 is used to measure the noise
performance. Batteries provide both the supply voltage and the
input current in order to minimize the introduction of spurious
noise and ground loop effects. The entire evaluation system,
including the current setting resistors, is mounted in a closed
aluminum enclosure to provide additional shielding to external
noise sources.

LECROY 9210

CH A

9213

200k

1nF

R1

1k

1nF

1k

16 15 14 13

COMM COMM COMM COMM

VRDZ

1

VREF

2

AD8305

3

IREF

4

INPT

VSUM VNEG VNEG VPOS

5 6 7 8

TDS5104

VOUT

SCAL

BFIN

VLOG

12

11

10

9

0.1F

CH1

+V

S

Figure 13. Configuration for Logarithmic
Amplifier Pulse Response Measurement

Figure 13 shows the setup used to make the pulse response
measurements. As with the bandwidth measurement, the VLOG
is connected directly to BFIN and the buffer amplifier is config­ured for unity gain. The buffer’s output is connected through a
short cable to the TDS5104 scope with input impedance set to
1 MW. The LeCroy’s output is offset to create the initial pedestal
current for a given value of R1, the pulse then creates one-decade
current step.

16 15 14 13

COMM COMM COMM COMM

VRDZ

1

VREF

ALKALINE

“D” CELL

1k

2

3

IREF

4

INPT

200k

1nF

R1

+

–

1k

1nF

AD8305

VSUM VNEG VNEG VPOS

5 6 7 8

Figure 12. Configuration for Noise Spectral
Density Measurement

VOUT

SCAL

BFIN

VLOG

12

11

10

9

0.1F

ALKALINE

“D” CELL

+

–

+

–

+

–

EVALUATION BOARD

An evaluation board is available for the AD8305, the schematic
for which is shown in Figure 16. It can be configured for a wide
variety of experiments. The buffer gain is factory-set to unity,
providing a slope of 200 mV/decade, and the intercept is set to 1 nA.
Table I describes the various configuration options.

REV. A–14–

AD8305

Table I. Evaluation Board Configuration Options

Component Function Default Condition

P1 Supply Interface. Provides access to supply pins, VNEG, COMM, and VPOS. P1 = Installed

P2, R8, R9, R10,
R11, R17, R18 the VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored

R2, R3, R4, R6, R14, Buffer Amplifier/Output Interface. The logarithmic slope of the AD8305 R2 = R6 = 0 W (Size 0603)
C2, C7, C9, C10 can be altered using the buffer’s gain-setting resistors,

R1, R7, R19, R20 Intercept Adjustment. The voltage dropped across resistor R1 determines the R1 = 200 kW (Size 0603)

R12, R15, C3, Supply Decoupling.
C4, C5, C6

C11 VSUM Decoupling Capacitor. C11 = 1 nF (Size 0603)
R13, R16, C1, C8 Input Compensation. Provides essential HF compensation at the input pins,

IREF, INPT, PD, Input Interface. The test board is configured to accept a current through the IREF = INPT = Installed
LK1, R5 SMA connector labeled INPT. An SC-style packaged photodiode can be PD = Not Installed

J1 SC-Style Photodiode. Allows for direct mounting of SC style photodiodes. J1 = Not Installed

Monitor Interface. By adding 0 W resistors to R8, R9, R10, R11, R17,

using a high impedance probe.

R2 and R3. R4, R14,
and C2 allow variation in the buffer loading.
provided for a variety of filtering applications. C2 = C7 = Open (Size 0603)

intercept reference current, nominally set to 10 mA using a 200 kW 1% resistor. R7 = R19 = 0 W (Size 0603)
R7 and R19 can be used to adjust the output-offset voltage at the VLOG output. R20 = Open (Size 0603)

INPT and IREF. C1 = C8 = 1 nF (Size 0603)

used in place of the INPT SMA for optical interfacing. By removing R1 and LK1 = Installed
adding a 0 W short for R5, a second current can be applied to the IREF input R5 = Open (Size 0603)
(also SMA) for evaluating the AD8305 in log-ratio applications.

R6, C7, C9, and C10 are

and R18, P2 = Not Installed

R8 = R9 = R10 = Open (Size 0603)
R17 = R18 = Open (Size 0603)

R3 = R4 = Open (Size 0603)
R11 = R14 = 0 W (Size 0603)

C9 = C10 = Open (Size 0603)
VLOG = VOUT = Installed

C3 = C4 = 0.01 ␮F
(Size 0603)
C5 = C6 = 0.1 ␮F (Size 0603)
R12 = R15 = 0 W (Size 0603)

R13 = R16 = 1 kW (Size 0603)

REV. A

–15–

AD8305

Figure 14. Component Side Layout Figure 15. Component Side Silkscreen

REV. A–16–

AD8305

SC-STYLE

PD

IREF

INPT

LK1

VRDZ

VREF

C11

R4
OPEN

R8

OPEN

R11

0

R10

OPEN

R14

0

VOUT

VOUT

VLOG

VLOG

1

2

3

4

5

6

16 15 14 13

R20

R13

C1

OPEN

OPEN

R7
0

R1
200k
1%

1k

1nF

R16

C8

R19

0

1k

1nF

I

REF

I

PD

R17

OPEN

R18

OPEN

R5

OPEN

1

2

3

R9

1nF

VSUM

COMM COMM COMM COMM

1

VRDZ

2

VREF

AD8305

IREF

3

INPT

4

VSUM VNEG VNEG VPOS

5 6 7 8

C3

0.01F

R15 R12

0

C6

0.1F

VNEG VPOS

1

0

AGND

23

P1

VOUT

SCAL

BFIN

VLOG

C4

0.01F

C5

0.1F

12

R2

0

11

10

9

OPEN

C10

OPEN

C7
OPEN

R3

R6

0

C2

OPEN

C9
OPEN

VRDZ

AGND

VOUT

VREF

VSUM

VLOG

Figure 16. Evaluation Board Schematic

P2

REV. A

–17–

AD8305

PIN 1

INDICATOR

1.00

0.90

0.80

SEATING

PLANE

OUTLINE DIMENSIONS

16-Lead Leadframe Chip-Scale Package [LFCSP]

3 mm  3 mm Body

(CP-16)

Dimensions shown in millimeters

0.50

0.40

BOTTOM

VIEW

0.30

12 MAX

3.00

BSC SQ

2.75

BSC SQ

0.80 MAX

0.65 NOM

0.05 MAX

0.01 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2

0.30

0.23

0.18

TOP

VIEW

0.45

0.50

BSC

1.50 REF

0.60 MAX
PIN 1 INDICATOR

1

2

1.45

1.30

SQ

1.15

0.25 MIN

REV. A–18–

AD8305

Revision History

Location Page

3/03—Data Sheet changed from REV. 0 to REV. A.

Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to TPC 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REV. A

–19–

C03053–0–3/03(A)

–20–

PRINTED IN U.S.A.