ANALOG DEVICES AD8305 Service Manual

100 dB Range (10 nA to 1 mA)

FEATURES

Optimized for fiber optic photodiode interfacing
Measures current over 5 decades

Law conformance 0.1 dB from 10 nA to 1 mA
Single- or dual-supply operation (3 V to 12 V total)
Full log-ratio capabilities
Nominal slope of 10 mV/dB (200 mV/decade)
Nominal intercept of 1 nA (set by external resistor)

Optional adjustment of slope and intercept
Complete and temperature stable
Rapid response time for a given current level
Miniature 16-lead chip scale package

(LFCSP 3 mm × 3 mm)
Low power: ~5 mA quiescent current

APPLICATIONS

Optical power measurement
Wide range baseband logarithmic compression
Measurement of current and voltage ratios
Optical absorbance measurement

200kΩ

V

BIAS

Logarithmic Converter

FUNCTIONAL BLOCK DIAGRAM

V

P

80kΩ

Q2
Q1

VPOS

2.5V

V

BE2

TEMPERATURE

–
+

COMPENSAT ION

V

BE1

Figure 1.

BIAS

GENERATOR

VRDZ

VREF

IREF

I

PD

INPT

VSUM

0.5V

20kΩ

COMM

0.5V

VNEG

AD8305

0.20 log

14.2kΩ
I

LOG

6.69kΩ

COMM

SCAL

451Ω

COMM

10

BFIN

I

PD

1nA

VOUT

VLOG

03053-001

GENERAL DESCRIPTION

The AD83051 is an inexpensive microminiature logarithmic converter
optimized for determining optical power in fiber optic systems. It uses
an advanced implementation of a classic translinear (junction based)
technique to provide a large dynamic range in a versatile and easily
used form. A single-supply voltage of between 3 V and 12 V is
adequate; dual supplies may optionally be used. The low quiescent
current (typically 5 mA) permits use in battery-operated applications.

The input current, I
collector current of an optimally scaled NPN transistor, which converts
this current to a voltage (V
second such converter is used to handle the reference current (I
applied to pin I
(0.5 V). This is generally acceptable for photodiode applications where
the anode does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating I
front end is available at Pin VLOG.

The basic logarithmic slope at this output is nominally 200 mV/decade
(10 mV/dB). Thus, a 100 dB range corresponds to an output change of
1 V. When this voltage (or the buffer output) is applied to an ADC that
permits an external reference voltage to be employed, the AD8305
voltage reference output of 2.5 V at Pin VREF can be used to improve
the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit),

AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other

values of the logarithmic slope can be provided using a simple external
resistor network.

1

Protected by U.S. Patent No. 5,519,308.

, of 10 nA to 1 mA applied to the INPT pin is the

PD

) with a precise logarithmic relationship. A

BE

. These input nodes are biased slightly above ground

REF

. The output of the logarithmic

REF

REF

)

The logarithmic intercept (also known as the reference current) is
nominally positioned at 1 nA by the use of the externally generated
current, I

, of 10 μA, provided by a 200 kΩ resistor connected

REF

between VREF, at 2.5 V, and the reference input, IREF, at 0.5 V. The
intercept can be adjusted over a wide range by varying this resistor.
The AD8305 can also operate in a log ratio mode, with the numerator
current applied to INPT and the denominator current applied to IREF.

A buffer amplifier is provided for driving a substantial load, for use in
raising the basic slope of 10 mV/dB to higher values, as a precision
comparator (threshold detector), or in implementing low-pass filters.
Its rail-to-rail output stage can swing to within 100 mV of the positive
and negative supply rails, and its peak current sourcing capacity is
25 mA.

It is a fundamental aspect of translinear logarithmic converters that the
small signal bandwidth falls as the current level diminishes, and the
low frequency noise-spectral density increases. At the 10 nA level, the
bandwidth of the AD8305 is about 50 kHz and increases in proportion
to I

up to a maximum value of about 15 MHz. Using the buffer

PD

amplifier, the increase in noise level at low currents can be addressed by
using it to realize lowpass filters of up to three poles.

The AD8305 is available in a 16-lead LFCSP package and is specified
for operation from −40°C to +85°C.

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] ©2003–2010 Analog Devices, Inc. All rights reserved.

AD8305

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5

Typical Performance Characteristics ............................................. 6

General Structure ........................................................................... 11

Theory .......................................................................................... 11

REVISION HISTORY

4/10—Rev. A to Rev. B

Updated Data Sheet ............................................................ Universal

Change to Figure 2 and Table 3 ...................................................... 5

Added Power Supply Sequencing Section ................................... 12

Added Figure 34; Renumbered Sequentially .............................. 12

Changes to Ordering Guide .......................................................... 24

3/03—Rev. 0 to Rev. A

Changes to TPC 3 ............................................................................. 4

Changes to TPC 18 ........................................................................... 6

Changes to Figure 3 ........................................................................ 11

Changes to Figure 8 ........................................................................ 13

Updated Outline Dimensions ....................................................... 18

Managing Intercept and Slope .................................................. 12

Response Time and Noise Considerations ............................. 12

Power Supply Sequencing ......................................................... 12

Applications ..................................................................................... 14

Calibration ....................................................................................... 15

Using A Negative Supply ............................................................... 16

Log-Ratio Applications .................................................................. 17

Reversing The Input Polarity ........................................................ 18

Characterization Methods ............................................................. 19

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. B | Page 2 of 24

AD8305

SPECIFICATIONS

VP = 5 V, VN = 0 V, TA = 25°C, R

Table 1.

Parameter Conditions Min Typ Max Unit

INPUT INTERFACE Pin 4, INPT, Pin 3, IREF

Specified Current Range, IPD Flows toward INPT pin 10 nA
1 mA
Input Current Min/Max Limits Flows toward INPT pin 10 mA
Reference Current, I

, Range Flows toward IREF pin 10 nA

REF

1 mA
Summing Node Voltage Internally preset; may be altered by the user 0.46 0.5 0.54 V
Temperature Drift −40°C < TA < +85°C 0.015 mV/°C
Input Offset Voltage V

LOGARITHMIC OUTPUT Pin 9, VLOG

Logarithmic Slope 190 200 210 mV/dec

−40°C < TA < +85°C 185 215 mV/dec
Logarithmic Intercept

1

0.3 1 1.7 nA

−40°C < TA < +85°C 0.1 2.5 nA
Law Conformance Error 10 nA < IPD < 1 mA 0.1 0.4 dB
Wideband Noise
Small Signal Bandwidth

2

2

I

Maximum Output Voltage 1.7 V
Minimum Output Voltage Limited by VN = 0 V 0.01 V
Output Resistance 4.375 5 5.625 kΩ

REFERENCE OUTPUT Pin 2, VREF

Voltage With Reference to Ground 2.435 2.5 2.565 V

−40°C < TA < +85°C 2.4 2.6 V
Maximum Output Current Sourcing (grounded load) 20 mA
Incremental Output Resistance Load current < 10 mA 2 Ω

OUTPUT BUFFER Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT

Input Offset Voltage −20 +20 mV
Input Bias Current Flowing out of Pin 10 or Pin 11 0.4 mA
Incremental Input Resistance 35 MΩ
Output Range RL = 1 kΩ to ground VP − 0.1 V
Incremental Output Resistance Load current < 10 mA 0.5 Ω
Peak Source/Sink Current 25 mA
Small Signal Bandwidth GAIN = 1 15 MHz
Slew Rate 0.2 V to 4.8 V output swing 15 V/μs

POWER SUPPLY Pin 8, VPOS; Pin 6 and Pin 7, VNEG

Positive Supply Voltage (VP − VN) ≤ 12 V 3 5 12 V
Quiescent Current 5.4 6.5 mA
Negative Supply Voltage (Optional) (VP − VN) ≤ 12 V −5.5 0 V

1

Other values of logarithmic intercept can be achieved by adjusting R

2

Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.

= 200 kΩ, and VRDZ connected to VREF, unless otherwise noted.

REF

− V

, V

− V

INPT

SUM

IREF

−20 +20 mV

SUM

IPD > 1 μA 0.7 mV√Hz

> 1 μA 0.7 MHz

PD

.

REF

Rev. B | Page 3 of 24

AD8305

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VP − VN 12 V
Input Current 20 mA
Internal Power Dissipation 500 mW

1

θ

30°C/W

JA

Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

1

With package die paddle soldered to thermal pad containing nine vias

connected to inner and bottom layers.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 4 of 24

AD8305

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16 COMM

15 COMM

14 COMM

13 COMM

VRDZ 1

VREF 2

IREF 3
INPT 4

NOTES

1. CONNECT EPAD TO GROUND.

PIN 1
INDICATOR

AD8305

TOP VIEW

(Not to Scale)

VNEG 6

VSUM 5

12 VOUT
11 SCAL
10 BFIN

9 VLOG

VPOS 8

VNEG 7

03053-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 VRDZ

Top of a Resistive Divider Network that Offsets V

to Position the Intercept. Normally connected to VREF;

LOG

may also be connected to ground when bipolar outputs are to be provided.
2 VREF Reference Output Voltage of 2.5 V.
3 IREF Accepts (Sinks) Reference Current, I
4 INPT

Accepts (Sinks) Photodiode Current, I

.

REF

. Usually connected to photodiode anode such that photo current

PD

flows into INPT.
5 VSUM

Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and I

REF

node

potential.
6, 7 VNEG Optional Negative Supply, VN (this pin is usually grounded; for details of usage, see the Applications section.
8 VPOS Positive Supply, (VP − VN ) ≤ 12 V.
9 VLOG Output of the Logarithmic Front End.
10 BFIN Buffer Amplifier Noninverting Input.
11 SCAL Buffer Amplifier Inverting Input.
12 VOUT Buffer Output.
13 to 16 COMM Analog Ground.
EPAD The exposed pad must be soldered to ground.

Rev. B | Page 5 of 24

AD8305

R

R
R

TYPICAL PERFORMANCE CHARACTERISTICS

VP = 5 V, VN = 0 V, R

= 200 kΩ, TA = 25°C, unless otherwise noted.

REF

1.6
TA = –40°C, 0°C, +25°C, +70°C, +85 ° C

= 0V

V

N

1.4

1.2

–40°C
+25°C
+85°C

100n 1µ

10n 10µ 100µ1m10m

vs. IPD for Multiple Temperatures

LOG

–40°C

+25°C
+85°C

10n 10µ 100µ 1m 10m100n 1µ

(V)

LOG

V

( V)

V

1.0

0.8

0.6

0.4

0.2

0

1n

Figure 3. V

1.8

1.6

1.4

1.2

1.0

LOG

0.8

0.6

0.4

0.2

0

1n

0°C
+70°C

IPD (A)

TA = –40°C, 0 °C, +25°C, +70°C, +85°C
V

= 0V

N

0°C
+70°C

I

(A)

REF

2.0

1.5

1.0

0.5

0

–0.5

OR; dB (10mV/dB)
ER

–1.0

–1.5

–2.0

03053-003

–40°C

1n 10n 10µ 100µ1m10m100n 1µ

Figure 6. Law Conformance Error vs. IPD (at I

TA = –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

+85°C

0°C

+70°C

+25°C

IPD (A)

= 10 μA) for Multiple

REF

03053-006

Temperatures, Normalized to 25°C

2.0

1.5

1.0

0.5

0

–0.5

ERROR; dB (10mV/dB)

–1.0

–1.5

–2.0

03053-004

1n 10n 10µ 100µ1m10m100n 1µ

TA = –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

+70°C

+25°C

I

(A)

PD

+85°C

0°C

–40°C

03053-007

Figure 4. V

vs. I

for Multiple Temperatures

LOG

REF

Figure 7. Law Conformance Error vs. I

(at IPD = 10 μA) for Multiple

REF

Temperatures, Normalized to 25°C

1.8

1.6

1.4

1.2

1.0

(V)

LOG

0.8

V

0.6

0.4

0.2

0

1n 10n 10µ 100µ 1m 10m100n 1µ

Figure 5. V

vs. IPD for Multiple Values of I

LOG

10nA

100nA

1µA

10µA

100µA

1mA

IPD (A)

(Decade Steps from 10 nA to 1 mA)

REF

3053-005

0.5

0.4

0.3

0.2

0.1

0

–0.1

OR; dB (10mV/dB)

–0.2

E

–0.3

–0.4

–0.5

1n 10n 10µ 100µ 1m 10m100n 1µ

10µA

1µA

100µA 1mA

Figure 8. Law Conformance Error vs. I

10nA

I

(A)

PD

for Multiple Values of I

PD

100nA

(Decade Steps

REF

03053-008

from 10 nA to 1 mA)

Rev. B | Page 6 of 24

AD8305

R
R

V

R
R

1.8

1.6

1.4

1.2

1.0

(V)

LOG

0.8

V

0.6

0.4

0.2

0

1n

10n 100n 1µ 10µ 100µ 1m 10m

10nA

100nA

I

REF

1µA

(A)

10µA

100µA

1mA

03053-009

0.5

0.4

0.3
10µA

0

1mA

100µA

1n 10n 100n 1µ 10µ 100µ 1m 10m

OR; dB (10mV/dB)
E

0.2

0.1

–0.1

–0.2

–0.3

–0.4
–0.5

10nA

100nA

I

(A)

REF

1µA

03053-012

Figure 9. V

vs. I

for Multiple Values of IPD (Decade Steps from

LOG

REF

10 nA to 1 mA)

0.5

0.4

0.3

0.2

0.1

0

–0.1

OR; dB (10mV/dB)

–0.2

E

–0.3

–0.4
–0.5

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 10. Law Conformance Error vs. I

+3V, 0V
+5V, 0V

+9V, 0V

+3V, –0.5V

+5V, –5V

IPD (A)

for Various Supply Conditions (See

PD

Annotations)

0.4

0.3

0.2

0.1

(mV)

INPT

0

–

–0.1

SUM

V

–0.2

+12V, 0V

Figure 12. Law Conformance Error vs. I

for Multiple Values of IPD (Decade

REF

Steps from 10 nA to 1 mA)

1.4

1.2

1.0

0.8

(V)

OUT

0.6

V

0.4

0.2

03053-010

1.6

1.4

1.2

1.0

(V)

0.8

OUT

V

0.6

0.4

100µATO 1mA:T-RISE =<1µs,
T-FA LL = < 1µ s

10µATO 10µA:T-RISE = <1µs,
T-FA LL = < 1µ s

1µATO 10µA:T-RISE = 1µs,

T-FAL L = 5µ s
100nA TO 1µA:T- RI S E = 5µs,

T-FALL = 20µs

10nA TO 100nA:T -R I SE = 20µs,
T-FAL L = 30 µs

0

Figure 13. Pulse Response − I

10nATO 100nA:T -R I SE = 30µs,
T-FALL = 20µs

100nA TO 1µA: T-RISE = 30µs,
T-FA LL = 5 µ s

1µATO 10µA:T- RISE = 5µs,

T-FAL L = 1µ s
10µATO 100µA :T-RISE = 1µs,

T-FA LL = < 1µ s
100µA TO 1mA:T-RISE = <1µs,

T-FA LL = < 1µ s

TIME (µs)

PD

to V

OUT

(G = 1)

160140120100806040200–20

180

03053-013

–0.3

–0.4

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 11. V

IPD (A)

INPT

− V

SUM

vs. IPD

03053-011

0.2

0

Figure 14. Pulse Response − I

TIME (µs)

160140120100806040200–20

180

03053-014

to V

(G = 1)

REF

OUT

Rev. B | Page 7 of 24

AD8305

√

10

0

–10

(V)

–20

OUT

V

–30

–40

10nA

100nA

10µA

100µA

1mA

1µA

3

0

–3

–6

NORMALIZED RESPONSE (dB)

–9

AV = 5

A

V

= 2.5

= 1

A

V

= 2

A

V

–50

100

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 15. Small Signal AC Response (5% Sine Modulation), from I

(G = 1) for I

10

0

–10

–20

–30

NORMALIZE D RE SPONSE (dB)

–40

–50

100 1k 10k 100k 1M 10M 100M

in Decade Steps from 10 nA to 1 mA, I

PD

100nA

10nA

FREQUENCY (Hz)

10µA

1mA

1µA

= 10 μA

REF

100µA

Figure 16. Small Signal AC Response (5% Sine Modulation), from I

(G = 1) for I

100

in Decade Steps from 10 nA to 1 mA, IPD = 10 μA

REF

–12

10k 100k 1M 10M 100M

03053-015

to V

PD

OUT

03053-016

to V

REF

OUT

Figure 18. Small Signal AC Response of the Buffer for Various Closed-Loop

2.0

1.5

1.0

0.5

0

DRIFT (mV)

–0.5

OS

V

–1.0

–1.5

–2.0

Figure 19. Buffer Input Offset Drift vs. Temperature (3σ to Either Side of

6

FREQUENCY (Hz)

= 1 kΩ CL < 2 pF)

Gains (R

L

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Mean)

03053-018

90806040200–20 10 30 50 70–10–30–40

03053-019

10nA

10

Hz)

(µV rms/

0.01

0.1

1

100

1k 10k 100k 1M 10M

100nA

1µA

FREQUENCY (Hz)

Figure 17. Spot Noise Spectral Density at V

10µA

100µA

(G = 1) vs. Frequency for IPD in

OUT

03053-017

5

4

3

(mV rms)

2

1

0

10n 100n 1µ 10µ 100µ 10m1m

IPD (A)

Figure 20. Total Wideband Noise Voltage at V

vs. IPD (G = 1)

OUT

3053-020

Decade Steps from 10 nA to 1 mA

Rev. B | Page 8 of 24