Analog Devices AD829 g Datasheet

High Speed, Low Noise
Video Op Amp
FEATURES High Speed
120 MHz Bandwidth, Gain = –1 230 V/s Slew Rate 90 ns Settling Time to 0.1%
Ideal for Video Applications
0.02% Differential Gain
0.04ⴗ Differential Phase
Low Noise
1.7 nV/Hz Input Voltage Noise
1.5 pA/Hz Input Current Noise
Excellent DC Precision
1 mV Max Input Offset Voltage (Over Temp)
0.3 mV/C Input Offset Drift
Flexible Operation
Specified for 5 V to 15 V Operation 3 V Output Swing into a 150 Load External Compensation for Gains 1 to 20 5 mA Supply Current
Available in Tape and Reel in Accordance with
EIA-481A Standard

GENERAL DESCRIPTION

The AD829 is a low noise (1.7 nV/Hz), high speed op amp with custom compensation that provides the user with gains of ±1 to ±20 while maintaining a bandwidth greater than 50 MHz. The AD829’s 0.04° differential phase and 0.02% differential gain performance at 3.58 MHz and 4.43 MHz, driving reverse­terminated 50 or 75 cables, makes it ideally suited for professional video applications. The AD829 achieves its 230 V/µs uncompensated slew rate and 750 MHz gain bandwidth while requiring only 5 mA of current from power supplies.
The AD829’s external compensation pin gives it exceptional versatility. For example, compensation can be selected to optimize the bandwidth for a given load and power supply voltage. As a gain-of-two line driver, the –3 dB bandwidth can be increased to 95 MHz at the expense of 1 dB of peaking. The AD829’s output can also be clamped at its external compensation pin.
The AD829 exhibits excellent dc performance. It offers a mini­mum open-loop gain of 30 V/mV into loads as low as 500 Ω, low input voltage noise of 1.7 nV/Hz, and a low input offset voltage of 1 mV maximum. Common-mode rejection and power supply rejection ratios are both 120 dB.
This op amp is also useful in multichannel, high speed data conversion where its fast (90 ns to 0.1%) settling time is impor­tant. In such applications, the AD829 serves as an input buffer for 8-bit to 10-bit A/D converters and as an output I/V con­verter for high speed DACs.
REV. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

CONNECTION DIAGRAMS

8-Lead
PDIP(N), Cerdip (Q), and SOIC (R) Packages
OFFSET NULL
–IN
+IN
–V
1
2
3
4
S
AD829
TOP VIEW
(Not to Scale)
8
OFFSET NULL
+V
7
S
6
OUTPUT
C
5
COMP
20-Lead LCC Pinout
NC
NC
OFFSET
NULL
OFFSET
NULL
NC
20 19123
NC
COMP
C
NC
18
+V
17
NC
16
OUTPUT
15
14
NC
4
NC
5
–IN
6
NC
+IN
NC
NC = NO CONNECT
7
8
910111213
TOP VIEW
(Not to Scale)
NC
AD829
NC
–V
Operating as a traditional voltage feedback amplifier, the AD829 provides many of the advantages a transimpedance amplifier offers. A bandwidth greater than 50 MHz can be maintained for a range of gains through the replacement of the external com­pensation capacitor. The AD829 and the transimpedance amplifier are both unity gain stable and provide similar voltage noise performance (1.7 nV/Hz); however, the current noise of the AD829 (1.5 pA/Hz) is less than 10% of the noise of transimpedance amps. The inputs of the AD829 are symmetrical.

PRODUCT HIGHLIGHTS

1. Input voltage noise of 2 nV/Hz, current noise of 1.5 pA/Hz,
and 50 MHz bandwidth, for gains of 1 to 20, make the AD829 an ideal preamp.
2. Differential phase error of 0.04° and a 0.02% differential
gain error, at the 3.58 MHz NTSC and 4.43 MHz PAL and SECAM color subcarrier frequencies, make the op amp an outstanding video performer for driving reverse-terminated 50 and 75 cables to ± 1 V (at their terminated end).
3. The AD829 can drive heavy capacitive loads.
4. Performance is fully specified for operation from ±5 V to ±15 V supplies.
5. The AD829 is available in plastic, CERDIP, and small outline packages. Chips and MIL-STD-883B parts are also available. The SOIC-8 package is available for the extended tempera­ture range of –40°C to +125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
AD829–SPECIFICATIONS
(@ TA = 25C and VS = 15 V dc, unless otherwise noted.)
Model Conditions V
S
Min Typ Max Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE ±5 V, ±15 V 0.2 1 0.2 1 0.1 0.5 mV
AD829JR AD829AR AD829AQ/S
T
MIN
to T
MAX
110.5 mV
Offset Voltage Drift ±5 V, ±15 V 0.3 0.3 0.3 µV/°C
INPUT BIAS CURRENT ±5 V, ±15 V 3.3 7 3.3 7 3.3 7 µA
T
MIN
to T
MAX
8.2 9.5 9.5 µA
INPUT OFFSET CURRENT ±5 V, ±15 V 50 500 50 500 50 500 nA
T
MIN
to T
MAX
500 500 500 nA
Offset Current Drift ±5 V, ±15 V 0.5 0.5 0.5 nA/°C
OPEN-LOOP GAIN V
= ±2.5 V ± 5 V
O
R
= 500 30 65 30 65 30 65 V/mV
LOAD
to T
T
MIN
R V R T
R
MAX
= 150 40 40 40 V/mV
LOAD
= ± 10 V ± 15 V
OUT
= 1 k 50 100 50 100 50 100 V/mV
LOAD
to T
MIN
MAX
= 500 85 85 85 V/mV
LOAD
20 20 20 V/mV
20 20 20 V/mV
DYNAMIC PERFORMANCE
Gain Bandwidth Product ±5 V 600 600 600 MHz
Full Power Bandwidth
1, 2
VO = 2 V p-p R
= 500 Ω±5 V 25 25 25 MHz
LOAD
±15 V 750 750 750 MHz
VO = 20 V p-p R
= 1 kΩ±15 V 3.6 3.6 3.6 MHz
Slew Rate
2
LOAD
R
= 500 Ω±5 V 150 150 150 V/µs
LOAD
R
= 1 kΩ±15 V 230 230 230 V/µs
LOAD
Settling Time to 0.1% AV = –19
–2.5 V to +2.5 V ±5 V 65 65 65 ns
Phase Margin
DIFFERENTIAL GAIN ERROR
2
3
DIFFERENTIAL PHASE ERROR3R
10 V Step ±15 V 90 90 90 ns C
= 10 pF ±15 V
LOAD
R
= 1 k 60 60 60 Degrees
LOAD
R
= 100 Ω±15 V
LOAD
C
= 30 pF 0.02 0.02 0.02
COMP
= 100 Ω±15 V
LOAD
C
= 30 pF 0.04 0.04 0.04 Degrees
COMP
%
COMMON-MODE REJECTION VCM = ± 2.5 V ±5 V 100 120 100 120 100 120 dB
VCM = ± 12 V ±15 V 100 120 100 120 100 120 dB T
MIN
to T
MAX
96 96 96 dB
POWER SUPPLY REJECTION VS = ± 4.5 V to ±18 V 98 120 98 120 98 120 dB
T
MIN
to T
MAX
94 94 94 dB
INPUT VOLTAGE NOISE f = 1 kHz ±15 V 1.7 2 1.7 2 1.7 2 nV/Hz
INPUT CURRENT NOISE f = 1 kHz ± 15 V 1.5 1.5 1.5 pA/Hz
INPUT COMMON-MODE
VOLTAGE RANGE ±5 V +4.3 +4.3 +4.3 V
–3.8 –3.8 –3.8 V
±15 V +14.3 +14.3 +14.3 V
–13.8 –13.8 –13.8 V
OUTPUT VOLTAGE SWING R
= 500 Ω±5 V ±3.0 ± 3.6 ±3.0 ±3.6 ±3.0 ± 3.6 V
LOAD
R
= 150 Ω±5 V ±2.5 ± 3.0 ±2.5 ±3.0 ±2.5 ± 3.0 V
LOAD
R
50 Ω±5 V ± 1.4 ±1.4 ±1.4 V
LOAD =
R
= 1 kΩ±15 V ± 12 ± 13.3 ±12 ±13.3 ± 12 ±13.3 V
LOAD
R
= 500 Ω±15 V ± 10 ± 12.2 ±10 ±12.2 ± 10 ±12.2 V
LOAD
Short Circuit Current ±5 V, ±15 V 32 32 32 mA
INPUT CHARACTERISTICS
Input Resistance (Differential) 13 13 13 k Input Capacitance (Differential)
4
55 5pF
Input Capacitance (Common Mode) 1.5 1.5 1.5 pF
CLOSED-LOOP OUTPUT
RESISTANCE AV = +1, f = 1 kHz 2 2 2 m
–2–
REV. G
AD829
Model Conditions V
S
Min Typ Max Min Typ Max Min Typ Max Unit
POWER SUPPLY
Operating Range ±4.5 ±18 ±4.5 ±18 ± 4.5 ± 18 V Quiescent Current ±15 V 5 6.5 5 6.5 5 6.5 mA
AD829JR AD829AR AD829AQ/S
T
MIN
to T
MAX
8.0 8.0 8.2/8.7 mA
±15 V 5.3 6.8 5.3 6.8 5.3 6.8 mA
T
MIN
to T
MAX
8.3 9.0 8.5/9.0 mA
TRANSISTOR COUNT Number of Transistors 46 46 46
NOTES
1
Full Power Bandwidth = Slew Rate/2 π V
2
Tested at Gain = +20, C
3
3.58 MHz (NTSC) and 4.43 MHz (PAL and SECAM).
4
Differential input capacitance consists of 1.5 pF package capacitance plus 3.5 pF from the input differential pair.
COMP
= 0 pF.
PEAK
.
Specifications subject to change without notice.
REV. G
–3–
AD829

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
1
PDIP (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
CERDIP (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Differential Input Voltage
3
. . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q, E) . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD829J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD829A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
AD829S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Maximum internal power dissipation is specified so that TJ does not exceed 150°C at an ambient temperature of 25°C. Thermal characteristics:
8-lead PDIP package: θJA = 100°C/W (derate at 8.7 mW/°C) 8-lead CERDIP package: θJA = 110°C/W (derate at 8.7 mW/°C) 20-lead LCC package: θJA = 77°C/W 8-lead SOIC package: θJA = 125°C/W (derate at 6 mW/°C).
3
If the differential voltage exceeds 6 V, external series protection resistors should be added to limit the input current.

METALLIZATION PHOTO

Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
SUBSTRATE CONNECTED TO +V
2.5
2.0
1.5
1.0
PDIP
CERDIP
S
LCC
0.5
MAXIMUM POWER DISSIPATION (W)
0
–55 –45–35 –25–15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125
SOIC
AMBIENT TEMPERATURE (C)
Figure 1. Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD829 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. G–4–

ORDERING GUIDE

Model Temperature Range Package Description Package Option
AD829AR –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829AR-REEL –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829AR-REEL7 –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829ARZ* –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829ARZ-REEL* –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829ARZ-REEL7* –40°C to +125°C 8-Lead Plastic SOIC R-8 AD829JN 0°C to 70°C 8-Lead Plastic PDIP N-8 AD829JR 0°C to 70°C 8-Lead Plastic SOIC R-8 AD829JR-REEL 0°C to 70°C 8-Lead Plastic SOIC R-8 AD829JR-REEL7 0°C to 70°C 8-Lead Plastic SOIC R-8 AD829AQ –40°C to +125°C 8-Lead CERDIP Q-8 AD829SQ –55°C to +125°C 8-Lead CERDIP Q-8 AD829SQ/883B –55°C to +125°C 8-Lead CERDIP Q-8 5962-9312901MPA –55°C to +125°C 8-Lead CERDIP Q-8 AD829SE/883B –55°C to +125°C 20-Lead LCC E-20A 5962-9312901M2A –55°C to +125°C 20-Lead LCC E-20A AD829JCHIPS Die AD829SCHIPS Die
*Z = Pb-free part.
AD829
REV. G
–5–
AD829–Typical Performance Characteristics
(ⴗC)
(ⴗC)
OUTPUT VOLTAGE SWING (V p–p)
30
25
20
15
10
5
0
10 100
1k 10k
LOAD RESISTANCE (⍀)
5 V SUPPLIES
15 V SUPPLIES
(Hz)
20
15
+V
OUT
10
–V
OUT
5
INPUT COMMON-MODE RANGE (V)
0
02051015
SUPPLY VOLTAGE (ⴞV)
TPC 1. Input Common-Mode Range vs. Supply Voltage
6.0
5.5
5.0
4.5
QUIESCENT CURRENT (mA)
20
15
10
VOLTAGE (V)
5
MAGNITUDE OF THE OUTPUT
0
02051015
SUPPLY VOLTAGE (±V)
+V
OUT
–V
R
TPC 2. Output Voltage Swing vs. Supply Voltage
5–
4
VS = 5V, 15V
3
INPUT BIAS CURRENT (A)
OUT
LOAD
= 1k
TPC 3. Output Voltage Swing vs. Resistive Load
100
10
1
0.1
0.01
AV = +20 C
COMP
= 0pF
AV = +1 C
COMP
= 68pF
4.0 02051015
SUPPLY VOLTAGE (ⴞV)
TPC 4. Quiescent Current vs. Supply Voltage
7
6
5
4
QUIESCENT CURRENT (mA)
3
60–20–02040 60 80 100 14040
VS = 15V
VS = 5V
120
TEMPERATURE
TPC 7. Quiescent Current vs. Temperature
2–
40
60–20–02040 60 80 100 140
TEMPERATURE (ⴗC)
TPC 5. Input Bias Current vs. Temperature
40
NEGATIVE
35
30
25
20
SHORT CIRCUIT CURRENT LIMIT (mA)
15
60–20–02040 60 80 100 14040
CURRENT LIMIT
POSITIVE
CURRENT LIMIT
VS = 5V
AMBIENT TEMPERATURE
TPC 8. Short-Circuit Current Limit vs. Temperature
120
120
CLOSED-LOOP OUTPUT IMPEDANCE ()
0.001 1k 10k 100k 1M 10M 100M
FREQUENCY
TPC 6. Closed-Loop Output Impedance vs. Frequency
65
VS = ±15V
= +20
A
V
= 0pF
C
60
55
50
–3 dB BANDWIDTH (MHz)
45
COMP
60–20–02040 60 80 100 14040
TEMPERATURE (ⴗC)
TPC 9. –3 dB Bandwidth vs. Temperature
120
REV. G–6–
AD829
(Hz)
)
(
)
(Hz)
10
8
6
4
2
0
020406080100 120 160
1%
1%
140
2–
4–
6–
8–
0.1%
ERROR A
V
= –19
C
COMP
= 0pF
–10
OUTPUT SWING FROM 0 TO ⴞV
SETTLING TIME (ns)
0.1%
)
120
100
80
60
40
OPEN-LOOP GAIN (dB)
20
0 100 1k 10k 100k 1M 10M 100M
GAIN 5V SUPPLIES 500 LOAD
C
COMP
FREQUENCY (Hz)
= 0pF
GAIN 15V SUPPLIES 1k LOAD
PHASE
TPC 10. Open-Loop Gain and Phase Margin vs. Frequency
120
100
80
60
CMRR (dB)
C
= 0pF
40
COMP
100
80
60
40
20
PHASE (Degrees)
0
–20
105
100
95
90
85
OPEN-LOOP GAIN (dB)
80
75
10 100
VS = ⴞ15V
VS = ⴞ5V
1k
LOAD RESISTANCE (⍀)
TPC 11. Open-Loop Gain vs. Resistive Load
30
25
20
15
VS = ±5V
= 500
R
L
10
= +20
A
V
OUTPUT VOLTAGE (V p–p)
C
5
COMP
= 0pF
VS = ±15V
= 1k
R
L
= +20
A
V
C
COMP
= 0pF
10k
120
+
SUPPLY
100
80
SUPPLY
60
PSRR (dB)
40
C
= 0pF
COMP
20
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
TPC 12. Power Supply Rejection Ratio (PSRR) vs. Frequency
20
1k 10k 100k 1M 10M 100M
FREQUENCY
TPC 13. Common-Mode Rejection Ratio vs. Frequency
–70
–75
–80
–85
–90
THD (dB)
–95
–100
–105
–110
100 300 1k 3k 10k 30k 100k
VIN = 3V RMS
= –1
A
V
C
COMP
C
LOAD
RL = 500
RL = 2k
FREQUENCY (Hz
TPC 16. Total Harmonic Distortion (THD) vs. Frequency
REV. G
= 30pF
= 100pF
0
1
INPUT FREQUENCY
10 100
MHz
TPC 14. Large Signal Frequency Response
–20
THIRD HARMONIC
SECOND HARMONIC
1.0M
FREQUENCY
1.5M
–30
–40
THD (dB)
–50
–60
–70
0
VIN = 2.24V RMS
= –1
A
V
= 250
R
L
= 0
C
LOAD
= 30pF
C
COMP
500k
TPC 17. Second and Third Harmonic Distortion vs. Frequency
–7–
2.0M
TPC 15. Output Swing and Error vs. Settling Time
5
4
3
2
1
INPUT VOLTAGE NOISE (nV/ Hz)
0
10 100 1k 10k 100k
FREQUENCY (Hz
1M 10M
TPC 18. Input Voltage Noise Spectral Density
AD829
(ⴗC)
(V)
(
)
+V
S
0.1␮F
C
COMP
(EXTERNAL)
–V
S
0.1␮F
OFFSET
NULL
ADJUST
20k
AD829
400
350
300
250
200
SLEW RATE (V/␮s)
150
100
AV = +20 SLEW RATE 10% to 90%
VS = 15V
60–20–02040 60 80 100 14040
RISE
FALL
RISE
FALL
VS = 5V
120
TEMPERATURE
TPC 19. Slew Rate vs. Temperature
HP8130A
5ns RISE TIME
0.05
0.04
DIFFERENTIAL PHASE (Degrees)
0.03 5 10 15
SUPPLY VOLTAGE
0.043
TPC 20. Differential Gain and Phase vs. Supply
C
COMP
+15V
AD829
15pF
0.1␮F
50
CABLE
0.1␮F
50
DIFF GAIN
DIFF PHASE
5pF
50
300
0.03
0.02
0.01
CABLE
Percent
DIFFERENTIAL GAIN
Figure 2. Offset Null and External Shunt Compensation Connections
50
TEKTRONIX TYPE 7A24 PREAMP
50
–15V
300
Figure 3a. Follower Connection. Gain = +2
Figure 3b. Gain-of-2 Follower
Large Signal Pulse Response
Figure 3c. Gain-of-2 Follower Small Signal Pulse Response
REV. G–8–
AD829
HP8130A
5ns RISE TIME
50
CABLE
45
5
100
C
COMP
+15V
AD829
–15V
= 0pF
0.1␮F
0.1␮F
1pF
2k
105
Figure 4a. Follower Connection. Gain = +20
FET PROBE
TEKTRONIX
TYPE 7A24
PREAMP
Figure 4b. Gain-of-20 Follower Large Signal Pulse Response
50
HP8130A
5ns RISE TIME
CABLE
Figure 5a. Unity Gain Inverter Connection
50
300
300
+15V
AD829
–15V
5pF
0.1␮F
0.1␮F
C
15pF
COMP
Figure 4c. Gain-of-20 Follower
Small Signal Pulse Response
50
50
CABLE
TEKTRONIX TYPE 7A24 PREAMP
50
REV. G
Figure 5b. Unity Gain Inverter
Large Signal Pulse Response
Figure 5c. Unity Gain Inverter
Small Signal Pulse Response
–9–
AD829

THEORY OF OPERATION

The AD829 is fabricated on Analog Devices’ proprietary comple­mentary bipolar (CB) process, which provides PNP and NPN transistors with similar f the AD829 input stage consists of an NPN differential pair in which each transistor operates at 600 µA collector current. This gives the input devices a high transconductance, which in turn gives the AD829 a low noise figure of 2 nV/
The input stage drives a folded cascode that consists of a fast pair of PNP transistors. These PNPs drive a current mirror that provides a differential-input-to-single-ended-output conversion. The high speed PNPs are also used in the current-amplifying output stage, which provides high current gain of 40,000. Even under conditions of heavy loading, the high f PNPs, produced using the CB process, permits cascading two stages of emitter followers while maintaining 60° phase margin at closed-loop bandwidths greater than 50 MHz.
Two stages of complementary emitter followers also effectively buffer the high impedance compensation node (at the C from the output so the AD829 can maintain a high dc open-loop gain, even into low load impedances: 92 dB into a 150 load and 100 dB into a 1 kload. Laser trimming and PTAT biasing ensure low offset voltage and low offset voltage drift, enabling the user to eliminate ac coupling in many applications.
For added flexibility, the AD829 provides access to the internal frequency compensation node. This allows the user to customize frequency response characteristics for a particular application.
Unity gain stability requires a compensation capacitance of 68 pF (Pin 5 to ground), which will yield a small signal bandwidth of 66 MHz and slew rate of 16 V/µs. The slew rate and gain band- width product will vary inversely with compensation capacitance. Table I and Figure 8 show the optimum compensation capacitance and the resulting slew rate for a desired noise gain. For gains between 1 and 20, C bandwidth relatively constant. The minimum gain that will still provide stability depends on the value of external compensation capacitance.
An RC network in the output stage (Figure 6) completely removes the effect of capacitive loading when the amplifier is compensated for closed-loop gains of 10 or higher. At low frequen­cies, and with low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case, C is bootstrapped and does not contribute to the compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the output impedance of the output stage this reduces the gain, and subsequently, C is incompletely boot­strapped. Therefore, some fraction of C contributes to the compensation capacitance, and the unity gain bandwidth falls. As the load capacitance is further increased, the bandwidth continues to fall and the amplifier remains stable.

Externally Compensating the AD829

The AD829 is stable with no external compensation for noise gains greater than 20. For lower gains, two different methods of frequency compensating the amplifier can be used to achieve closed-loop stability: shunt and current feedback compensation.
s of 600 MHz. As shown in Figure 6,
T
Hz @ 1 kHz.
s of the NPN and
T
COMP
can be chosen to keep the small signal
COMP
pin)
+V
S
15
IN+
1.2mA
IN–
OFFSET NULL
C
COMP
C
12.5pF
R
500
15
OUTPUT
–V
S
Figure 6. Simplified Schematic

Shunt Compensation

Figures 7 and 8 show that shunt compensation has an external compensation capacitor, C
, connected between the com-
COMP
pensation pin and ground. This external capacitor is tied in parallel with approximately 3 pF of internal capacitance at the compensation node. In addition, a small capacitance, C
LEAD
, in parallel with resistor R2, compensates for the capacitance at the amplifier’s inverting input.
R2
C
LEAD
+V
S
0.1␮F
0.1␮F
C
COMP
1k
V
OUT
50
COAX
CABLE
V
IN
50
R1
AD829
–V
S
Figure 7. Inverting Amplifier Connection Using External Shunt Compensation
+V
S
C
0.1␮F
0.1␮F
COMP
V
OUT
R2
1k
C
LEAD
R1
50
CABLE
V
IN
50
AD829
–V
S
Figure 8. Noninverting Amplifier Connection Using External Shunt Compensation
REV. G–10–
Table I. Component Selection for Shunt Compensation
(
)
Slew
Follower Inverter R1 R2 C
C
L
COMP
Rate –3 dB Small Signal
Gain Gain ()(⍀) (pF) (pF) (V/␮s) Bandwidth (MHz)
1Open 100 0 68 16 66 2–11 k1 k5 25 38 71 5–4511 2.0 k 1 7 90 76 10 –9 226 2.05 k 0 3 130 65 20 –19 105 2 k 0 0 230 55 25 –24 105 2.49 0 0 230 39 100 –99 20 2 k 0 0 230 7.5
AD829
Table I gives the recommended C
COMP
and C
LEAD
values, as well as the corresponding slew rates and bandwidth. The capacitor values were selected to provide a small signal frequency response with less than 1 dB of peaking and less than 10% overshoot. For this table, supply voltages of ±15 V should be used. Figure 9 is a graphical extension of the table that shows the slew rate/gain trade-off for lower closed-loop gains, when using the shunt compensation scheme.
100
C
COMP
(pF)
10
COMP
C
1
1 10010
Figure 9. Value of C
SLEW RATE
VS = 15V
NOISE GAIN
and Slew Rate vs. Noise Gain
COMP
1k
s
V/
100
SLEW RATE
10

Current Feedback Compensation

Bipolar, nondegenerated, single pole, and internally compensated amplifiers have their bandwidths defined as
fT=
2 π r
1
eCCOMP
=
2 π
kT
I
C
COMP
q
where
f
is the unity gain bandwidth of the amplifier.
T
I is the collector current of the input transistor.
is the compensation capacitance.
C
COMP
r
is the inverse of the transconductance of the input transistors.
e
kT/q approximately equals 26 mV @ 27°C.
Since both f
and slew rate are functions of the same variables,
T
the dynamic behavior of an amplifier is limited. Since
Slew Rate =
C
2I
COMP
then
Slew Rate
f
T
= 4 π
kT
q
This shows that the slew rate will be only 0.314 V/µs for every MHz of bandwidth. The only way to increase slew rate is to increase the f
, and that is difficult because of process limitations.
T
Unfortunately, an amplifier with a bandwidth of 10 MHz can only slew at 3.1 V/µs, which is barely enough to provide a full power bandwidth of 50 kHz.
The AD829 is especially suited to a new form of compensation that allows for the enhancement of both the full power band­width and slew rate of the amplifier. The voltage gain from the inverting input pin to the compensation pin is large; therefore, if a capacitance is inserted between these pins, the amplifier’s bandwidth becomes a function of its feedback resistor and the capacitance. The slew rate of the amplifier is now a function of its internal bias (2I) and the compensation capacitance.
Since the closed-loop bandwidth is a function of R
and C
F
COMP
(Figure 10), it is independent of the amplifier closed-loop gain, as shown in Figure 12. To preserve stability, the time constant
and C
of R
F
65 MHz. For example, with C
needs to provide a bandwidth of less than
COMP
= 15 pF and RF = 1 k, the
COMP
small signal bandwidth of the AD829 is 10 MHz. Figure 11 shows that the slew rate is in excess of 60 V/µs. As shown in Figure 12, the closed-loop bandwidth is constant for gains of –1 to –4; this is a property of current feedback amplifiers.
R
F
C
COMP
0.1␮F +V
AD829
–V
S
S
V
OUT
R
0.1␮F 1k
L
50
COAX
CABLE
V
IN
*RECOMMENDED VALUE
OF C
<7pF
7pF
50
COMP
R1
C1*
FOR C
0pF 15pF
IN4148
1
C
SHOULD NEVER EXCEED
COMP
15pF FOR THIS CONNECTION
Figure 10. Inverting Amplifier Connection Using Current Feedback Compensation
REV. G
–11–
AD829
)
Figure 11. Large Signal Pulse Response of Inverting Amplifier Using Current Feedback Compensation,
= 15 pF, C1 = 15 pF, RF = 1 kΩ, R1 = 1 k
C
COMP
15
GAIN = –4
12
9
GAIN = –2
6
–3dB @ 9.6MHz
3
GAIN = –1
0
–3
–6
CLOSED-LOOP GAIN (dB)
–9
–12
–15
–3dB @ 10.2MHz
VIN = –30dBM
= 15V
V
S
R
= 1k
L
= 1k
R
F
C
= 15pF
COMP
C
= 15pF
1
100k 100M
1M 10M
FREQUENCY (Hz
–3dB @ 8.2MHz
Figure 12. Closed-Loop Gain vs. Frequency for the Circuit of Figure 9
Figure 13 is an oscilloscope photo of the pulse response of a unity gain inverter that has been configured to provide a small signal bandwidth of 53 MHz and a subsequent slew rate of 180 V/µs; resistor R
= 3 k and capacitor C
F
= 1 pF. Figure 14
COMP
shows the excellent pulse response as a unity gain inverter, this using component values of R
F
= 1 k and C
COMP
= 4 pF.
Figures 15 and 16 show the closed-loop frequency response of the AD829 for different closed-loop gains and different supply voltages.
If a noninverting amplifier configuration using current feedback compensation is needed, the circuit of Figure 17 is recommended. This circuit provides a slew rate twice that of the shunt com­pensated noninverting amplifier of Figure 18 at the expense of gain flatness. Nonetheless, this circuit delivers 95 MHz bandwidth with ±1 dB flatness into a back terminated cable, with a differ­ential gain error of only 0.01% and a differential phase error of only 0.015° at 4.43 MHz.
Figure 13. Large Signal Pulse Response of the Inverting Amplifier Using Current Feedback Compensation, C
= 1 pF, RF = 3 kΩ, R1 = 3 k
COMP
Figure 14. Small Signal Pulse Response of Inverting Amplifier Using Current Feedback Compensation,
= 4 pF, RF = 1 kΩ, R1 = 1 k
C
COMP
15
GAIN = –4
12
9
GAIN = –2
6
3
GAIN = –1
0
–3
VS = 15V
–6
CLOSED-LOOP GAIN (dB)
–9
–12
–15
= 1k
R
L
= 1k
R
F
= –30dBM
V
IN
110
C
= 2pF
COMP
C
= 3pF
COMP
C
= 4pF
COMP
FREQUENCY (MHz)
100
Figure 15. Closed-Loop Frequency Response for the Inverting Amplifier Using Current Feedback Compensation
REV. G–12–
AD829
)
–17
–20
–23
–26
–29
–32
–35
OUTPUT LEVEL (dB)
–38
–41
–44
–47
110
VIN = –20dBM
= 1k
R
L
= 1k
R
F
GAIN = –1
= 4pF
C
COMP
FREQUENCY (MHz
5V
15V
100
Figure 16. Closed-Loop Frequency Response vs. Supply for the Inverting Amplifier Using Current Feedback Compensation

A Low Error Video Line Driver

The buffer circuit shown in Figure 18 will drive a back-terminated 75 video line to standard video levels (1 V p-p) with 0.1 dB gain flatness to 30 MHz with only 0.04° and 0.02% differential phase and gain at the 4.43 MHz PAL color subcarrier frequency. This level of performance, which meets the requirements for high definition video displays and test equipment, is achieved using only 5 mA quiescent current.

A High Gain, Video Bandwidth, Three Op Amp In Amp

Figure 19 shows a three op amp instrumentation amplifier circuit that provides a gain of 100 at video bandwidths. At a circuit gain of 100, the small signal bandwidth equals 18 MHz into a FET probe. Small signal bandwidth equals 6.6 MHz with a 50 Ω load. The 0.1% settling time is 300 ns.
3pF
+V
IN
(G = 20)
A1
2pF to 8pF
SETTLING TIME
AC CMR ADJUST
+15V
0.1␮F
50
COAX
CABLE
V
IN
AD829
50
3pF
–15V
0.1␮F
C
COMP
50
2k
2k
50
COAX
CABLE
50
V
OUT
Figure 17. Noninverting Amplifier Connection Using Current Feedback Compensation
+15V
0.1␮F
75
V
IN
C
30pF
COMP
AD829
–15V
0.1␮F
75
75
300
300
COAX
CABLE
OPTIONAL 2pF to 7pF FLATNESS TRIM
75
V
OUT
Figure 18. A Video Line Driver with a Flatness over Frequency Adjustment
The input amplifiers operate at a gain of 20, while the output op amp runs at a gain of 5. In this circuit, the main bandwidth limitation is the gain/bandwidth product of the output amplifier. Extra care should be taken while breadboarding this circuit, since even a couple of extra picofarads of stray capacitance at the com­pensation pins of A1 and A2 will degrade circuit bandwidth.
210
+V
IN
REV. G
970
DC CMR ADJUST
50
A3
1k
AD848
4000
(
(G = 5)
R
G
+ 1(5
2k
+15V
COMM
–15V
10␮F
10␮F
INPUT
FREQUENCY
100 Hz 1 MHz 10 MHz
0.1␮F
0.1␮F
+V
–V
CMRR
64.6dB
44.7dB
23.9dB
S
S
1F
1F
0.1␮F
0.1␮F
PIN 7
EACH AMPLIFIER
PIN 4
AD829
2k
1pF
R
G
1pF
2k
200
200
3pF
AD829
A2
(G = 20)
3pF
CIRCUIT GAIN =
Figure 19. A High Gain, Video Bandwidth, Three Op Amp In Amp Circuit
–13–
AD829

OUTLINE DIMENSIONS

8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
0.100 (2.54)
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
BSC
5
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.015 (0.38) MIN
SEATING PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
85
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
BSC
6.20 (0.2440)
5.80 (0.2284)
41
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8 0
1.27 (0.0500)
0.40 (0.0157)
45
20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20A)
Dimensions shown in inches and (millimeters)
1
VIEW
0.150 (3.81) BSC
0.200 (5.08) REF
0.100 (2.54) REF
0.015 (0.38) MIN
3
4
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
8
BSC
9
45 TYP
0.075 (1.91)
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18) R TYP
0.075 (1.91) REF
0.055 (1.40)
0.045 (1.14)
REF
19
18
14
13
20
BOTTOM
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.342 (8.69) SQ
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.358 (9.09)
MAX
0.088 (2.24)
0.054 (1.37)
SQ
8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
PIN 1
0.200 (5.08) MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.055 (1.40)
MIN
0.100 (2.54) BSC
0.405 (10.29) MAX
MAX
85
1
4
0.070 (1.78)
0.030 (0.76)
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) MIN
SEATING PLANE
0.320 (8.13)
0.290 (7.37)
15
0
0.015 (0.38)
0.008 (0.20)
REV. G–14–
AD829

Revision History

Location Page
4/04—Data Sheet changed from REV. F to REV. G.
Added new Figure 1 and renumbered all figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated Figure 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/03—Data Sheet changed from REV. E to REV. F.
Renumbered Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes made to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes made to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes made to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes made to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REV. G
–15–
C00880–0–4/04(G)
–16–
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