ANALOG DEVICES AD8295 Service Manual

Precision Instrumentation Amplifier

V

www.BDTIC.com/ADI

FEATURES

Saves board space
Includes precision in-amp, 2 op amps, and

2 matched resistors
4 mm × 4 mm LFCSP
No heat slug for more routing room
Differential output fully specified
In-amp specifications

Gain set with 1 external resistor (gain range: 1 to 1000)

8 nV/√Hz @ 1 kHz, maximum input voltage noise

90 dB minimum CMRR (G = 1)

0.8 nA maximum input bias current

1.2 MHz, −3 dB bandwidth (G = 1)

2 V/μs slew rate
Wide power supply range: ±2.3 V to ±18 V
1 ppm/°C, 0.03% resistor matching

APPLICATIONS

Industrial process controls
Wheatstone bridges
Precision data acquisition systems
Medical instrumentation
Strain gages
Transducer interfaces
Differential output

GENERAL DESCRIPTION

The AD8295 contains all the components necessary for a
precision instrumentation amplifier front end in one small
4 mm × 4 mm package. It contains a high performance
instrumentation amplifier, two general-purpose operational
amplifiers, and two precisely matched 10 k resistors.

The AD8295 is designed to make PCB routing easy and
efficient. The AD8295 components are arranged in a logical
way so that typical application circuits have short routes and
few vias. Unlike most chip scale packages, the AD8295 does not
have an exposed metal pad on the back of the part, which frees
additional space for routing and vias. The AD8295 comes in a
4 mm × 4 mm LFCSP that requires half the board space of an
8-pin SOIC package.

with Signal Processing Amplifiers

AD8295

CONNECTION DIAGRAM

+

OUT

IA

REF

Military
Grade

A2 +IN A2 –IN

A2

A1

A1 OUT A1 R2

Figure 1.

13141516

R1
20kΩ

R2
20kΩ

8765

Low
Power

12

11

10

9

A2 OUT

A1 +IN

A1 R1

A1 –IN

07343-001

High Speed
PGA

S

AD8295

1

–IN

R

2

G

R

3

G

4

+IN

–V

S

Table 1. Instrumentation Amplifiers by Category

General
Purpose

Zero
Drift

AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
AD8295 AD82931

1

Rail-to-rail output.

The AD8295 includes a high performance, programmable gain
instrumentation amplifier. Gain is set from 1 to 1000 with a
single resistor. The low noise and excellent common-mode
rejection of the AD8295 enable the part to easily detect small
signals even in the presence of large common-mode interference.
For a similar instrumentation amplifier without the associated
signal conditioning circuitry, see the AD8221 or AD8222 data
sheet.

The AD8295 operates on both single and dual supplies and is
well suited for applications where ±10 V input voltages are
encountered. Performance is specified over the entire industrial
temperature range of −40°C to +85°C for all grades. The
AD8295 is operational from −40°C to +125°C; see the Ty pi ca l
Performance Characteristics section for expected operation up
to 125°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD8295

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Connection Diagram ....................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Instrumentation Amplifier Specifications, Single-Ended and

Differential Output Configurations ........................................... 3

Op Amp Specifications ................................................................ 5

Internal Resistor Network ........................................................... 6

Power and Temperature Specifications ..................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Characteristics .............................................................. 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

In-Amp .......................................................................................... 9

Op Amps ...................................................................................... 16



System .......................................................................................... 18

Theory of Operation ...................................................................... 19

Uncommitted Op Amps ............................................................ 19

Instrumentation Amplifier........................................................ 19

Layout .......................................................................................... 20

Input Protection ......................................................................... 21

Input Bias Current Return Path ............................................... 21

RF Interference ........................................................................... 21

Differential Output .................................................................... 22

Applications Information .............................................................. 23

Creating a Reference Voltage at Midscale ............................... 23

High Accuracy G = −1 Configuration with Low-Pass Filter .. 23

2-Pole Sallen-Key Filter ............................................................. 24

AC-Coupled Instrumentation Amplifier ................................ 24

Driving Differential ADCs ........................................................ 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8295

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SPECIFICATIONS

INSTRUMENTATION AMPLIFIER SPECIFICATIONS, SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS

VS = ±15 V, V

Table 2.

A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION

RATIO (CMRR)

CMRR, DC to 60 Hz 1 kΩ source imbalance

G = 1 80 90 dB
G = 10 100 110 dB
G = 100 120 130 dB
G = 1000 130 140 dB

CMRR at 8 kHz

G = 1 80 80 dB
G = 10 90 100 dB
G = 100 100 120 dB
G = 1000 110 120 dB

NOISE

Voltage Noise, 1 kHz

Input Voltage Noise, eNI V
Output Voltage Noise, eNO V

RTI f = 0.1 Hz to 10 Hz

G = 1 2 2 μV p-p
G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.25 0.25 μV p-p

Current Noise f = 1 kHz 40 40 fA/√Hz

f = 0.1 Hz to 10 Hz 6 6 pA p-p

VOLTAGE OFFSET RTI VOS = (V

Input Offset, V

Over Temperature TA = −40°C to +85°C 150 80 μV
Average TC 0.4 0.3 μV/°C

Output Offset, V

Over Temperature TA = −40°C to +85°C 0.8 0.5 mV
Average TC 9 5 μV/°C

Offset RTI vs. Supply (PSR) VS = ±2.3 V to ±18 V

G = 1 90 110 94 110 dB
G = 10 110 120 114 130 dB
G = 100 124 130 130 140 dB
G = 1000 130 140 140 150 dB

INPUT CURRENT

Input Bias Current 0.5 2.0 0.2 0.8 nA

Over Temperature TA = −40°C to +85°C 3.0 1.5 nA
Average TC 1 1 pA/°C

Input Offset Current 0.2 1 0.1 0.5 nA

Over Temperature TA = −40°C to +85°C 1.5 0.6 nA
Average TC 1 0.5 2 pA/°C

= 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. The differential configuration is shown in Figure 59.

REF

= −10 V to +10 V

V

CM

RTI noise =

2

+ (eNO/G)2)

√(e

NI

, V

, V

IN+

, V

IN+

V

OSI

V

OSO

= ±5 V to ±15 V 120 60 μV

S

= ±5 V to ±15 V 500 350 μV

S

= 0 V 8 8 nV/√Hz

IN−

REF

, V

= 0 V 75 75 nV/√Hz

IN−

REF

) + (V

OSI

OSO

/G)

Rev. 0 | Page 3 of 28

AD8295

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A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V
Gain Error V

G = 1 0.05 0.02 %
G = 10 0.3 0.1 %
G = 100 0.3 0.1 %
G = 1000 0.3 0.1 %

Gain Nonlinearity V

G = 1 3 10 1 5 ppm
G = 10 7 20 7 20 ppm
G = 100 7 20 7 20 ppm

Gain vs. Temperature

G = 1 5 1 ppm/°C
G > 1 −50 −50 ppm/°C

DYNAMIC RESPONSE (SINGLE-

ENDED CONFIGURATION)
Small Signal −3 dB Bandwidth

G = 1 1200 1200 kHz
G = 10 750 750 kHz
G = 100 140 140 kHz
G = 1000 15 15 kHz

Settling Time 0.01% 10 V step

G = 1 to 100 10 10 μs
G = 1000 80 80 μs

Settling Time 0.001% 10 V step

G = 1 to 100 13 13 μs
G = 1000 110 110 μs

Slew Rate

G = 1 1.5 2 1.5 2 V/μs
G = 5 to 1000 2 2.5 2 2.5 V/μs

DYNAMIC RESPONSE (DIFFERENTIAL

OUTPUT CONFIGURATION)
Small Signal −3 dB Bandwidth

G = 1 1200 1200 kHz
G = 10 1000 1000 kHz
G = 100 140 140 kHz
G = 1000 15 15 kHz

Settling Time 0.01% 10 V step

G = 1 to 100 10 10 μs
G = 1000 80 80 μs

Settling Time 0.001% 10 V step

G = 1 to 100 13 13 μs
G = 1000 110 110 μs

Slew Rate

G = 1 1.5 2 1.5 2 V/μs
G = 5 to 1000 2 2.5 2 2.5 V/μs

REFERENCE INPUT

RIN 20 20 kΩ
IIN V
Voltage Range −VS +VS −VS +VS V
Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V

± 10 V

OUT

= −10 V to +10 V

OUT

, V

, V

IN+

= 0 V 50 60 50 60 μA

IN−

REF

Rev. 0 | Page 4 of 28

AD8295

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A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit

INPUT

Input Impedance

Differential 100||2 100||2 GΩ||pF
Common Mode 100||2 100||2 GΩ||pF

Input Operating Voltage Range

Over Temperature TA = −40°C to +85°C −VS + 2.0 +VS − 1.2 −VS + 2.0 +VS − 1.2 V

Input Operating Voltage Range

Over Temperature TA = −40°C to +85°C −VS + 2.0 +VS − 1.2 −VS + 2.0 +VS − 1.2 V

OUTPUT RL = 10 kΩ

Output Swing VS = ±2.3 V to ±5 V −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V

Over Temperature TA = −40°C to +85°C −VS + 1.4 +VS − 1.3 −VS + 1.4 +VS − 1.3 V

Output Swing VS = ±5 V to ±18 V −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 V

Over Temperature TA = −40°C to +85°C −VS + 1.6 +VS − 1.5 −VS + 1.6 +VS − 1.5 V

Short-Circuit Current 18 18 mA

1

One input grounded; G = 1.

OP AMP SPECIFICATIONS

VS = ±15 V, TA = 25°C, RL = 2 kΩ, unless otherwise noted.

1

V

= ±2.3 V to ±5 V −VS + 1.9 +VS − 1.1 −VS + 1.9 +VS − 1.1 V

S

1

V

= ±5 V to ±18 V −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 V

S

Table 3.

A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage, VOS 40 20 μV

Average TC TA = −40°C to +85°C 4 2 μV/°C

Input Bias Current

T
T

1

10 8 nA

= −40°C 20 16 nA

A

= +85°C 10 8 nA

A

Input Offset Current 2 0.5 nA

Over Temperature TA = −40°C to +85°C 2 0.5 nA
Input Voltage Range −VS + 1.2 +VS − 1.2 −VS + 1.2 +VS − 1.2 V
Open-Loop Gain 100 125 116 125 dB
Common-Mode Rejection Ratio 100 100 dB
Power Supply Rejection Ratio 90 110 94 110 dB
Voltage Noise Density 40 40 nV/√Hz
Voltage Noise f = 0.1 Hz to 10 Hz 2.2 2.2 μV p-p

DYNAMIC PERFORMANCE

Gain Bandwidth Product 1 1 MHz
Slew Rate 2.6 2.6 V/μs

OUTPUT CHARACTERISTICS

Output Swing VS = ±2.3 V to ±5 V −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V

Over Temperature TA = −40°C to +85°C −VS + 1.4 +VS − 1.3 −VS + 1.4 +VS − 1.3 V
Output Swing VS = ±5 V to ±18 V −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 V

Over Temperature TA = −40°C to +85°C −VS + 1.6 +VS − 1.5 −VS + 1.6 +VS − 1.5 V
Short-Circuit Current 18 18 mA

1

Op amp uses an npn input stage, so input bias current always flows into the inputs.

Rev. 0 | Page 5 of 28

AD8295

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INTERNAL RESISTOR NETWORK

When used with internal Op Amp A1, TA = 25°C, unless otherwise noted. Use in external op amp feedback loops is not recommended.

Table 4.

Parameter Test Conditions Min Typ Max Min Typ Max Unit

Nominal Resistor Value 20 20 kΩ
Resistor Matching 0.1 0.03 %
Matching Temperature Coefficient TA = −40°C to +85°C 5 1 ppm/°C
Absolute Resistor Accuracy 0.2 0.1 %
Absolute Temperature Coefficient TA = −40°C to +85°C −50 −50 ppm/°C

A Grade B Grade

POWER AND TEMPERATURE SPECIFICATIONS

VS = ±15 V, V

Table 5.

A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

Operating Range ±2.3 ±18 ±2.3 ±18 V
Quiescent Current In-amp + two op amps 2 2.3 2 2.3 mA

Over Temperature TA = −40°C to +85°C 2.5 2.5 mA

TEMPERATURE RANGE

Specified Performance −40 +85 −40 +85 °C
Operational Performance

1

See the section for expected operation from 85°C to 125°C. Typical Performance Characteristics

= 0 V, TA = 25°C, unless otherwise noted.

REF

1

−40 +125 −40 +125 °C

Rev. 0 | Page 6 of 28

AD8295

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Input Voltage

Common-Mode ±VS
Differential ±VS

Storage Temperature Range −65°C to +130°C
Operating Temperature Range1 −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 130°C
ESD (Human Body Model) 2000 V
ESD (Charge Device Model) 500 V
ESD (Machine Model) 200 V

1

Temperature range for specified performance is −40°C to +85°C. See the

Typical Performance Characteristics section for expected operation from
85°C to 125°C.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

Specifications are provided for a device in free air.

Table 7.

Package θJA Unit

16-Lead LFCSP_VQ 86 °C/W

ESD CAUTION

Rev. 0 | Page 7 of 28

AD8295

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S

A2 –IN

OUT

+V

A2 +IN

14

13

15

16

PIN 1
INDICATO R

1–IN

2R

G

AD8295

3R

G

TOP VIEW

4+IN

(Not to Scale)

5

6

S

–V

REF

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN In-Amp Negative Input.
2, 3 RG In-Amp Gain-Setting Resistor Terminals.
4 +IN In-Amp Positive Input.
5 −VS Negative Supply.
6 REF In-Amp Reference Terminal. Drive with a low impedance source. Output is referred to this pin.
7 A1 OUT Op Amp A1 Output.
8 A1 R2 Resistor R2 Terminal. Connected internally to Op Amp A1 inverting input.
9 A1 −IN Op Amp A1 Inverting Input. Midpoint of resistor divider.
10 A1 R1 Resistor R1 Terminal. Connected internally to Op Amp A1 inverting input.
11 A1 +IN Op Amp A1 Noninverting Input.
12 A2 OUT Op Amp A2 Output.
13 A2 −IN Op Amp A2 Inverting Input.
14 A2 +IN Op Amp A2 Noninverting Input.
15 OUT In-Amp Output.
16 +VS Positive Supply.

12 A2 OUT

11 A1 +IN

10 A1 R1

9 A1 –I N

8

7

1 R2
A

A1 OUT

07343-017

Rev. 0 | Page 8 of 28

AD8295

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

IN-AMP

VS = ±15 V, REF = 0 V, TA = 25°C, RL = 10 kΩ, unless otherwise noted.

800

600

HITS

400

200

0

–100 –50 0 50 100

CMRR (µV/V)

Figure 3. Typical Distribution for CMRR, G = 1

800

700

600

500

400

HITS

300

200

100

0

–100 –50 0 50 100

V

(µV)

OSI

Figure 4. Typical Distribution of Input Offset Voltage

700

600

800

600

HITS

400

200

0

–1.0 –0.5 0 0.5 1.0

07343-057

INPUT OFF SET CURRENT (n A)

07343-060

Figure 6. Typical Distribution of Input Offset Current

5

4

3

2

1

0

–1

–2

INPUT COMMON-MODE VOLTAGE (V)

–3

–4

–5 –4 –3 –2 –1 0 1 2 3 4 5

07343-058

OUTPUT VOLTAGE (V)

G = 1
V

= ±2.5V, ±5V

S

07343-045

Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1,

V

= ±2.5 V, ±5 V, REF = 0 V

S

15

10

G = 1
V

S

= ±15V

500

400

HITS

300

200

100

0

–2 –1 0 1 2

INPUT BIAS CURRENT (nA)

Figure 5. Typical Distribution of Input Bias Current

07343-059

5

0

–5

–10

INPUT COMMON-MODE VOLTAGE (V)

–15

–15 –10 –5 0 5 10 15

Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1,

Rev. 0 | Page 9 of 28

OUTPUT VOLTAGE (V)

= ±15 V, REF = 0 V

V

S

07343-046

AD8295

www.BDTIC.com/ADI

5

4

3

2

1

0

–1

–2

INPUT COMMON-MODE VOLTAGE (V)

–3

–4

–5–4–3–2–1012345

OUTPUT VOLTAGE (V)

G = 100
V

= ±2.5V, ±5V

S

Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100,

V

= ±2.5 V, ±5 V, REF = 0 V

S

15

10

5

0

–5

–10

INPUT COMMON-MODE VOL TAGE (V)

–15

–15 –10 –5 0 5 10 15

OUTPUT VOLTAGE (V)

G = 100
V

= ±15V

S

Figure 10. Input Common-Mode Range vs. Output Voltage, G = 100,

= ±15 V, REF = 0 V

V

S

0

INPUT BIAS CURRENT (nA)

–0.050

–0.100

–0.150

–0.200

±5V

–0.250

–0.300

±15V

07343-047

07343-048

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

CHANGE IN INPUT OFFSET VOLTAGE (µV)

0

024681

WARM-UP TIME (Min)

Figure 12. Change in Input Offset Voltage vs. Warm-Up Time

5

4

3

NEGATIVE BIAS

2

1

0

–1

CURRENT (nA)

–2

–3

–4

–5

–40 –20 0 20 40 60 80 100 120 140

POSITIVE BIAS

OFFSET

TEMPERATURE ( °C)

Figure 13. Input Bias Current and Offset Current vs. Temperature

180

160

GAIN = 1000

140

GAIN = 100

GAIN = 10

120

GAIN = 1

100

80

POSITIVE PSRR (dB)

60

40

0

07343-062

07343-063

–0.350

–15 –10 –5 0 5 10 15

COMMON-MO DE VOLTAGE (V)

Figure 11. Input Bias Current vs. Common-Mode Voltage

07343-061

20

0.1 1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 14. Positive PSRR vs. Frequency, RTI, G = 1 to 1000

Rev. 0 | Page 10 of 28

07343-049

AD8295

www.BDTIC.com/ADI

180

160

GAIN = 1000

140

GAIN = 100

GAIN = 10

120

GAIN = 1

100

80

NEGATIVE PSRR (dB)

60

40

20

0.1 1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 15. Negative PSRR vs. Frequency, RTI, G = 1 to 1000

200

150

100

50

0

–50

GAIN ERROR (ppm)

–100

–150

–200

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (° C)

Figure 16. Gain Error vs. Temperature, G = 1

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

10

GAIN (dB)

GAIN = 1

0

–10

–20

–30

–40

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency

07343-050

07343-064

07343-044

180

170

160

GAIN = 1000

150

GAIN = 100

140

130

GAIN = 10

120

110

GAIN = 1

100

CMRR (dB)

90

80

70

60

50

40

0.1 1 10 100 1 k 10k 100k

FREQUENCY (Hz)

Figure 18. CMRR vs. Frequency, RTI

180

170

160

GAIN = 1000

150

140

GAIN = 100

130

120

GAIN = 10

110

100

GAIN = 1

CMRR (dB)

90

80

70

60

50

40

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 19. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

+

–0

V

S

–0.4

–0.8

–1.2

–1.6

–2.0

+2.0

+1.6

+1.2

INPUT VOLTAGE LIMIT (V)

+0.8

REFERRED TO SUPPLY VOLTAGES

+0.4

–VS+0

2 6 10 14 18

FROM +V

FROM –V

SUPPLY VOLTAGE (V)

Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1

07343-051

07343-052

07343-020

Rev. 0 | Page 11 of 28

AD8295

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+

V

–0

S

–0.4

–0.8

–1.2

–1.6

+1.6

+1.2

OUTPUT VOLT AGE SWING (V)

+0.8

REFERRED TO SUPPLY VOLTAGES

+0.4

+0

–V

S

2 6 10 14 18

R

= 10kΩ

L

RL = 10kΩ

SUPPLY VOLTAGE (V)

RL = 2kΩ

R

= 2kΩ

L

Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1

30

07343-021

4

3

2

1

10kΩ LOAD

0

–1

–2

NONLINEARIT Y (1ppm/DI V)

–3

–4

–10 –8 –6 –4 –2 0 2 4 6 8 10

600Ω LOAD

2kΩ LOAD

V

OUT

(V)

Figure 24. Gain Nonlinearity, G = 1

40

30

07343-024

20

10

OUTPUT VOLTAGE SWING (V p-p)

0

1 10 100 1k 10k

LOAD RESIST ANCE (Ω)

Figure 22. Output Voltage Swing vs. Load Resistance

+VS–0

–1

–2

–3

+3

+2

OUTPUT VOLTAGE SWING (V)

REFERRED TO S UPPLY VOL TAGES

+1

+0

–V

S

011110987654321

OUTPUT CURRENT (mA)

SOURCING

SINKING

Figure 23. Output Voltage Swing vs. Output Current, G = 1

20

10

0

–10

–20

NONLINEARIT Y (10ppm/DI V)

–30

–40

–10–8–6–4–20246810

07343-022

Figure 25. Gain Nonlinearity, G = 100

1k

GAIN = 1

100

GAIN = 10

GAIN = 100

10

GAIN = 1000

VOLTAGE NOISE RTI (nV/ Hz)

1

2

07343-023

110

100 1k 10k 100 k

FREQUENCY (Hz)

Figure 26. Voltage Noise Spectral Density vs. Frequency, G = 1 to 1000

2kΩ LOAD

V

(V)

OUT

600Ω LOAD

GAIN = 1000
BW LIMIT

10kΩ LOAD

07343-025

07343-027

Rev. 0 | Page 12 of 28

AD8295

www.BDTIC.com/ADI

2µV/DIV 1s/ DIV

Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

0.1µV/DI V 1s/DIV

Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000

1k

07343-028

5pA/DIV 1s/DIV

07343-031

Figure 30. 0.1 Hz to 10 Hz Current Noise

30

GAIN = 10, 100, 1000

GAIN = 1

25

20

15

10

MAX OUTPUT VOLTAGE (V p-p)

5

07343-029

0

1k 10k 100k 1M

FREQUENCY (Hz)

07343-032

Figure 31. Large Signal Frequency Response

5V/DIV

100

7.4µs TO 0. 01%

8.3µs TO 0.001%

CURRENT NOISE (fA/ Hz)

10

1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 29. Current Noise Spectral Density vs. Frequency

07343-030

Figure 32. Large Signal Pulse Response and Settling Time, G = 1

0.002%/DIV

Rev. 0 | Page 13 of 28

20µs/DIV

07343-033

AD8295

www.BDTIC.com/ADI

5V/DIV

4.8µs TO 0.01%

6.6µs TO 0.001%

0.002%/DIV

20µs/DIV

07343-034

Figure 33. Large Signal Pulse Response and Settling Time, G = 10

5V/DIV

9.2µs TO 0. 01%

16.2µs TO 0.001%

0.002%/DIV

20µs/DIV

07343-035

Figure 34. Large Signal Pulse Response and Settling Time, G = 100

5V/DIV

Figure 36. Small Signal Pulse Response, G = 1, R

Figure 37. Small Signal Pulse Response, G = 10, R

4µs/DIV20mV/DIV

= 2 kΩ, CL = 100 pF

L

4µs/DIV20mV/DIV

= 2 kΩ, CL = 100 pF

L

07343-037

07343-038

83µs TO 0.01%

112µs TO 0. 001%

0.002%/DIV

200µs/DIV

Figure 35. Large Signal Pulse Response and Settling Time, G = 1000

07343-036

Rev. 0 | Page 14 of 28

Figure 38. Small Signal Pulse Response, G = 100, R

10µs/DIV20mV/DIV

= 2 kΩ, CL = 100 pF

L

07343-039

AD8295

www.BDTIC.com/ADI

1k

100

Figure 39. Small Signal Pulse Response, G = 1000, R

15

10

SETTLED TO 0.001%

5

SETTLING TIME (µs)

0

0 5 10 15 20

SETTLED TO 0.01%

OUTPUT VOLTAGE STEP SIZE (V)

Figure 40. Settling Time vs. Step Size, G = 1

100µs/DIV20mV/DIV

= 2 kΩ, CL = 100 pF

L

07343-040

10

SETTLING TIME (µs)

1

1 10 100

SETTL ED TO 0. 001%

SETTLE D TO 0.01%

GAIN

1k

07343-042

Figure 41. Settling Time vs. Gain for a 10 V Step

07343-041

Rev. 0 | Page 15 of 28

AD8295

www.BDTIC.com/ADI

OP AMPS

VS = ±15 V, TA = 25°C, RL = 10 kΩ, Op Amp A1 and Op Amp A2, unless otherwise noted.

80

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

GAIN (dB)

20

10

GAIN = 1

0

–10

–20

0.1 1 10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 42. Closed-Loop Gain vs. Frequency, G = 1 to 1000

140

120

100

80

PSRR (dB)

60

40

20

0.1 1 10 100 1k 10k 100k 1M

+PSRR

–PSRR

FREQUENCY (Hz)

Figure 43. PSRR vs. Frequency

1k

100

NOISE (nV/ Hz)

10

1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 44. Voltage Noise Density vs. Frequency

07343-065

07343-066

07343-067

8

6

4

2

0

–2

VOLTAGE NOISE (µV)

–4

–6

–8

012345678910

TIME (S ec)

Figure 45. 0.1 Hz to 10 Hz Noise

14

12

10

8

6

4

2

CURRENT (nA)

0

–2

–4

–6

–40

–30

+BIAS CURRENT

OFFSET CURRENT

0

–20

–10

–BIAS CURRENT

102030405060708090

TEMPERATURE ( °C)

100

110

120

130

Figure 46. Input Bias Current and Input Offset Current vs. Temperature

40

30

20

10

0

–10

–20

GAIN ERROR (ppm)

–30

–40

–50

–60

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (° C)

Figure 47. Gain Drift Using On-Chip Resistor Divider, G = 1

07343-068

07343-069

07343-070

Rev. 0 | Page 16 of 28

AD8295

www.BDTIC.com/ADI

40

30

20

10

0

–10

–20

GAIN ERROR (ppm)

–30

–40

–50

–60

–40 –20 0 20 40 60 80 100 120 140

Figure 48. Gain Drift Using On-Chip Resistor Divider, G = 2

TEMPERATURE (° C)

07343-071

Rev. 0 | Page 17 of 28

AD8295

www.BDTIC.com/ADI

SYSTEM

VS = ±15 V, V

80

60

40

20

GAIN (dB)

0

–20

= 0 V, TA = 25°C, unless otherwise noted.

REF

GAIN = 1000

GAIN = 100

GAIN = 10

GAIN = 1

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

+125°C

+85°C

+25°C

–40°C

–40

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 49. Differential Output Configuration, Gain vs. Frequency

80

70

60

50

40

30

20

COMMON-MO DE OUTPUT ( dB)

10

0

1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 50. Differential Output Configuration,

Common-Mode Output vs. Frequency

0

2 4 6 8 10 12 14 16

07343-054

SUPPLY VOLTAGE (±V)

07343-072

Figure 51. Supply Current vs. Supply Voltage

07343-055

Rev. 0 | Page 18 of 28

AD8295

www.BDTIC.com/ADI

THEORY OF OPERATION

As shown in Figure 52, the AD8295 contains a precision
instrumentation amplifier, two uncommitted op amps, and a
precision resistor array. These components allow many common
applications to be wired using simple pin-strapping, directly at
the IC. This not only saves printed circuit board (PCB) space
but also improves circuit performance because both temperature
drift and resistor tolerance errors are reduced.

OUT

REF

A2 +IN A2 –IN

A1 OUT A1 R2

13141516

A2

R1

A1

20kΩ

R2
20kΩ

8765

12

11

10

9

A2 OUT

A1 +IN

A1 R1

A1 –IN

07343-004

+V

S

AD8295

1

–IN

R

2

G

IA

R

3

G

4

+IN

–V

S

Figure 52. Functional Block Diagram

UNCOMMITTED OP AMPS

The AD8295 has two uncommitted op amps that can be used
independently. These op amps allow simple pin-strapping for
many common applications circuits.

Op Amp A1 has its inverting input connected to a precision 2:1
voltage divider resistor network. Because this network is internal
to the IC, these resistors are closely matched and also track each
other, with temperature variations. Op Amp A1 and the associated
resistor network can be used to create either a noninverting gain
stage of 2 or an inverting gain stage of −1 with excellent gain
accuracy and gain drift.

Op Amp A2 is a more conventional op amp, with standard
inverting and noninverting inputs and an output.

INSTRUMENTATION AMPLIFIER

Gain Selection

The transfer function of the AD8295 is

= G × (V

V

OUT

where placing a resistor across the RG terminals sets the gain of
the AD8295 according to the following equation:

G

1 +=

− V

IN−

) + V

REF

IN+

k4.49

GR

Resistor values can be obtained by referring to Tab l e 9 or by
using the following gain equation:

k4.49

R

G

1

−=G

Table 9. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG Calculated Gain

49.9 kΩ 1.990

12.4 kΩ 4.984

5.49 kΩ 9.998

2.61 kΩ 19.93

1.00 kΩ 50.40
499 Ω 100
249 Ω 199.4
100 Ω 495

49.9 Ω 991

The AD8295 defaults to G = 1 when no gain resistor is used.
Gain accuracy is a combination of both the R

accuracy and

G

the accuracy listed in the specifications in Tabl e 2, including
accuracy over temperature. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.

Common-Mode Input Voltage Range

The AD8295 in-amp architecture applies gain internally and
then removes the common-mode voltage. Therefore, internal
nodes in the AD8295 experience a combination of both the
gained signal and the common-mode signal. This combined
signal can be limited by the voltage supplies even when the
individual input and output signals are not. Figure 7 through
Figure 10 show the allowable common-mode input voltage
ranges for various output voltages and supply voltages.

If Figure 7 through Figure 10 indicate that internal voltage
limiting may be an issue, the common-mode range can be
improved by lowering the gain in the instrumentation amplifier
by one half and applying a second G = 2 stage. Figure 53 shows
how to do this amplification with the internal circuitry of the
AD8295, requiring no additional external components.

A1 TOTAL GAIN = IN-AMP × 2

+IN

+

R

IN-AMP

G

–

–IN

Figure 53. Applying Gain in a Later Stage Allows Wider Input

REF

+

A1

–

Common-Mode Range

R2
20kΩ

R1
20kΩ

A1 OUT

07343-019

Rev. 0 | Page 19 of 28

AD8295

www.BDTIC.com/ADI

Reference Terminal

The output voltage of the AD8295 instrumentation amplifier
is developed with respect to the potential on the reference
terminal. This is useful when the output signal needs to be
offset to a precise dc level.

The reference pin input can be driven slightly beyond the rails.
The REF pin is protected with ESD diodes, and the REF voltage
should not exceed either +V

or −VS by more than 0.3 V.

S

For best performance, the source impedance to the REF terminal
should be kept below 1 Ω. Additional impedance at the REF
terminal can significantly degrade the CMRR of the amplifier.
When the reference source has significant output impedance
(for example, a resistive voltage divider), buffer the signal before
driving the REF pin. Internal Op Amp A1 or A2 can be used for
this purpose, as shown in Figure 54.

INCORRECT CORRECT

AD8295

+V

S

R

A

R

B

REF

Figure 54. Driving the Reference Pin

+V

S

R

A

+

R

C

B

AD8295

REF

OP AMP
BUFFER

Noise at the reference feeds directly to the output. Therefore, in
Figure 54, Capacitor C is added to filter out any high frequency
noise on the positive power supply line. For very clean supplies,
the capacitor may not be needed. The filter frequency is a trade­off between noise rejection and start-up time, and is given by
the following equation:

f

LOWPASS

1

C

π=2

RR

B

A

RR

+

B

A

LAYOUT

The AD8295 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the board
layout. The AD8295 pins are arranged in a logical manner to
aid in this task. Unlike most LFCSP packages, the AD8295
package was designed without the thermal pad to allow routes
and vias directly beneath the chip.

Careful board layout maximizes system performance. Traces
from the gain setting resistor to the R
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the local ground of the AD8295 or to a
voltage that is referenced to the local ground of the AD8295.

pins should be kept as

G

07343-010

Common-Mode Rejection over Frequency

The AD8295 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances such
as line noise and its associated harmonics. The AD8295 pinout
and hidden paddle package were designed so that the board
designer can take full advantage of this performance with a
well-implemented layout.

Poor layout can cause some of the common-mode signal to be
converted to a differential signal before it reaches the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resistance
in the input path (for example, for input protection) should be
placed close to the in-amp inputs to minimize their interaction
with parasitic capacitance from the PCB traces.

Parasitic capacitance at the gain setting pins can also affect
CMRR over frequency. The traces to the R

resistor should be

G

kept as short as possible. If the board design has a component at
the gain setting pins (for example, a switch or jumper), the part
should be chosen so that the parasitic capacitance is as small as
possible.

Unused Op Amps

When not in use, the internal op amps should be connected
in a unity-gain configuration, with the noninverting input
connected to a bias point in the input range of the op amp.
These connections ensure that the AD8295 op amp uses
minimum power and does not disturb the internal power
supplies of the AD8295. These connections are shown as
dotted lines in several of the applications figures.

Reference

The output voltage of the instrumentation amplifier section of
the AD8295 is developed with respect to the potential on the
reference terminal (REF); care should be taken to tie the REF
pin to the appropriate local ground.

Rev. 0 | Page 20 of 28

AD8295

www.BDTIC.com/ADI

Power Supplies

A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect perfor­mance. See the PSRR performance curves in Figure 14 and
Figure 15 for more information.

A 0.1 µF capacitor should be placed as close as possible to each
supply pin. An additional capacitor, a 10 µF tantalum for the
lower frequencies, can be used farther away from the IC. In
most cases, the 10 µF bypass capacitor can be shared by other
integrated circuits on the same PCB.

+V

S

REF

10µF

LOAD

V

OUT

07343-005

0.1µF

+IN

AD8295

R

G

IN-AMP

–IN

0.1µF 10µF

–V

S

Figure 55. Supply Decoupling, REF, and Output Referred to Local Ground

INPUT PROTECTION

All terminals of the AD8295 are protected against ESD
by diodes at the inputs. If voltages beyond the supplies are
anticipated, resistors should be placed in series with the inputs
to limit the current. Resistors should be chosen so that current
does not exceed 6 mA into the internal ESD diodes in the over­load condition. These resistors can be the same as those used
for RFI protection. (See the RF Interference section for more
information.)

For applications where the AD8295 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps, such as BAV199Ls,
FJH1100s, or SP720s can be used.

INPUT BIAS CURRENT RETURN PATH

The input bias currents of the AD8295 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 56. Otherwise, the input currents charge up the input
capacitance until the in-amp is turned off or saturated.

INCORRECT

+V

S

AD8295

IN-AMP

–V

S

TRANSFORMER

+V

S

AD8295

IN-AMP

–V

S

THERMOCOUPL E

+V

S

C

AD8295

C

CAPACITIVELY COUPLED

IN-AMP

–V

S

REF

REF

REF

f

HIGH- PASS

10MΩ

1

=

2πRC

CAPACITIVEL Y COUPLED

CORRECT

TRANSFORMER

THERMOCOUPL E

C

R

C

R

+V

S

AD8295

IN-AMP

–V

S

+V

S

AD8295

IN-AMP

–V

S

+V

S

AD8295

IN-AMP

–V

S

REF

REF

REF

Figure 56. Creating an Input Bias Current Return Path

RF INTERFERENCE

RF interference is often a problem when amplifiers are used in
applications where there are strong RF signals. The precision
circuits in the AD8295 can rectify the RF signals so that they
appear as a dc offset voltage error. To avoid this rectification,
place a low-pass filter before the input. Figure 57 shows such a
network in front of the instrumentation amplifier. The filter
limits both the differential and common-mode bandwidth, as
shown in the following equations:

where C

FILTER

FILTER

≥ 10CC.

D

)(

Difff

CMf

)( =

=

1

D

1

RC

π2

C

)2(π2

CCR

+

C

07343-006

Rev. 0 | Page 21 of 28

AD8295

www.BDTIC.com/ADI

1nF

C

C

R

4.02kΩ

R

4.02kΩ

C

D

C

C

10nF

1nF

R

0.1µF

G

0.1µF

+IN

–IN

+V

S

AD8295

IN-AMP

–V

S

REF

10µF

10µF

V

OUT

07343-007

Figure 57. RFI Suppression

Lower cutoff frequencies improve RFI robustness. Accuracy of

capacitors is important, because any mismatch between

the C

C

the R × C
input degrades the CMRR of the AD8295. Keeping C
10 times larger than C

at the positive input and the R × CC at the negative

C

at least

D

is recommended.

C

DIFFERENTIAL OUTPUT

The AD8295 can be pin-strapped to provide a differential
output; the simplified schematic is shown in Figure 58 and the
full pin connection is shown in Figure 59. This configuration
uses the instrumentation amplifier to maintain the differential
voltage, while the op amp maintains the common-mode voltage.
Because the in-amp precisely controls the output relative to its
reference pin, this circuit has the same excellent dc performance
as the single-ended output configuration. The transfer function
for the differential and common-mode outputs are as follows:

DIFF_OUT

CM_OUT

= V

= (V

V

V

where:

G

1 +=

This configuration is fully specified (see Ta bl e 2, Figure 49, and
Figure 50). DC performance is the same as for the single-ended
configuration; ac performance is slightly different.

OUT+

OUT+

k4.49

GR

− V

+ V

OUT−

OUT−

= G × (V

)/2 = V

REF

IN+

− V

IN−

)

+V

S

0.1µF

+V

S

–IN

AD8295

R

R

+IN

1

G

2

G

3

4

–V

S

0.1µF

–V

S

–INPUT

+INPUT

NOTES

1. CONNECT AS SHOWN IF A2 I S NOT BEI NG USED.

OUT

IA

A1

REF

A2
+IN

13141516

A2

R1
20kΩ

R2
20kΩ

8765

A1
OUTA1R2

A2
–IN

A2
OUT

12

A1
+IN

V

REF

11

INPUT

A1
R1

10

9

A1
–IN

+OUT

–OUT

07343-008

Figure 59. Minimum Component Connections for Differential Output

An alternative differential output configuration, which also
requires no external components, is shown in Figure 60. Unlike
the previous circuit, this configuration uses an inverting op amp
configuration to double the gain from the instrumentation
amplifier. Because this configuration requires less gain from
the instrumentation amplifier, it can have a wider frequency
response and a wider input common-mode range vs. output
voltage. However, because it does not take advantage of feed­back at the reference pin of the instrumentation amplifier, dc
performance includes the errors from the op amp and the
resistor network. When using the internal precision components
of the AD8295, these errors have a minimal effect on overall
accuracy. This configuration is not specified in this data sheet.

R2

REF

R1

20kΩ

20kΩ

–

A1

+

+IN

–IN

+

R

IN-AMP

G

–

INPUT

V

REF

Figure 60. Alternative Differential Output Configuration

+OUT

–OUT

07343-043

+IN

+

–IN

IN-AMP

–

REF

20kΩ

20kΩ

V

–

A1

REF

INPUT

+

+OUT

–OUT

07343-018

Figure 58. Differential Output Using an Op Amp

Rev. 0 | Page 22 of 28

AD8295

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

CREATING A REFERENCE VOLTAGE AT MIDSCALE HIGH ACCURACY G = −1 CONFIGURATION WITH

A reference voltage other than ground is often useful, for
example, when driving a single-supply ADC. Creating a
reference voltage derived from a voltage divider is straight­forward with the AD8295 (see Figure 61). In this configuration,
Op Amp A2 is used to provide a buffered V

/2 reference for the

S

in-amp section. This configuration is very similar to the one
described in the Reference Terminal section.

Note that the internal resistors of Op Amp A1 are not used
to provide V

/2. Instead, external 1% (or better) resistors are

S

used. Because the negative input of Op Amp A1 is permanently
connected to the junction of internal resistors R1 and R2,
Op Amp A1 operates as a low voltage clamp, preventing the
resistor string from providing a convenient V

/2 voltage.

S

Noise at the reference feeds directly to the output, so if the
reference voltage is derived from a noisy source, filtering is
required. In Figure 61, Capacitor C1 has been added to filter
out high frequency noise on the positive power supply line.
The 10 uF capacitor and the 100 k resistors shown in Figure 61
roll off noise starting at 0.3 Hz. The filter frequency is a trade­off between noise rejection and start-up time.

+V

S

100kΩ

A2

–IN

C1
10µF

A2
OUT

12

A1
+IN

11

10

9

A1
R1

A1
–IN

VS/2
BUFFERED

07343-009

A2

+IN

A1

7

A1

OUTA1R2

100kΩ

131416

A2

R1
20kΩ

R2
20kΩ

865

–INPUT

+INPUT

–IN

R

R

+IN

+V

G

G

+V

S

AD8295

1

2

3

4

S

0.1µF

IA

REF

OUTPUT

15

OUT

Figure 61. Single-Supply Connection with Buffered Reference

LOW-PASS FILTER

The circuit in Figure 62 uses Op Amp A1 and the resistor string
to provide a precise G = −1 configuration. Because no external
resistors are used to set the gain, gain accuracy and gain drift
depend only on the internally matched resistors, yielding excel­lent performance.

Adding a capacitor across Resistor R2 is a simple way to provide
a single-pole low-pass filter that rolls off at 20 dB per decade.
This capacitor is shown as C1 in Figure 62.

A2

+V

S

–IN

AD8295

R

R

+IN

f

LOW PASS

1

2

G

3

G

4

–V

S

= 1/(2π 20kΩ C1).

IA

INPUT

V

REF

–INPUT

+INPUT

NOTES

1.

Figure 62. Single-Pole Output Filter Using a Single External Capacitor

If the connections to Pin 10 and Pin 11 in Figure 62 are changed
so that Pin 10 connects to ground and Pin 11 connects to the
in-amp output, the result is a G = 2 circuit, also with excellent
gain accuracy and drift. In the G = 2 configuration, Capacitor C1
lowers the gain from 2 to 1 at higher frequencies.

OUT

A2
+IN

A2

A1

A1
OUTA1R2

13141516

R1
20kΩ

R2
20kΩ

8765

–IN

V

REF

BUFFERED

A2
OUT

12

V

INPUT

11

REF

A1
R1

10

A1
–IN

9

C1

LP FILTERED
OUTPUT

07343-011

Rev. 0 | Page 23 of 28

AD8295

www.BDTIC.com/ADI

2-POLE SALLEN-KEY FILTER

Figure 63 shows the in-amp output section of the AD8295 being
low-pass filtered using a 2-pole Sallen-Key filter. The filter section
consists of Op Amp A2, External Resistors R1 and R2, as well as
Capacitors C1 and C2. Resistor R3 compensates for input offset
current errors and is equal to the parallel combination of R1 and
R2. The ratio of capacitance between C1 and C2 sets the filter
quality factor, Q. For most applications, a filter Q of 0.5 to 0.7
provides a good trade-off between performance and stability.
High Q, non-polarized capacitors, such as NPO ceramic, should
be used. The exact pole frequencies are dependent on the
tolerance of the resistors and capacitors used.

The design equations for a Sallen-Key filter can be greatly
simplified if the resistors and capacitors are made equal.
When C1 = C2 and R1 = R2, Q is 0.5 and the design equation
simplifies to

f = 1/(2πRC)

where R is in ohms and C is in farads.

For example, with R1 = R2 = 10 k, and C1 = C2 = 2.2 nF,

f = 7.2 kHz

When C1 is not equal to C2 and R1 is not equal to R2, the
values of Q and the cutoff frequency are calculated as follows:

2121

Q+=

fπ=

2

–IN

–INPUT

R

G

R

G

+IN

+INPUT

CCRR

)21(2

RRC

1

C2 C1 R2 R1

+V

S

0.1µF

+V

S

AD8295

1

2

3

4

–V

S

0.1µF

–V

S

Figure 63. 2-Pole Sallen-Key Filter

R2

R1

OUT

IA

A1

REF

C2

A2
+IN

13141516

A2

R1
20kΩ

R2
20kΩ

8765

A1
OUTA1R2

A2
–IN

C1

R3

LP FILTERED

A2

OUTPUT

OUT

12

A1
+IN

11

A1

10

R1

A1
–IN

9

07343-012

AC-COUPLED INSTRUMENTATION AMPLIFIER

The circuit in Figure 64 provides a one-pole high-pass filter,
using only one external capacitor.

At low frequencies, Capacitor C1 has a high impedance, thus
operating Op Amp A1 at high gain (G = X
its high gain, Op Amp A1 is able to drive the in-amp reference
pin until it forces the output of the in-amp to 0 V. Therefore, no
signal appears at the circuit output.

At higher frequencies, the gain of Op Amp A1 drops and the
op amp is no longer able to maintain the in-amp output at 0 V.
Therefore, at frequencies above the RC filter bandwidth, the
in-amp operates in a normal manner, and the signal appears at
the output.

The 3 dB corner frequency is set by Internal Resistor R1 and
External Capacitor C1 as follows:

f = 1/((2π × 20 k) × C1)

The precision of R1 (better than 0.2%) means that the filter
bandwidth depends mainly on the tolerance of Capacitor C1.

At low frequencies, Op Amp A1 drives the appropriate voltage
on the reference pin to null out the original signal. Voltage
supplies should be chosen so that Op Amp A1 has enough
output headroom to produce the nulling voltage.

–INPUT

+INPUT

–IN

R

R

+IN

+V

S

OUT

AD8295

1

G

2

G

3

4

IA

REF

–V

S

Figure 64. AC-Coupled Connection

A2 +IN A2 –IN

A2

A1

7

A1 OUT

/20 k). Because of

C

13141516

12

A2 OUT

A1 +IN

11

A1 R1

10

R1
20kΩ

A1 –IN

R2

9

20kΩ

865

A1 R2

C1

OUTPUT

07343-015

Rev. 0 | Page 24 of 28

AD8295

www.BDTIC.com/ADI

DRIVING DIFFERENTIAL ADCs

Figure 65 shows how to configure the AD8295 to drive a differ­ential ADC. The circuit shown uses very little board space and
consumes little power. With the AD7690, this configuration
gives excellent dc performance and a THD of 83 dB (10 kHz
input). For applications that need better distortion performance,
a dedicated ADC driver, such as the ADA4941-1 or ADA4922-1
is recommended.

The 500  resistors and the 2.2 nF capacitors form a low-pass,
antialiasing filter at 144 kHz. The four elements of the filter also
prevent the switching transients produced by a typical SAR
converter from destabilizing the AD8295. The capacitors provide
charge to the switched capacitor front end of the ADC, and the
resistors shield the AD8295 from driving any sharp current

+7V

0.1µF

+V

S

–IN

AD8295

R

R

+IN

1

G

2

–7V

–V

0.1µF

IA

REF

S

G

3

4

–INPUT

+INPUT

A2
+IN

OUT

A2

R1

A1

20kΩ

R2
20kΩ

A1
OUTA1R2

Figure 65. Driving a Differential ADC

A2
–IN

13141516

8765

changes. If the application requires a lower frequency anti­aliasing filter than the one shown, increasing the capacitor
values produces much better distortion results than increasing
the resistor values.

The 500  resistors also give the ADC protection against over­voltage. Because the AD8295 runs on wider supply voltages
than a typical ADC, there is a possibility of overdriving some
converters. This is not an issue with a PulSAR® ADC, such as
the AD7690, because its input can handle a 130 mA overdrive,
which is much higher than the short-circuit limit of the AD8295.
However, other converters have less robust inputs and may
benefit from the resistive protection.

+7V

0.1µF

500Ω

2.2nF

2.2nF

500Ω

ADR435

+5V

10kΩ

10kΩ

0.1µF

IN+

AD7690

GND

IN–

+5V

VDD

REF

0.1µF

+5V

10µF

+

07343-014

A2
OUT

12

A1
+IN

11

+2.5V

A1
R1

10

9

A1
–IN

+OUT

–OUT

Rev. 0 | Page 25 of 28

AD8295

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.08

0.65

BSC

0.75

0.60

0.50

0.60 MAX

12

9

13

8

BOTTOM VI EW

16

1

1.95 REF
SQ

4

5

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

4.00

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.35

0.30

0.25

3.75

BCS SQ

0.20 REF

0.60 MAX

0.05 MAX

0.02 NOM
COPLANARITY

COMPLIANTTOJEDEC STANDARDS MO-263-VBBC

040908-A

Figure 66. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle

CP-16-19

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8295ACPZ-R7
AD8295ACPZ-RL
AD8295ACPZ-WP
AD8295BCPZ-R7
AD8295BCPZ-RL
AD8295BCPZ-WP

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 16-Lead LFCSP_VQ, 7-Inch Tape and Reel CP-16-19

1

−40°C to +85°C 16-Lead LFCSP_VQ, 13-Inch Tape and Reel CP-16-19

1

−40°C to +85°C 16-Lead LFCSP_VQ, Waffle Pack CP-16-19

1

−40°C to +85°C 16-Lead LFCSP_VQ, 7-Inch Tape and Reel CP-16-19

1

−40°C to +85°C 16-Lead LFCSP_VQ, 13-Inch Tape and Reel CP-16-19

1

−40°C to +85°C 16-Lead LFCSP_VQ, Waffle Pack CP-16-19

Rev. 0 | Page 26 of 28

AD8295

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 27 of 28

AD8295

www.BDTIC.com/ADI

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07343-0-10/08(0)

Rev. 0 | Page 28 of 28