Datasheet AD8283 Datasheet (ANALOG DEVICES)

Radar Receive Path AFE:

FEATURES

6 channels of LNA, PGA, AAF
1 channel of direct-to-ADC
Programmable gain amplifier (PGA)
Includes low noise preamplifier (LNA)
SPI-programmable gain = 16 dB to 34 dB in 6 dB steps
Antialiasing filter (AAF)
Programmable third-order low-pass elliptic filter (LPF) from

1 MHz to 12 MHz
Analog-to-digital converter (ADC)
12 bits of accuracy up to 80 MSPS
SNR = 67 dB
SFDR = 68 dB
Low power, 170 mW per channel at 12 bits/80 MSPS
Low noise, 3.5 nV/√Hz maximum of input referred

voltage noise
Power-down mode
72-lead, 10 mm × 10 mm, LFCSP package
Specified from −40°C to +105°C
Qualified for automotive applications

APPLICATIONS

Automotive radar

Adaptive cruise control

Collision avoidance

Blind spot detection

Self-parking

Electronic bumper

6-Channel LNA/PGA/AAF with ADC

AD8283

FUNCTIONAL BLOCK DIAGRAM

AVDD33x

AVDD18x

INA+

INA–

INB+

INB–

INC+

INC–

IND+

IND–

INE+

INE–

INF+

INF–

INADC+
INADC–

ZSEL

SPI

CS

PGALNA

PGALNA

PGALNA

PGALNA

PGALNA

PGALNA

SCLK

PDWN

MUXA

DVDD18x

AAF

AAF

AAF

AAF

AAF

AAF

SDIO

MUX

AUX

12-BIT

ADC

CLK+

VREF

DVDD33x

REFERENCE

DRV

AD8283

CLK–

RBIAS

DSYNC

D[0:11]

Figure 1.

09795-001

GENERAL DESCRIPTION

The AD8283 is designed for low cost, low power, compact size,
flexibility, and ease of use. It contains six channels of a low noise
preamplifier (LNA) with a programmable gain amplifier (PGA)
and an antialiasing filter (AAF) plus one direct-to-ADC
channel, all integrated with a single 12-bit analog-to-digital
converter (ADC).

Each channel features a gain range of 16 dB to 34 dB in 6 dB
increments and an ADC with a conversion rate of up to 80 MSPS.
The combined input-referred noise voltage of the entire channel

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

is 3.5 nV/√Hz at maximum gain. The channel is optimized for
dynamic performance and low power in applications where a
small package size is critical.

Fabricated in an advanced CMOS process, the AD8283 is
available in a 10 mm × 10 mm, RoHS-compliant, 72-lead
LFCSP. It is specified over the automotive temperature range of

−40°C to +105°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD8283

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 3

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 10

Theory of operation ....................................................................... 14

Radar Receive Path AFE............................................................ 14

Channel Overview...................................................................... 15

ADC ............................................................................................. 16

Clock Input Considerations...................................................... 16

Clock Duty Cycle Considerations............................................ 17

Clock Jitter Considerations....................................................... 17

SDIO Pin...................................................................................... 17

SCLK Pin ..................................................................................... 17

CS

Pin .......................................................................................... 17

RBIAS Pin.................................................................................... 18

Voltage Reference....................................................................... 18

Power and Ground Recommendations................................... 18

Exposed Paddle Thermal Heat Slug Recommendations ...... 18

Serial Peripheral Interface (SPI)................................................... 19

Hardware Interface..................................................................... 19

Memory Map .................................................................................. 21

Reading the Memory Map Table.............................................. 21

Logic Levels................................................................................. 21

Reserved Locations .................................................................... 21

Default Values............................................................................. 21

Application Diagrams.................................................................... 25

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

Automotive Products................................................................. 27

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8283

SPECIFICATIONS

AC SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f
MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 1.

AD8283W
Parameter1 Conditions Min Typ Max Unit

ANALOG CHANNEL CHARACTERISTICS LNA, PGA, and AAF channel

Gain 16/22/28/34 dB
Gain Range 18 dB
Gain Error −1.25 +1.25 dB
Input Voltage Range Channel gain =16 dB 0.25 V p-p
Channel gain = 22 dB 0.125
Channel gain = 28 dB 0.0625
Channel gain = 34 dB 0.03125
Input Resistance 200 Ω input impedance selected 0.180 0.230 0.280 kΩ
200 kΩ input impedance selected 160 200 240
Input Capacitance 22 pF
Input-Referred Voltage Noise Max gain at1 MHz 1.85 nV/√Hz

Min gain at 1 MHz 6.03 nV/√Hz
Noise Figure Max gain, RS = 50 Ω, unterminated 7.1 dB
Max Gain, RS=RIN = 50 Ω 12.7 dB
Output Offset Gain = 16 dB −60 +60 LSB
Gain = 34 dB −250 +250 LSB
AAF Low-Pass Filter Cutoff −3 dB, programmable 1.0 to 12.0 MHz
AAF Low-Pass Filter Cutoff Tolerance After filter autotune −10 ±5 +10 %
AAF Attenuation in Stop Band Third order elliptical filter
2× cutoff 30 dB
3× cutoff 40 dB
Group Delay Variation Filter set at 2 MHz 400 ns
Channel-to-Channel Phase Variation Frequencies up to −3 dB −5 ±0.5 +5 Degrees
¼ of −3 dB frequency −1 +1 Degrees
Channel-to-Channel Gain Matching Frequencies up to −3 dB −0.5 ±0.1 +0.5 dB
1/4 of −3 dB frequency −0.25 +0.25 dB
1 dB Compression Relative to output 9.8 dBm
Crosstalk −70 −55 dBc

POWER SUPPLY

AVDD18x 1.7 1.8 1.9 V
AVDD33x 3.1 3.3 3.5 V
DVDD18x 1.7 1.8 1.9 V
DVDD33x 3.1 3.3 3.5 V
I

Full-channel mode 190 mA

AVDD18

I

Full-channel mode 190 mA

AVDD33

I

22 mA

DVDD18

I

2 mA

DVDD33

Total Power Dissipation – per

channel

Full-channel mode, no signal, typical
supply voltage × maximum supply

170 mW

current; excludes output current
Power-Down Dissipation 5 mW
Power Supply Rejection Ratio (PSRR) Relative to input 1.6 mV/V

SAMPLE

= 80

Rev. 0 | Page 3 of 28

AD8283

AD8283W
Parameter1 Conditions Min Typ Max Unit

ADC

Resolution 12 Bits
Max Sample Rate 80 MSPS
Signal-to-Noise Ratio (SNR) fIN = 1 MHz 68.5 dB
Signal-to-Noise and Distortion

(SINAD)
SNRFS 68 dB
Differential Nonlinearity (DNL) Guaranteed no missing codes 1 LSB
Integral Nonlinearity (INL) 10 LSB
Effective Number of Bits (ENOB) 10.67 LSB
ADC Output Characteristics

Maximum Cap Load Per bit 20 pF
I

Peak Current with Cap Load

DVDD33

ADC REFERENCE

Output Voltage Error VREF = 1.024 V ±25 mV
Load Regulation At 1.0 mA, VREF = 1.024 V 2 mV
Input Resistance 6 kΩ

FULL CHANNEL CHARACTERISTICS LNA, PGA, AAF, and ADC

SNRFS FIN = 1 MHz

Gain = 16 dB 68 dB
Gain = 22 dB 68 dB
Gain = 28 dB 68 dB
Gain = 34 dB 66 dB

SINAD FIN = 1 MHz

Gain = 16 dB 67 dB
Gain = 22 dB 68 dB
Gain = 28 dB 67 dB
Gain = 34 dB 66 dB

SFDR FIN = 1 MHz

Gain = 16 dB 68 dB
Gain = 22 dB 74 dB
Gain = 28 dB 74 dB
Gain = 34 dB 73 dB

Harmonic Distortion

Second Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −70 dBc

F

Third Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −66 dBc

F

IM3 Distortion

Gain Response Time 600 ns
Overdrive Recovery Time 200 ns

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

66 dB

Peak current per bit when driving a

40 mA
20 pf load; can be programmed via
the SPI port if required

=1 MHz at −10 dBFS, gain = 34 dB −70 dBc

IN

=1 MHz at −10 dBFS, gain = 34 dB −75 dBc

IN

= 1 MHz, f F

F

IN1

= 1.1 MHz, −1 dBFS,

IN2

−69 dBc

gain = 34 dB

Rev. 0 | Page 4 of 28

AD8283

DIGITAL SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f
MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 2.

Parameter1 Temperature Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF

LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)

Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF

LOGIC INPUT (CS)

Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 3.0 V
Logic 0 Voltage (IOL = 50 μA) Full 0.3 V

LOGIC OUTPUT (D[11:0], DSYNC)

Logic 1 Voltage (IOH = 2 mA) Full 3.0 V
Logic 0 Voltage (IOL = 2 mA) Full 0.05 V

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.

SAMPLE

= 80

Rev. 0 | Page 5 of 28

AD8283

SWITCHING SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f
MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 3.

Parameter1 Temperature Min Typ Max Unit

CLOCK

Clock Rate Full 10 80 MSPS
Clock Pulse Width High (tEH) at 80 MSPS Full 6.25 ns
Clock Pulse Width Low (tEL) at 80 MSPS Full 6.25 ns
Clock Pulse Width High (tEH) at 40 MSPS Full 12.5 ns
Clock Pulse Width Low (tEL) at 40 MSPS Full 12.5 ns

OUTPUT PARAMETERS

Propagation Delay (tPD) at 80 MSPS Full 1.5 2.5 5.0 ns
Rise Time (tR) Full 1.9 ns
Fall Time (tF) Full 1.2 ns
Data Set-Up Time (tDS) at 80 MSPS Full 9.0 10.0 11.0 ns
Data Hold Time (tDH) at 80 MSPS Full 1.5 4.0 5.0 ns
Data Set-Up Time (tDS) at 40 MSPS Full 21.5 22.5 23.5 ns
Data Hold Time (tDH) at 40 MSPS Full 1.5 4.0 5.0 ns
Pipeline Latency Full 7 Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

N –1

N

SAMPLE

= 80

INAx

CLK–

CLK+

D[11:0]

t

t

EL

EH

t

PD

N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N

t

DS

t

DH

Figure 2. Timing Definitions for Switching Specifications

09795-002

Rev. 0 | Page 6 of 28

AD8283

ABSOLUTE MAXIMUM RATINGS

Table 4.

With

Parameter

Electrical

AVDD18x GND −0.3 V to +2.0 V
AVDD33x GND −0.3 V to +3.5 V
DVDD18x GND −0.3 V to +2.0 V
DVDD33x GND −0.3 V to +3.5 V
Analog Inputs

INx+, INx-

Auxiliary Inputs

INADC+, INADC-

Digital Outputs

D[11:0], DSYNC, SDIO
CLK+, CLK− GND −0.3 V to +3.9 V
PDWN, SCLK, CS, AUX,

MUXA, ZSEL
RBIAS, VREF GND −0.3 V to +2.0 V

Environmental

Operating Temperature

Range (Ambient)
Storage Temperature

Range (Ambient)
Maximum Junction

Temperature
Lead Temperature

(Soldering, 10 sec)

Respect To

GND −0.3 V to +3.5 V

GND −0.3 V to +2.0 V

GND −0.3 V to +3.5 V

GND −0.3 V to +3.9 V

−40°C to +105°C

−65°C to +150°C

150°C

300°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 28

AD8283

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

NC

DSYNC

PDWN

DVDD18

SCLK

SDIO

CS

AUX

MUXA

ZSEL
TEST1
TEST2

DVDD33SPI

AVDD18

AVDD33A

INA–

DVDD33DRVNCNCD0D1D2D3D4D5D6D7D8D9

7271706968676665646362616059585756

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17INA+
18NC

PIN 1
INDICATOR

AD8283

(TOP VIEW)

D10

D11

DVDD33DRV

NC

55

NC

54

TEST4

53

DVDD18CLK

52

CLK+

51

CLK–

50

DVDD33CLK

49

AVDD33REF

48

VREF

47

RBIAS

46

BAND

45

APOUT

44

ANOUT

43

TEST3

42

AVDD18ADC

41

AVD D18

40

INADC+

39

INADC–

38

NC

37

192021222324252627282930313233

NC

NC

INB–

INC–

INB+

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PI N.

2. THE EXPO SED PADDLE SHOULD BE TIED TO ANALOG /DIGITAL GROUND PLANE.

AVDD33B

IND–

INC+

IND+

AVDD33C

AVDD33D

INE–

AVDD33E

INE+

34

INF–

AVDD33F

35INF+

36NC

09795-003

Figure 3.

Table 5. Pin Function Descriptions

Pin No. Name Description

0 GND Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane.
1 NC No Connection. Pin can be tied to any potential.
2 DSYNC Data Out Synchronization.
3 PDWN Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI.
4 DVDD18 1.8 V Digital Supply.
5 SCLK Serial Clock.
6 SDIO Serial Data Input/Output.
7

CS

Chip Select Bar.

8 AUX Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA.
9 MUXA Logic high forces to Channel A unless AUX is asserted.
10 ZSEL Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ; logic low allows selection through SPI.
11 TEST1 Pin should not be used; tie to ground.
12 TEST2 Pin should not be used; tie to ground.
13 DVDD33SPI 3.3 V Digital Supply, SPI Port.
14 AVDD18 1.8 V Analog Supply.
15 AVDD33A 3.3 V Analog Supply, Channel A.
16 INA− Negative LNA Analog Input for Channel A.
17 INA+ Positive LNA Analog Input for Channel A.
18 NC No Connect. Pin can be tied to any potential.
19 NC No Connect. Pin can be tied to any potential.
20 NC No Connect. Pin can be tied to any potential.
21 AVDD33B 3.3 V Analog Supply, Channel B.
22 INB−- Negative LNA Analog Input for Channel B.
23 INB+ Positive LNA Analog Input for Channel B.
24 AVDD33C 3.3 V Analog Supply, Channel C.
25 INC− Negative LNA Analog Input for Channel C.
26 INC+ Positive LNA Analog Input for Channel C.

Rev. 0 | Page 8 of 28

AD8283

Pin No. Name Description

27 AVDD33D 3.3 V Analog Supply, Channel D.
28 IND− Negative LNA Analog Input for Channel D.
29 IND+ Positive LNA Analog Input for Channel D.
30 AVDD33E 3.3 V Analog Supply, Channel E.
31 INE− Negative LNA Analog Input for Channel E.
32 INE+ Positive LNA Analog Input for Channel E.
33 AVDD33F 3.3 V Analog Supply, Channel F.
34 INF− Negative LNA Analog Input for Channel F.
35 INF+ Positive LNA Analog Input for Channel F.
36 NC No Connect, Pin can be tied to any potential.
37 NC No Connect. Pin can be tied to any potential.
38 INADC− Negative Analog Input for Alternate Channel F (ADC Only).
39 INADC+ Positive Analog Input for Alternate Channel F (ADC Only).
40 AVDD18 1.8 V Analog Supply.
41 AVDD18ADC 1.8 V Analog Supply, ADC.
42 TEST3 Pin should not be used; tie to ground.
43 ANOUT Analog Outputs (Debug Purposes Only). Pin should be floated.
44 APOUT Analog Outputs (Debug Purposes Only). Pin should be floated.
45 BAND Band Gap Voltage (Debug Purposes Only). Pin should be floated.
46 RBIAS External resistor to set the internal ADC core bias current.
47 VREF Voltage Reference Input/Output.
48 AVDD33REF 3.3 V Analog Supply, References.
49 DVDD33CLK 3.3 V Digital Supply, Clock.
50 CLK- Clock Input Complement.
51 CLK+ Clock Input True.
52 DVDD18CLK 1.8 V Digital Supply, Clock.
53 TEST4 Pin should not be used; tie to ground.
54 NC No Connect. Pin can be tied to any potential.
55 NC No Connect. Pin can be tied to any potential.
56 DVDD33DRV 3.3 V Digital Supply, Output Driver.
57 D11 ADC Data Out (MSB).
58 D10 ADC Data Out.
59 D9 ADC Data Out.
60 D8 ADC Data Out.
61 D7 ADC Data Out.
62 D6 ADC Data Out.
63 D5 ADC Data Out.
64 D4 ADC Data Out.
65 D3 ADC Data Out.
66 D2 ADC Data Out.
67 D1 ADC Data Out.
68 D0 ADC Data Out (LSB).
69 NC No Connect. Pin should be left open.
70 NC No Connect. Pin should be left open.
71 DVDD33DRV 3.3 V Supply, Output Driver.
72 NC No Connect. Pin can be tied to any potential.

Rev. 0 | Page 9 of 28

AD8283

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 3.3 V, 1.8 V, TA = 25°C, FS = 80 MSPS, RIN =200 k, VREF = 1.0 V.

50

40

34dB

28dB

30

22dB

20

16dB

10

0

GAIN (dB)

–10

–20

–30

–40

0.1 1 10 100

FREQUENCY (MHz)

Figure 4. Channel Gain vs. Frequency

1.0
34dB

28dB

0.8
22dB

16dB

0.6

0.4

0.2

0

–0.2

GAIN ERROR (dB)

–0.4

–0.6

–0.8

–1.0

–40 –15 10 35 60 85

TEMPERATURE (° C)

Figure 5. Gain Error vs. Temperature at All Gains

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

8

PERCENTAGE OF DEVICES (%)

6
4
2
0

16.00

16.16

16.32

16.48

16.08

16.24

16.4

(dB)

16.56

16.64

16.72

16.8

16.88

16.96

09795-014

09795-038

09795-032

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10

PERCENTAGE OF DEV ICES (%)

8
6
4
2
0

33.50

33.66

33.82

33.98

34.14

33.58

33.74

33.90

(LSB)

34.06

34.22

34.30

34.38

Figure 7. Gain Error Histogram (Gain = 34 dB)

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4

PERCENTAGE OF DEVICES (%)

3
2
1
0

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

0.01

0.03

0.05

0.07

0.09

0.11

(dB)

0.13

0.15

0.17

0.19

0.21

0.22

Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB)

10

9

8

7

6

5

4

3

2

PERCENTAGE OF DEV ICES (%)

1

0

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

0.01

0.03

0.05

0.07

0.09

0.11

(dB)

0.13

0.15

0.17

0.19

0.21

0.22

Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB) Figure 6. Gain Error Histogram (Gain = 16 dB)

0.23

0.23

34.46

0.24

0.24

0.25

0.25

09795-033

09795-034

09795-035

Rev. 0 | Page 10 of 28

AD8283

√

√

12000

10000

8000

70

SNR

65

SINAD

60

6000

NUMBER OF HIT S

4000

2000

0

–7 –6 –5 –4 –3 –2 –1 0 1

CODE

2

34567

Figure 10. Output Referred Noise Histogram (Gain = 16 dB)

7000

6000

5000

4000

3000

NUMBER OF HITS

2000

1000

0

–7–6–5–4–3–2–101234567

CODE

Figure 11. Output Referred Noise Histogram (Gain = 34 dB)

15

10

Hz)

16dB

NOISE (nV/

5

22dB

28dB

34dB

0

0.1 1 10

FREQUENCY (MHz)

Figure 12. Short Circuit Input-Referred Noise vs. Frequency

55

50

SNR/SINAD (dBF S)

45

40

16 22 28 34

09795-015

GAIN (dB)

09795-017

Figure 13. SNR vs. Gain

20

10

0

–10

–20

GAIN (dB)

–30

12MHz
8MHz

–40

4MHz
2MHz
1MHz

–50

0.1 1 10 100

09795-016

FREQUENCY (Hz)

09795-022

Figure 14. Filter Response

200

180

160

140

Hz)

120

100

NOISE (nV/

09795-030

34dB

28dB

80

22dB

60

16dB

40

20

0

0.1 1 10
FREQUENCY (M Hz)

09795-031

Figure 15. Short-Circuit Output-Referred Noise vs. Frequency

Rev. 0 | Page 11 of 28

AD8283

A

–

1000

900

800

700

600

Y (ns)

500

DEL

400

300

200

100

0

0.1 1 10 100

40

–45

–50

–55

–60

–65

HARMONIC (dBc)

–70

–75

FREQUENCY ( MHz)

Figure 16. Group Delay vs. Frequency

SECOND –1dBFS
SECOND –10dBFS
THIRD –1dBFS
THIRD –10dBF S

1MHz
2MHz
4MHz
8MHz
12MHz

1.5

1.0

0.5

0

AMPLITUDE (V)

–0.5

–1.0

–1.5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

09795-019

TIME (µs)

09795-041

Figure 19. Overdrive Recovery

LEVEL
560mV

TRIG HOLDOFF

1.5µs

MEAN(C2) 7.177mV
µ: 7.1773964m
m: 7177m M: 7.177m

SDO

3

ANALOG
OUTPUT

2

σ:0

MEAN(C2) 220mV
µ: 220m
m: 220m M: 220m
σ:0

FREQ(C2) 997.8kHz
µ: 997.75504k
m: 997.8k M: 997.8k
σ:0

–80

01234567

INPUT FREQ UENCY (MHz)

Figure 17. Harmonic Distortion vs. Frequency

500

450

400

350

300

250

200

IMPEDANCE (Ω)

150

100

50

0

0.01 0.1 1 10 100

FREQUENCY ( MHz)

Figure 18. R

vs. Frequency

IN

200000

180000

160000

140000

120000

100000

80000

60000

40000

20000

0

09795-039

CH3 1V

CH2 500mV M1µs 1.25GS/s

Ω

A CH2 560mV

800ps/pt

09795-024

Figure 20. Gain Step Response

30

25

20

34dB 50Ω TERMINATED

15

34dB UNTERMINAT ED

10

NOISE FI GURE (dB)

5

0

0.1 1 10

09795-040

FREQUENCY (MHz )

09795-042

Figure 21. Noise Figure vs. Frequency

Rev. 0 | Page 12 of 28

AD8283

10

9

8

7

6

5

4

3

PERCENTAGE OF DEV ICES (%)

2

1

0

–60

–52

–44

–36

–28

–20

–56

–48

–40

–12–8–404812162024283236404448525660

–32

–24

–16

(LSB)

09795-036

Figure 22. Channel Offset Distribution (Gain = 16 dB)

12

11

10

9

8

7

6

5

4

3

PERCENTAGE OF DEVICES (%)

2

1

0

–200

–160

–120

–80

–180

–140

–100

–40

–60

–20020406080100

(LSB)

120

140

160

180

200

09795-037

Figure 23. Channel Offset Distribution (Gain = 34 dB)

Rev. 0 | Page 13 of 28

AD8283

K

THEORY OF OPERATION

RADAR RECEIVE PATH AFE

The primary application for the AD8283 is high-speed ramp,
frequency modulated, continuous wave radar (HSR-FMCW
radar). Figure 25 shows a simplified block diagram of an HSR­FMCW radar system. The signal chain requires multiple
channels, each including a low noise amplifier (LNA), a
programmable gain amplifier (PGA), an antialiasing filter
(AAF), and an analog-to-digital converter (ADC). The AD8283
provides all of these key components in a single 10 × 10 LFCSP
package.

The performance of each component is designed to meet the
demands of an HSR-FMCW radar system. Some examples of
these performance metrics are the LNA noise, PGA gain range,

REF.
OSCIL LATO R

AAF cutoff characteristics, and ADC sample rate and
resolution.

The AD8283 includes a multiplexer (mux) in front of the ADC
as a cost saving alternative to having an ADC for each channel.
The mux automatically switches between each active channel
after each ADC sample. The DSYNC output indicates when
Channel A data is at the ADC output, and data for each active
channel follows sequentially with each clock cycle.

The effective sample rate for each channel is reduced by a factor
equal to the number of active channels. The ADC resolution of
12 bits with up to 80 MSPS sampling satisfies the requirements
for most HSR-FMCW approaches.

PA

VCO

CHIRP RAMP
GENERATOR

PGALNA

AAF

PGALNA

AAF

12-BIT

MUX

PGALNA

AAF

ADC

DSP

AD8283

ANTENNA

09795-004

Figure 24. Radar System Overview

SDIO SCL

AD8283

MUX

CONTROLL ER

MUX

PIPELINE

ADC

12-BIT

80MSPS

PARALLEL

3.3V CMOS

DSYNC

D11:D0

09795-005

INx+

INx–

200Ω/

200kΩ

22dB

PGALNA

–6dB,

0dB,
6dB,
12dB

SPI

INTERFACE

AAF

THIRD-ORDER

ELLIPTICAL FILTER

Figure 25. Simplified Block Diagram of a Single Channel

Rev. 0 | Page 14 of 28

AD8283

CHANNEL OVERVIEW

Each channel contains an LNA, a PGA, and an AAF in the
signal path. The LNA input impedance can be either 200  or
200 k. The PGA has selectable gains that result in channel
gains ranging from 16 dB to 34 dB. The AAF has a three-pole
elliptical response with a selectable cutoff frequency. The mux
is synchronized with the ADC and automatically selects the
next active channel after the ADC acquires a sample.

The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion including the
LNA, which is designed to be driven from a differential signal
source.

Low Noise Amplifier (LNA)

Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contributions on the following PGA and AAF. The input
impedance can be either 200  or 200 k and is selected through
the SPI port or by the ZSEL pin.

The LNA supports differential output voltages as high as 4.0 V p-p
with positive and negative excursions of ±1.0 V from a common­mode voltage of 1.5 V. With the output saturation level fixed,
the channel gain sets the maximum input signal before
saturation.

Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input­referred noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB.
The use of a fully differential topology and negative feedback
minimizes second-order distortion. Differential signaling
enables smaller swings at each output, further reducing third­order distortion.

Recommendation

To achieve the best possible noise performance, it is important
to match the impedances seen by the positive and negative
inputs. Matching the impedances ensures that any common­mode noise is rejected by the signal path.

Antialiasing Filter (AAF)

The filter that the signal reaches prior to the ADC is used to
band limit the signal for antialiasing.

The antialiasing filter uses a combination of poles and zeros to
create a third-order elliptical filter. An elliptical filter is used to
achieve a sharp roll off after the cutoff frequency. The filter uses
on-chip tuning to trim the capacitors to set the desired cutoff
frequency. This tuning method reduces variations in the cutoff
frequency due to standard IC process tolerances of resistors
and capacitors. The default −3 dB low-pass filter cutoff is 1/3 or
1/4 the ADC sample clock rate. The cutoff can be scaled to 0.7,

0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI.
Tuning is normally off to avoid changing the capacitor settings

during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming the
filter cutoff scaling or ADC sample rate. Occasional retuning
during an idle time is recommended to compensate for
temperature drift.

A cut-off range of 1 MHz to 12 MHz is possible. An example
follows:

• Four channels selected: A, B, C, and AUX

• ADC clock: 30 MHz

• Per channel sample rate = 30/4 = 7.5 MSPS

• Default tuned cutoff frequency = 7.5/4 = 1.88 MHz

Mux and Mux Controller

The mux is designed to automatically scan through each active
channel. The mux remains on each channel for one clock cycle,
then switches to the next active channel. The mux switching is
synchronized to the ADC sampling so that the mux switching
and channel settling time do not interfere with ADC sampling.

As indicated in Table 8, Register Address 0C, Flex Mux Control,
Channel A, is usually the first converted input. The one
exceptions occurs when Channel AUX is the sole input (see
Figure 26 for timing). Channel AUX is always forced to be the
last converted input. Unselected codes put the respective
channels (LNA, PGA, and Filter) in power-down mode unless
Register Address 0C, Bit 6, is set to 1. Figure 26 shows the
timing of the clock input and data/DSYNC outputs.

Rev. 0 | Page 15 of 28

AD8283

*

*

N

INAx

CLK–

CLK+

D[11:0]

DSYNC

NOTES

1. FOR ABOV E CONFIG URATION REG ISTER ADDRESS 0C SET TO 1010 (CHANNEL A, B, C, D, E AND F ENABL ED).

2. DSYNC IS ALWAYS ALIG NED WITH CHANNEL A UNLESS CHANNEL A O R CHANNEL AUX IS T HE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE.

3. THERE IS A SEVEN CLOCK CYCL E LATENCY FROM SAMPL ING A CHANNEL T O ITS DI GITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS.

XXXX

OUTA

t

PD

t

N – 1

DS

OUTB OUTC OUTD OUTE OUTF OUTA

t

DH

N + 1

N

Figure 26. Data and DSYNC Timing

ADC

The AD8283 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock. The output staging block aligns the
data, corrects errors, and passes the data to the output buffers.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD8283 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or using capacitors. These pins are biased
internally and require no additional bias.

Figure 27 shows the preferred method for clocking the AD8283.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50MHz, is converted from single ended to
differential using an RF transformer. The back-to-back Schottky

3.3V

OUT

VFAC3

0.1µF

50Ω

MINI-CIRCUITS

ADT1-1WT, 1:1Z

100Ω

XFMR

0.1µF

®

0.1µF

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

CLK–

Figure 27. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a
differential PECL or LVDS signal to the sample clock input pins
as shown in and Figure 28 and Figure 29. The AD951x/AD952x
family of clock drivers offers excellent jitter performance.

3.3V

VFAC3

OUT

50Ω

*

0.1µF

0.1µF

AD951x/AD9 52x

FAMILY

CLK

PECL DRIVER

CLK

0.1µF

100Ω

0.1µF

240Ω240Ω

diodes across the secondary transformer limit clock excursions
into the AD8283 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD8283, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.

50Ω RESISTOR IS OPTIONAL.

Figure 28. Differential PECL Sample Clock

3.3V

*

50Ω

VFAC3

OUT

0.1µF

0.1µF

AD951x/AD952x

FAMILY

CLK

LVDS DRIVER

CLK

0.1µF

100Ω

0.1µF

OUTB

ADC

AD8283

CLK+

ADC

AD8283

CLK–

CLK+

ADC

AD8283

CLK–

9795-006

09795-007

09795-008

50Ω RESISTOR IS OPTIONAL.

09795-009

Figure 29. Differential LVDS Sample Clock

Rev. 0 | Page 16 of 28

AD8283

V

V

In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 kΩ resistor (see Figure 30). Although the
CLK+ input circuit supply is AVDD18, this input is designed to
withstand input voltages of up to 3.3 V, making the selection of
the drive logic voltage very flexible. The AD951x/AD952x
family of parts can be used to provide 3.3 V inputs (see Figure 31).
In this case, 39 kΩ is not needed.

3.3

VFAC3

OUT

*

50Ω RESISTOR IS OPTIONAL.

3.3

VFAC3

OUT

*

50Ω RESISTOR IS OPTIONAL.

0.1µF

50Ω

0.1µF

Figure 30. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

50Ω

0.1µF

Figure 31. Single-Ended 3.3 V CMOS Sample Clock

*

*

AD951x/AD952x

FAMILY

CLK

1.8V

CMOS DRIVER

CLK

AD951x/AD952x

FAMILY

CLK

3.3V

CMOS DRIVER

CLK

0.1µF

OPTIONAL

100Ω

OPTIONAL

100Ω

39kΩ

0.1µF

0.1µF

0.1µF

CLK+

ADC

AD8283

CLK–

CLK+

ADC

AD8283

CLK–

CLOCK DUTY CYCLE CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD8283 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD8283.

When the DCS is on, noise and distortion performance are
nearly flat for a wide range of duty cycles. However, some
applications may require the DCS function to be off. If so, keep
in mind that the dynamic range performance can be affected when
operated in this mode. See Table 8 for more details on using this
feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.

09795-010

09795-011

CLOCK JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t

SNR Degradation = 20 × log 10[1/2 × π × f

) can be calculated by

J

A

× tJ]

A

In this equation, the RMS aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD8283.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.

Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).

SDIO PIN

The SDIO pin is required to operate the SPI. It has an internal 30
kΩ pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.

SCLK PIN

The SCLK pin is required to operate the SPI port interface. It has
an internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.

CS PIN

The CS pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is both

1.8 V and 3.3 V tolerant.

RBIAS PIN

To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using
other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, it is imperative
that at least a 1.0% tolerance on this resistor be used to achieve
consistent performance.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the
AD8283. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input
span of 2.0 V p-p for the ADC. VREF is set internally by
default, but the VREF pin can be driven externally with a 1.0 V

)

Rev. 0 | Page 17 of 28

AD8283

reference to achieve more accuracy. However, this device does
not support ADC full-scale ranges below 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin, use
ceramic low-ESR capacitors. These capacitors should be close to
the reference pin and on the same layer of the PCB as the
AD8283. The VREF pin should have both a 0.1 µF capacitor
and a 1 µF capacitor connected in parallel to the analog ground.
These capacitor values are recommended for the ADC to
properly settle and acquire the next valid sample.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD8283, it is recommended
that two separate 1.8 V supplies and two separate 3.3 V supplies
be used: one for analog 1.8 V (AVDD18x) and digital 1.8 V
(DVDD18x) and one for analog 3.3 V (AVDD33x) and digital

3.3 V (DVDD33x). If only one supply is available for both analog
and digital, for example, AVDD18x and DVDD18x, it should be
routed to the AVDD18x first and then tapped off and isolated
with a ferrite bead or a filter choke preceded by decoupling
capacitors for the DVDD18x. The same is true for the analog
and digital 3.3 V supplies. The user should employ several
decoupling capacitors on all supplies to cover both high and low
frequencies. These should be located close to the point of entry
at the PC board level and close to the parts, with minimal trace
lengths.

A single PC board ground plane should be sufficient when using
the AD8283. With proper decoupling and smart partitioning of
the PC board’s analog, digital, and clock sections, optimum
performance can be achieved easily.

EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS

It is required that the exposed paddle on the underside of the
device be connected to a quiet analog ground to achieve the
best electrical and thermal performance of the AD8283. An
exposed continuous copper plane on the PCB should mate to
the AD8283 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be filled or plugged with nonconductive epoxy.

To maximize the coverage and adhesion between the device and
PCB, partition the continuous copper pad by overlaying a silk­screen or solder mask to divide this into several uniform sections.
This ensures several tie points between the two during the reflow
process. Using one continuous plane with no partitions only
guarantees one tie point between the AD82833 and PCB. For
more detailed information on packaging and for more PCB
layout examples, see the AN-772 Application Note.

Rev. 0 | Page 18 of 28

AD8283

SERIAL PERIPHERAL INTERFACE (SPI)

The AD8283 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. This offers
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the Analog Devices, Inc., AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.

There are three pins that define the serial port interface, or SPI.
They are the SCLK, SDIO, and
is used to synchronize the read and write data presented to the
device. The SDIO (serial data input/output) is a dual-purpose
pin that allows data to be sent to and read from the device’s
internal memory map registers. The
active low control that enables or disables the read and write
cycles (see ). Tab le 6

Table 6. Serial Port Pins

Pin Function

SCLK

SDIO

CS Chip select bar (active low). This control gates the read

The falling edge of the CS in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in and . Figure 32 Table 7

In normal operation,
commands are to be received and processed. When
low, the device processes SCLK and SDIO to process instructions.
Normally,
complete. However, if connected to a slow device,
brought high between bytes, allowing older microcontrollers
enough time to transfer data into shift registers.
when transferring one, two, or three bytes of data. When W0 and

W1 are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until
to end the communication cycle. This allows complete memory
transfers without having to provide additional instructions.
Regardless of the mode, if
byte transfer, the SPI state machine is reset and the device waits
for a new instruction.

Serial clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.

Serial data input/output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.

and write cycles.

CS

CS

remains low until the communication cycle is

CS

pins. The SCLK (serial clock)

CS

(chip select bar) is an

is used to signal to the device that SPI

CS

is brought

CS

can be

CS

can be stalled

CS

is taken high

CS

is taken high in the middle of any

Rev. 0 | Page 19 of 28

In addition to the operation modes, the SPI port can be
configured to operate in different manners. For applications
that do not require a control port, the
held high. This places the remainder of the SPI pins in their
secondary mode as defined in the SDIO Pin and SCLK Pin
sections.
CS

communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the
line. When operating in 2-wire mode, it is recommended to use
a 1-, 2-, or 3-byte transfer exclusively. Without an active
line, streaming mode can be entered but not exited.

In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.

Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Inter facing to
High Speed ADCs via SPI.

CS

can also be tied low to enable 2-wire mode. When

is tied low, SCLK and SDIO are the only pins required for

CS

line can be tied and

CS

CS

HARDWARE INTERFACE

The pins described in Tabl e 6 constitute the physical interface
between the user’s programming device and the serial port of
the AD8283. The SCLK and
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.

This interface is flexible enough to be controlled by either serial
PROMS or PIC microcontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).

If the user chooses not to use the SPI interface, these pins serve
a dual function and are associated with secondary functions
when the
the SDIO Pin and SCLK Pin sections for details on which pin­strappable functions are supported on the SPI pins.

CS

is strapped to AVDD during device power-up. See

CS

pins function as inputs when

AD8283

t

HI

t

CLK

t

LO

D5 D4 D3 D2 D1 D0

CS

SCLK

SDIO

DON’T CAR E

t

t

DS

S

t

DH

R/W W1 W0 A12 A11 A10 A9 A8 A7

Figure 32. Serial Timing Details

Table 7. Serial Timing Definitions

Parameter Minimum Timing (ns) Description

tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
t

40 Period of the clock

CLK

t

5

S

t

2

H

Setup time between CS
Hold time between CS

and SCLK

and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
t

16 Minimum period that SCLK should be in a logic low state

LO

t

10

EN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 32).

10

t

DIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 32)

t

H

DON’T CARE

DON’T CAREDON’T CAR E

09795-012

Rev. 0 | Page 20 of 28

AD8283

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: the
chip configuration registers map (Address 0x00 and Address 0x01),
the device index and transfer registers map (Address 0x04 to
Address 0xFF), and the ADC channel functions registers map
(Address 0x08 to Address 0x2C).

The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The Bit 7 (MSB) column is the start of the
default hexadecimal value given. For example, Address 0x09,
the clock register, has a default value of 0x01, meaning that Bit 7
= 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0,
and Bit 0 = 1, or 0000 0001 in binary. This setting is the default
for the duty cycle stabilizer in the on condition. By writing a 0
to Bit 0 of this address followed by an 0x01 to the SW transfer
bit in Register 0xFF, the duty cycle stabilizer turns off. It is
important to follow each writing sequence with a write to the
SW transfer bit to update the SPI registers.

Note that all registers except Register 0x00, Register 0x04,
Register 0x05, and Register 0xFF are buffered with a master
slave latch and require writing to the transfer bit. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.

RESERVED LOCATIONS

Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 8, where an X
refers to an undefined feature.

Rev. 0 | Page 21 of 28

AD8283

Table 8. AD8283 Memory Map Register

Addr.
(Hex)

Chip Configuration Registers

00 CHIP_PORT_CONFIG 0 LSB first

01 CHIP_ID Chip ID Bits[7:0]

Device Index and Transfer Registers

04 DEVICE_INDEX_2 X X X X X X Data

05 DEVICE_INDEX_1 X X X X Data

FF DEVICE_UPDATE X X X X X X X SW

Channel Functions Registers

08 GLOBAL_MODES X X X X X X Internal power-

09 GLOBAL_CLOCK X X X X X X X Duty

0C FLEX_MUX_CONTROL X Power-

Register Name

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

1 = on
0 = off
(default)

down of
unused
channels
0 = PD
(power­down;
default)
1 =
power-on

Soft
reset
1 = on
0 = off
(default)

X X Mux input active channels

1 1 Soft

(AD8283 = 0xA2, default)

Channel
D
1 = on
(default)
0 = off

0000 = A
0001 = Aux
0010 = AB
0011 = A Aux
0100 = ABC
0101 = AB Aux
0110 = ABCD
0111 = ABC Aux
1000 = ABCDE
1001 = ABCD Aux
1010 = ABCDEF
1011 = ABCDE Aux

reset
1 = on
0 = off
(default)

Data
Channel
C
1 = on
(default)
0 = off

LSB first
1 = on
0 = off
(default)

Channel
F
1 = on
(default)
0 = off

Data
Channel
B
1 = on
(default)
0 = off

down mode
00 = chip run
(default)
01 = full power­down
11 = reset

Bit 0
(LSB)

0 0x18 The nibbles

Data
Channel
E
1 = on
(default)
0 = off

Data
Channel
A
1 = on
(default)
0 = off

transfer
1 = on
0 = off
(default)

cycle
stabilizer
1 = on
(default)
0 = off

Default
Value

Read
only

0x0F Bits are set to

0x0F Bits are set to

0x00 Synchronously

0x00 Determines the

0x01 Turns the

0x00 Sets which mux

Default Notes/
Comments

should be
mirrored so
that LSB- or
MSB-first mode
is set correct
regardless of
shift mode.

The default is a
unique chip ID,
specific to the
AD8283. This is
a read-only
register.

determine
which on-chip
device receives
the next write
command.

determine
which on-chip
device receives
the next write
command.

transfers data
from the
master shift
register to the
slave.

power-down
mode (global).

internal duty
cycle stabilizer
on and off
(global).

input channel(s)
are in use and
whether to
power down
unused
channels.

Rev. 0 | Page 22 of 28

AD8283

Addr.
(Hex)

Register Name

0D FLEX_TEST_IO User test mode

0F FLEX_CHANNEL_INPUT Filter cutoff frequency control

10 FLEX_OFFSET X X 6-bit LNA offset adjustment

11 FLEX_GAIN_1 X X X X X 010 = 16 dB(default)

12 FLEX_BIAS_CURRENT X X X X 1 X LNA bias

14 FLEX_OUTPUT_MODE X X X X X 1 =

15 FLEX_OUTPUT_ADJUST 0 =

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate
once

0000 = 1.3 × 1/4 × f
0001 = 1.2 × 1/4 × f
0010 = 1.1 × 1/4 × f
0011 = 1.0 × 1/4 × f
0100 = 0.9 × 1/4 × f
0101 = 0.8 × 1/4 × f
0110 = 0.7 × 1/4 × f

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

0111 = N/A
1000 = 1.3 × 1/3 × f
1001 = 1.2 × 1/3 × f
1010 = 1.1 × 1/3 × f
1011 = 1.0 × 1/3 × f
1100 = 0.9 × 1/3 × f
1101 = 0.8 × 1/3 × f
1110 = 0.7 × 1/3 × f
1111 = N/A

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

SAMPLECH

X X X Output drive current
enable
Data
Bits
[11:0]
1 =
disable
Data
Bits
[11:0]

Reset PN
long
gen
1 = on
0 = off
(default)

Reset PN
short
gen
1 = on
0 = off
(default)

Output test mode—see

Table 9
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the OUTPUT_MODE register)

X X X X 0x30 Low pass filter

(default)

10 0000 for LNA bias high, mid-high, mid-low (default)
10 0001 for LNA bias low

011 = 22 dB
100 = 28 dB
101 = 34 dB

00 = high
01 = mid-high
(default)
10 = mid-low
11 = low

0 = offset binary
output
invert

(local)

(default)

1 = twos comple-

ment (global)

0000 = low

1111 = high (default)

Bit 0
(LSB)

Default
Value

Default Notes/
Comments

0x00 When this

register is set,
the test data is
placed on the
output pins in
place of
normal data.
(Local, except
for PN
sequence.)

cutoff (global).

= ADC

f

SAMPLECH

sample rate/
number of
active
channels.

Note that the
absolute range
is limited to
1 MHz to
12 MHz.

0x20 LNA force

offset
correction
(local).

0x00 Total LNA +

PGA gain
adjustment
(local)

0x09 LNA bias

current
adjustment
(global).

0x00 Configures the

outputs and
the format of
the data.

0x0F Used to select

output drive
strength to
limit the noise
added to the
channels by
output
switching.

Rev. 0 | Page 23 of 28

AD8283

Addr.
(Hex)

18 FLEX_VREF X 0 =

19 FLEX_USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1A FLEX_USER_PATT1_

1B FLEX_USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1C FLEX_USER_PATT2_

2B FLEX_FILTER X Enable

2C CH_IN_IMP X X X X X X 0 =

Register Name

MSB

MSB

Table 9. Flexible Output Test Modes

Output Test Mode
Bit Sequence

Pattern Name Digital Output Word 1 Digital Output Word 2

0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 0000 Same Yes
0010 +Full-scale short 1111 1111 1111 Same Yes
0011 −Full-scale short 0000 0000 0000 Same Yes
0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No
0101 PN sequence long N/A N/A Yes
0110 PN sequence short N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 N/A No
1010 1× sync 0000 0011 1111 N/A No
1011 One bit high 1000 0000 0000 N/A No
1100 Mixed bit frequency 1010 0011 0011 N/A No

Bit 7
(MSB)

B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

internal
reference
1 =
external
reference

automatic
low-pass
tuning
1 = on
(self­clearing)

X X X X 00 = 0.625 V

01 = 0.750 V
10 = 0.875 V
11 = 1.024 V

(default)

X X 0x00

Bit 0
(LSB)

200Ω
(default)
1 =
200kΩ

Default
Value

0x03 Select internal

0x00 Input imped-

Default Notes/
Comments

reference
(recommended
default) or ex­ternal reference
(global); adjust
internal refer­ence.

pattern, 1 LSB.

pattern, 1 MSB.

pattern, 2 LSBs.

pattern, 2
MSBs.

ance adjust­ment (global).

Subject to Data
Format Select

Rev. 0 | Page 24 of 28

AD8283

APPLICATION DIAGRAMS

3.3V

INA–

INA+

DSYNC

PDWN

SCLK

SDIO

CS

AUX

MUXA

ZSEL

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

10kΩ

0.1µF

0.1µF

AVDD33REF

AVDD33A

AVDD33B

AVDD33C

AVDD33D

AVDD33E

AVDD33F

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

3.3V

NCNC
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
INA+
NC

DVDD33SPI

0.1µF

DVDD33CLK

0.1µF

DVDD33DRV

0.1µF

DVDD33DRV

0.1µF

D0D1D2D3D4D5D6D7D8D9D10

1.8V

0.1µF

0.1µF

D11

7271706968676665646362616059585756

NC

NC

NC

DVDD33DRV

D0D1D2D3D4D5D6D7D8

D9

D10

D11

DVDD18CLK

DVDD33CLK
AVDD33REF

AD8283

(TOP VIEW)

AVDD18ADC

NCNCAVDD33B

INB–

INB+

AVDD33C

INC–

INC+

AVDD33D

IND–

IND+

AVDD33E

INE–

INE+

AVDD33F

INF–35INF+36NC

DVDD18

DVDD18CLK

55

NC

TEST4

DVDD33DRV

CLK+
CLK–

VREF

RBIAS

BAND
APOUT
ANOUT

TEST3

AVDD18
INADC+

INADC–

NC

NC

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

1.8V

10kΩ

0.1µF

0.1µF

0.1µF

CLK+
CLK–

0.1µF 0.1µF

1%

0.1µF

0.1µF

AVDD18

AVDD18

AVDD18ADC

INADC+

INADC–

192021222324252627282930313233

INB–

INC–

NOTES

1. ALL CAPACIT ORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLO SE TO T HE PART.

0.1µF

0.1µF

INB+

INC+

0.1µF

0.1µF

34

0.1µF

0.1µF

0.1µF

INF+

INE+

IND+

0.1µF

0.1µF

0.1µF

INF–

INE–

IND–

09795-013

Figure 33. Differential Inputs

Rev. 0 | Page 25 of 28

AD8283

3.3V

INA

DSYNC

PDWN

SCLK

SDIO

AUX

MUXA

ZSEL

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

CS

AVDD33REF

AVDD33A

AVDD33B

AVDD33C

AVDD33D

AVDD33E

AVDD33F

10kΩ

R

0.1µF

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

3.3V

0.1µF

0.1µF

0.1µF

0.1µF

DVDD33SPI

DVDD33CLK

DVDD33DRV

DVDD33DRV

D0D1D2D3D4D5D6D7D8D9D10

7271706968676665646362616059585756

D0D1D2D3D4D5D6D7D8

NC

NC

NC

NCNC
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
INA+
NC

DVDD33DRV

NCNCAVDD33B

INB–

INB+

AVDD33C

AD8283

(TOP VIEW)

INC–

INC+

AVDD33D

192021222324252627282930313233

1.8V

IND–

IND+

DVDD18

0.1µF

DVDD18CLK

0.1µF

1.8V

0.1µF

0.1µF

0.1µF

AVDD18

AVDD18

AVDD18ADC

D11

55

D9

NC

D11

D10

54

NC

CLK+
CLK–

VREF

BAND

NC

0.1µF

53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

CLK+
CLK–

0.1µF 0.1µF

10kΩ

1%

0.1µF

0.1µF

INADC+

INADC–

INF

TEST4

DVDD33DRV

DVDD18CLK

DVDD33CLK

AVDD33REF

RBIAS

APOUT
ANOUT

TEST3

AVDD18ADC

AVDD18

INADC+
INADC–

AVDD33E

INE–

INE+

AVDD33F

INF–35INF+36NC

34

INB

INC

NOTES

1. RESIST OR R (INx– INPUTS) SHOUL D MATCH THE OUT PUT IMP EDANCE OF THE INPUT DRIVE R.

2. ALL CAPACIT ORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLO SE TO T HE PART.

0.1µF

0.1µF

0.1µF

0.1µF

INE

IND

09795-029

Figure 34. Single-Ended Inputs

Rev. 0 | Page 26 of 28

AD8283

OUTLINE DIMENSIONS

0.60

0.42

0.24

55

54

EXPOSED PAD

(BOTTOM VIEW)

37

36

8.50 REF

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

72

19

PIN 1
INDICATOR

1

8.60

8.50 SQ

8.40

18

0.25 MIN

PIN 1

INDICATOR

0.90

0.85

0.80

SEATING

PLANE

12° MAX

10.00

BSC SQ

TOP VIE W

0.30

0.23

0.18

0.70

0.65

0.60

9.75

BSC SQ

0.05 MAX

0.01 NOM

0.20 REF

0.60

0.42

0.24

0.50
BSC

0.50

0.40

0.30

COPLANARITY

0.08

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4

07-26-2010-C

Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm Body, Very Thin Quad

(CP-72-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2, 3 Temperature Range Package Description Package Option

AD8283WBCPZ-RL −40°C to +105°C 72-Lead LFCSP_VQ, 13” Tape and Reel CP-72-5
AD8283WBCPZ −40°C to +105°C 72-Lead LFCSP_VQ, Waffle Pack CP-72-5

1

Z = RoHS Compliant Part.

2

W = Qualilfied for Automotive Applications.

3

Compliant to JEDEC Standard MO-220-VNND-4.

AUTOMOTIVE PRODUCTS

The AD8283WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for this model.

Rev. 0 | Page 27 of 28

AD8283

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09795-0-4/11(0)

Rev. 0 | Page 28 of 28