ANALOG DEVICES AD8283 Service Manual

Radar Receive Path AFE:

FEATURES

6 channels of LNA, PGA, AAF 1 channel of direct-to-ADC Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) SPI-programmable gain = 16 dB to 34 dB in 6 dB steps Antialiasing filter (AAF) Programmable third-order low-pass elliptic filter (LPF) from

1 MHz to 12 MHz Analog-to-digital converter (ADC) 12 bits of accuracy up to 80 MSPS SNR = 67 dB SFDR = 68 dB Low power, 170 mW per channel at 12 bits/80 MSPS Low noise, 3.5 nV/√Hz maximum of input referred

voltage noise Power-down mode 72-lead, 10 mm × 10 mm, LFCSP package Specified from −40°C to +105°C Qualified for automotive applications

APPLICATIONS

Automotive radar

Adaptive cruise control

Collision avoidance

Blind spot detection

Self-parking

Electronic bumper

6-Channel LNA/PGA/AAF with ADC

AD8283

FUNCTIONAL BLOCK DIAGRAM

AVDD33x

AVDD18x

INA+

INA–

INB+

INB–

INC+

INC–

IND+

IND–

INE+

INE–

INF+

INF–

INADC+ INADC–

ZSEL

SPI

CS

PGALNA

SCLK

PDWN

MUXA

DVDD18x

AAF

SDIO

MUX

AUX

12-BIT

ADC

CLK+

VREF

DVDD33x

REFERENCE

DRV

AD8283

CLK–

RBIAS

DSYNC

D[0:11]

Figure 1.

09795-001

GENERAL DESCRIPTION

The AD8283 is designed for low cost, low power, compact size, flexibility, and ease of use. It contains six channels of a low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF) plus one direct-to-ADC channel, all integrated with a single 12-bit analog-to-digital converter (ADC).

Each channel features a gain range of 16 dB to 34 dB in 6 dB increments and an ADC with a conversion rate of up to 80 MSPS. The combined input-referred noise voltage of the entire channel

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

Fabricated in an advanced CMOS process, the AD8283 is available in a 10 mm × 10 mm, RoHS-compliant, 72-lead LFCSP. It is specified over the automotive temperature range of

−40°C to +105°C.

AD8283

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8283

SPECIFICATIONS

AC SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 1.

AD8283W Parameter1 Conditions Min Typ Max Unit

ANALOG CHANNEL CHARACTERISTICS LNA, PGA, and AAF channel

Gain 16/22/28/34 dB Gain Range 18 dB Gain Error −1.25 +1.25 dB Input Voltage Range Channel gain =16 dB 0.25 V p-p Channel gain = 22 dB 0.125 Channel gain = 28 dB 0.0625 Channel gain = 34 dB 0.03125 Input Resistance 200 Ω input impedance selected 0.180 0.230 0.280 kΩ 200 kΩ input impedance selected 160 200 240 Input Capacitance 22 pF Input-Referred Voltage Noise Max gain at1 MHz 1.85 nV/√Hz

Min gain at 1 MHz 6.03 nV/√Hz Noise Figure Max gain, RS = 50 Ω, unterminated 7.1 dB Max Gain, RS=RIN = 50 Ω 12.7 dB Output Offset Gain = 16 dB −60 +60 LSB Gain = 34 dB −250 +250 LSB AAF Low-Pass Filter Cutoff −3 dB, programmable 1.0 to 12.0 MHz AAF Low-Pass Filter Cutoff Tolerance After filter autotune −10 ±5 +10 % AAF Attenuation in Stop Band Third order elliptical filter 2× cutoff 30 dB 3× cutoff 40 dB Group Delay Variation Filter set at 2 MHz 400 ns Channel-to-Channel Phase Variation Frequencies up to −3 dB −5 ±0.5 +5 Degrees ¼ of −3 dB frequency −1 +1 Degrees Channel-to-Channel Gain Matching Frequencies up to −3 dB −0.5 ±0.1 +0.5 dB 1/4 of −3 dB frequency −0.25 +0.25 dB 1 dB Compression Relative to output 9.8 dBm Crosstalk −70 −55 dBc

POWER SUPPLY

AVDD18x 1.7 1.8 1.9 V AVDD33x 3.1 3.3 3.5 V DVDD18x 1.7 1.8 1.9 V DVDD33x 3.1 3.3 3.5 V I

Full-channel mode 190 mA

AVDD18

I

Full-channel mode 190 mA

AVDD33

I

22 mA

DVDD18

I

2 mA

DVDD33

Total Power Dissipation – per

channel

Full-channel mode, no signal, typical supply voltage × maximum supply

170 mW

current; excludes output current Power-Down Dissipation 5 mW Power Supply Rejection Ratio (PSRR) Relative to input 1.6 mV/V

SAMPLE

= 80

Rev. 0 | Page 3 of 28

AD8283

AD8283W Parameter1 Conditions Min Typ Max Unit

ADC

Resolution 12 Bits Max Sample Rate 80 MSPS Signal-to-Noise Ratio (SNR) fIN = 1 MHz 68.5 dB Signal-to-Noise and Distortion

(SINAD) SNRFS 68 dB Differential Nonlinearity (DNL) Guaranteed no missing codes 1 LSB Integral Nonlinearity (INL) 10 LSB Effective Number of Bits (ENOB) 10.67 LSB ADC Output Characteristics

Maximum Cap Load Per bit 20 pF I

Peak Current with Cap Load

DVDD33

ADC REFERENCE

Output Voltage Error VREF = 1.024 V ±25 mV Load Regulation At 1.0 mA, VREF = 1.024 V 2 mV Input Resistance 6 kΩ

FULL CHANNEL CHARACTERISTICS LNA, PGA, AAF, and ADC

SNRFS FIN = 1 MHz

Gain = 16 dB 68 dB Gain = 22 dB 68 dB Gain = 28 dB 68 dB Gain = 34 dB 66 dB

SINAD FIN = 1 MHz

Gain = 16 dB 67 dB Gain = 22 dB 68 dB Gain = 28 dB 67 dB Gain = 34 dB 66 dB

SFDR FIN = 1 MHz

Gain = 16 dB 68 dB Gain = 22 dB 74 dB Gain = 28 dB 74 dB Gain = 34 dB 73 dB

Harmonic Distortion

Second Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −70 dBc

F

Third Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −66 dBc

F

IM3 Distortion

Gain Response Time 600 ns Overdrive Recovery Time 200 ns

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

66 dB

Peak current per bit when driving a

40 mA 20 pf load; can be programmed via the SPI port if required

=1 MHz at −10 dBFS, gain = 34 dB −70 dBc

IN

=1 MHz at −10 dBFS, gain = 34 dB −75 dBc

IN

= 1 MHz, f F

F

IN1

= 1.1 MHz, −1 dBFS,

IN2

−69 dBc

gain = 34 dB

Rev. 0 | Page 4 of 28

AD8283

DIGITAL SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 2.

Parameter1 Temperature Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF

LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)

Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF

LOGIC INPUT (CS)

Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 3.0 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V

LOGIC OUTPUT (D[11:0], DSYNC)

Logic 1 Voltage (IOH = 2 mA) Full 3.0 V Logic 0 Voltage (IOL = 2 mA) Full 0.05 V

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.

SAMPLE

= 80

Rev. 0 | Page 5 of 28

AD8283

SWITCHING SPECIFICATIONS

AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, f MSPS, R

= 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f

S

/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,

SAMPLECH

unless otherwise noted.

Table 3.

Parameter1 Temperature Min Typ Max Unit

CLOCK

Clock Rate Full 10 80 MSPS Clock Pulse Width High (tEH) at 80 MSPS Full 6.25 ns Clock Pulse Width Low (tEL) at 80 MSPS Full 6.25 ns Clock Pulse Width High (tEH) at 40 MSPS Full 12.5 ns Clock Pulse Width Low (tEL) at 40 MSPS Full 12.5 ns

OUTPUT PARAMETERS

Propagation Delay (tPD) at 80 MSPS Full 1.5 2.5 5.0 ns Rise Time (tR) Full 1.9 ns Fall Time (tF) Full 1.2 ns Data Set-Up Time (tDS) at 80 MSPS Full 9.0 10.0 11.0 ns Data Hold Time (tDH) at 80 MSPS Full 1.5 4.0 5.0 ns Data Set-Up Time (tDS) at 40 MSPS Full 21.5 22.5 23.5 ns Data Hold Time (tDH) at 40 MSPS Full 1.5 4.0 5.0 ns Pipeline Latency Full 7 Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

N –1

N

SAMPLE

= 80

INAx

CLK–

CLK+

D[11:0]

t

EL

EH

t

PD

N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N

t

DS

t

DH

Figure 2. Timing Definitions for Switching Specifications

09795-002

Rev. 0 | Page 6 of 28

AD8283

ABSOLUTE MAXIMUM RATINGS

Table 4.

With

Parameter

Electrical

AVDD18x GND −0.3 V to +2.0 V AVDD33x GND −0.3 V to +3.5 V DVDD18x GND −0.3 V to +2.0 V DVDD33x GND −0.3 V to +3.5 V Analog Inputs

INx+, INx-

Auxiliary Inputs

INADC+, INADC-

Digital Outputs

D[11:0], DSYNC, SDIO CLK+, CLK− GND −0.3 V to +3.9 V PDWN, SCLK, CS, AUX,

MUXA, ZSEL RBIAS, VREF GND −0.3 V to +2.0 V

Environmental

Operating Temperature

Range (Ambient) Storage Temperature

Range (Ambient) Maximum Junction

Temperature Lead Temperature

(Soldering, 10 sec)

Respect To

GND −0.3 V to +3.5 V

GND −0.3 V to +2.0 V

GND −0.3 V to +3.5 V

GND −0.3 V to +3.9 V

−40°C to +105°C

−65°C to +150°C

150°C

300°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 28

AD8283

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

DSYNC

PDWN

DVDD18

SCLK

SDIO

CS

AUX

MUXA

ZSEL TEST1 TEST2

DVDD33SPI

AVDD18

AVDD33A

INA–

DVDD33DRVNCNCD0D1D2D3D4D5D6D7D8D9

7271706968676665646362616059585756

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17INA+ 18NC

PIN 1 INDICATOR

AD8283

(TOP VIEW)

D10

D11

DVDD33DRV

NC

55

NC

54

TEST4

53

DVDD18CLK

52

CLK+

51

CLK–

50

DVDD33CLK

49

AVDD33REF

48

VREF

47

RBIAS

46

BAND

45

APOUT

44

ANOUT

43

TEST3

42

AVDD18ADC

41

AVD D18

40

INADC+

39

INADC–

38

NC

37

192021222324252627282930313233

NC

INB–

INC–

INB+

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PI N.

2. THE EXPO SED PADDLE SHOULD BE TIED TO ANALOG /DIGITAL GROUND PLANE.

AVDD33B

IND–

INC+

IND+

AVDD33C

AVDD33D

INE–

AVDD33E

INE+

34

INF–

AVDD33F

35INF+

36NC

09795-003

Figure 3.

Table 5. Pin Function Descriptions

Pin No. Name Description

0 GND Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane. 1 NC No Connection. Pin can be tied to any potential. 2 DSYNC Data Out Synchronization. 3 PDWN Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI. 4 DVDD18 1.8 V Digital Supply. 5 SCLK Serial Clock. 6 SDIO Serial Data Input/Output. 7

CS

Chip Select Bar.

8 AUX Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA. 9 MUXA Logic high forces to Channel A unless AUX is asserted. 10 ZSEL Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ; logic low allows selection through SPI. 11 TEST1 Pin should not be used; tie to ground. 12 TEST2 Pin should not be used; tie to ground. 13 DVDD33SPI 3.3 V Digital Supply, SPI Port. 14 AVDD18 1.8 V Analog Supply. 15 AVDD33A 3.3 V Analog Supply, Channel A. 16 INA− Negative LNA Analog Input for Channel A. 17 INA+ Positive LNA Analog Input for Channel A. 18 NC No Connect. Pin can be tied to any potential. 19 NC No Connect. Pin can be tied to any potential. 20 NC No Connect. Pin can be tied to any potential. 21 AVDD33B 3.3 V Analog Supply, Channel B. 22 INB−- Negative LNA Analog Input for Channel B. 23 INB+ Positive LNA Analog Input for Channel B. 24 AVDD33C 3.3 V Analog Supply, Channel C. 25 INC− Negative LNA Analog Input for Channel C. 26 INC+ Positive LNA Analog Input for Channel C.

Rev. 0 | Page 8 of 28

AD8283

Pin No. Name Description

27 AVDD33D 3.3 V Analog Supply, Channel D. 28 IND− Negative LNA Analog Input for Channel D. 29 IND+ Positive LNA Analog Input for Channel D. 30 AVDD33E 3.3 V Analog Supply, Channel E. 31 INE− Negative LNA Analog Input for Channel E. 32 INE+ Positive LNA Analog Input for Channel E. 33 AVDD33F 3.3 V Analog Supply, Channel F. 34 INF− Negative LNA Analog Input for Channel F. 35 INF+ Positive LNA Analog Input for Channel F. 36 NC No Connect, Pin can be tied to any potential. 37 NC No Connect. Pin can be tied to any potential. 38 INADC− Negative Analog Input for Alternate Channel F (ADC Only). 39 INADC+ Positive Analog Input for Alternate Channel F (ADC Only). 40 AVDD18 1.8 V Analog Supply. 41 AVDD18ADC 1.8 V Analog Supply, ADC. 42 TEST3 Pin should not be used; tie to ground. 43 ANOUT Analog Outputs (Debug Purposes Only). Pin should be floated. 44 APOUT Analog Outputs (Debug Purposes Only). Pin should be floated. 45 BAND Band Gap Voltage (Debug Purposes Only). Pin should be floated. 46 RBIAS External resistor to set the internal ADC core bias current. 47 VREF Voltage Reference Input/Output. 48 AVDD33REF 3.3 V Analog Supply, References. 49 DVDD33CLK 3.3 V Digital Supply, Clock. 50 CLK- Clock Input Complement. 51 CLK+ Clock Input True. 52 DVDD18CLK 1.8 V Digital Supply, Clock. 53 TEST4 Pin should not be used; tie to ground. 54 NC No Connect. Pin can be tied to any potential. 55 NC No Connect. Pin can be tied to any potential. 56 DVDD33DRV 3.3 V Digital Supply, Output Driver. 57 D11 ADC Data Out (MSB). 58 D10 ADC Data Out. 59 D9 ADC Data Out. 60 D8 ADC Data Out. 61 D7 ADC Data Out. 62 D6 ADC Data Out. 63 D5 ADC Data Out. 64 D4 ADC Data Out. 65 D3 ADC Data Out. 66 D2 ADC Data Out. 67 D1 ADC Data Out. 68 D0 ADC Data Out (LSB). 69 NC No Connect. Pin should be left open. 70 NC No Connect. Pin should be left open. 71 DVDD33DRV 3.3 V Supply, Output Driver. 72 NC No Connect. Pin can be tied to any potential.

Rev. 0 | Page 9 of 28

ANALOG DEVICES AD8283 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS