ANALOG DEVICES AD8275 Service Manual

G = 0.2, Level Translation,

–

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FEATURES

Translates ±10 V to +4 V Drives 16-bit SAR ADCs Small MSOP package Input overvoltage: +40 V to −35 V (V Fast settling time: 450 ns to 0.001% Rail-to-rail output Wide supply operation: +3.3 V to +15 V High CMRR: 80 dB Low gain drift: 1 ppm/°C Low offset drift: 2.5 μV/°C

APPLICATIONS

Level translator ADC driver Instrumentation amplifier building block Automated test equipment

= 5 V)

S

16-Bit ADC Driver

AD8275

PIN CONFIGURATION

REF1

+10V

10V

1

AD8275

–IN

2

TOP VIEW

3

+IN

(Not to Scale)

–V

4

S

Figure 1.

TYPICAL APPLICATION

+5V

+V

50k

2

–IN

50k

3

VIN

+IN

–V

AD8275

Figure 2. Translating ±10 V to 4.096 V ADC Full Scale

7

S

10k

S

4

20k

0.1µF

SENSE

OUT

REF2

REF1

REF2

8

+V

7

S

6

OUT

SENSE

5

+4.048V

+2.048V

+0.048V

5

33

6

2.7nF

8

1

VREF

4.096V

07546-001

0.1µF

IN+

IN–

AD7685

10µF

VDD

GNDREF

07546-002

GENERAL DESCRIPTION

The AD8275 is a G = 0.2 difference amplifier that can be used to translate ±10 V signals to a +4 V level. It solves the problem typically encountered in industrial and instrumentation applications where ±10 V signals must be interfaced to a single-supply 4 V or 5 V ADC. The AD8275 interfaces the two signal levels, simplifying design.

The AD8275 has fast settling time of 450 ns and low distortion, making it suitable for driving medium speed successive approximation (SAR) ADCs. Its wide input voltage range and rail-torail outputs make it an easy to use building block. Single-supply operation reduces the power consumption of the amplifier and helps to protect the ADC from overdrive conditions.

Internal, matched, precision laser-trimmed resistors ensure low gain error, low gain drift of 1 ppm/°C (maximum), and high common-mode rejection of 80 dB. Low offset and low offset drift, combined with its fast settling time, make the AD8275 suitable for a variety of data acquisition applications where accurate and quick capture is required.

The AD8275 can be used as an analog front end, or it can follow buffers to level translate high voltages to a voltage range accepted by the ADC. In addition, the AD8275 can be configured for differential outputs if used with a differential ADC.

The AD8275 is available in a space-saving, 8-lead MSOP and is specified for performance over the −40°C to +85°C temperature range.

Table 1. Difference Amplifiers by Category

Single-Supply

Low Distortion High Voltage

Current Sense

AD8270 AD628 AD8202 AD8273 AD629 AD8203 AD8274 AD8205

AD8275 AD8206

AMP03 AD8216

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8275

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REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

AD8275

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SPECIFICATIONS

VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted. Specifications referred to output unless otherwise noted.

Table 2.

A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Small Signal Bandwidth −3 dB 10 15 10 15 MHz Slew Rate 4 V step 20 25 20 25 V/μs Settling Time to 0.01% 4 V step on output, CL = 100 pF 350 350 450 ns Settling Time to 0.001% 4 V step on output, CL = 100 pF 450 450 550 ns Overload Recovery Time 50% overdrive 300 300 ns

NOISE/DISTORTION

THD + N f = 1 kHz, V

Voltage Noise f = 0.1 Hz to 10 Hz, referred to output 1 4 1 4 μV p-p Spectral Noise Density f = 1 kHz, referred to output 40 40 nV/√Hz

GAIN V

Gain Error 0.024 0.024 % Gain Drift −40°C to +85°C 1 3 0.3 1 ppm/°C Gain Nonlinearity V

OFFSET AND CMRR

2

Offset

vs. Temperature −40°C to +85°C 2.5 2.5 7 μV/°C

vs. Power Supply VS = 3.3 V to 5 V 90 100 dB Reference Divider Accuracy 0.024 0.024 % Common-Mode Rejection

3

Ratio

INPUT CHARACTERISTICS

Input Voltage Range Impedance

Differential VCM = VS/2 108||2 108||2 kΩ||pF

Common Mode 27.5||2 27.5||2 kΩ||pF

OUTPUT CHARACTERISTICS

Output Swing V

Capacitive Load Short-Circuit Current Limit 30 30 mA

POWER SUPPLY

Specified Voltage Range 5 5 V Operating Voltage Range 3.3 15 3.3 15 V Supply Current IO = 0 mA, VS = ±2.5 V, reference and

Over Temperature IO = 0 mA, VS = ±2.5 V, reference and

TEMPERATURE RANGE

Specified Performance −40 +85 −40 +85 °C

1

Includes amplifier voltage and current noise, as well as noise of internal resistors.

2

Includes input bias and offset current errors.

3

See for CMRR vs. temperature. Figure 7

4

The input voltage range is a function of the voltage supplies, reference voltage, and ESD diodes. When operating on other supply voltages, see the

section, Figure 11, and for more information.

Ratings Table 5

5

Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy.

6

See Figure 25 to Figure 28 in the section for more information. Typical Performance Characteristics

1

= 4 V p-p, 22 kHz band

OUT

106 106 dB

pass filter

= 4.096 V, REF1 and RL connected

REF2

to GND, (V

= 4 V p-p, RL = 600 Ω, 2 kΩ, 10 kΩ 2.5 2.5 3 ppm

OUT

IN+

) − (V

) = −10 V to +10 V

IN−

Referred to output, VS = ±2.5 V,

0.2 0.2 V/V

300 700 150 500 μV

reference and input pins grounded

VCM = ±10 V, referred to output 80 96 86 dB

4

5

−12.3 +12 −12.3 +12 V

= 4.096 V, REF1 and RL connected

REF2

to GND, R

6

100 100 pF

= 2 kΩ

L

−V

+

S

0.048

+VS −

0.1

−VS +

0.048

+VS −

0.1

V

1.9 2.3 1.9 2.3 mA

input pins grounded

2.1 2.7 2.1 2.7 mA

input pins grounded, −40°C to +85°C

Absolute Maximum

Rev. 0 | Page 3 of 16

AD8275

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 18 V Output Short-Circuit Current

See derating curve (Figure 3)

midsupply, the total drive power is V dissipated in the package and some of which is dissipated in the load (V

The difference between the total drive power and the load power is the drive power dissipated in the package.

Voltage at +IN, −IN Pins −VS + 40 V, +VS − 40 V

−V

Voltage at REFx, +VS, − VS, SENSE,

− 0.5 V, +VS + 0.5 V

S

and OUT Pins

Current into REFx, +IN, −IN, SENSE,

and OUT Pins Storage Temperature Range −65°C to +130°C Specified Temperature Range −40°C to +85°C Thermal Resistance (θJA) 135°C/W Package Glass Transition Temperature

)

(T

G

ESD Human Body Model 2 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any

3 mA

140°C

In single-supply operation with R case is V

Airflow increases heat dissipation, effectively reducing θ addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces θ

Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board.

other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8275 package is limited by the associated rise in junction temperature (T the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8275. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure.

The still air thermal properties of the package and PCB (θ the ambient temperature (T the package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in

A

The junction temperature is calculated as follows:

T

= TA + (PD × θJA)

J

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V quiescent current (I

). Assuming the load (RL) is referenced to

S

) times the

S

) on

J

JA

),

ESD CAUTION

/2 × I

S

× I

OUT

= Quiescent Power + (Total Drive Power − Load Power)

P

D

OUT

2.00

1.75

1.50

1.25

1.00

0.75

0.50

MAXIMUM POWER DISSIPATION (W)

0.25

0

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

).

OUT

⎛

V

()

⎜

IVP

SS

⎜

2

⎝

⎞

V

×+×=

V

OUTS

⎟

–

⎟

R

L

⎠

referenced to –VS, the worst

L

= VS/2.

.

JA

–40 0–20 20 40 60 80 100 120

AMBIENT TEMPERATURE (°C)

, some of which is

OUT

2

OUT

R

L

JA

. In

07546-003

Rev. 0 | Page 4 of 16

AD8275

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF1

1

AD8275

–IN

2

TOP VIEW

3

+IN

(Not to Scale)

–V

4

S

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 REF1 Reference Pin. Sets the output voltage level (see the Reference section). 2 −IN Negative Input Pin. 3 +IN Positive Input Pin. 4 −VS Negative Supply Pin. 5 SENSE Sense Output Pin. Tie this pin to the OUT pin. 6 OUT Output Pin (Force Output). 7 +VS Positive Supply Pin. 8 REF2 Reference Pin. Sets the output voltage level (see the Reference section).

8

7

6

5

REF2

+V

S

OUT

SENSE

07546-001

Rev. 0 | Page 5 of 16

AD8275

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TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted.

300

14

12

10

8

HITS

6

4

2

7546-004

0

–600 –400 –200 0 200 400 600

OFFSET VO LTAGE (µV)

0

Figure 5. Typical Distribution of System Offset Voltage, Referred to Output

250

200

150

100

50

0

–50

–100

OFFSET VO LTAGE (µV)

–150

–200

–250

NORMALIZED AT 25°C, REP RESENTATI VE SAMPLES

–300

–40–200 20406080100120

TEMPERATURE ( °C)

Figure 8. Offset Voltage vs. Temperature, Normalized at 25°C,

Referred to Output

07546-007

70

60

50

40

HITS

30

20

10

0

–60 –40 –20 0 20 40 60

CMRR (µV/V)

Figure 6. Typical Distribution of CMRR, Referred to Output

60

40

20

0

CMRR (µV/V)

–20

–40

50

40

30

20

10

0

–10

GAIN ERROR (µV/ V)

–20

–30

–40

546-005 07

GAIN ERROR NORM ALIZ ED AT 25°C

–50

–45 –30 –15 0 15 30 45 60 75 90 105 120

TEMPERATURE ( °C)

07546-008

Figure 9. Gain Error vs. Temperature, Normalized at 25°C

5

4

3

2

QUIESCENT CURRENT (mA)

5V

3.3V

–60

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (° C)

Figure 7. CMRR vs. Temperature, Normalized at 25°C

07

Rev. 0 | Page 6 of 1

6

1

–50 –25

0

TEMPERATURE ( °C)

Figure 10. Quiescent Current vs. Temperature

546-006

25 50 75

100 125

07546-009

AD8275

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35

30

25

20

15

10

5

0

–5

–10

–15

INPUT COMMON-MODE VOLTAGE (V)

–20

–25

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5

OUTPUT VOL TAGE (V)

Figure 11. Input Common-Mode Voltage vs. Output Voltage, No Load

0

07546-010

120

100

80

60

40

20

POWER SUPPLY REJECTIO N (dB)

0

–20

100 1M100k10k1k

FREQUENCY (Hz)

Figure 14. Power Supply Rejection vs. Frequency, Referred to Output

6

07546-013

–5

–10

–15

–20

GAIN (dB)

–25

–30

–35

–40

1k100 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 12. Gain vs. Frequency

100

90

80

70

60

COMMON-MO DE REJECTION (dB)

50

40

100 1k 10k 100k 10M1M

FREQUENCY (Hz)

Figure 13. Common-Mode Rejection vs. Frequency, Referred to Input

5

4

3

2

1

MAXIMUM OUTPUT VOLTAGE (V p-p)

07546-011

0

1k100 10k 100k 1M 10M

FREQUENCY (Hz)

07546-014

Figure 15. Maximum Output Voltage vs. Frequency

20

15

10

5

0

–5

–10

GAIN NONLINEARITY (ppm)

–15

546-015

07546-012

–20

01234

OUTPUT VOLTAGE (V)

07

Figure 16. Gain Nonlinearity, RL = 600 Ω, 2 kΩ, 10 kΩ

Rev. 0 | Page 7 of 1

6

AD8275

V

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60

50

40

30

20

10

0

–10

–20

CURRENT (mA)

–30

–40

–50

–60

–70

–25–50 0 25 50 75 100 125

5V SOURCE

3.3V SOURCE

3.3V SINK

5V SINK

TEMPERATURE (° C)

Figure 17. Short-Circuit Current vs. Temperature, VS = 3.3 V, 5 V

+

S

–40°C

OUTPUT VOLTAGE SWING (V)

+VS– 0.2

+V

– 0.4

S

+V

– 0.6

S

+V

– 0.8

S

+V

– 1.0

S

–V

+ 1.0

S

–V

+ 0.8

S

–V

+ 0.6

S

(REFERRED TO SUPPLY RAIL S)

–V

+ 0.4

S

–V

+ 0.2

S

–V

+125° C

+125°C

–40°C

S

Figure 18. Output Voltage Swing vs. R

+85°C

+25°C

+85°C

+25°C

1k 10k100 100k

R

LOAD

()

LOAD

, VS = 5 V

+

S

+VS– 0.4

+125° C

+25°C

+85°C

+V

– 0.8

S

+V

– 1.2

S

+V

– 1.6

S

+V

– 2.0

S

–V

+ 2.0

S

–V

+ 1.6

S

–V

+ 1.2

S

OUTPUT VOL TAGE SWING (V)

(REFERRED TO SUPPLY RAILS)

–V

+ 0.8

S

–V

+ 0.4

S

–V

S

24681012140

OUTPUT CURRENT (mA)

Figure 19. Output Voltage Swing vs. Output Current, VS = 3.3 V

–40°C

+125°C

+25°C

–40°C

07546-016

07546-017

07546-018

+

OUTPUT VOL TAGE SWING (V)

+VS– 0.4

+V

S

+V

S

+V

S

+V

S

–V

S

–V

S

–V

S

(REFERRED TO SUPPLY RAILS)

–V

S

–V

S

– 0.8

– 1.2

– 1.6

– 2.0

+ 2.0

+ 1.6

+ 1.2

+ 0.8

+ 0.4

–V

S

+125° C

+25°C

S

2 4 6 8 1012140

OUTPUT CURRENT (mA)

+85°C

–40°C

+125°C

Figure 20. Output Voltage Swing vs. Output Current, VS = 5 V

1k

100

VOLTAGE NOISE DENSI TY (nV/ Hz)

10

1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 21. Voltage Noise Density vs. Frequency, Referred to Output

VOLTAGE NOISE (1µV/DIV)

TIME (1s/DIV)

Figure 22. 0.1 Hz to 10 Hz Voltage Noise, Referred to Output

+25°C

–40°C

07546-119

07546-019

6-020 0754

Rev. 0 | Page 8 of 16

AD8275

www.BDTIC.com/ADI

40

60

35

30

25

20

15

SLEW RATE (V/µs)

10

5

0

–40 –20 0 20 40 60 80 100 120

+SR

–SR

TEMPERATURE (° C)

Figure 23. Slew Rate vs. Temperature

C

= 47pF

LOAD

600

20mV/DIV

2k

NO LOAD

50

40

3.3V

30

5V

OVERSHOOT (%)

20

10

07546-021

0

0 20 40 60 80 100 120 140 160

CAPACITANCE (pF )

07546-024

Figure 26. Small Signal Overshoot vs. Capacitive Load,

No Resistive Load

60

50

40

30

OVERSHOOT (%)

20

3.3V

5V

10k

1µs/DIV

07546-022

Figure 24. Small Signal Step Response for Various Resistive Loads

(Step Responses Staggered for Clarity)

NO RESISTIVE LOAD

47pF

1µs/DIV

100pF

07546-023

20pF

NO CAP

20mV/DIV

Figure 25. Small Signal Pulse Response for Various Capacitive Loads

(Step Responses Staggered for Clarity)

10

0

0 20 40 60 80 100 120 140 160

CAPACITANCE (pF )

Figure 27. Small Signal Overshoot vs. Capacitive Load,

600 Ω in Parallel with Capacitive Load

60

50

40

30

OVERSHOOT (%)

20

10

0

0 20 40 60 80 100 120 140 160

3.3V

5V

CAPACITANCE (pF )

Figure 28. Small Signal Overshoot vs. Capacitive Load,

2 kΩ in Parallel with Capacitive Load

07546-025

07546-026

Rev. 0 | Page 9 of 16

AD8275

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1.0 V

= 4V p-p

OUT

10V/DIV

10mV/DIV

2µs/DIV

Figure 29. Large Signal Pulse Response and Settling Time, R

07546-027

= 2 kΩ

L

0.1

0.01

THD + N (%)

0.001

0.0001 10 100 10k1k 100k

Figure 30. THD + N vs. Frequency, V

FREQUENCY (Hz)

OUT

R

= 2k

L

= 4 V p-p

RL= 600

RL= 10k

07546-029

Rev. 0 | Page 10 of 16

AD8275

V

–

V

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD8275 level translates ±10 V signals at its inputs to 4 V at its output. It does this by attenuating the input signal by 5. A subtractor network performs the attenuation, the level shifting, and the differential-to-single-ended conversion. One benefit of the subtractor topology is that it can accept input signals beyond its supply voltage. The subtractor is composed of tightly matched resistors. By integrating the resistors and trimming the resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024% gain error.

+

S

SENSE

–V

S

+V

S

+V

S

OUT

–V

S

+V

S

+V

S

REF2

–V

S

+V

S

REF1

–V

S

6-030 0754

+IN

50k

INPUT

IN

ESD

7k

2.5V

–V

S

INPUT

ESD

50k

10k

+V

S

–V

S

–V

S

–V

S

20k

Figure 31. AD8275 Simplified Schematic

To achieve a wider input voltage range, the AD8275 uses an internal 2.5 V voltage bias tied to –V

and two 7 k resistors, as

S

shown in Figure 31. The resistors help to set the common mode of the internal amplifier. The benefit of this circuit is that it extends the input range without causing crossover distortion typical of amplifiers that have rail-to-rail complementary transistor inputs. The input range of the internal op amp is

− 0.9 V to −VS + 1.35 V.

+V

S

600

400

200

0

OFFSET (µV)

–200

–400

–600

–10 –8 –6

–4 –2 0 2 4 6 8 10

COMMON-MO DE VOLTAGE (V)

Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail

Input Amplifiers

07546-132

The AD8275 employs a balanced, high gain, linear output stage that adaptively generates current as required, eliminating the dynamic errors found in other amplifiers. This is useful when driving SAR ADCs, which can deliver kickback current into the output of the amplifier. The result is a design that achieves low distortion, consistent bandwidth, and high slew rate.

BASIC CONNECTION

The basic configurations for the AD8275 are shown in Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are tied together. A voltage, V REF2 pins, sets the output voltage level to V in Figure 33, if V

= 2 V and the inputs are tied to ground,

REF

the output remains at 2 V.

V

2

INN

3

V

INP

(V

) – (V

INP

=+V

OUT

Figure 33. Basic Configuration 1: Shared Reference

In contrast, Figure 34 shows REF1 tied to ground and REF2 tied to V

. In this example, the two 20 k resistors serve as a

REF

resistor divider, and V inputs of the AD8275 are grounded and V is 2.5 V.

50k

V

2

INN

–IN

50k

3

V

INP

+IN

AD8275

(V

V

=+

OUT

Figure 34. Basic Configuration 2: Split Reference

, applied to the tied REF1 and

REF

. For example,

REF

+5

+V

50k

–IN

50k

+IN

AD8275

5

INP

–V

)

INN

is divided by 2. For example, if both

REF

+5

7

+V

S

10k

20k

–V

S

4

) – (V

)5V

INN

7

S

10k

S

4

REF

20k

SENSE

0.1µF

SENSE

OUT

REF2

REF1

REF

0.1µF

OUT

REF2

REF1

+ 0V

2

5

6

V

8

1

= 5 V, the output

REF

5

6

V

REF

8

1

REF

V

OUT

07546-032

07546-031

Rev. 0 | Page 11 of 16

AD8275

50

R

REF1

1

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POWER SUPPLIES

Use a stable dc voltage to power the AD8275. Noise on the supply pins can adversely affect performance. Place a bypass capacitor of 0.1 µF between each supply pin and ground, as close to each pin as possible. A tantalum capacitor of 10 µF should also be used between each supply and ground. It can be farther away from the AD8275 and typically can be shared by other precision integrated circuits.

REFERENCE

The reference terminals are used to provide a bias level for the output. For example, in a single-supply 5 V operation, the reference terminals can be set so that the output is biased at

2.5 V. This ensures that the output can swing positive or negative around a 2.5 V level.

Figure 33 and Figure 34 illustrate two different ways to set the reference voltage. See the Basic Connection section for the differences between the two settings.

The allowable reference voltage range is a function of the common-mode input and supply voltages. The REF1 and REF2 pins should not exceed either +V

The REFx terminals should be driven by low source impedance because parasitic resistance in series with REF1 and REF2 can adversely affect CMRR and gain accuracy.

+V

S

7

50k

2

–IN

50k

3

+IN

AD8275

50k

2

–IN

50k

3

+IN

AD8275

SENSE

+V

10k

20k

–V

4

S

7

10k

20k

–V

4

S

OUT

REF2

REF1

SENSE

OUT

REF2

REF1

5

6

8

1

5

6

8

1

Figure 35. REF1 and REF2 Pin Guidelines

or −VS by more than 0.5 V.

S

INCORRECTCORRECT

+V

S

7

50k 10k

2

–IN

V

REF

V

REF

50k

3

+IN

AD8275

50k 10k

2

–IN

50k

3

+IN

AD8275

20k

–V

S

4

+V

S

7

20k

–V

S

4

SENSE

OUT

REF2

REF1

SENSE

OUT

REF2

REF1

5

6

V

REF

8

1

5

6

V

REF

8

1

07546-033

COMMON-MODE INPUT VOLTAGE RANGE

The common-mode voltage range is a function of the input voltage range of the internal op amp, the supply voltage, and the reference voltage.

Equation 1 expresses the maximum positive common-mode voltage range.

V

≤ 13.14(+VS) – 7.14(–VS) – 5((REF1 + REF2)/2) – 29.69 (1)

CM_POS

Equation 2 expresses the minimum common-mode voltage range.

≥ 6(–VS) – 5((REF1 + REF2)/2) – 0.11 (2)

V

CM_NEG

The voltage range of the internal op amp varies depending on temperature. The equations reflect a typical input voltage range of +V

− 0.9 V and −VS + 1.35 V over temperature. Tabl e 5 lists

S

expected common-mode ranges for typical configurations.

Table 5. Expected Common-Mode Voltage Range for Typical Configurations

+VS (V)1 V

(V) V

REF1

(V) VCM+ (V) VCM− (V)

REF2

5 5 0 23.5 −12.6 5 2.5 0 29.8 −6.4 5 4.096 0 25.8 −10.4

3.3 3.3 0 5.4 −8.4

3.3 2.5 0 7.4 −6.4 5 5 5 11.0 −25.1 5 4.096 4.096 15.5 −20.6 5 3 3 21.0 −15.1 5 2.5 2.5 23.5 −12.6 5 2.048 2.048 25.8 −10.4 5 1.25 1.25 29.8 −6.4 5 0 0 36.0 −0.1

1

–VS = 0 V.

INPUT PROTECTION

The inputs of the AD8275, +IN and −IN, are protected by ESD diodes that clamp 40 V above −V operating on a single +5 V supply, the ESD diode conducts at input voltages less than −35 V and greater than +40 V.

If the input voltage is expected to exceed the maximum ratings of the AD8275, use external transorbs. Adding series resistors to the inputs of the AD8275 is not recommended because the internal resistor ratios are matched to provide optimal CMRR and gain accuracy. Adding external series resistors to the input degrades the performance of the AD8275.

All other pins are protected by ESD diodes that clamp 0.5 V beyond either supply rail. For example, the voltage range of the REF1 and REF2 pins on a 5 V supply is −0.5 V to +5.5 V.

and 40 V below +VS. When

S

Rev. 0 | Page 12 of 16

AD8275

V

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CONFIGURATIONS

Figure 36 and Figure 37, along with Table 6 and Tabl e 7, provide examples of the possible input and output ranges for various supplies and reference voltages.

Note that Tab l e 6 and Ta b le 7 list the typical voltage range of the AD8275; these values do not reflect variation over process or temperature.

LINEAR V

HI

MID

LO

RANGE

+5

IN

2

V

INN

–IN

3

V

INP

+IN

AD8275

+V

50k

–V

7

S

10k

S

4

20k

0.1µF

SENSE

OUT

REF2

REF1

USEFUL V

HI

LO

5

6

8

1

OUT

+SWING

–SWING

V

OUT

V

REF

Figure 36. Split Reference Figure 37. Shared Reference

Table 6. Input and Output Relationships for Split Reference Configuration in Figure 36

Linear

V

+V

1

V

REF

S

V

OUT

= 0 V

IN

5 V 5 V 2.5 V

for

Differential

Range

V

IN

High: +12 V Mid: 0 V Low: −12.3 V

Useful V

OUT

Ranges

High: +4.95 V Swing: +2.45 V,

−2.455 V Low: +0.045 V

5 V 2.5 V 1.25 V

High: +18.3 V Mid: 0 V Low: −6 V

High: +4.95 V Swing: +3.7 V,

−1.205 V Low: +0.045 V

5 V 4.096 V 2.048 V

High: +14.3 V Mid: 0 V Low: −10 V

High: +4.95 V Swing: +2.902 V,

−2.003 V Low: +0.045 V

3.3 V 3.3 V 1.65 V

High: +8 V Mid: 0 V Low: −8 V

High: +3.24 V Swing: +1.59 V,

−1.605 V Low: +0.045 V

3.3 V 2.5 V 1.25 V

High: +10 V Mid: 0 V Low: −6 V

High: +3.24 V Swing: +1.99 V,

−1.205 V Low: +0.045 V

1

−VS = 0 V.

+5

LINEAR V

IN

RANGE

HI

MID

LO

2

V

INN

–IN

3

V

INP

+IN

AD8275

07546-136

+V

50k

–V

7

S

10k

S

4

20k

0.1µF

SENSE

OUT

REF2

REF1

USEFUL V

HI

LO

5

6

8

1

OUT

+SWING

–SWING

V

OUT

V

REF

07546-137

Table 7. Input and Output Relationships for Shared Reference Configuration in Figure 37

Linear

V

for

+V

1

V

S

REF

V

OUT

= 0 V

IN

5 V 5 V 5 V

5 V 4.096 V 4.096 V

Differential

Range

V

IN

High: −0.1 V Mid: 0 V Low: −24.7 V

High: +4.4 V Mid: 0 V Low: −20.2 V

Useful V

OUT

Ranges

High: +4.98 V Swing: −4.94 V Low: +0.06 V

High: +4.98 V Swing: +0.884 V to −4.03 V Low: +0.06 V

5 V 3 V 3 V

High: +9.5 V Mid: 0 V Low: −14.8 V

High: +4.95 V Swing: +1.9 V,

−2.955 V Low: +0.045 V

5 V 2.5 V 2.5 V

High: +12 V Mid: 0 V Low: −12.3 V

High: +4.95 V Swing: +2.45 V,

−2.455 V Low: +0.045 V

5 V 2.048 V 2.048 V

High: +14.3 V Mid: 0 V Low: −10 V

High: +4.95 V Swing: +2.902 V,

−2.003 V Low: +0.045 V

5 V 1.25 V 1.25 V

+18.3 V to

−6 V

High: +4.95 V Swing: +3.7 V,

−1.205 V Low: +0.045 V

0 V 0 V 0 V 24.5 V to 0.2 V

High: 4.95 V Swing: 4.95 V Low: 0.045 V

1

−VS = 0 V.

Rev. 0 | Page 13 of 16

AD8275

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APPLICATIONS INFORMATION

DRIVING A SINGLE-ENDED ADC

The AD8275 provides the common-mode rejection that SAR ADCs often lack. In addition, it enables designers to use costeffective, precision, 16-bit ADCs such as the AD7685, yet still condition ±10 V signals.

One important factor in selecting an ADC driver is its ability to settle within the acquisition window of the ADC. The AD8275 is able to drive medium speed SAR ADCs.

In Figure 38, the 2.7 nF capacitor serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 33  series resistor reduces the burden of the 2.7 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7685. The output impedance of the amplifier can affect the THD of the ADC. In this case, the combined impedance of the 33  resistor and the output impedance of the AD8275 provides extremely low THD of −112 dB. Figure 39 shows the ac response of the AD8275 driving the AD7685.

+5

+V

50k

2

–IN

50k

3

VIN

+IN

AD8275

–V

Figure 38. Driving a Single-Ended ADC

7

S

10k

S

4

20k

0.1µF

SENSE

OUT

REF2

REF1

0.1µF

5

33

6

2.7nF

8

1

VREF (ADR444,

IN+

IN–

ADR445)

+5

VDD

AD7685

GNDREF

10µF

0.1µF

10

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

–100 –110

ADC FULL SCALE (dB)

–120 –130 –140 –150 –160 –170

01 4 7 10

258

369

FREQUENCY (kHz)

07546-139

Figure 39. FFT of AD8275 Directly Driving the AD7685 Using the 5 V

Reference of the Evaluation Board (Input = 20 V p-p, 1 kHz, THD = −112 dB)

The AD8275 can condition signals for higher resolution ADCs such as 18-bit SAR converters, provided that a narrower bandwidth is sampled to limit noise.

DIFFERENTIAL OUTPUTS

In certain applications, it is necessary to create a differential signal. For example, high resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference.

Figure 40 shows how to configure the AD8275 to output a differential signal. The AD8655 op amp is used in an inverting topology to create a differential voltage. VREF sets the output midpoint. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by

07546-034

differential input ADCs or by instrumentation amplifiers.

When using this circuit to drive a differential ADC, V

can be

REF

set using a resistor divider from the ADC reference to make the output ratiometric with the ADC.

7

+V

S

50k

2

–IN

10

50k

3

+IN

AD8275

10k

20k

–V

S

4

SENSE

OUT

REF2

REF1

5

6

2k

8

1

2k

8.2µF

+V

AD8655

V

0.1µF

–V

REF

+5V

OUT

+4.5V

+2.5V

+0.5V

= 2.5V

+4.5V

+2.5V

+0.5V

Figure 40. AD8275 Configured for Differential Output (for Driving a Differential ADC)

Rev. 0 | Page 14 of 16

07546-035

AD8275

V

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INCREASING INPUT IMPEDANCE

In applications where a high input impedance is needed, low input bias current op amps can be used to buffer the AD8275. In Figure 41, an AD8620 is used to provide high input impedance. Input bias current is limited to 10 pA.

+5V

+13V

3

2

6

5

8

AD8620

1/2

AD8620

4

–13V

2/2

0.1µF

+V

1

7

50k

2

–IN

50k

3

+IN

AD8275

–V

INVERTING

INPUT

NON-

INVERTING

INPUT

Figure 41. Adding Op Amp Buffers for High Input Impedance

7

S

10k

20k

S

4

0.1µF

SENSE

OUT

REF2

REF1

5

6

8

1

V

OUT

V

REF

AC COUPLING

An integrator can be tied to the AD8275 in feedback to create a high-pass filter as shown in Figure 42. This circuit can be used to reject dc voltages and offsets. At low frequencies, the impedance of the capacitor, C, is high. Thus, the gain of the integrator is high. DC voltage at the output of the AD8275 is inverted and gained by the integrator. The inverted signal is injected back into the REFx pins, nulling the output. In contrast, at high frequencies, the integrator has low gain because the impedance of C is low. Voltage changes at high frequencies are inverted but at a low gain. The signal is injected into the REFx pins but it is not enough to null the output. High frequency signals are, therefore, allowed to pass.

When a signal exceeds f conditioned input signal.

+5

, the AD8275 outputs the

HIGH-PASS

0.1µF

07546-036

USING THE AD8275 AS A LEVEL TRANSLATOR IN A DATA ACQUISITION SYSTEM

Signal size varies dramatically in some data acquisition applications. Instrumentation amplifiers, such as the AD8253, AD8228, or AD8221, are often used at the inputs to provide CMRR and high input impedance. However, the instrumentation amplifiers output ±10 V signals and the ADC full scale is 5 V or 4.096 V. In Figure 43, the AD8275 serves as a level translator between the in-amp and the ADC. The AD8275, along with the AD8228 and the AD8253, have very low gain drift because all gain setting resistors are internal and laser-trimmed.

+5

+V

50k

2

–IN

+15V

–15V

IN-AMP

0.1µF

50k

3

+IN

AD8275

–V

Figure 43. Level Translation in a Data Acquisition System

7

S

4

10k

20k

0.1µF

SENSE

OUT

REF2

REF1

0.1µF

5

33

6

2.7nF

8

1

VREF

+IN

–IN

10µF

VCC

ADC

GNDREF

07546-143

50k

2

–IN

50k

3

+IN

AD8275

7

+V

S

10k

20k

–V

S

4

SENSE

OUT

REF2

REF1

5

6

8

1

0.1µF

OUT

V

f

HIGH- PASS

C

OP

AMP

+5V

=

2RC

R

V

REF

1

V

OUT

07546-037

Figure 42. AC-Coupled Level Translator

Rev. 0 | Page 15 of 16

AD8275

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8° 0°

0.80

0.60

0.40

3.20

3.00

2.80

PIN 1

.95 .85 .75

0.15

0.00

COPLANARITY

0.10

1

0.65 BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO -187-AA

Figure 44. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8275ARMZ AD8275ARMZ-R71 −40°C to +85°C 8-Lead MSOP, Tape and Reel RM-8 Y13 AD8275ARMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y13 AD8275BRMZ1 −40°C to +85°C 8-Lead MSOP RM-8 Y1V AD8275BRMZ-R71 −40°C to +85°C 8-Lead MSOP, Tape and Reel RM-8 Y1V AD8275BRMZ-RL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1V

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 8-Lead MSOP RM-8 Y13

Rev. 0 | Page 16 of 16

ANALOG DEVICES AD8275 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

PIN CONFIGURATION

TYPICAL APPLICATION

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

MAXIMUM POWER DISSIPATION

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

BASIC CONNECTION

POWER SUPPLIES

REFERENCE

COMMON-MODE INPUT VOLTAGE RANGE

INPUT PROTECTION

CONFIGURATIONS

APPLICATIONS INFORMATION

DRIVING A SINGLE-ENDED ADC

DIFFERENTIAL OUTPUTS

INCREASING INPUT IMPEDANCE

AC COUPLING

USING THE AD8275 AS A LEVEL TRANSLATOR IN A DATA ACQUISITION SYSTEM

OUTLINE DIMENSIONS

ORDERING GUIDE