ANALOG DEVICES AD8251 Service Manual

10 MHz, 20 V/μs, G = 1, 2, 4, 8 iCMOS

Programmable Gain Instrumentation Amplifier

FEATURES

Small package: 10-lead MSOP
Programmable gains: 1, 2, 4, 8
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance

High CMRR: 98 dB (minimum), G = 8
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.8 V/°C (maximum), G = 8

Excellent ac performance

Fast settling time: 785 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz, 10 V swing
High CMRR over frequency: 80 dB to 50 kHz (minimum)
Low noise: 18 nV/√Hz, G = 8 (maximum)
Low power: 4.1 mA

APPLICATIONS

Data acquisition
Biomedical analysis
Test and measurement

GENERAL DESCRIPTION

The AD8251 is an instrumentation amplifier with digitally
programmable gains that has GΩ input impedance, low output
noise, and low distortion, making it suitable for interfacing with
sensors and driving high sample rate analog-to-digital converters
(ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB,
and fast settling time of 785 ns (maximum) to 0.001%. Offset
drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C,
respectively, for G = 8. In addition to its wide input common
voltage range, it boasts a high common-mode rejection of 80 dB
at G = 1 from dc to 50 kHz. The combination of precision dc
performance coupled with high speed capabilities makes the
AD8251 an excellent candidate for data acquisition. Furthermore,
this monolithic solution simplifies design and manufacturing
and boosts performance of instrumentation by maintaining a
tight match of internal resistors and amplifiers.

The AD8251 user interface consists of a parallel port that allows
users to set the gain in one of two ways (see Figure 1). A 2-bit word
sent via a bus can be latched using the
to use the transparent gain mode where the state of the logic
levels at the gain port determines the gain.

WR

input. An alternative is

AD8251

FUNCTIONAL BLOCK DIAGRAM

A1 A0DGND WR

4562

1

–IN

10

+IN

8 3

+V

25

20

15

10

5

GAIN (dB)

0

–5

–10

1k 100M

Table 1. Instrumentation Amplifiers by Category

General
Purpose

AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624

1

Rail-to-rail output.

Zero Drift

The AD8251 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.

LOGIC

AD8251

S

10k 100k 1M 10M

–V

S

Figure 1.

G = 8

G = 4

G = 2

G = 1

FREQUENCY (Hz)

Figure 2. Gain vs. Frequency

Mil
Grade

Low
Power

REF

9

7

OUT

High Speed
PGA

06287-001

06287-002

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2010 Analog Devices, Inc. All rights reserved.

AD8251

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagram........................................................................... 5

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation..................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 16

Gain Selection ............................................................................. 16

Power Supply Regulation and Bypassing ................................ 18

Input Bias Current Return Path ............................................... 18

Input Protection ......................................................................... 18

Reference Terminal .................................................................... 19

Common-Mode Input Voltage Range..................................... 19

Layout .......................................................................................... 19

RF Interference........................................................................... 20

Driving an ADC ......................................................................... 20

Applications..................................................................................... 21

Differential Output .................................................................... 21

Setting Gains with a Microcontroller...................................... 21

Data Acquisition......................................................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

11/10—Rev. A to Rev. B

Changes to Voltage Offset, Offset RTI V

Parameter in Table 2......................................................................... 3

Updated Outline Dimensions....................................................... 23

5/08—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 1

, Average TC

OS

Changes to Table 2.............................................................................3

Changes to Table 3.............................................................................6

Inserted Figure 17; Renumbered Sequentially ..............................9

Inserted Figure 29........................................................................... 11

Changes to Timing for Latched Gain Mode Section ................. 17

5/07—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD8251

SPECIFICATIONS

+VS = 15 V, −VS = −15 V, V

Table 2.

Parameter Conditions Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR)

CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V

G = 1 80 98 dB
G = 2 86 104 dB
G = 4 92 110 dB
G = 8 98 110 dB

CMRR to 50 kHz +IN = −IN = −10 V to +10 V

G = 1 80 dB
G = 2 84 dB
G = 4 86 dB
G = 8 86 dB

NOISE

Voltage Noise, 1 kHz, RTI

G = 1 40 nV/√Hz
G = 2 27 nV/√Hz
G = 4 22 nV/√Hz
G = 8 18 nV/√Hz

0.1 Hz to 10 Hz, RTI
G = 1 2.5 μV p-p
G = 2 2.5 μV p-p
G = 4 1.8 μV p-p
G = 8 1.2 μV p-p

Current Noise, 1 kHz 5 pA/√Hz
Current Noise, 0.1 Hz to 10 Hz 60 pA p-p

VOLTAGE OFFSET

Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV

Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV
Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C

Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V

INPUT CURRENT

Input Bias Current 5 30 nA

Over Temperature T = −40°C to +85°C 40 nA
Average TC T = −40°C to +85°C 400 pA/°C

Input Offset Current 5 30 nA

Over Temperature T = −40°C to +85°C 30 nA
Average TC T = −40°C to +85°C 160 pA/°C

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 10 MHz
G = 2 10 MHz
G = 4 8 MHz
G = 8 2.5 MHz

Settling Time 0.01% ΔOUT = 10 V step

G = 1 615 ns
G = 2 460 ns
G = 4 460 ns
G = 8 625 ns

= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.

REF

Rev. B | Page 3 of 24

AD8251

Parameter Conditions Min Typ Max Unit

Settling Time 0.001% ΔOUT = 10 V step

G = 1 785 ns
G = 2 700 ns
G = 4 700 ns
G = 8 770 ns

Slew Rate

G = 1 20 V/μs
G = 2 30 V/μs
G = 4 30 V/μs
G = 8 30 V/μs

Total Harmonic Distortion + Noise

f = 1 kHz, R

= 10 kΩ, ±10 V,

L

G = 1, 10 Hz to 22 kHz band­pass filter

GAIN

Gain Range G = 1, 2, 4, 8 1 8 V/V
Gain Error OUT = ±10 V

G = 1 0.03 %
G = 2, 4, 8 0.04 %

Gain Nonlinearity OUT = −10 V to +10 V

G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 9 ppm
G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm
G = 4 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm
G = 8 RL = 10 kΩ, 2 kΩ, 600 Ω 15 ppm

Gain vs. Temperature All gains 3 10 ppm/°C

INPUT

Input Impedance

Differential 5.3||0.5
Common Mode 1.25||2

Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V
Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.7 V

OUTPUT

Output Swing −13.5 +13.5 V
Over Temperature T = −40°C to +85°C −13.5 +13.5 V
Short-Circuit Current 37 mA

REFERENCE INPUT

RIN 20 kΩ
IIN +IN, −IN, REF = 0 1 μA
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V

DIGITAL LOGIC

Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V
Digital Input Voltage Low Referred to GND DGND 2.1 V
Digital Input Voltage High Referred to GND 2.8 +VS V
Digital Input Current 1 μA
Gain Switching Time1 325 ns
t

See Figure 3 timing diagram 20 ns

SU

tHD See Figure 3 timing diagram 10 ns
t

-LOW

WR

t

-HIGH

WR

See Figure 3 timing diagram 20 ns
See Figure 3 timing diagram 40 ns

−110 dB

GΩ||pF
GΩ||pF

Rev. B | Page 4 of 24

AD8251

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range ±5 ±15 V
Quiescent Current, +IS 4.1 4.5 mA
Quiescent Current, −IS 3.7 4.5 mA
Over Temperature T = −40°C to +85°C 4.5 mA

TEMPERATURE RANGE

Specified Performance −40 +85 °C

1

Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM

WR

t

WR-HIGH

t

WR-LOW

A0, A1

t

SU

t

HD

6287-003

Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

Rev. B | Page 5 of 24

AD8251

(

)

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±17 V
Power Dissipation See Figure 4
Output Short-Circuit Current Indefinite1
Common-Mode Input Voltage +VS + 13 V to −VS − 13 V
Differential Input Voltage +VS + 13 V, −VS − 13 V2
Digital Logic Inputs ±VS
Storage Temperature Range −65°C to +125°C

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some in the load (V

The difference between the total drive power and the load
power is the drive power dissipated in the package.

Operating Temperature Range3 −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 140°C
θJA (Four-Layer JEDEC Standard Board) 112°C/W
Package Glass Transition Temperature 140°C

1

Assumes the load is referenced to midsupply.

2

Current must be kept to less than 6 mA.

3

Temperature for specified performance is −40°C to +85°C. For performance

to +125°C, see the Typical Performance Characteristics section.

In single-supply operation with R
case is V

Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum

reduces the θ

Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a four-layer JEDEC
standard board.

rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8251 package is
limited by the associated rise in junction temperature (T
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8251. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.

The still air thermal properties of the package and PCB (θ
the ambient temperature (T
the package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in

A

The junction temperature is calculated as

θPTT ×+=

J

D

A

JA

) on

J

JA

),

ESD CAUTION

). Assuming the load (RL) is referenced to

S

= Quiescent Power + (Total Drive Power − Load Power)

P

D

⎛

V

V

OUTS

()

D

= VS/2.

OUT

2.00

1.75

1.50

1.25

1.00

0.75

0.50

MAXIMUM POWER DISSIPATI ON (W)

0.25

0

–40 –20 120100806040200

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

⎜

IVP

SS

.

JA

×+×=

⎜

R

2

⎝

L

AMBIENT TEM P E RATURE (°C)

) is the sum of the

D

) times the

S

/2 × I

S

⎞

V

OUT

⎟

–

⎟

R

⎠

referenced to −VS, the worst

L

, some of which is

OUT

2

L

OUT

× I

OUT

JA

).

. In

06287-004

Rev. B | Page 6 of 24

AD8251

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

1
2

DGND

–V

A0
A1

3

S

4
5

AD8251

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Inverting Input Terminal. True differential input.
2 DGND Digital Ground.
3 −VS Negative Supply Terminal.
4 A0 Gain Setting Pin (LSB).
5 A1 Gain Setting Pin (MSB).
6

WR

Write Enable.
7 OUT Output Terminal.
8 +VS Positive Supply Terminal.
9 REF Reference Voltage Terminal.
10 +IN Noninverting Input Terminal. True differential input.

10

+IN

9

REF
+V

8

S

7

OUT

6

WR

06287-005

Rev. B | Page 7 of 24

AD8251

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.

2700

2400

2100

1800

1500

1200

900

NUMBER OF UNIT S

600

300

0

–120 –90 –60 –30 0 30 60 90

CMRR (µV/V)

Figure 6. Typical Distribution of CMRR, G = 1

500

400

300

200

NUMBER OF UNIT S

100

0

–200 –100

INPUT OFFSET VOLTAGE, V

OSI

Figure 7. Typical Distribution of Offset Voltage, V

, RTI (µV)

06287-006

120

06287-007

2001000

OSI

800

700

600

500

400

300

NUMBER OF UNIT S

200

100

0

–30 –10–20

INPUT OFFSET CURRENT (nA)

Figure 9. Typical Distribution of Input Offset Current

90

80

70

60

50

40

NOISE (nV/Hz)

30

20

10

0

1 100k

10 100 1k 10k

FREQUENCY (Hz)

G = 1

G = 2
G = 4

G = 8

Figure 10. Voltage Spectral Density Noise vs. Frequency

06287-009

3020100

06287-010

800

600

400

NUMBER OF UNIT S

200

0

–30 –10–20

INPUT BIAS CURRENT ( nA)

Figure 8. Typical Distribution of Input Bias Current

06287-008

3020100

Rev. B | Page 8 of 24

1s/DIV2µV/DIV

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

6287-011

AD8251

150

1.25µV/DI V

1s/DIV

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 8

18

16

14

12

10

8

NOISE (pA/Hz)

6

4

2

0

1 100k

10 100 1k 10k

FREQUENCY (Hz)

Figure 13. Current Noise Spectral Density vs. Frequency

1s/DIV140pA/DIV

Figure 14. 0.1 Hz to 10 Hz Current Noise

130

110

90

G = 1

70

PSRR (dB)

50

30

6287-012

10

10 1M

100 1k 10k 100k

FREQUENCY (Hz)

Figure 15. Positive PSRR vs. Frequency, RTI

150

130

110

90

G=1

70

PSRR (dB)

50

30

06287-013

10

10 1M

100 1k 10k 100k

FREQUENCY (Hz)

Figure 16. Negative PSRR vs. Frequency, RTI

10

9

8

7

6

5

4

3

2

1

CHANGE IN OFFSET VOLTAGE, RTI (µV)

6287-014

0

0.01
WARM-UP TIME (minutes)

Figure 17. Change in Offset Voltage, RTI vs. Warmup Time

G = 8

G=2

G=4

G = 4

10.1

G=8

G = 2

06287-016

06287-017

10

06287-117

Rev. B | Page 9 of 24

AD8251

20

15

15

10

5

0

–5

–10

INPUT BIAS CURRENT AND OFFSET CURRENT (nA)

–60 140

–40 –20 0 20 40 60 80 120100

IB+

I

OS

TEMPERATURE (ºC)

I

–

B

Figure 18. Input Bias Current and Offset Current vs. Temperature

140

120

100

CMRR (dB)

80

60

G = 2

G = 4

G = 8

G = 1

10

5

0

CMRR (µV/V)

–5

–10

06287-019

–15

–50 130

–30 –10 10 30 50 70 90 110

TEMPERATURE (° C)

06287-022

Figure 21. ΔCMRR vs. Temperature, G = 1

25

20

15

10

5

GAIN (dB)

0

–5

G = 8

G = 4

G = 2

G = 1

VS = ±15V

= 200mV p-p

V

IN

= 2k

R

L

40

10

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 19. CMRR vs. Frequency

140

120

G = 8

100

G = 4

CMRR (dB)

80

60

40

G = 2

G = 1

10 1M

100 1k 10k 100k

FREQUENCY (Hz)

Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance

06287-020

–10

1k 100M

10k 100k 1M 10M

FREQUENCY (Hz)

06287-023

Figure 22. Gain vs. Frequency

40

30

20

10

0

–10

–20

GAIN NONL INEARITY (10ppm/DIV)

–30

06287-021

–40

–10–8–6–4–20246810

OUTPUT VOLTAGE ( V)

Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, R

= 10 kΩ, 2 kΩ, 600 Ω

L

06287-024

Rev. B | Page 10 of 24

AD8251

40

30

20

10

0

–10

–20

GAIN NONLINEARITY (10ppm/DIV)

–30

–40

–10–8–6–4–20246810

OUTPUT VOLTAGE ( V)

Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, R

40

30

20

10

0

–10

–20

GAIN NONLINEARITY (10ppm/DIV)

–30

–40

–10–8–6–4–20246810

OUTPUT VOLTAGE ( V)

Figure 25. Gain Nonlinearity vs. Output Voltage, G = 4, R

40

30

20

10

0

–10

–20

GAIN NONLINEARITY ( 10p pm/DIV)

–30

–40

–10–8–6–4–20246810

OUTPUT VOLTAGE ( V)

Figure 26. Gain Nonlinearity vs. Output Voltage, G = 8, R

06287-025

= 10 kΩ, 2 kΩ, 600 Ω

L

06287-026

= 10 kΩ, 2 kΩ, 600 Ω

L

06287-027

= 10 kΩ, 2 kΩ, 600 Ω

L

16

12

–14.2V, +7.1V

8

4

0

–4

–8

COMMON-MODE VOLTAGE (V)

–12

–14.2V, –7.1V +14V, –7V

–16

–16 16

–4V, +2.2V

–12 –8 –4 0 4 8 12

0V, +13.5V

0V, ±15V

0V, +3.85V

VS= ±5V

–4V, –2V

0V, –3.9V

0V, –13.5V

OUTPUT VOLTAGE (V)

+14V, +7V

+4V, +2V

+4V, –2V

06287-028

Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1

16

–13V, +13.5V

12

8

4

0

–4

–8

COMMON-MODE VOLTAGE (V)

–12

–13V, –13.1V

–16

–16 16

–4V, +4V

–4V, –3.9V

–12 –8 –4 0 4 8 12

0V, +13.5V

VS ±15V

0V, +4V

+4V, +3. 9V

VS= ±5V

0V, –3.9V

0V, –13.5V

OUTPUT VOLTAGE (V)

+4V, –4V

+13V, +13V

+13V, –13.5V

06287-029

Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 8

35

IB+

–

I

30

25

20

15

10

5

0

INPUT BIAS CURRENT AND OFFSET CURRENT (nA)

–15 –5–10 5010

B

I

OS

COMMON-MODE VOLT AG E ( V)

06287-129

15

Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage

Rev. B | Page 11 of 24

AD8251

V

V

V

V

+

S

–1

–2

INPUT VOLTAGE (V)

+2

REFERRED TO SUPPLY VOLTAGES

+1

–V

S

41

6 8 10 12 14

+85°C

+25°C

+125°C

SUPPLY VOLT AG E ( ±VS)

–40°C

+125°C

–40°C

+25°C

+85°C

Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, V

15

10

FAULT CONDI TION

(OVER DRIVEN INPUT)

5

0

CURRENT (mA)

–5

–10

–15

–16 16

G = 8

–12 –8 –4 0 4 8 12

DIFFERENTIAL INPUT V OLTAGE ( V )

FAULT CONDI TION

(OVER DRIVEN INPUT)

G = 8

Figure 31. Fault Current Draw vs. Input Voltage, G = 8, R

+

S

–0.2
–0.4
–0.6
–0.8
–1.0

1.0

0.8

OUTPUT VOLT AG E S WING (V)

0.6

REFERRED TO SUPPLY VOLTAGES

0.4

0.2

–V

S

41

+

8

5

°

C

–40°C

+25°C

–40°C

+

8

5

°

C

6 8 10 12 14

SUPPLY VOLTAGE (±VS)

+125°C

+25°C

+125°C

Figure 32. Output Voltage Swing vs. Supply Voltage, G = 8, R

= 0 V, RL = 10 kΩ

REF

+V

S

+IN

–IN

–V

S

= 10 kΩ

L

= 2 kΩ

L

06287-030

6

06287-031

06287-032

6

+

S

–0.2
–0.4
–0.6
–0.8
–1.0

1.0

0.8

OUTPUT VOLT AG E S WING (V)

0.6

REFERRED TO SUPPLY VOLTAGES

0.4

0.2

–V

S

41

+85°C

–40°C

–40°C

+125°C

6 8 10 12 14

SUPPLY VOLTAGE (±VS)

Figure 33. Output Voltage Swing vs. Supply Voltage, G = 8, R

+125°C

+

5

2

5

+

2

°

C

°

C

+85°C

06287-033

6

= 10 kΩ

L

15

+25°C

+85°C

10

5

0

–5

OUTPUT VOLTAGE SWING (V)

–40°C

–10

+25°C

–15

100 10k

–40°C

+125°C

+125°C

+85°C

1k

LOAD RESIST ANCE ()

06287-034

Figure 34. Output Voltage Swing vs. Load Resistance

+

S

–0.4
–0.8
–1.2
–1.6
–2.0

2.0

1.6

1.2

OUTPUT VOLTAGE SWING (V)

0.8

REFERRED TO SUPPLY VOLTAGES

0.4

–V

+85°C

+25°C

+25°C

+85°C

S

41

+125°C

–40°C

–40°C

+125°C

6 8 10 12 14

OUTPUT CURRENT (mA)

06287-035

6

Figure 35. Output Voltage Swing vs. Output Current

Rev. B | Page 12 of 24

AD8251

47pF

100pF

2µs/DIV20mV/DIV

06287-036

NO

LOAD

Figure 36. Small Signal Pulse Response for Various Capacitive Loads

5V/DIV

585ns TO 0.01%

0.002%/DIV

723ns TO 0.001%

5V/DIV

376ns TO 0.01%

0.002%/DIV

640ns TO 0.001%

2µs/DIV

Figure 39. Large Signal Pulse Response and Settling Time,

= 10 kΩ

G = 4, R

L

5V/DIV

364ns TO 0.01%

0.002%/DIV

522ns TO 0.001%

06287-039

2µs/DIV

Figure 37. Large Signal Pulse Response and Settling Time,

= 10 kΩ

G = 1, R

L

5V/DIV

400ns TO 0.01%

0.002%/DIV

600ns TO 0.001%

2µs/DIV

Figure 38. Large Signal Pulse Response and Settling Time,

G = 2, R

= 10 kΩ

L

06287-037

2µs/DIV

06287-040

Figure 40. Large Signal Pulse Response and Settling Time,

= 10 kΩ

G = 8, R

L

06287-038

25mV/DIV 2µs/DIV

06287-041

Figure 41. Small Signal Response,

= 2 kΩ, CL = 100 pF

G = 1, R

L

Rev. B | Page 13 of 24

AD8251

1200

1000

25mV/DIV 2µs/DIV

Figure 42. Small Signal Response,

= 2 kΩ, CL = 100 pF

G = 2, R

L

25mV/DIV 2µs/DIV

Figure 43. Small Signal Response,

G = 4, R

= 2 kΩ, CL = 100 pF

L

800

600

TIME (ns)

400

200

06287-042

0

22

Figure 45. Settling Time vs. Step Size, G = 1, R

SETTL ED TO 0.001%

SETTL E D TO 0.01%

4 6 8 1012141618

STEP SIZE (V)

= 10 kΩ

L

06287-045

0

1200

1000

800

600

TIME (ns)

400

200

06287-043

0

22

4 6 8 1012141618

Figure 46. Settling Time vs. Step Size, G = 2, R

SETTL E D TO 0.001%

SETTL E D TO 0.01%

STEP SIZE (V)

= 10 kΩ

L

06287-046

0

1200

25mV/DIV 2µs/DIV

Figure 44. Small Signal Response,

G = 8, R

= 2 kΩ, CL = 100 pF

L

06287-044

Rev. B | Page 14 of 24

1000

800

600

TIME (ns)

400

200

0

22

4 6 8 1012141618

Figure 47. Settling Time vs. Step Size, G = 4, R

SETTLED TO 0. 00 1%

SETTL E D TO 0.01%

STEP SIZE (V)

= 10 kΩ

L

06287-047

0

AD8251

–

–

1200

1000

800

600

TIME (ns)

400

200

SETTL ED TO 0.001%

SETTL E D TO 0.01%

0

22

4 6 8 1012141618

STEP SIZE (V)

Figure 48. Settling Time vs. Step Size, G = 8, R

50
–55
–60
–65
–70
–75
–80
–85
–90

THD + N (dB)

–95

–100
–105
–110
–115
–120

10 1M

G = 8

G = 4

G = 1

100 1k 10k 100k

G = 2

FREQUENCY (Hz)

Figure 49. Total Harmonic Distortion + Noise vs. Frequency,

10 Hz to 22 kHz Band-Pass Filter, R

= 2 kΩ

L

= 10 kΩ

L

50
–55
–60
–65
–70
–75
–80

G = 8

–85
–90

THD + N (dB)

–95

–100
–105
–110

06287-048

0

–115
–120

10 1M

G = 4

G = 1

100 1k 10k 100k

FREQUENCY (Hz)

Figure 50. Total Harmonic Distortion + Noise vs. Frequency,

10 Hz to 500 kHz Band-Pass Filter, R

06287-049

G = 2

= 2 kΩ

L

06287-050

Rev. B | Page 15 of 24

AD8251

–

V

V

V

V

THEORY OF OPERATION

+

S

+V

S

2.2k

IN

–V

S

+V

S

+IN

2.2k

–V

S

The AD8251 is a monolithic instrumentation amplifier based
on the classic 3-op-amp topology, as shown in Figure 51. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS®
process that provides precision, linear performance, and a
robust digital interface. A parallel interface allows users to
digitally program gains of 1, 2, 4, and 8. Gain control is achieved
by switching resistors in an internal, precision resistor array (as
shown in Figure 51). Although the AD8251 has a voltage feedback
topology, the gain bandwidth product increases for gains of 1, 2,
and 4 because each gain has its own frequency compensation.
This results in maximum bandwidth at higher gains.

All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser trimmed
resistors allow for a maximum gain error of less than 0.03%
for G = 1 and minimum CMRR of 98 dB for G = 8. A pinout
optimized for high CMRR over frequency enables the AD8251
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 50 kHz (G = 1). The balanced input reduces the parasitics
that, in the past, adversely affected CMRR performance.

GAIN SELECTION

Logic low and logic high voltage limits are listed in the
Specifications section. Typically, logic low is 0 V and logic high
is 5 V; both voltages are measured with respect to DGND. See
Tabl e 2 for the permissible voltage range of DGND. The gain of
the AD8251 can be set using two methods.

–V

S

A1

DIGITAL
GAIN
CONTROL

A2

+V

S

WR

–V

S

Figure 51. Simplified Schematic

2.2k

2.2k

+

S

A1A0

–V

S

10k 10k

+V

S

OUT

–V

S

+V

S

REF

–V

S

6287-061

+V

–V

10k

S

S

A3

10k

DGND

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 52
shows an example of this gain setting method, referred to through-

WR

out the data sheet as transparent gain mode. Tie

to the negative
supply to engage transparent gain mode. In this mode, any change
in voltage applied to A0 and A1 from logic low to logic high, or
vice versa, immediately results in a gain change. is the
truth table for transparent gain mode, and shows the

Tabl e 5

Figure 52

AD8251 configured in transparent gain mode.

+15

10F0.1µF

+IN

WR

–15V

A1

+5V

A0

+5V
G = 8

AD8251

REF

–IN

10F0.1µF

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO 
THE VOLTAGE LEVE LS ON A0 AND A1 DETERM INE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 8.

DGND DGND

–15V

.

S

Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 8

6287-051

Rev. B | Page 16 of 24

AD8251

V

Table 5. Truth Table Logic Levels for Transparent Gain Mode

A1 A0 Gain

WR

−VS Low Low 1

−VS Low High 2

−VS High Low 4

−VS High High 8

Latched Gain Mode

Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a

WR

data bus. The gain of the AD8251 can be set using
allowing other devices to share A0 and A1. shows a

Figure 53

as a latch,

schematic using this method, known as latched gain mode. The
AD8251 is in this mode when

WR

is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the

WR

signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table in

for more information on these gain changes. Tabl e 6

+15

10F0.1µF

+IN

WR

+

A1

A0

G = PREVIOUS
STATE

WR

A1

A0

+5V
0V

+5V
0V

+5V
0V

G = 8

AD8251

–IN

10F0.1µF

NOTE:

1. ON THE DO WNWARD EDGE OF WR, AS IT TRANSITI ONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RES ULTING I N A
GAIN CHANGE. IN THIS EX AM PLE, THE GAIN SWITCHES TO G = 8.

–

–15V

Figure 53. Latched Gain Mode, G = 8

REF

DGND DGND

06287-052

t

WR-HIGH

Table 6. Truth Table Logic Levels for Latched Gain Mode

A1 A0 Gain

WR

High to low Low Low Change to 1
High to low Low High Change to 2
High to low High Low
High to low High High
Low to low X
Low to high X
High to high X

1

X = don’t care.

1

X

1

X

1

X

1

1

1

Change to 4

Change to 8
No change
No change
No change

On power-up, the AD8251 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8251 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, t

, before the downward edge of WR

SU

latches in the gain. Similarly, they must be held for a minimum
hold time of t
the gain is latched in correctly. After t

after the downward edge of WR to ensure that

HD

, A0 and A1 can change

HD

logic levels, but the gain does not change (until the next

WR

downward edge of
be held high is t
can be held low is t
listed in The time required for a gain change is

Table 2 .

). The minimum duration that WR can
, and the minimum duration that WR

WR-HIGH

. Digital timing specifications are

WR-LOW

dominated by the settling time of the amplifier. A timing
diagram is shown in .

Figure 54

When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.

t

WR-LOW

WR

t

SU

A0, A1

Figure 54. Timing Diagram for Latched Gain Mode

Rev. B | Page 17 of 24

t

HD

6287-053

AD8251

V

POWER SUPPLY REGULATION AND BYPASSING

The AD8251 has high PSRR. However, for optimal performance,
a stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect per­formance. As in all linear circuits, bypass capacitors must be
used to decouple the amplifier.

Place a 0.1 µF capacitor close to each supply pin. A 10 µF tantalum
capacitor can be used farther away from the part (see Figure 55)
and, in most cases, it can be shared by other precision integrated
circuits.

+

S

0.1µF

WR

A1

+IN

A0

AD8251

–IN

DGND

0.1µF 10µF

DGND

–V

S

Figure 55. Supply Decoupling, REF, and Output Referred to Ground

REF

10µF

LOAD

OUT

06287-054

INPUT BIAS CURRENT RETURN PATH

The AD8251 input bias current must have a return path to its
local analog ground. When the source, such as a thermocouple,
cannot provide a return current path, one should be created
(see Figure 56).

INCORRECT

+V

S

AD8251

REF

–V

TRANSFORMER

S

+V

S

AD8251

REF

–V

THERMOCOUPLE

C

C

CAPACITIVELY COUPLED

S

+V

S

AD8251

–V

S

REF

Figure 56. Creating an I

10M

f

=

HIGH-PASS

2RC

CAPACITIVELY COUPLED

BIAS

CORRECT

TRANSFORMER

THERMOCOUPLE

C

R

1

C

R

Return Path

+V

S

AD8251

–V

S

+V

S

AD8251

–V

S

+V

S

AD8251

–V

S

REF

REF

REF

INPUT PROTECTION

All terminals of the AD8251 are protected against ESD. Note
that 2.2 k series resistors precede the ESD diodes as shown in
Figure 51. The resistors limit current into the diodes and allow
for dc overload conditions 13 V above the positive supply and
13 V below the negative supply. An external resistor should be
used in series with each input to limit current for voltages
greater than 13 V beyond either supply rail. In either scenario,
the AD8251 safely handles a continuous 6 mA current at room
temperature. For applications where the AD8251 encounters
extreme overload voltages, external series resistors and low
leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s,
should be used.

06287-055

Rev. B | Page 18 of 24

AD8251

REFERENCE TERMINAL

The reference terminal, REF, is at one end of a 10 k resistor
(see Figure 51). The instrumentation amplifier output is referenced
to the voltage on the REF terminal; this is useful when the output
signal needs to be offset to voltages other than its local analog
ground. For example, a voltage source can be tied to the REF
pin to level shift the output so that the AD8251 can interface
with a single-supply ADC. The allowable reference voltage
range is a function of the gain, common-mode input, and
supply voltages. The REF pin should not exceed either +V
or −V

by more than 0.5 V.

S

S

For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source imped­ance to the REF terminal should be kept low because parasitic
resistance can adversely affect CMRR and gain accuracy.

INCORRECT

AD8251

V

REF

Figure 57. Driving the Reference Pin

V

REF

CORRECT

AD8251

+

OP1177

–

6287-056

COMMON-MODE INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8251 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8251 experience a combination of both the gained
signal and the common-mode signal. This combined signal
can be limited by the voltage supplies even when the individual
input and output signals are not. Figure 27 and Figure 28 show
the allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.

LAYOUT

Grounding

In mixed-signal circuits, low level analog signals need to be
isolated from the noisy digital environment. Designing with the
AD8251 is no exception. Its supply voltages are referenced to an
analog ground. Its digital circuit is referenced to a digital ground.
Although it is convenient to tie both grounds to a single ground
plane, the current traveling through the ground wires and PCB
can cause errors. Therefore, use separate analog and digital
ground planes. Analog and digital ground should meet at one
point only: star ground.

The output voltage of the AD8251 develops with respect to the
potential on the reference terminal. Take care to tie REF to the
appropriate local analog ground or to connect it to a voltage that
is referenced to the local analog ground.

Coupling Noise

To prevent coupling noise onto the AD8251, follow these
guidelines:

• Do not run digital lines under the device.

• Run the analog ground plane under the AD8251.

• Shield fast switching signals with digital ground to avoid

radiating noise to other sections of the board, and never
run them near analog signal paths.

• Avoid crossover of digital and analog signals.

• Connect digital and analog ground at one point only

(typically under the ADC).

• Use large traces on the power supply lines to ensure a low

impedance path. Decoupling is necessary; follow the
guidelines listed in the Power Supply Regulation and
Bypassing section.

Common-Mode Rejection

The AD8251 has high CMRR over frequency, giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical instrumentation amplifiers
whose CMRR falls off around 200 Hz. The typical instrumentation
amplifiers often need common-mode filters at their inputs to
compensate for this shortcoming. The AD8251 is able to reject
CMRR over a greater frequency range, reducing the need for
input common-mode filtering.

Careful board layout maximizes system performance. To
maintain high CMRR over frequency, lay out the input traces
symmetrically. Ensure that the traces maintain resistive and
capacitive balance; this holds for additional PCB metal layers
under the input pins and traces. Source resistance and capaci­tance should be placed as close to the inputs as possible. Should
a trace cross the inputs (from another layer), it should be routed
perpendicular to the input traces.

Rev. B | Page 19 of 24

AD8251

V

V

–

RF INTERFERENCE DRIVING AN ADC

RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 58. The
filter limits the input signal bandwidth according to the following
relationship:

1

RC

2π2

C

0.1µF

+IN

–IN

0.1µF

1

D

+

C

+15

AD8251

–15V

)CC(R

10µF

V

OUT

REF

10µF

6287-057

FilterFreq

FilterFreqπ2=

where C

≥ 10 CC.

D

R

R

DIFF

CM

=

C

C

C

D

C

C

Figure 58. RFI Suppression

Val u es o f R a nd CC should be chosen to minimize RFI. A
mismatch between the R × C

at negative input degrades the CMRR of the AD8251.

R × C

C

By using a value of C

, the effect of the mismatch is reduced and performance is

C

C

that is 10 times larger than the value of

D

at the positive input and the

C

improved.

An instrumentation amplifier is often used in front of an ADC
to provide CMRR. Usually, instrumentation amplifiers require a
buffer to drive an ADC. However, the low output noise, low
distortion, and low settle time of the AD8251 make it an
excellent ADC driver.

In Figure 59, a 1 nF capacitor and a 49.9 Ω resistor create an
antialiasing filter for the AD7612. The 1 nF capacitor stores and
delivers the necessary charge to the switched capacitor input of
the ADC. The 49.9  series resistor reduces the burden of the
1 nF load from the amplifier and isolates it from the kickback
current injected from the switched capacitor input of the AD7612.
Selecting too small a resistor improves the correlation between
the voltage at the output of the AD8251 and the voltage at the
input of the AD7612 but may destabilize the AD8251. A trade­off must be made between selecting a resistor small enough to
maintain accuracy and large enough to maintain stability.

+15

10F0.1µF

+IN

IN

10F0.1µF

AD8251

–15V

WR

A1

A0

49.9

1nF

REF

DGNDDGND

+12V –12V

0.1F

AD7612

+5V

ADR435

0.1F

Figure 59. Driving an ADC

06287-058

Rev. B | Page 20 of 24

AD8251

V

–

V

V

APPLICATIONS

DIFFERENTIAL OUTPUT

In certain applications, it is necessary to create a differential
signal. High resolution ADCs often require a differential input.
In other cases, transmission over a long distance can require
differential signals for better immunity to interference.

Figure 61 shows how to configure the AD8251 to output a
differential signal. An op amp, the AD817, is used in an
inverting topology to create a differential voltage. V
output midpoint according to the equation shown in the figure.
Errors from the op amp are common to both outputs and are
thus common mode. Likewise, errors from using mismatched
resistors cause a common-mode dc offset error. Such errors are
rejected in differential signal processing by differential input
ADCs or instrumentation amplifiers.

When using this circuit to drive a differential ADC, V
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.

0.1F

AMPLITUDE

+5

–5V

+IN

V

IN

REF

+12

+

AD8251

G = 1

–

sets the

can be

REF

WR

A1

A0

REF

4.99k

SETTING GAINS WITH A MICROCONTROLLER

+15

V

OUT

10F0.1µF

+IN

IN

10F0.1µF

Figure 60. Programming Gain Using a Microcontroller

A = VIN + V

2

AMPLITUDE

REF

+2.5V
–2.5V

+

AD8251

–

–15V

0V

WR

A1

A0

REF

MICRO-

CONTROLLER

DGNDDGND

TIME

06287-059

+12V

10F

–12V

0.1F

DGND

–12V

4.99k

10F

DGND

–12V
10pF

0.1µF

Figure 61. Differential Output with Level Shift

AD817

V

OUT

+–

+12V

0.1µF

B = –VIN + V

2

REF

V
0V

REF

AMPLITUDE

+2.5V

0V

0V

–2.5V

TIME

06287-060

Rev. B | Page 21 of 24

AD8251

–

DATA ACQUISITION

The AD8251 makes an excellent instrumentation amplifier
for use in data acquisition systems. Its wide bandwidth, low
distortion, low settling time, and low noise enable it to
condition signals in front of a variety of 16-bit ADCs.

Figure 63 shows a schematic of the AD825x data acquisition
demonstration board. The quick slew rate of the AD8251 allows
it to condition rapidly changing signals from the multiplexed
inputs. An FPGA controls the AD7612, AD8251, and ADG1209.
In addition, mechanical switches and jumpers allow users to pin
strap the gains when in transparent gain mode.

This system achieved −106 dB of THD at 1 kHz and a signal-to­noise ratio of 91 dB during testing, as shown in Figure 62.

+CH1
+CH2

+CH3
+CH4

–CH4

–CH3
–CH2
–CH1

806
806

806
806

806

806
806

806

0.1µF

0.1µF

+12V

14

V

DD

4

S1A

5

S2A

6

S3A
S4A

7

ADG1209

10

S4B

11

S3B

12

S2B

13

S1B

V

SS
3

–12V

2

EN

GND

A1

16

DA

DB

A0

1

+12V

8

9

15

JMP

+
10µF 10µF

DGND

0

0

+5V

2k

0

0

GND

–12V

+

DGND

2

DGND

C

C

+IN

10

+

–IN

1

C3

0.1µF

AD8251

–

C

D

C

C

6

WR

A1

–V

+V

S

3

8

+12V –12V

70
–80
–90

–100

–110
–120
–130
–140

AMPLITUDE (dB)

–150
–160
–170
–180

05

5 1015202530354045

FREQUENCY (kHz)

06287-062

0

Figure 62. FFT of the AD825x DAQ Demo Board

Using the AD8251 1 kHz Signal

JMP

JMP

+5V

+5V

7

DGND

2k

DGND
OUT

0 49.9

JMP

5

4

A0

REF

9

S

C4

0.1µF

2k

–V

S

ALTERA

EPF6010ATC144-3

+IN

AD7612

1nF

ADR435

DGND

JMP

+5V

R8
2k

DGND

06287-067

Figure 63. Schematic of ADG1209, AD8251, and AD7612 in the AD825x DAQ Demo Board

Rev. B | Page 22 of 24

AD8251

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 64. 10-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

091709-A

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

AD8251ARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T
AD8251ARMZ-RL −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T
AD8251ARMZ-R7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T
AD8251-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. B | Page 23 of 24

AD8251

NOTES

©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06287-0-11/10(B)

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