ANALOG DEVICES AD8251 Service Manual
10 MHz, 20 V/μs, G = 1, 2, 4, 8 iCMOS
Programmable Gain Instrumentation Amplifier
FEATURES
Small package: 10-lead MSOP
Programmable gains: 1, 2, 4, 8
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance
High CMRR: 98 dB (minimum), G = 8
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.8 V/°C (maximum), G = 8
Excellent ac performance
Fast settling time: 785 ns to 0.001% (maximum)
High slew rate: 20 V/µs (minimum)
Low distortion: −110 dB THD at 1 kHz, 10 V swing
High CMRR over frequency: 80 dB to 50 kHz (minimum)
Low noise: 18 nV/√Hz, G = 8 (maximum)
Low power: 4.1 mA
APPLICATIONS
Data acquisition
Biomedical analysis
Test and measurement
GENERAL DESCRIPTION
The AD8251 is an instrumentation amplifier with digitally
programmable gains that has GΩ input impedance, low output
noise, and low distortion, making it suitable for interfacing with
sensors and driving high sample rate analog-to-digital converters
(ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB,
and fast settling time of 785 ns (maximum) to 0.001%. Offset
drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C,
respectively, for G = 8. In addition to its wide input common
voltage range, it boasts a high common-mode rejection of 80 dB
at G = 1 from dc to 50 kHz. The combination of precision dc
performance coupled with high speed capabilities makes the
AD8251 an excellent candidate for data acquisition. Furthermore,
this monolithic solution simplifies design and manufacturing
and boosts performance of instrumentation by maintaining a
tight match of internal resistors and amplifiers.
The AD8251 user interface consists of a parallel port that allows
users to set the gain in one of two ways (see Figure 1). A 2-bit word
sent via a bus can be latched using the
to use the transparent gain mode where the state of the logic
levels at the gain port determines the gain.
WR
input. An alternative is
AD8251
FUNCTIONAL BLOCK DIAGRAM
A1 A0DGND WR
4562
1
–IN
10
+IN
8 3
+V
25
20
15
10
5
GAIN (dB)
0
–5
–10
1k 100M
Table 1. Instrumentation Amplifiers by Category
General
Purpose
AD82201 AD82311 AD620 AD6271 AD8250
AD8221 AD85531 AD621 AD6231 AD8251
AD8222 AD85551 AD524 AD82231 AD8253
AD82241 AD85561 AD526
AD8228 AD85571 AD624
1
Rail-to-rail output.
Zero Drift
The AD8251 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making it
an excellent solution for applications where size and packing
density are important considerations.
LOGIC
AD8251
S
10k 100k 1M 10M
–V
S
Figure 1.
G = 8
G = 4
G = 2
G = 1
FREQUENCY (Hz)
Figure 2. Gain vs. Frequency
Mil
Grade
Low
Power
REF
9
7
OUT
High Speed
PGA
06287-001
06287-002
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD8251
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation..................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 16
Gain Selection ............................................................................. 16
Power Supply Regulation and Bypassing ................................ 18
Input Bias Current Return Path ............................................... 18
Input Protection ......................................................................... 18
Reference Terminal .................................................................... 19
Common-Mode Input Voltage Range..................................... 19
Layout .......................................................................................... 19
RF Interference........................................................................... 20
Driving an ADC ......................................................................... 20
Applications..................................................................................... 21
Differential Output .................................................................... 21
Setting Gains with a Microcontroller...................................... 21
Data Acquisition......................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
11/10—Rev. A to Rev. B
Changes to Voltage Offset, Offset RTI V
Parameter in Table 2......................................................................... 3
Updated Outline Dimensions....................................................... 23
5/08—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
, Average TC
OS
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................6
Inserted Figure 17; Renumbered Sequentially ..............................9
Inserted Figure 29........................................................................... 11
Changes to Timing for Latched Gain Mode Section ................. 17
5/07—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8251
SPECIFICATIONS
+VS = 15 V, −VS = −15 V, V
Table 2.
Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V
G = 1 80 98 dB
G = 2 86 104 dB
G = 4 92 110 dB
G = 8 98 110 dB
CMRR to 50 kHz +IN = −IN = −10 V to +10 V
G = 1 80 dB
G = 2 84 dB
G = 4 86 dB
G = 8 86 dB
NOISE
Voltage Noise, 1 kHz, RTI
G = 1 40 nV/√Hz
G = 2 27 nV/√Hz
G = 4 22 nV/√Hz
G = 8 18 nV/√Hz
0.1 Hz to 10 Hz, RTI
G = 1 2.5 μV p-p
G = 2 2.5 μV p-p
G = 4 1.8 μV p-p
G = 8 1.2 μV p-p
Current Noise, 1 kHz 5 pA/√Hz
Current Noise, 0.1 Hz to 10 Hz 60 pA p-p
VOLTAGE OFFSET
Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV
Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV
Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C
Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V
INPUT CURRENT
Input Bias Current 5 30 nA
Over Temperature T = −40°C to +85°C 40 nA
Average TC T = −40°C to +85°C 400 pA/°C
Input Offset Current 5 30 nA
Over Temperature T = −40°C to +85°C 30 nA
Average TC T = −40°C to +85°C 160 pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 10 MHz
G = 2 10 MHz
G = 4 8 MHz
G = 8 2.5 MHz
Settling Time 0.01% ΔOUT = 10 V step
G = 1 615 ns
G = 2 460 ns
G = 4 460 ns
G = 8 625 ns
= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
REF
Rev. B | Page 3 of 24
AD8251
Parameter Conditions Min Typ Max Unit
Settling Time 0.001% ΔOUT = 10 V step
G = 1 785 ns
G = 2 700 ns
G = 4 700 ns
G = 8 770 ns
Slew Rate
G = 1 20 V/μs
G = 2 30 V/μs
G = 4 30 V/μs
G = 8 30 V/μs
Total Harmonic Distortion + Noise
f = 1 kHz, R
= 10 kΩ, ±10 V,
L
G = 1, 10 Hz to 22 kHz bandpass filter
GAIN
Gain Range G = 1, 2, 4, 8 1 8 V/V
Gain Error OUT = ±10 V
G = 1 0.03 %
G = 2, 4, 8 0.04 %
Gain Nonlinearity OUT = −10 V to +10 V
G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 9 ppm
G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm
G = 4 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm
G = 8 RL = 10 kΩ, 2 kΩ, 600 Ω 15 ppm
Gain vs. Temperature All gains 3 10 ppm/°C
INPUT
Input Impedance
Differential 5.3||0.5
Common Mode 1.25||2
Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V
Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.7 V
OUTPUT
Output Swing −13.5 +13.5 V
Over Temperature T = −40°C to +85°C −13.5 +13.5 V
Short-Circuit Current 37 mA
REFERENCE INPUT
RIN 20 kΩ
IIN +IN, −IN, REF = 0 1 μA
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V
DIGITAL LOGIC
Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V
Digital Input Voltage Low Referred to GND DGND 2.1 V
Digital Input Voltage High Referred to GND 2.8 +VS V
Digital Input Current 1 μA
Gain Switching Time1 325 ns
t
See Figure 3 timing diagram 20 ns
SU
tHD See Figure 3 timing diagram 10 ns
t
-LOW
WR
t
-HIGH
WR
See Figure 3 timing diagram 20 ns
See Figure 3 timing diagram 40 ns
−110 dB
GΩ||pF
GΩ||pF
Rev. B | Page 4 of 24
AD8251
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range ±5 ±15 V
Quiescent Current, +IS 4.1 4.5 mA
Quiescent Current, −IS 3.7 4.5 mA
Over Temperature T = −40°C to +85°C 4.5 mA
TEMPERATURE RANGE
Specified Performance −40 +85 °C
1
Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
WR
t
WR-HIGH
t
WR-LOW
A0, A1
t
SU
t
HD
6287-003
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. B | Page 5 of 24
AD8251
(
)
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±17 V
Power Dissipation See Figure 4
Output Short-Circuit Current Indefinite1
Common-Mode Input Voltage +VS + 13 V to −VS − 13 V
Differential Input Voltage +VS + 13 V, −VS − 13 V2
Digital Logic Inputs ±VS
Storage Temperature Range −65°C to +125°C
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some in the load (V
The difference between the total drive power and the load
power is the drive power dissipated in the package.
Operating Temperature Range3 −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 140°C
θJA (Four-Layer JEDEC Standard Board) 112°C/W
Package Glass Transition Temperature 140°C
1
Assumes the load is referenced to midsupply.
2
Current must be kept to less than 6 mA.
3
Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
In single-supply operation with R
case is V
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
reduces the θ
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a four-layer JEDEC
standard board.
rating conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8251 package is
limited by the associated rise in junction temperature (T
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8251. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still air thermal properties of the package and PCB (θ
the ambient temperature (T
the package (P
) determine the junction temperature of the die.
D
), and the total power dissipated in
A
The junction temperature is calculated as
θPTT ×+=
J
D
A
JA
) on
J
JA
),
ESD CAUTION
). Assuming the load (RL) is referenced to
S
= Quiescent Power + (Total Drive Power − Load Power)
P
D
⎛
V
V
OUTS
()
D
= VS/2.
OUT
2.00
1.75
1.50
1.25
1.00
0.75
0.50
MAXIMUM POWER DISSIPATI ON (W)
0.25
0
–40 –20 120100806040200
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
⎜
IVP
SS
.
JA
×+×=
⎜
R
2
⎝
L
AMBIENT TEM P E RATURE (°C)
) is the sum of the
D
) times the
S
/2 × I
S
⎞
V
OUT
⎟
–
⎟
R
⎠
referenced to −VS, the worst
L
, some of which is
OUT
2
L
OUT
× I
OUT
JA
).
. In
06287-004
Rev. B | Page 6 of 24
AD8251
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
1
2
DGND
–V
A0
A1
3
S
4
5
AD8251
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input.
2 DGND Digital Ground.
3 −VS Negative Supply Terminal.
4 A0 Gain Setting Pin (LSB).
5 A1 Gain Setting Pin (MSB).
6
WR
Write Enable.
7 OUT Output Terminal.
8 +VS Positive Supply Terminal.
9 REF Reference Voltage Terminal.
10 +IN Noninverting Input Terminal. True differential input.
10
+IN
9
REF
+V
8
S
7
OUT
6
WR
06287-005
Rev. B | Page 7 of 24
AD8251
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.
2700
2400
2100
1800
1500
1200
900
NUMBER OF UNIT S
600
300
0
–120 –90 –60 –30 0 30 60 90
CMRR (µV/V)
Figure 6. Typical Distribution of CMRR, G = 1
500
400
300
200
NUMBER OF UNIT S
100
0
–200 –100
INPUT OFFSET VOLTAGE, V
OSI
Figure 7. Typical Distribution of Offset Voltage, V
, RTI (µV)
06287-006
120
06287-007
2001000
OSI
800
700
600
500
400
300
NUMBER OF UNIT S
200
100
0
–30 –10–20
INPUT OFFSET CURRENT (nA)
Figure 9. Typical Distribution of Input Offset Current
90
80
70
60
50
40
NOISE (nV/Hz)
30
20
10
0
1 100k
10 100 1k 10k
FREQUENCY (Hz)
G = 1
G = 2
G = 4
G = 8
Figure 10. Voltage Spectral Density Noise vs. Frequency
06287-009
3020100
06287-010
800
600
400
NUMBER OF UNIT S
200
0
–30 –10–20
INPUT BIAS CURRENT ( nA)
Figure 8. Typical Distribution of Input Bias Current
06287-008
3020100
Rev. B | Page 8 of 24
1s/DIV2µV/DIV
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
6287-011
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