Datasheet AD8250 Datasheet (ANALOG DEVICES)

10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS
Programmable Gain Instrumentation Amplifier

FEATURES

Small package: 10-lead MSOP Programmable gains: 1, 2, 5, 10 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance
High CMRR 98 dB (minimum), G = 10 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.7 V/°C (maximum), G = 10
Excellent ac performance
Fast settling time: 615 ns to 0.001% (maximum) High slew rate: 20 V/µs (minimum) Low distortion: −110 dB THD at 1 kHz High CMRR over frequency: 80 dB to 50 kHz (minimum) Low noise: 18 nV/√Hz, G = 10 (maximum) Low power: 4.1 mA

APPLICATIONS

Data acquisition Biomedical analysis Test and measurement

GENERAL DESCRIPTION

The AD8250 is an instrumentation amplifier with digitally programmable gains that has GΩ input impedance, low output noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB and fast settling time of 615 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.7 μV/°C and 10 ppm/°C, respectively, for G = 10. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8250 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers.
The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word sent via a bus can be latched using the
to use the transparent gain mode where the state of the logic levels at the gain port determines the gain.
input. An alternative is
WR
AD8250

FUNCTIONAL BLOCK DIAGRAM

A1 A0DGND WR
4562
1
–IN
10
+IN
8 3
+V
25
20
15
10
5
GAIN (dB)
0
–5
–10
1k 10k 100k 1M 10M 100M
Table 1. Instrumentation Amplifiers by Category
General Purpose Zero Drift
AD82201 AD82311 AD620 AD6271 AD8250 AD8221 AD85531 AD621 AD6231 AD8251 AD8222 AD85551 AD524 AD82231 AD8253 AD82241 AD85561 AD526 AD8228 AD85571 AD624
1
Rail-to-rail output.
The AD8250 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations.
LOGIC
S
–V
S
Figure 1.
G = 10
G = 5
G = 2
G = 1
FREQUENCY (Hz)
Figure 2. Gain vs. Frequency
Mil Grade
AD8250
Low Power
REF
9
7
OUT
06288-001
High Speed PGA
06288-023
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD8250

TABLE OF CONTENTS

Features.............................................................................................. 1
Input Bias Current Return Path ............................................... 17
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation..................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Gain Selection ............................................................................. 15
Power Supply Regulation and Bypassing ................................17
Input Protection ......................................................................... 17
Reference Terminal .................................................................... 18
Common-Mode Input Voltage Range..................................... 18
Layout .......................................................................................... 18
RF Interference........................................................................... 19
Driving an ADC ......................................................................... 19
Applications..................................................................................... 20
Differential Output .................................................................... 20
Setting Gains with a Microcontroller...................................... 20
Data Acquisition......................................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22

REVISION HISTORY

11/10—Rev. A to Rev. B
Changes to Voltage Offset, Offset RTI V
Temperature Coefficient Parameter in Table 2............................. 3
Updated Outline Dimensions....................................................... 22
5/08—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 6
Added Figure 17; Renumbered Sequentially ................................ 9
Changes to Figure 23...................................................................... 10
, Average
OS
Changes to Figure 24 to Figure 26................................................ 11
Added Figure 29 ............................................................................. 11
Changes to Figure 31...................................................................... 12
Deleted Figure 43 to Figure 46; Renumbered Sequentially ...... 14
Inserted Figure 45 and Figure 46.................................................. 14
Changes to Timing for Latched Gain Mode Section ................. 16
Changes to Layout Section and Coupling Noise Section.......... 18
Changes to Figure 59...................................................................... 21
1/07—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8250

SPECIFICATIONS

+VS = 15 V, −VS = −15 V, V
Table 2.
Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V
G = 1 80 98 dB G = 2 86 104 dB G = 5 94 110 dB G = 10 98 110 dB
CMRR to 50 kHz +IN = −IN = −10 V to +10 V
G = 1 80 dB G = 2 86 dB G = 5 90 dB G = 10 90 dB
NOISE
Voltage Noise, 1 kHz, RTI
G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 5 21 nV/√Hz G = 10 18 nV/√Hz
0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 5 1.5 μV p-p G = 10 1.0 μV p-p
Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p
VOLTAGE OFFSET
Offset RTI VOS G = 1, 2, 5, 10 ±(70 + 200/G) ±(200 + 600/G) μV
Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average Temperature Coefficient T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C
Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V
INPUT CURRENT
Input Bias Current 5 30 nA
Over Temperature T = −40°C to +85°C 40 nA Average Temperature Coefficient T = −40°C to +85°C 400 pA/°C
Input Offset Current 5 30 nA
Over Temperature T = −40°C to +85°C 30 nA Average Temperature Coefficient T = −40°C to +85°C 160 pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 10 MHz G = 2 10 MHz G = 5 10 MHz G = 10 3 MHz
Settling Time 0.01% ΔOUT = 10 V step
G = 1 585 ns G = 2 605 ns G = 5 605 ns G = 10 648 ns
= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
REF
Rev. B | Page 3 of 24
AD8250
Parameter Conditions Min Typ Max Unit
Settling Time 0.001% ΔOUT = 10 V step
G = 1 615 ns G = 2 635 ns G = 5 635 ns G = 10 685 ns
Slew Rate
G = 1 20 V/μs G = 2 25 V/μs G = 5 25 V/μs G = 10 25 V/μs
Total Harmonic Distortion
f = 1 kHz, R
= 10 kΩ, ±10 V,
L
G = 1, 10 Hz to 22 kHz band-pass filter
GAIN
Gain Range G = 1, 2, 5, 10 1 10 V/V Gain Error OUT = ±10 V
G = 1 0.03 % G = 2, 5, 10 0.04 %
Gain Nonlinearity OUT = −10 V to +10 V
G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 6 ppm G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 5 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 10 ppm
Gain vs. Temperature All gains 10 ppm/°C
INPUT
Input Impedance
Differential 5.3||0.5 Common Mode 1.25||2
Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.7 V
OUTPUT
Output Swing −13.5 +13.5 V Over Temperature T = −40°C to +85°C −13.5 +13.5 V Short-Circuit Current 37 mA
REFERENCE INPUT
RIN 20 kΩ IIN +IN, −IN, REF = 0 1 μA Voltage Range −VS +VS V Gain to Output 1 ± 0.0001 V/V
DIGITAL LOGIC
Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V Digital Input Voltage Low Referred to GND DGND 2.1 V Digital Input Voltage High Referred to GND 2.8 +VS V Digital Input Current 1 μA Gain Switching Time1 325 ns t
See Figure 3 timing diagram 20 ns
SU
tHD See Figure 3 timing diagram 10 ns t
-LOW
WR
t
-HIGH
WR
See Figure 3 timing diagram 20 ns See Figure 3 timing diagram 40 ns
−110 dB
||pF GΩ||pF
Rev. B | Page 4 of 24
AD8250
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −IS 3.7 4.5 mA Over Temperature T = −40°C to +85°C 4.5 mA
TEMPERATURE RANGE
Specified Performance −40 +85 °C
1
Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM

WR
t
WR-HIGH
t
WR-LOW
A0, A1
t
SU
t
HD
6288-057
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. B | Page 5 of 24
AD8250

ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Rating
Supply Voltage ±17 V Power Dissipation See Figure 4 Output Short-Circuit Current Indefinite1 Common-Mode Input Voltage +VS + 13 V, −VS − 13 V Differential Input Voltage +VS + 13 V, −VS − 13 V2 Digital Logic Inputs ±VS Storage Temperature Range −65°C to +125°C Operating Temperature Range3 −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 140°C θJA (Four-Layer JEDEC Standard Board) 112°C/W Package Glass Transition Temperature 140°C
1
Assumes that the load is referenced to midsupply.
2
Current must be kept to less than 6 mA.
3
Temperature for specified performance is −40°C to +85°C. For performance
to 125°C, see the Typical Performance Characteristics section.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8250 package is limited by the associated rise in junction temperature (T the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8250. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ the ambient temperature (T the package (P
) determine the junction temperature of the die.
D
), and the total power dissipated in
A
The junction temperature is calculated as
T
= TA + (PD × θJA)
J
) on
J
JA
),
The power dissipated in the package (P quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V quiescent current (I
). Assuming that the load (RL) is referenced
S
to midsupply, the total drive power is V is dissipated in the package and some in the load (V
The difference between the total drive power and the load power is the drive power dissipated in the package.
P
= Quiescent Power + (Total Drive PowerLoad Power)
D
V
V
()
D
IVP
SS
⎜ ⎝
OUTS
×+×=
2
R
L
In single-supply operation with R case is V
OUT
= VS/2.
Airflow increases heat dissipation, effectively reducing θ addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ
.
JA
Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four-layer JEDEC standard board.
2.00
1.75
1.50
1.25
1.00
0.75
0.50
MAXIMUM POWER DISSIPATI ON (W)
0.25
0
–40 –20 120100806040200
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
AMBIENT TEM P E RATURE (°C)

ESD CAUTION

) is the sum of the
D
) times the
S
/2 × I
S
⎞ ⎟
⎟ ⎠
2
V
OUT
R
L
referenced to −VS, the worst
L
, some of which
OUT
× I
OUT
OUT
JA
. In
).
06288-004
Rev. B | Page 6 of 24
AD8250

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN
1 2
DGND
–V
A0 A1
3
S
4 5
AD8250
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −VS Negative Supply Terminal. 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6
WR
Write Enable.
7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input.
10
+IN
9
REF +V
8
S
7
OUT
6
WR
06288-005
Rev. B | Page 7 of 24
AD8250

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.
1400
500
1200
1000
800
600
NUMBER OF UNITS
400
200
0
–120 –90 –60 –30 0 30 60 90 120
CMRR (µV/V)
Figure 6. Typical Distribution of CMRR, G = 1
350
300
250
200
150
NUMBER OF UNITS
100
50
0
–200 2001000–100 –50 50–150 150
OFFSET VOLTAGE RTI ( µ V)
Figure 7. Typical Distribution of Offset Voltage, V
400
300
200
NUMBER OF UNITS
100
0
–30 3020100–20 –10
06288-006
INPUT OF FSET CURRENT (nA)
06288-009
Figure 9. Typical Distribution of Input Offset Current
90
80
70
60
50
40
30
NOISE RTI ( nV/ Hz)
20
10
0
1 10 100 1k 10k 100k
06288-007
OSI
Figure 10. Voltage Spectral Density Noise vs. Frequency
G = 1
G = 2 G = 5
G = 10
FREQUENCY (Hz)
06288-010
600
500
400
300
200
NUMBER OF UNITS
100
0
–30 3010 200–10–20
INPUT BIAS CURRENT (nA)
Figure 8. Typical Distribution of Input Bias Current
06288-008
Rev. B | Page 8 of 24
1s/DIV2µV/DIV
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
6288-011
AD8250
150
G = 10 G = 5
130
110
G = 2 G = 1
90
70
PSRR (dB)
50
30
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 10
18
16
14
12
10
8
6
CURRENT NOISE ( pA/ Hz)
4
2
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 13. Current Noise Spectral Density vs. Frequency
Figure 14. 0.1 Hz to 10 Hz Current Noise
1s/DIV1µV/DIV
6288-012
06288-013
1s/DIV140pA/DIV
6288-014
10
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 15. Positive PSRR vs. Frequency, RTI
150
130
110
90
70
PSRR (dB)
50
30
10
1 10 100 1k 10k 100k 1M
G = 2
FREQUENCY (Hz)
G = 10
G = 5
G = 1
Figure 16. Negative PSRR vs. Frequency, RTI
10
9
8
7
6
5
4
3
2
1
CHANGE IN OFFSET VOLTAGE, RT I (µV)
0
0.01 0.1 WARMUP TIME (Minutes)
1
Figure 17. Change in Offset Voltage, RTI vs. Warmup Time
06288-016
06288-017
10
06288-117
Rev. B | Page 9 of 24
AD8250
15
10
I
5
0
–5
–10
–15
INPUT BIAS CURRENT AND OFFSET CURRENT (nA)
–40 –25 –10 5 20 35 50 65 80 95 110 125
B
+
I
B
I
OS
TEMPERATURE (°C)
Figure 18. Input Bias Current and Offset Current vs. Temperature
140
G = 10
120
100
G = 2
80
CMRR (dB)
60
G = 5
G = 1
10
8
6
4
2
0
–2
CMRR (µV/V)
–4
–6
–8
–10
–50 –30 –10 10 30 50 70 90 110 130
06288-019
TEMPERATURE ( °C)
06288-049
Figure 21. CMRR vs. Temperature, G = 1
25
20
15
10
5
GAIN (dB)
0
G = 10
G = 5
G = 2
G = 1
40
20
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 19. CMRR vs. Frequency
140
G = 10
120
100
80
CMRR (dB)
60
40
20
1 10 100 1k 10k 100k 1M
G = 2
G = 5
G = 1
FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance
–5
–10
1k 10k 100k 1M 10M 100M
06288-020
FREQUENCY (Hz)
06288-023
Figure 22. Gain vs. Frequency
40
f = 1kHz
30
20
10
0
–10
–20
GAIN NONLINEARITY (10ppm/DIV)
–30
–40
10–8–6–4–20246810
06288-021
Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, R
OUTPUT VO LTAGE (V)
= 10 kΩ, 2 kΩ, 600 Ω
L
06288-024
Rev. B | Page 10 of 24
AD8250
40
f = 1kHz
30
20
10
0
–10
–20
GAIN NONLINEARITY (10ppm/DIV)
–30
–40
10–8–6–4–20246810
OUTPUT VO LTAGE (V)
Figu re 24. Gain Nonlinearity vs. Output Voltage, G = 2, R
40
f = 1kHz
30
20
10
0
–10
–20
GAIN NONLINEARITY (10ppm/DIV)
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity vs. Output Voltage, G = 5, R
40
f = 1kHz
30
20
10
0
–10
–20
GAIN NONLINEARITY (10ppm/DIV)
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figu re 26. Gain N online arity vs. Output Voltage, G = 10, R
06288-025
= 10 kΩ, 2 kΩ, 600 Ω
L
06288-026
= 10 kΩ, 2 kΩ, 600 Ω
L
06288-027
= 10 kΩ, 2 kΩ, 600 Ω
L
16
12
–13.8V, +6.9V
8
4
0
–4
–8
–13.8V, –6. 9V +13.8V, –6. 9V
INPUT COMMON-MODE VOLTAGE (V)
–12
–16
–16 –12 –8 –4 0 4 8 12 16
–3.8V, +1.9V
–3.8V, –1.9V
0V, +13.8V
= ±15V
V
S
0V, +3.7V
V
0V, –4.0V
0V, –14V
OUTPUT VO LTAGE (V)
= ±5V
S
+3.9V, +1.9V
+3.8V, –2.1V
+13.8V, + 6.9V
06288-028
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1
16
–14.1V, +13.6V
12
8
4
0
–4
–8
INPUT COMMON-MODE VOLTAGE (V)
–12
–16
–16 –12 –8 –4 0 4 8 12 16
–4.2V, +2.2V +4.3V, +2.1V
–4.2V, –2. 0V
–14.1V, –13. 6V
0V, +13.8V
= ±15V
V
S
+0V, +3.5V
= ±5V
V
S
+4.3V, –2.1V
0V, –4.1V
0V, –14V
OUTPUT VO LTAGE (V)
+13.6V, + 13.1V
+13.6V, –13.1V
06288-029
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 10
35
30
25
20
15
10
5
0
OFFSET CURRENT (nA)
INPUT BIAS CURRENT AND
–5
–10
–15
–15 –10 –5 0 5 10 15
COMMON-MO DE VO LTAGE (V)
IB+ I I
B OS
06288-129
Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage
Rev. B | Page 11 of 24
AD8250
V
V
V
V
+
S
–1
+125°C
–2
+85°C
+25°C
–40°C
+ –0.2 –0.4 –0.6 –0.8 –1.0
S
+125°C
+85°C
+25°C
–40°C
INPUT VOLTAGE
+2
+1
REFERRED TO S UPPLY VOL TAGE (V)
–V
S
4 6 8 10 12 14 16
+85°C
SUPPLY VOLTAGE (±VS)
+25°C
+125°C
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, V
15
10
FAULT CONDI TION
(OVER DRIVEN INPUT)
5
0
CURRENT (mA)
–5
–10
–15
–16 –12 –8 –4 0 4 8 12 16
G = 10
DIFFERENTIAL INPUT VOLTAGE (V)
FAULT CONDI TION
(OVER DRIVEN INPUT)
G = 10
Figure 31. Fault Current Draw vs. Input Voltage, G = 10, R
+
S
–0.2 –0.4 –0.6 –0.8 –1.0
+1.0 +0.8
OUTPUT VOLTAGE SWING
+0.6
REFERRED TO S UPPLY VOL TAGE (V)
+0.4 +0.2
–V
S
4 6 8 10 12 14 16
+125°C
+85°C
+85°C
+125°C
SUPPLY VOLTAGE (±VS)
+25°C
+25°C
–40°C
–40°C
Figure 32. Output Voltage Swing vs. Supply Voltage, G = 10, R
–40°C
= 0 V, RL = 10 kΩ
REF
+V
S
+IN
–IN
–V
S
= 10 kΩ
L
= 2 kΩ
L
+1.0 +0.8
OUTPUT VOLTAGE SWING
+0.6
REFERRED TO S UPPLY VOL TAGE (V)
+0.4 +0.2
–V
S
4 6 8 10 12 14 16
06288-030
+125°C
SUPPLY VOLTAGE (±VS)
+25°C
+85°C
Figure 33. Output Voltage Swing vs. Supply Voltage, G = 10, R
–40°C
= 10 kΩ
L
06288-033
15
10
5
0
–5
OUTPUT VO LTAGE SWING (V)
–10
–15
100 1k 10k
06288-031
+125°C
–40°C
+85°C
+25°C
+25°C
+85°C
+125°C
LOAD RESISTANCE ()
–40°C
06288-034
Figure 34. Output Voltage Swing vs. Load Resistance
+
S
+85°C
–0.4 –0.8 –1.2 –1.6 –2.0 +2.0 +1.6 +1.2
OUTPUT VOLTAGE SWING
+0.8
REFERRED TO SUPPLY VOLTAGE (V)
+0.4
–V
06288-032
+125°C
+25°C
–40°C
+25°C
–40°C
+125°C
+85°C
S
02 6 10 144 8 12 16
OUTPUT CURRENT ( mA)
06288-035
Figure 35. Output Voltage Swing vs. Output Current
Rev. B | Page 12 of 24
AD8250
47pF
100pF
TIME (µs)
2µs/DIV20mV/DIV
06288-036
NO
LOAD
(V)
OUT
V
Figure 36. Small Signal Pulse Response for Various Capacitive Loads
5V/DIV
585ns TO 0.01%
0.002%/DIV
615ns TO 0.001%
5V/DIV
605ns TO 0.01%
0.002%/DIV
635ns TO 0.001%
TIME (µs)
2µs/DIV
06288-039
Figure 39. Large Signal Pulse Response and Settling Time
= 10 kΩ
G = 5, R
L
5V/DIV
648ns TO 0.01%
0.002%/DIV
685ns TO 0.001%
2µs/DIV
TIME (µs)
Figure 37. Large Signal Pulse Response and Settling Time,
= 10 kΩ
G = 1, R
L
5V/DIV
605ns TO 0.01%
0.002%/DIV
635ns TO 0.001%
2µs/DIV
TIME (µs)
Figure 38. Large Signal Pulse Response and Settling Time
= 10 kΩ
G = 2, R
L
06288-037
TIME (µs)
2µs/DIV
06288-040
Figure 40. Large Signal Pulse Response and Settling Time
= 10 kΩ
G = 10, R
L
(V)
OUT
V
06288-038
TIME (µs)
2µs/DIV20mV/DIV
06288-042
Figure 41. Small Signal Response
= 2 kΩ, CL = 100 pF
G = 1, R
L
Rev. B | Page 13 of 24
AD8250
–50 –55 –60 –65 –70 –75
(V)
OUT
V
2µs/DIV20mV/DIV
TIME (µs)
06288-043
Figure 42. Small Signal Response
= 2 kΩ, CL = 100 pF
G = 2, R
L
–80 –85 –90
THD + N (dB)
–95 –100 –105 –110 –115 –120
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 45. Total Harmonic Distortion + Noise vs. Frequency,
10 Hz to 22 kHz Band-Pass Filter, RL = 2 kΩ
G = 1 G = 2 G = 5 G = 10
06288-149
–50
–60
–70
(V)
OUT
V
2µs/DIV20mV/DIV
TIME (µs)
06288-044
Figure 43. Small Signal Response
G = 5, RL = 2 kΩ, CL = 100 pF
–80
THD + N (dB)
–90
–100
–110
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 46. Total Harmonic Distortion + Noise vs. Frequency,
10 Hz to 500 kHz Band-Pass Filter, R
G = 1 G = 2 G = 5 G = 10
= 2 kΩ
L
06288-150
(V)
OUT
V
2µs/DIV20mV/DIV
TIME (µs)
06288-045
Figure 44. Small Signal Response,
G = 10, R
= 2 kΩ, CL = 100 pF
L
Rev. B | Page 14 of 24
AD8250
V
V
V
V

THEORY OF OPERATION

+IN
+
S
+V
S
2.2k
IN
–V
S
+V
S
2.2k
–V
S
–V
A1
DIGITAL GAIN CONTROL
A2
+V
WR
S
S
2.2k
2.2k
+
S
A1A0
–V
S
10k 10k
10k
+V
S
DGND
A3
10k
+V
S
OUT
–V
S
+V
S
REF
–V
S
–V
S
Figure 47. Simplified Schematic
The AD8250 is a monolithic instrumentation amplifier based on the classic, 3-op-amp topology as shown in Figure 47. It is fabricated on the Analog Devices, Inc., proprietary iCMOS® process that provides precision, linear performance, and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 2, 5, and 10. Gain control is achieved by switching resistors in an internal, precision resistor array (as shown in Figure 47). Although the AD8250 has a voltage feedback topology, the gain bandwidth product increases for gains of 1, 2, and 5 because each gain has its own frequency compensation. This results in maximum bandwidth at higher gains.
All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout optimized for high CMRR over frequency enables the AD8250 to offer a guaranteed minimum CMRR over frequency of 80 dB at 50 kHz (G = 1). The balanced input reduces the parasitics that, in the past, adversely affected CMRR performance.

GAIN SELECTION

Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. See Tabl e 2 for the permissible voltage range of DGND. The gain of the AD8250 can be set using two methods.
–V
S
6288-054

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 48 shows an example of this gain setting method, referred to through­out the data sheet as transparent gain mode. Tie
WR
to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. is the truth table for transparent gain mode, and shows the
Tabl e 5
Figure 48
AD8250 configured in transparent gain mode.
+15
10F0.1µF
+IN
–IN
10F0.1µF
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO THE VOLT AGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EX AMP LE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.
Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10
WR
A1
AD8250
DGND DGND
–15V
A0
REF
–15V +5V +5V G = 10
.
S
06288-055
Rev. B | Page 15 of 24
AD8250
V
Table 5. Truth Table Logic Levels for Transparent Gain Mode
A1 A0 Gain
WR
−VS Low Low 1
−VS Low High 2
−VS High Low 5
−VS High High 10

Latched Gain Mode

Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8250 can be set using allowing other devices to share A0 and A1. shows a
WR
Figure 49
as a latch,
schematic using this method, known as latched gain mode. The AD8250 is in this mode when
WR
is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the
WR
signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table in for more information on these gain changes. Tabl e 6
+15
WR
10F0.1µF
+IN
–IN
10F0.1µF
NOTE:
1. ON THE DO WNWARD EDGE O F WR, AS IT TRANSITIO NS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RE SULTING I N A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.
+
AD8250
DGND DGND
–15V
Figure 49. Latched Gain Mode, G = 10
A1
A0
G = PREVIOUS STATE
REF
WR
A1
A0
+5V 0V
+5V 0V
+5V 0V
G = 10
06288-056
Table 6. Truth Table Logic Levels for Latched Gain Mode
A1 A0 Gain
WR
High to low Low Low Change to 1 High to low Low High Change to 2 High to low High Low High to low High High Low to low X Low to high X High to high X
1
X = don’t care.
1
X
1
X
1
X
1
1
1
Change to 5
Change to 10 No change No change No change
On power-up, the AD8250 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8250 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 at power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 have to be held for a minimum setup time, t WR
latches in the gain. Similarly, they must be held for a minimum hold time of t ensure that the gain is latched in correctly. After t
, before the downward edge of
SU
after the downward edge of WR to
HD
, A0 and A1
HD
can change logic levels, but the gain does not change (until the
WR
next downward edge of can be held high is t WR
can be held low is t listed in The time required for a gain change is dominated
Table 2 .
). The minimum duration that WR
, and the minimum duration that
WR-HIGH
. Digital timing specifications are
WR-LOW
by the settling time of the amplifier. A timing diagram is shown in .
Figure 50
When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8250. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board. Pull-up or pull-down resistors should be used to provide a well-defined voltage at the A0 and A1 pins.
t
WR-HIGH
WR
t
SU
A0, A1
Figure 50. Timing Diagram for Latched Gain Mode
Rev. B | Page 16 of 24
t
WR-LOW
t
HD
6288-057
AD8250
V

POWER SUPPLY REGULATION AND BYPASSING

The AD8250 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect per­formance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier.
Place a 0.1 µF capacitor close to each supply pin. A 10 µF tantalum capacitor can be used farther away from the part (see Figure 51) and, in most cases, it can be shared by other precision integrated circuits.
+
S
0.1µF
WR
A1
+IN
A0
AD8250
–IN
DGND
0.1µF 10µF
DGND
–V
S
Figure 51. Supply Decoupling, REF, and Output Referred to Ground
REF
10µF
LOAD
OUT
06288-058

INPUT BIAS CURRENT RETURN PATH

The AD8250 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 52).
INCORRECT
+V
S
AD8250
–V
TRANSFORMER
S
+V
S
AD8250
–V
THERMOCOUPLE
C
C
CAPACITIVELY COUPLED
S
+V
S
AD8250
–V
S
REF
Figure 52. Creating an I
REF
REF
10M
f
=
HIGH-PASS
2RC
CAPACITIVELY COUPLED
BIAS
CORRECT
TRANSFORMER
THERMOCOUPLE
C
R
1
C
R
Return Path
+V
S
AD8250
–V
S
+V
S
AD8250
–V
S
+V
S
AD8250
–V
S
REF
REF
REF

INPUT PROTECTION

All terminals of the AD8250 are protected against ESD. Note that 2.2 k series resistors precede the ESD diodes as shown in Figure 47. The resistors limit current into the diodes and allow for dc overload conditions 13 V above the positive supply and 13 V below the negative supply. An external resistor should be used in series with each input to limit current for voltages greater than 13 V beyond either supply rail. In either scenario, the AD8250 safely handles a continuous 6 mA current at room temperature. For applications where the AD8250 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used.
06288-059
Rev. B | Page 17 of 24
AD8250

REFERENCE TERMINAL

The reference terminal, REF, is at one end of a 10 k resistor (see Figure 47). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8250 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +V
by more than 0.5 V.
or −V
S
S
The output voltage of the AD8250 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground.

Coupling Noise

To prevent coupling noise onto the AD8250, do the following guidelines:
Do not run digital lines under the device.
Run the analog ground plane under the AD8250.
For best performance, especially in cases where the output is not measured with respect to the REF terminal, source imped­ance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy.
INCORRECT
AD8250
V
REF
Figure 53. Driving the Reference Pin
V
REF
CORRECT
AD8250
+
OP1177
6288-060

COMMON-MODE INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8250 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8250 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 27 and Figure 28 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains.

LAYOUT

Grounding

In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8250 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PCB can cause errors. Therefore, use separate analog and digital ground planes. Analog and digital ground should meet at only one point: star ground.
Shield fast switching signals with digital ground to avoid
radiating noise to other sections of the board, and never run them near analog signal paths.
Avoid crossover of digital and analog signals.
Connect digital and analog ground at one point only
(typically under the ADC).
Use the large traces on power supply lines to ensure a low
impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section.

Common-Mode Rejection

The AD8250 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical instrumentation amplifiers whose CMRR falls off around 200 Hz. Typical instrumentation amplifiers often need common-mode filters at their inputs to compensate for this shortcoming. The AD8250 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering.
Careful board layout maximizes system performance. To maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capaci­tance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), route it perpendicular to the input traces.
Rev. B | Page 18 of 24
AD8250
V
V

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 54. The filter limits the input signal bandwidth according to the following relationship:
FilterFreq
FilterFreq
where C
≥ 10 CC.
D
R
R
=
DIFF
=
CM
π
2
C
C
C
D
C
C
Figure 54. RFI Suppression
π
1
RC
C
0.1µF
+IN
–IN
0.1µF
1
D
CCR
+
C
+15
AD8250
–15V
)(22
10µF
OUT
REF
10µF
6288-061

DRIVING AN ADC

An instrumentation amplifier is often used in front of an ADC to provide CMRR. Usually, instrumentation amplifiers require a buffer to drive an ADC. However, the low output noise, low distortion, and low settle time of the AD8250 make it an excellent ADC driver.
In this example, a 1 nF capacitor and a 49.9 Ω resistor create an antialiasing filter for the AD7612. The 1 nF capacitor stores and delivers the necessary charge to the switched capacitor input of the ADC. The 49.9  series resistor reduces the burden of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8250 and the voltage at the input of the AD7612 but may destabilize the AD8250. A trade­off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability.
+15
10F0.1µF
+IN
IN
10F0.1µF
WR
AD8250
A1
A0
49.9
1nF
REF
DGNDDGND
+12V –12V
0.1F
AD7612
+5V
ADR435
0.1F
Values of R and CC should be chosen to minimize RFI. A mismatch between the R × C
at the negative input degrades the CMRR of the AD8250.
R × C
C
By using a value of C
, the effect of the mismatch is reduced and performance is
C
C
D
at the positive input and the
C
that is 10 times larger than the value of
improved.
–15V
06288-062
Figure 55. Driving an ADC
Rev. B | Page 19 of 24
AD8250
V
V
V

APPLICATIONS

DIFFERENTIAL OUTPUT

In certain applications, it is necessary to create a differential signal. High resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference.
Figure 57 shows how to configure the AD8250 to output a differential signal. An op amp, the AD817, is used in an inverting topology to create a differential voltage. V midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers.
sets the output
REF

SETTING GAINS WITH A MICROCONTROLLER

+15
10F0.1µF
+IN
IN
10F0.1µF
Figure 56. Programming Gain Using a Microcontroller
+
AD8250
–15V
WR
A1
CONTROLLER
A0
REF
DGNDDGND
MICRO-
06288-063
When using this circuit to drive a differential ADC, V
can be
REF
set using a resistor divider from the ADC reference to make the output ratiometric with the ADC.
+12
0.1F
+5
–5V
AMPLITUDE
+IN
V
IN
0.1F
+12V
–12V
10F
+
10F
WR
AD8250
G = 1
DGND
–12V
DGND
A1
A0
REF
4.99k
4.99k
Figure 57. Differential Output with Level Shift
–12V 10pF
0.1µF
V
OUT
AD817
V
OUT
A = VIN + V
2
+
+12V
0.1µF
B = –VIN + V
2
REF
REF
V 0V
AMPLITUDE
+2.5V
0V
–2.5V
REF
AMPLITUDE
+2.5V
0V
0V
–2.5V
TIME
TIME
06288-064
Rev. B | Page 20 of 24
AD8250

DATA ACQUISITION

The AD8250 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs.
Figure 59 shows a schematic of the AD825x data acquisition demonstration board. The quick slew rate of the AD8250 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8250, and ADG1209. In addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode.
This system achieved −111 dB of THD at 1 kHz and a signal-to­noise ratio of 91 dB during testing, as shown in Figure 58.
+CH1 +CH2
+CH3 +CH4
–CH4
–CH3 –CH2 –CH1
806 806
806 806
806
806 806
806
0.1µF
0.1µF
+12V
V
4
S1A
5
S2A
6
S3A S4A
7
ADG1209
10
S4B
11
S3B
12
S2B
13
S1B
V
–12V
+12V
+ 10µF 10µF
14
2
DD
EN
DA
DB
GND
A0
1
A1
16
SS 3
8
9
15
JMP
DGND
0
0
+5V
2k
0
0
GND
–12V
+
DGND
DGND
C
C
+IN
10
C
D
–IN
1
C
C
C3
0.1µF
2
6
WR
+
AD8250
–V
+V
S
8
+12V –12V
JMP
5
4
A1
A0 OUT
REF
9
S
3
C4
0.1µF
0 –10 –20 –30 –40 –50 –60 –70 –80 –90
AMPLITUDE ( dB)
–100 –110 –120 –130 –140
0 5 10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
Figure 58. FFT of the AD825x DAQ Demo Board Using the AD8250,
1 kHz Signal
JMP
JMP
+5V
7
+5V
DGND
2k
DGND
049.9
2k
–V
S
ALTERA
EPF6010ATC144-3
+IN
AD7612
1nF
ADR435
06288-066
DGND
JMP
+5V
R8 2k
DGND
06288-065
Figure 59. Schematic of ADG1209, AD8250, and AD7612 in the AD825x DAQ Demo Board
Rev. B | Page 21 of 24
AD8250

OUTLINE DIMENSIONS

3.10
3.00
2.90
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
10
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-187-BA
6
5.15
4.90
1
4.65
5
1.10 MAX
0.30
0.15
15° MAX
6° 0°
0.23
0.13
0.70
0.55
0.40
091709-A
Figure 60. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding
AD8250ARMZ –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H00 AD8250ARMZ-RL –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H00 AD8250ARMZ-R7 –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 AD8250-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
H00
Rev. B | Page 22 of 24
AD8250
NOTES
Rev. B | Page 23 of 24
AD8250
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06288-0-11/10(B)
Rev. B | Page 24 of 24
Loading...