ANALOG DEVICES AD8250 Service Manual

10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS

Programmable Gain Instrumentation Amplifier

FEATURES

Small package: 10-lead MSOP Programmable gains: 1, 2, 5, 10 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance

High CMRR 98 dB (minimum), G = 10 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.7 V/°C (maximum), G = 10

Excellent ac performance

Fast settling time: 615 ns to 0.001% (maximum) High slew rate: 20 V/µs (minimum) Low distortion: −110 dB THD at 1 kHz High CMRR over frequency: 80 dB to 50 kHz (minimum) Low noise: 18 nV/√Hz, G = 10 (maximum) Low power: 4.1 mA

APPLICATIONS

Data acquisition Biomedical analysis Test and measurement

GENERAL DESCRIPTION

The AD8250 is an instrumentation amplifier with digitally programmable gains that has GΩ input impedance, low output noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB and fast settling time of 615 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.7 μV/°C and 10 ppm/°C, respectively, for G = 10. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8250 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers.

The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word sent via a bus can be latched using the

to use the transparent gain mode where the state of the logic levels at the gain port determines the gain.

input. An alternative is

WR

AD8250

FUNCTIONAL BLOCK DIAGRAM

A1 A0DGND WR

4562

1

–IN

10

+IN

8 3

+V

25

20

15

10

5

GAIN (dB)

0

–5

–10

1k 10k 100k 1M 10M 100M

Table 1. Instrumentation Amplifiers by Category

General Purpose Zero Drift

AD82201 AD82311 AD620 AD6271 AD8250 AD8221 AD85531 AD621 AD6231 AD8251 AD8222 AD85551 AD524 AD82231 AD8253 AD82241 AD85561 AD526 AD8228 AD85571 AD624

1

Rail-to-rail output.

The AD8250 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations.

LOGIC

S

–V

S

Figure 1.

G = 10

G = 5

G = 2

G = 1

FREQUENCY (Hz)

Figure 2. Gain vs. Frequency

Mil Grade

AD8250

Low Power

REF

9

7

OUT

06288-001

High Speed PGA

06288-023

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8250

REVISION HISTORY

11/10—Rev. A to Rev. B

Changes to Voltage Offset, Offset RTI V

Temperature Coefficient Parameter in Table 2............................. 3

Updated Outline Dimensions....................................................... 22

5/08—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 1

Changes to Table 2............................................................................ 3

Changes to Table 3............................................................................ 6

Added Figure 17; Renumbered Sequentially ................................ 9

Changes to Figure 23...................................................................... 10

, Average

OS

Changes to Figure 24 to Figure 26................................................ 11

Added Figure 29 ............................................................................. 11

Changes to Figure 31...................................................................... 12

Deleted Figure 43 to Figure 46; Renumbered Sequentially ...... 14

Inserted Figure 45 and Figure 46.................................................. 14

Changes to Timing for Latched Gain Mode Section ................. 16

Changes to Layout Section and Coupling Noise Section.......... 18

Changes to Figure 59...................................................................... 21

1/07—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD8250

SPECIFICATIONS

+VS = 15 V, −VS = −15 V, V

Table 2.

Parameter Conditions Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR)

CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V

G = 1 80 98 dB G = 2 86 104 dB G = 5 94 110 dB G = 10 98 110 dB

CMRR to 50 kHz +IN = −IN = −10 V to +10 V

G = 1 80 dB G = 2 86 dB G = 5 90 dB G = 10 90 dB

NOISE

Voltage Noise, 1 kHz, RTI

G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 5 21 nV/√Hz G = 10 18 nV/√Hz

0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 5 1.5 μV p-p G = 10 1.0 μV p-p

Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p

VOLTAGE OFFSET

Offset RTI VOS G = 1, 2, 5, 10 ±(70 + 200/G) ±(200 + 600/G) μV

Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average Temperature Coefficient T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C

Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V

INPUT CURRENT

Input Bias Current 5 30 nA

Over Temperature T = −40°C to +85°C 40 nA Average Temperature Coefficient T = −40°C to +85°C 400 pA/°C

Input Offset Current 5 30 nA

Over Temperature T = −40°C to +85°C 30 nA Average Temperature Coefficient T = −40°C to +85°C 160 pA/°C

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 10 MHz G = 2 10 MHz G = 5 10 MHz G = 10 3 MHz

Settling Time 0.01% ΔOUT = 10 V step

G = 1 585 ns G = 2 605 ns G = 5 605 ns G = 10 648 ns

= 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.

REF

Rev. B | Page 3 of 24

AD8250

Parameter Conditions Min Typ Max Unit

Settling Time 0.001% ΔOUT = 10 V step

G = 1 615 ns G = 2 635 ns G = 5 635 ns G = 10 685 ns

Slew Rate

G = 1 20 V/μs G = 2 25 V/μs G = 5 25 V/μs G = 10 25 V/μs

Total Harmonic Distortion

f = 1 kHz, R

= 10 kΩ, ±10 V,

L

G = 1, 10 Hz to 22 kHz band-pass filter

GAIN

Gain Range G = 1, 2, 5, 10 1 10 V/V Gain Error OUT = ±10 V

G = 1 0.03 % G = 2, 5, 10 0.04 %

Gain Nonlinearity OUT = −10 V to +10 V

G = 1 RL = 10 kΩ, 2 kΩ, 600 Ω 6 ppm G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 5 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 10 ppm

Gain vs. Temperature All gains 10 ppm/°C

INPUT

Input Impedance

Differential 5.3||0.5 Common Mode 1.25||2

Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V Over Temperature T = −40°C to +85°C −VS + 1.6 +VS − 1.7 V

OUTPUT

Output Swing −13.5 +13.5 V Over Temperature T = −40°C to +85°C −13.5 +13.5 V Short-Circuit Current 37 mA

REFERENCE INPUT

RIN 20 kΩ IIN +IN, −IN, REF = 0 1 μA Voltage Range −VS +VS V Gain to Output 1 ± 0.0001 V/V

DIGITAL LOGIC

Digital Ground Voltage, DGND Referred to GND −VS + 4.25 0 +VS − 2.7 V Digital Input Voltage Low Referred to GND DGND 2.1 V Digital Input Voltage High Referred to GND 2.8 +VS V Digital Input Current 1 μA Gain Switching Time1 325 ns t

See Figure 3 timing diagram 20 ns

SU

tHD See Figure 3 timing diagram 10 ns t

-LOW

WR

t

-HIGH

WR

See Figure 3 timing diagram 20 ns See Figure 3 timing diagram 40 ns

−110 dB

GΩ||pF GΩ||pF

Rev. B | Page 4 of 24

AD8250

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −IS 3.7 4.5 mA Over Temperature T = −40°C to +85°C 4.5 mA

TEMPERATURE RANGE

Specified Performance −40 +85 °C

1

Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM

WR

t

WR-HIGH

t

WR-LOW

A0, A1

t

SU

t

HD

6288-057

Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

Rev. B | Page 5 of 24

AD8250

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±17 V Power Dissipation See Figure 4 Output Short-Circuit Current Indefinite1 Common-Mode Input Voltage +VS + 13 V, −VS − 13 V Differential Input Voltage +VS + 13 V, −VS − 13 V2 Digital Logic Inputs ±VS Storage Temperature Range −65°C to +125°C Operating Temperature Range3 −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 140°C θJA (Four-Layer JEDEC Standard Board) 112°C/W Package Glass Transition Temperature 140°C

1

Assumes that the load is referenced to midsupply.

2

Current must be kept to less than 6 mA.

3

Temperature for specified performance is −40°C to +85°C. For performance

to 125°C, see the Typical Performance Characteristics section.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8250 package is limited by the associated rise in junction temperature (T the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8250. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure.

The still-air thermal properties of the package and PCB (θ the ambient temperature (T the package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in

A

The junction temperature is calculated as

T

= TA + (PD × θJA)

J

) on

J

JA

),

The power dissipated in the package (P quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V quiescent current (I

). Assuming that the load (RL) is referenced

S

to midsupply, the total drive power is V is dissipated in the package and some in the load (V

The difference between the total drive power and the load power is the drive power dissipated in the package.

P

= Quiescent Power + (Total Drive Power − Load Power)

D

⎛

V

()

D

⎜

IVP

SS

⎜ ⎝

OUTS

×+×=

2

R

L

In single-supply operation with R case is V

OUT

= VS/2.

Airflow increases heat dissipation, effectively reducing θ addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ

.

JA

Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four-layer JEDEC standard board.

2.00

1.75

1.50

1.25

1.00

0.75

0.50

MAXIMUM POWER DISSIPATI ON (W)

0.25

0

–40 –20 120100806040200

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

AMBIENT TEM P E RATURE (°C)

ESD CAUTION

) is the sum of the

D

) times the

S

/2 × I

S

⎞ ⎟

⎟ ⎠

2

V

OUT

–

R

L

referenced to −VS, the worst

L

, some of which

OUT

× I

OUT

JA

. In

).

06288-004

Rev. B | Page 6 of 24

AD8250

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

1 2

DGND

–V

A0 A1

3

S

4 5

AD8250

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −VS Negative Supply Terminal. 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6

WR

Write Enable.

7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input.

10

+IN

9

REF +V

8

S

7

OUT

6

WR

06288-005

Rev. B | Page 7 of 24

AD8250

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 k, unless otherwise noted.

1400

500

1200

1000

800

600

NUMBER OF UNITS

400

200

0

–120 –90 –60 –30 0 30 60 90 120

CMRR (µV/V)

Figure 6. Typical Distribution of CMRR, G = 1

350

300

250

200

150

NUMBER OF UNITS

100

50

0

–200 2001000–100 –50 50–150 150

OFFSET VOLTAGE RTI ( µ V)

Figure 7. Typical Distribution of Offset Voltage, V

400

300

200

NUMBER OF UNITS

100

0

–30 3020100–20 –10

06288-006

INPUT OF FSET CURRENT (nA)

06288-009

Figure 9. Typical Distribution of Input Offset Current

90

80

70

60

50

40

30

NOISE RTI ( nV/ Hz)

20

10

0

1 10 100 1k 10k 100k

06288-007

OSI

Figure 10. Voltage Spectral Density Noise vs. Frequency

G = 1

G = 2 G = 5

G = 10

FREQUENCY (Hz)

06288-010

600

500

400

300

200

NUMBER OF UNITS

100

0

–30 3010 200–10–20

INPUT BIAS CURRENT (nA)

Figure 8. Typical Distribution of Input Bias Current

06288-008

Rev. B | Page 8 of 24

1s/DIV2µV/DIV

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

6288-011

ANALOG DEVICES AD8250 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

MAXIMUM POWER DISSIPATION

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS