ANALOG DEVICES AD8231 Service Manual

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A

Zero Drift, Digitally Programmable

FEATURES

Digitally/pin programmable gain

G = 1, 2, 4, 8, 16, 32, 64, 128

Specified from −40°C to +125°C

50 nV/°C maximum input offset drift
10 ppm/°C maximum gain drift

Excellent dc performance

80 dB minimum CMR, G = 1
15 µV maximum input offset voltage
500 pA maximum bias current

0.7 µV p-p noise (0.1 Hz to 10 Hz)

Good ac performance

2.7 MHz bandwidth, G = 1

1.1 V/s slew rate
Rail-to-rail input and output
Shutdown/multiplex
Extra op amp
Single supply range: 3 V to 6 V
Dual supply range: ±1.5 V to ±3 V

APPLICATIONS

Pressure and strain transducers
Thermocouples and RTDs
Programmable instrumentation
Industrial controls
Weigh scales

GENERAL DESCRIPTION

The AD8231 is a low drift, rail-to-rail, instrumentation ampli­fier with software programmable gains of 1, 2, 4, 8, 16, 32, 64, or

128. The gains are programmed via digital logic or pin
strapping.

The AD8231 is ideal for applications that require precision
performance over a wide temperature range, such as industrial
temperature sensing and data logging. Because the gain setting
resistors are internal, maximum gain drift is only 10 ppm/°C.
Because of the auto-zero input stage, maximum input offset is
15 µV and maximum input offset drift is just 50 nV/°C. CMRR
is also guaranteed over temperature at 80 dB for G = 1, increas­ing to 110 dB at higher gains.

Instrumentation Amplifier

AD8231

FUNCTIONAL BLOCK DIAGRAM

A216A115A014CS

13

1

NC

LOGIC

2

–INA

+IN

NC

3

4

IN-AMP

AD8231

5

SDN

OP

AMP

7

6

+INB

Figure 1.

–INB

Table 1. Instrumentation/Difference Amplifiers by Category

High
Performance

AD8221 AD6231AD628 AD620 AD6271AD8231

1

AD8220
AD8222 AD524 AD8251

1

AD8224

AD624 AD8556
AD8557

1

Rail-to-rail output.

Low
Cost

AD85531AD629 AD621 AD8250

AD526 AD8555

High
Voltage

Mil
Grade

The AD8231 also includes an uncommitted op amp that can be
used for additional gain, differential signal driving or filtering.
Like the in-amp, the op amp has an auto-zero architecture, rail­to-rail input, and rail-to-rail output.

The AD8231 includes a shutdown feature that reduces current
to a maximum of 1 µA. In shutdown, both amplifiers also have
a high output impedance. This allows easy multiplexing of
multiple amplifiers without additional switches.

The AD8231 is specified over the extended industrial tempera­ture range of −40°C to +125°C. It is available in a 4 mm × 4 mm
16-lead LFCSP (chip scale).

12

+V

S

11

–V

S

10

OUTA

9

REF

8

OUTB

Low
Power

06586-001

Digital
Gain

1

1

1

1

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD8231

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Instrumentation Amplifier Performance Curves..................... 9

Operational Amplifier Performance Curves ..........................12

Performance Curves Valid for Both Amplifiers..................... 13

Theory of Operation ...................................................................... 14

Amplifier Architecture .............................................................. 14

Gain Selection............................................................................. 14

Reference Terminal .................................................................... 14

Layout .......................................................................................... 15

Input Bias Current Return Path ............................................... 15

RF Interference........................................................................... 15

Common-Mode Input Voltage Range..................................... 16

Applications Information.............................................................. 17

Differential Output .................................................................... 17

Multiplexing................................................................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD8231

SPECIFICATIONS

VS = 5 V, V

Table 2.

Parameter Conditions Min Typ Max Unit
INSTRUMENTATION AMPLIFIER

OFFSET VOLTAGE VOS RTI = V

Input Offset, V

Average Temperature Drift TA = −40°C to +125°C 0.01 0.05 μV/°C

Output Offset, V

Average Temperature Drift TA = −40°C to +125°C 0.05 0.5 μV/°C

INPUT CURRENTS

Input Bias Current 250 500 pA

T

Input Offset Current 20 100 pA
T
GAINS 1, 2, 4, 8, 16, 32, 64, 128

Gain Error

G = 1 0.05 %
G = 2 to 128 0.8 %

Gain Drift

G = 1 3 10 ppm/°C
G = 2 to 128 3 10 ppm/°C

CMRR

G = 1 80 dB

G = 2 86 dB

G = 4 92 dB

G = 8 98 dB

G = 16 104 dB

G = 32 110 dB

G = 64 110 dB

G = 128 110 dB
NOISE en = √(e

Input Voltage Noise, eni f = 1 kHz 32 nV/√Hz

f = 1 kHz, TA = −40°C 27 nV/√Hz

f = 1 kHz, TA = 125°C 39 nV/√Hz

f = 0.1 Hz to 10 Hz, 0.7 μV p-p

Output Voltage Noise, eno f = 1 kHz 58 nV/√Hz
f = 1 kHz, TA = −40°C 50 nV/√Hz
f = 1 kHz, TA = 125°C 70 nV/√Hz
f = 0.1 Hz to 10 Hz 1.1 μV p-p
OTHER INPUT CHARACTERISTICS

Common-Mode Input Impedance 10||5 GΩ||pF

Power Supply Rejection Ratio 100 110 dB

Input Operating Voltage Range 0.05 4.95 V
REFERENCE INPUT

Input Impedance

Voltage Range

= 2.5 V, G = 1, RL = 10 kΩ, TA = 25°C, unless otherwise noted.

REF

+ V

OSI

4 15 μV

OSI

15 30 μV

OSO

= −40°C to +125°C 5 nA

A

= −40°C to +125°C 0.5 nA

A

2

+ (eno/G)2), V

ni

/G

OSO

, V

IN+

= 2.5 V

IN−

28 kΩ

−0.2 +5.2 V

Rev. 0 | Page 3 of 20

AD8231

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Bandwidth

G = 1 2.7 MHz
G = 2 2.5 MHz

Gain Bandwidth Product

G = 4 to 128 7 MHz

Slew Rate 1.1 V/μs

OUTPUT CHARACTERISTICS

Output Voltage High RL = 100 kΩ to ground 4.9 4.94 V
R

= 10 kΩ to ground 4.8 4.88 V

L

Output Voltage Low RL = 100 kΩ to 5 V 60 100 mV
R

= 10 kΩ to 5 V 80 200 mV

L

Short-Circuit Current 70 mA

DIGITAL INTERFACE

Input Voltage Low TA = −40°C to +125°C 1.0 V
Input Voltage High TA = −40°C to +125°C 4.0 V

T

Setup Time to CS high
Hold Time after CS high

OPERATIONAL AMPLIFIER

= −40°C to +125°C 50 ns

A

T

= −40°C to +125°C 20 ns

A

INPUT CHARACTERISTICS

Offset Voltage, VOS 5 15 μV

Temperature Drift TA = −40°C to +125°C 0.01 0.06 uV/°C
Input Bias Current 250 500 pA
T

= −40°C to +125°C 5 nA

A

Input Offset Current 20 100 pA
T

= −40°C to +125°C 0.5 nA

A

Input Voltage Range 0.05 4.95 V
Open-Loop Gain 100 120 V/mV
Common-Mode Rejection Ratio 100 120 dB
Power Supply Rejection Ratio 100 115 dB
Voltage Noise Density 20 nV/√Hz
Voltage Noise f = 0.1 Hz to 10 Hz 0.4 μV p-p

DYNAMIC PERFORMANCE

Gain Bandwidth Product 1 MHz
Slew Rate 0.5 V/μs

OUTPUT CHARACTERISTICS

Output Voltage High RL = 100 kΩ to ground 4.9 4.96 V
R

= 10 kΩ to ground 4.8 4.92 V

L

Output Voltage Low RL = 100 kΩ to 5 V 60 100 mV
R

= 10 kΩ to 5 V 80 200 mV

L

Short-Circuit Current 70 mA

BOTH AMPLIFIERS
POWER SUPPLY

Quiescent Current 4 5 mA
Quiescent Current (Shutdown) 0.01 1 μA

Rev. 0 | Page 4 of 20

AD8231

VS = 3.0 V, V

Table 3.

Parameter Conditions Min Typ Max Unit
INSTRUMENTATION AMPLIFIER

OFFSET VOLTAGE VOS RTI = V

Input Offset, V
Average Temperature Drift 0.01 0.05 μV/°C
Output Offset, V
Average Temperature Drift 0.05 0.5 μV/°C

INPUT CURRENTS

Input Bias Current 250 500 pA
T
Input Offset Current 20 100 pA
T

GAINS 1, 2, 4, 8, 16, 32, 64, 128

Gain Error

G = 1 0.05 %
G = 2 to 128 0.8 %

Gain Drift

G = 1 3 10 ppm/°C
G = 2 to 128 3 10 ppm/°C

CMRR

G = 1 80 dB
G = 2 86 dB
G = 4 92 dB
G = 8 98 dB
G = 16 104 dB
G = 32 110 dB
G = 64 110 dB
G = 128 110 dB

NOISE

Input Voltage Noise, eni f = 1 kHz 40 nV/√Hz
f = 1 kHz, TA = −40°C 35 nV/√Hz
f = 1 kHz, TA = 125°C 48 nV/√Hz
f = 0.1 Hz to 10 Hz 0.8 μV p-p
Output Voltage Noise, eno f = 1 kHz 72 nV/√Hz
f = 1 kHz, TA = −40°C 62 nV/√Hz
f = 1 kHz, TA = 125°C 83 nV/√Hz
f = 0.1 Hz to 10 Hz 1.4 μV p-p

OTHER INPUT CHARACTERISTICS

Common-Mode Input Impedance 10||5 GΩ||pF
Power Supply Rejection Ratio 100 110 dB
Input Operating Voltage Range 0.05 2.95 V

REFERENCE INPUT

Input Impedance
Voltage Range

= 1.5 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.

REF

+ V

OSI

4 15 μV

OSI

15 30 μV

OSO

= −40°C to +125°C 5 nA

A

= −40°C to +125°C 0.5 nA

A

2

= √(e

e

n

V

IN+

+ (eno/G)2)

ni

, V

= 2.5 V, TA = 25°C

IN−

/G

OSO

28 kΩ||pF

−0.2 +3.2 V

Rev. 0 | Page 5 of 20

AD8231

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Bandwidth

G = 1 2.7 MHz

G = 2 2.5 MHz
Gain Bandwidth Product

G = 4 to 128 7 MHz
Slew Rate 1.1 V/μs

OUTPUT CHARACTERISTICS

Output Voltage High RL = 100 kΩ to ground 2.9 2.94 V
R
Output Voltage Low RL = 100 kΩ to 3 V 60 100 mV
R
Short-Circuit Current 70 mA

DIGITAL INTERFACE

Input Voltage Low TA = −40°C to +125°C 0.7 V
Input Voltage High TA = −40°C to +125°C 2.3 V

Setup Time to CS high
Hold Time after CS high

OPERATIONAL AMPLIFIER
INPUT CHARACTERISTICS

Offset Voltage, VOS 5 15 μV
Temperature Drift TA = −40°C to +125°C 0.01 0.06 μV/°C
Input Bias Current 250 500 pA
T
Input Offset Current 20 100 pA
T
Input Voltage Range 0.05 2.95 V
Open-Loop Gain 100 120 V/mV
Common-Mode Rejection Ratio 100 120 dB
Power Supply Rejection Ratio 100 115 dB
Voltage Noise Density 27 nV/√Hz
Voltage Noise f = 0.1 Hz to 10 Hz 0.6 μV p-p

DYNAMIC PERFORMANCE

Gain Bandwidth Product 1 MHz
Slew Rate 0.5 V/μs

OUTPUT CHARACTERISTICS

Output Voltage High RL = 100 kΩ to ground 2.9 2.96 V
R
Output Voltage Low RL = 100 kΩ to 3 V 60 100 mV
R
Short-Circuit Current 70 mA

BOTH AMPLIFIERS
POWER SUPPLY

Quiescent Current 3.5 4.5 mA
Quiescent Current (Shutdown) 0.01 1 μA

= 10 kΩ to ground 2.8 2.88 V

L

= 10 kΩ to 3 V 80 200 mV

L

TA = −40°C to +125°C 60 ns
TA = −40°C to +125°C 20 ns

= −40°C to +125°C 5 nA

A

= −40°C to +125°C 0.5 nA

A

= 10 kΩ to ground 2.8 2.82 V

L

= 10 kΩ to 3 V 80 200 mV

L

Rev. 0 | Page 6 of 20

AD8231

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 6 V
Output Short-Circuit Current Indefinite1
Input Voltage (Common-Mode) −VS − 0.3 V to +VS + 0.3 V
Differential Input Voltage −VS − 0.3 V to +VS + 0.3 V
Storage Temperature Range –65°C to +150°C
Operational Temperature Range –40°C to +125°C
Package Glass Transition Temperature 130°C
ESD (Human Body Model) 1.5 kV
ESD (Charged Device Model) 1.5 kV
ESD (Machine Model) 0.2 kV

1

For junction temperatures between 105°C and 130°C, short-circuit operation

beyond 1000 hours may impact part reliability.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

Table 5.

Thermal Pad θJA Unit

Soldered to Board 54 °C/W
Not Soldered to Board 96 °C/W

The θJA values in Tabl e 5 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, then it is
also assumed it is connected to a plane. θ

at the exposed pad

JC

is 6.3°C/W.

Maximum Power Dissipation

The maximum safe power dissipation for the AD8231 is limited
by the associated rise in junction temperature (T

) on the die. At

J

approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform­ance of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.

ESD CAUTION

Rev. 0 | Page 7 of 20

AD8231

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S

A1

A2

A0

C

14

13

15

16

PIN 1

1NC

2(IN-AMP –IN) –INA

3(IN-AMP +IN) +INA

4NC

INDICATO R

AD8231

TOP VIEW

(Not to Scale)

12 +V

S

11 –V

S

10 OUTA (IN-AMP OUT)

9REF

NC = NO CONNECT

8

7

5

6

SDN

–INB

+INB

(OP AMP OUT) OUTB

06586-002

Figure 2. 16-Lead LFCSP (Chip Scale)

Table 6. Pin Function Descriptions

Pin Number Mnemonic Description

1 NC No Connect.
2 −INA In-Amp Negative Input.
3 +INA In-Amp Positive Input.
4 NC No Connect.
5

SDN

Shutdown.
6 +INB Op Amp Positive Input.
7 −INB Op Amp Negative Input.
8 OUTB Op Amp Output.
9 REF

In-Amp Reference Pin. It should be driven with a low impedance. Output is referred to

this pin.
10 OUTA In-Amp Output.
11 −VS Negative Power Supply. Connect to ground in single supply applications.
12 +VS Positive Power Supply.
13

CS

Chip Select. Enables digital logic interface.
14 A0 Gain Setting Bit (LSB).

15 A1 Gain Setting Bit.
16 A2 Gain Setting Bit (MSB).

Rev. 0 | Page 8 of 20

AD8231

TYPICAL PERFORMANCE CHARACTERISTICS

INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES

6

0V, 4.96V

5

4

INPUT COMMO N-MODE VOL TAGE (V)

3

2

1

0

0654321

5V SINGLE SUPPLY

0V, 2.96V

3V SINGLE SUPPLY

0V, 0.04V

2.92V, 1.5V

OUTPUT VOLTAGE (V)

4.92V, 2.5V

Figure 3. Input Common-Mode Range vs. Output Voltage, V

REF

= 0 V

06586-003

50

40

30

20

10

0

GAIN (dB)

–10

–20

–30

–40

100 10M1M100k10k1k

G = +128

G = +64

G = +32

G = +16

G = +8

G = +4

G = +2

G = +1

FREQUENCY (Hz)

Figure 6. Gain vs. Frequency

06586-009

6

5

0.02V, 4.22V

4

3

0.02V, 2.22V

2

1

0.02V, 0.78V

INPUT COMMON-MODE VOLTAGE (V)

0

05

Figure 4. Input Common-Mode Range vs. Output Voltage, V

6

5

4

0.02V, 3.72V

3

2

0.02V, 1.72V

1

INPUT COMMO N-MODE VOL TAGE (V)

0.02V, 1.28V

0

054.54.03.53.02.52.01.51.00.5

Figure 5. Input Common-Mode Range vs. Output Voltage, V

1.5V, 4.96V

5V SINGLE SUPPLY

1.5V, 2.96V

2.98V, 2.22V

3V SINGLE SUPPLY

2.98V, 0.78V

1.5V, 0.04V

OUTPUT VOLTAGE (V)

2.5V, 4.96V

5V SINGLE SUPPLY

2.5V, 2.96V

3V SINGL E

SUPPLY

2.5V, 0.04V

OUTPUT VOLTAGE (V)

2.98V, 2.72V

2.98V, 0.28V

4.98V, 3.22V

4.98V, 1.78V

REF

4.98V, 3.72V

4.98V,1.28V

REF

.04.54.03.53.02.52.01.51.00.5

06586-004

= 1.5 V

.0

06586-005

= 2.5 V

140

120

100

CMRR (dB)

80

60

40

10 100 1k 10k 100k

G = +128

G = +8

G = +1

FREQUENCY (Hz)

Figure 7. CMRR vs. Frequency

G = +128, 0.4µV/DIV

G = +1, 1µV/DIV

Figure 8. 0.1 Hz to 10 Hz Noise

1s/DIV

06586-010

06586-012

Rev. 0 | Page 9 of 20

AD8231

100

G = +1
G = +8

90

G = +128

80

70

60

50

40

NOISE (nV/ Hz)

30

20

10

0

1 10 100 1k

FREQUENCY (Hz)

06586-011

Figure 9. Voltage Noise Spectral Density vs. Frequency, 5 V, 1 Hz to 1000 Hz

1.0

0.8

0.6

0.4

0.2

0

–0.2

BIAS CURRENT (nA)

–0.4

–0.6

–0.8

–1.0

–1.5 1.51.20.90.60.30–0.3–0.6–0.9–1.2

VCM (V)

Figure 12. Bias Current vs. Common-Mode Voltage, 3 V

+VS = +1.5V
–V

= –1.5V

S

V

= 0V

REF

06586-007

1000

NOISE (nV/ Hz)

G = +1
G = +8

900

G = +128

800

700

600

500

400

300

200

100

0

1 10 100 1 k 10k 100k

FREQUENCY (Hz)

06586-008

Figure 10. Voltage Noise Spectral Density vs. Frequency, 5V, 1 Hz to 1 MHz

2.0

1.5

1.0

0.5

0

–0.5

BIAS CURRENT (nA)

–1.0

–1.5

–2.0

–2.5 2.52.01.51.00.50–0.5–1.0–1.5–2.0

VCM (V)

+VS = +2.5V
–V

= –2.5V

S

V

= 0V

REF

06586-006

Figure 11. Bias Current vs. Common-Mode Voltage, 5 V

5µs/DIV20mV/DIV

06586-013

Figure 13. Small Signal Pulse Response, G = 1, R

500pF

NO

LOAD

300pF

800pF

= 2 kΩ, CL = 500 pF

L

4µs/DIV20mV/DIV

06586-014

Figure 14. Small Signal Pulse Response for Various Capacitive Loads, G = 1

Rev. 0 | Page 10 of 20

AD8231

G = +8

G = +32
G = +128

2V/DIV

17.6µs TO 0. 01%

21.4µs TO 0.001%

Figure 15. Small Signal Pulse Response, G = 8, 32, 128, R

2V/DIV

3.95µs TO 0. 01%
4µs TO 0. 001%

Figure 16. Large Signal Pulse Response, G = 1, V

2V/DIV

10µs/DIV20mV/DIV

= 2 kΩ, CL = 500 pF

L

10µs/DIV0.001%/DIV

= 5 V

S

06586-015

06586-016

Figure 18. Large Signal Pulse Response, G = 128, V

25

20

0.001%

15

10

SETTLING TIME (µs)

5

0

1110010

GAIN (V/V)

Figure 19. Settling Time vs. Gain for a 4 V p-p Step, V

25

20

15

0.01%

0.001%

0.01%

100µs/DIV0.001%/DIV

06586-018

= 5 V

S

k

06586-019

= 5 V

S

3.75µs TO 0.01%

3.8µs TO 0.001%

10µs/DIV0.001%/DIV

Figure 17. Large Signal Pulse Response, G = 8, V

= 5 V

S

06586-017

Rev. 0 | Page 11 of 20

10

SETTLING TIME (µs)

5

0

1110010

GAIN (V/V)

Figure 20. Settling Time vs. Gain for a 2 V p-p Step, V

k

06586-020

= 3 V

S

AD8231

–

–

OPERATIONAL AMPLIFIER PERFORMANCE CURVES

100

80

90

–100

NO

LOAD

60

40

20

OPEN-LOOP GAIN (dB)

0

RL = 10kΩ

= 200pF

C

L

–20

10 10M1M100k10k1k100

FREQUENCY (Hz)

Figure 21. Open Loop Gain and Phase vs. Frequency, V

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

RL = 10kΩ

= 200pF

C

L

–20

10 10M1M100k10k1k100

FREQUENCY (Hz)

Figure 22. Open Loop Gain and Phase vs. Frequency, V

76° PHASE

MARGIN

72° PHASE

MARGIN

= 5 V

S

= 3 V

S

–110

–120

–130

–140

–150

90

–100

–110

–120

–130

–140

–150

300pF

800pF

1nF

OPEN-LOOP PHASE SHIFT (Degrees)

06586-021

Figure 24. Small Signal Response for Various Capacitive Loads, V

NO

LOAD

OUTPUT VOLTAGE (0.5V/DIV)

OPEN-LOOP PHASE SHIFT (Degrees)

06586-022

Figure 25. Large Signal Transient Response, V

1.5nF

1nF║2kΩ

1.5nF║2kΩ

TIME (5µs/DIV)

5µs/DIV20mV/DIV

= 5 V

S

06586-024

= 3 V

S

06586-025

NO

LOAD

1nF║2kΩ

1.5nF║2kΩ

OUTPUT VOLTAGE (0.5V/DIV)

TIME (5µs/DIV)

Figure 26. Large Signal Transient Response, V

= 3 V

S

06586-026

NO

LOAD

800pF

1nF

2nF

1.5nF

5µs/DIV20mV/DIV

Figure 23. Small Signal Response for Various Capacitive Loads, V

06586-023

= 5 V

S

Rev. 0 | Page 12 of 20

AD8231

PERFORMANCE CURVES VALID FOR BOTH AMPLIFIERS

7

6

5

4

(mA)

3

SUPPLY

I

2

1

+125°C

+85°C

+25°C

–40°C

5

4

–40°C SOURCE

+25°C SOURCE

+85°C SOURCE

3

+125°C SOURCE

–40°C SINK

+25°C SINK

2

OUTPUT VO LTAGE (V )

+85°C SINK

+125°C SINK

1

0

2.7 5.95.55.14.74. 33.93.53.1

V

SUPPLY

Figure 27. Supply Current vs. Supply Voltage

3.0

2.5

2.0

1.5

1.0

OUTPUT VO LTAGE (V )

0.5

–40°C SOURCE

+25°C SOURCE

+85°C SOURCE

+125°C SOURCE

–40°C SINK

+25°C SINK

+85°C SINK

+125°C SINK

0

022015105

OUTPUT CURRENT (mA)

Figure 28. Output voltage Swing vs. Output Current, V

(V)

0

022015105

06586-028

Figure 29. Output Voltage Swing vs. Output Current, V

5

06586-029

= 3 V

S

OUTPUT CURRENT (mA)

5

06586-030

= 5 V

S

Rev. 0 | Page 13 of 20

AD8231

THEORY OF OPERATION

CS A0 A1 A2 SDN

OUTB

–INA

A1

14kΩ14kΩ

A4

A3

–INB

+INB

OUTA

+INA

A2

+V

S

Figure 30. Simplified Schematic

AMPLIFIER ARCHITECTURE

The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage.

Figure 30 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of A3 and four 14 k
resistors. Amplifier A1, Amplifier A2, and Amplifier A3 are all
zero drift, rail-to-rail input, rail-to rail-output amplifiers.

The AD8231 design makes it extremely robust over tempera­ture. The AD8231 uses an internal thin film resistor to set the
gain. Since all of the resistors are on the same die, gain
temperature drift performance and CMRR drift performance
are better than can be achieved with topologies using external
resistors. The AD8231 also uses an auto-zero topology to null
the offsets of all its internal amplifiers. Since this topology
continually corrects for any offset errors, offset temperature
drift is nearly nonexistent.

The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.

GAIN SELECTION

The AD8231’s gain is set by voltages applied to the A0, A1,
and A2 pins. To change the gain, the
low. When the

CS

pin is driven high, the gain is latched, and
voltages at the A0 to A2 pins have no effect.
different gain settings.

The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to
through

Figure 20 to determine the settling time for different

gains.

CS

pin must be driven

Tabl e 7 shows the

Figure 16

14kΩ14kΩ

AD8231

S

REF–V

6586-031

Table 7. Truth Table for AD8231 Gain Settings

A2 A1 A0 Gain

CS

Low Low Low Low 1
Low Low Low High 2
Low Low High Low 4
Low Low High High 8
Low High Low Low 16
Low High Low High 32
Low High High Low 64
Low High High High 128
High X X X No change

REFERENCE TERMINAL

The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to level­shift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +V

For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in
terminal, REF, is at one end of a 14 k resistor. Additional
impedance at the REF terminal adds to this 14 k resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.

or −VS by more than 0.3 V.

S

Figure 30, the reference

Rev. 0 | Page 14 of 20

AD8231

V

INCORRECT

AD8231

IN-AMP

REF

V

REF

CORRECT

+

AD8231

OP AMP

–

AD8231

IN-AMP

06586-032

Figure 31. Driving the Reference Pin

LAYOUT

The AD8231 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout. The AD8231 pinout is arranged in
a logical manner to aid in this task.

Power Supplies

The AD8231 should be decoupled with a 0.1 µF bypass capacitor
between the two supplies. This capacitor should be placed as close
as possible to Pin 11 and Pin 12, either directly next to the pins or
beneath the pins on the backside of the board. The AD8231’s auto­zero architecture requires a low ac impedance between the supplies.
Long trace lengths to the bypass capacitor increase this impedance,
which results in a larger input offset voltage.

A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.

Package Considerations

The AD8231 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; it may not have the same thermal pad size and
leads. Refer to the
PCB symbol has the correct dimensions. Space between the
leads and thermal pad should be kept as wide as possible for the
best bias current performance.

Thermal Pad

The AD8231 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to −V
left unconnected or connected to the negative supply rail. For
high vibration applications, a landing is recommended.

Because the AD8231 dissipates little power, heat dissipation is
rarely an issue. If improved heat dissipation is desired (for
example, when ambient temperatures are near 125°C or when
driving heavy loads), connect the thermal pad to the negative
supply rail. For the best heat dissipation performance, the
negative supply rail should be a plane in the board. See the
Thermal Resistance section for thermal coefficients with and
without the pad soldered.

Outline Dimensions section to verify that the

. The pad can either be

S

INPUT BIAS CURRENT RETURN PATH

The input bias current of the AD8231 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in

Figure 32.

INCORRECT

+V

S

AD8231

REF

–V

S

TRANSFORMER

+V

S

AD8231

REF

–V

S

THERMOCOUPL E

+V

S

C

AD8231

C

CAPACITIVELY COUPLED

REF

–V

S

Figure 32. Creating an I

f

HIGH-PASS

10MΩ

1

=

2πRC

CAPACITIVEL Y COUPLED

TRANSFORMER

THERMOCOUPL E

C

R

C

R

Path

BIAS

CORRECT

+V

S

AD8231

–V

S

+V

S

AD8231

–V

S

+V

S

AD8231

–V

S

REF

REF

REF

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the input
of the instrumentation amplifier, as shown in
filter limits the input signal bandwidth according to the
following relationship:

FilterFreq

FilterFreqπ=

C

where

≥ 10CC.

D

Diff

CM

=

1

D

1

RC

2

C

)(22

CCR

+π

C

Figure 33. The

6586-033

Rev. 0 | Page 15 of 20

AD8231

V

C

C

1nF

R

4.02kΩ

4.02kΩ

C

D

10nF

R

C

C

1nF

0.1µF

+INA

–INA

0.1µF

+

S

AD8231

–V

S

REF

10µF

10µF

V

OUT

06586-034

Figure 33. RFI Suppression

Figure 33 shows an example where the differential filter
frequency is approximately 2 kHz, and the common-mode filter
frequency is approximately 40 kHz.

Val u es of R an d C
between the R × C

should be chosen to minimize RFI. Mismatch

C

at the positive input and the R × CC at

C

negative input degrades the CMRR of the AD8231. By using a
value of C

ten times larger than the value of CC, the effect of

D

the mismatch is reduced and performance is improved.

COMMON-MODE INPUT VOLTAGE RANGE

The 3-op amp architecture of the AD8231 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8231 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal could
be limited, refer to
formula:

If more common mode range is required, the simplest solution is to
apply less gain in the instrumentation amplifier. The extra op amp
can be used to provide another gain stage after the in-amp. Because
the AD8231 has good offset and noise performance at low gains,
applying less gain in the instrumentation amplifier generally has a
limited impact on the overall system performance.

Figure 3 through Figure 5 or use the following

×

GainV

V04.0 −+<

VV

DIFF

±<+−

CMS

2

V

S

V04.0

Rev. 0 | Page 16 of 20

AD8231

APPLICATIONS INFORMATION

DIFFERENTIAL OUTPUT

Figure 34 shows how to create a differential output in-amp
using the AD8231 uncommitted op amp. Errors from the op
amp are common to both outputs and are thus common-mode.
Errors from mismatched resistors also create a common-mode
dc offset. Because these errors are common-mode, they will
likely be rejected by the next device in the signal chain.

3

+IN

IN-AMP

2

–IN

Figure 34. Differential Output Using Op Amp

REF

9

4.99kΩ

4.99kΩ

10

76

–

OP AMP

+OUT

V

REF

+

8

–OUT

06586-035

MULTIPLEXING

SDN0

SDN1

SDN2

SDN3

06586-036

Figure 35.

The outputs of both the AD8231 in-amp and op amp are high
impedance in the shutdown state. This feature allows several
AD8231s to be multiplexed together without any external
switches.

Figure 35 shows an example of such a configuration.
All the outputs are connected together and only one amplifier is
turned on at a time. This feature is analogous to the high Z
mode of digital tristate logic. Because the output impedance in
shutdown is multiple megaohms, several thousand AD8231s
can theoretically be multiplexed in such a way.

The AD8231 can enter and leave shutdown mode very quickly.
However, when the amplifier wakes up and reconnects its input
circuitry, the voltage at its internal input nodes changes dramati­cally. It will take time for the output of the amplifier to settle.
Refer to

Figure 16 through Figure 20 to determine the settling
time for different gains. This settling time limits how quickly
the user can multiplex the AD8231 with the

SDN

pin.

Rev. 0 | Page 17 of 20

AD8231

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.30

0.25

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

(BOTTOM VIEW)

13

12

9

8

16

1

4

5

1.95 BSC

PIN 1
INDICATOR

5

2

.

2

S

0

1

.

2

9

.

1

5

0.25 MIN

Q

COMPLIANT TO JEDEC STANDARDS MO-220-VGG C

021207-A

Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8231ACPZ-R7
AD8231ACPZ-RL
AD8231ACPZ-WP

1

Z = RoHS Compliant Part.

1

1

1

−40°C to +125°C 16-Lead LFCSP_VQ, 7” Tape and Reel CP-16-4

−40°C to +125°C 16-Lead LFCSP_VQ, 13” Tape and Reel CP-16-4

−40°C to +125°C 16-Lead LFCSP_VQ, Waffle Pack CP-16-4

Rev. 0 | Page 18 of 20

AD8231

NOTES

Rev. 0 | Page 19 of 20

AD8231

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06586-0-5/07(0)

Rev. 0 | Page 20 of 20