ANALOG DEVICES AD8226 Service Manual

Wide Supply Range, Rail-to-Rail

FEATURES

Gain set with 1 external resistor
Gain range: 1 to 1000 Input voltage goes below ground Inputs protected beyond supplies Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supplies: ±1.35 V to ±18 V Bandwidth (G = 1): 1.5 MHz CMRR (G = 1): 90 dB minimum for BR models Input noise: 22 nV/√Hz Typical supply current: 350 μA Specified temperature: −40°C to +125°C 8-lead SOIC and MSOP packages

APPLICATIONS

Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems
Output Instrumentation Amplifier
AD8226

PIN CONFIGURATION

AD8226
1
–IN
2
R
G
3
R
G
4
+IN
TOP VIEW
(Not to S cale)
Figure 1.
Table 1. Instrumentation Amplifiers by Category
General Purpose
Zero Drift
Military Grade
AD8220 AD8231 AD620 AD627 AD8250 AD8221 AD8290 AD621 AD623 AD8251 AD8222 AD8293 AD524 AD8223 AD8253 AD8224 AD8553 AD526 AD8226 AD8228 AD8556 AD624 AD8227 AD8295 AD8557
1
Visit www.analog.com for the latest instrumentation amplifiers.
8
+V
7
V
OUT
6
REF
5
–V
Low Power
S
S
07036-001
1
High Speed PGA

GENERAL DESCRIPTION

The AD8226 is a low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain between 1 and 1000.
The AD8226 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range also includes the ability to go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The AD8226 operates on supplies ranging from ±1.35 V to ±18 V for dual supplies and 2.2 V to 36 V for single supply.
The robust AD8226 inputs are designed to connect to real­world sensors. In addition to its wide operating range, the
AD8226 can handle voltages beyond the rails. For example, with a ±5 V supply, the part is guaranteed to withstand ±35 V at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection.
The AD8226 is perfect for multichannel, space-constrained industrial applications. Unlike other low cost, low power instrumentation amplifiers, the AD8226 is designed with a minimum gain of 1 and can easily handle ±10 V signals. With its MSOP package and 125°C temperature rating, the AD8226 thrives in tightly packed, zero airflow designs.
The AD8226 is available in 8-lead MSOP and SOIC packages, and is fully specified for −40°C to +125°C operation.
For a device with a similar package and performance as the AD8226 but with gain settable from 5 to 1000, consider using
AD8227.
the
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
AD8226

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Architecture ................................................................................. 19

REVISION HISTORY

7/09—Rev. 0 to Rev. A
Added BRZ and BRM Models .......................................... Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 1
Changes to General Description Section ...................................... 1
Changes to Gain vs. Temperature Parameter, Output Parameter,
and Operating Range Parameter, Table 2 ......................................... 4
Changes to Common-Mode Rejection Ratio (CMRR) Parameter
and to Input Offset, V
Parameter, Table 3 ........................................................................ 5
Changes to Gain vs. Temperature Parameter, Table 3 ................. 6
Changes to Gain Selection Section ............................................... 19
Changes to Reference Terminal Section and Input Voltage
Range Section .............................................................................. 20
Changes to Ordering Guide .......................................................... 25
1/09—Revision 0: Initial Version
, Average Temperature Coefficient
OSO
Gain Selection ............................................................................. 19
Reference Terminal .................................................................... 20
Input Voltage Range ................................................................... 20
Layout .......................................................................................... 20
Input Bias Current Return Path ............................................... 21
Input Protection ......................................................................... 22
Radio Frequency Interference (RFI) ........................................ 22
Applications Information .............................................................. 23
Differential Drive ....................................................................... 23
Precision Strain Gage ................................................................. 24
Driving an ADC ......................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
Rev. A | Page 2 of 28
AD8226

SPECIFICATIONS

+VS = +15 V, −VS = −15 V, V
Table 2.
ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = −10 V to +10 V
CMRR with DC to 60 Hz
G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB
CMRR with DC at 5 kHz
G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB
NOIS E Total noise: eN = √(e
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
Input Offset, V
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C Output Offset, V
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 μV/°C Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current
T
T
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C Input Offset Current TA = +25°C 1.5 0.5 nA T T
Average Temperature Coefficient TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
V
OSI
V
OSO
1
T
= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
REF
2
+ (eNO/G)2)
NI
= V
+ (V
V
OS
OSI
= ±5 V to ±15 V 200 100 μV
S
= ±5 V to ±15 V 1000 500 μV
S
= +25°C 5 20 27 5 20 27 nA
A
= +125°C 5 15 25 5 15 25 nA
A
= −40°C 5 30 35 5 30 35 nA
A
= +125°C 1.5 0.5 nA
A
= −40°C 2 0.5 nA
A
OSO
/G)
Rev. A | Page 3 of 28
AD8226
ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 10 V step
G = 1 25 25 μs G = 10 15 15 μs G = 100 40 40 μs
G = 1000 350 350 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V Gain Error V
G = 1 0.04 0.01 %
G = 5 to 1000 0.3 0.1 % Gain Nonlinearity V
G = 1 to 10 RL ≥ 2 kΩ 10 10 ppm
G = 100 RL ≥ 2 kΩ 75 75 ppm
G = 1000 RL ≥ 2 kΩ 750 750 ppm Gain vs. Temperature
2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
T
G > 1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT VS = ±1.35 V to +36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range
3
T
T T Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 2 kΩ to Ground
T
T
T
RL = 10 kΩ to Ground
T
T
T
RL = 100 kΩ to Ground
T Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V Quiescent Current TA = +25°C 350 425 350 425 μA T T T
TEMPERATURE RANGE −40 +125 −40 +125 °C
1
The input stage uses pnp transistors; therefore, input bias current always flows into the part.
2
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the section for more information. Input Voltage Range
±10 V
OUT
= −10 V to +10 V
OUT
= 85°C to 125°C 5 2 ppm/°C
A
= +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V
A
= +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V
A
= −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V
A
= +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V
A
= +125°C −VS + 0.4 +VS – 1.0 −VS + 0.4 +VS – 1.0 V
A
= −40°C −VS + 1.2 +VS – 1.1 −VS + 1.2 +VS – 1.1 V
A
= +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
A
= +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V
A
= −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
A
= −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V
A
= −40°C 250 325 250 325 μA
A
= +85°C 450 525 450 525 μA
A
= +125°C 525 600 525 600 μA
A
Rev. A | Page 4 of 28
AD8226
+VS = 2.7 V, −VS = 0 V, V
Table 3.
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 1.7 V
CMRR with DC to 60 Hz
G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB
CMRR with DC at 5 kHz
G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB
NOISE Total noise: eN = √(e
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2.0 2.0 μV p-p G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage: VOS = V
Input Offset, V
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C Output Offset, V
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 μV/°C Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current T T
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C Input Offset Current TA = +25°C 1.5 0.5 nA T T
Average Temperature Coefficient TA =−40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
200 100 μV
OSI
1000 500 μV
OSO
1
T
= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
REF
2
+ (eNO/G2))
NI
+ (V
/G)
OSI
OSO
= +25°C 5 20 27 5 20 27 nA
A
= +125°C 5 15 25 5 15 25 nA
A
= −40°C 5 30 35 5 30 35 nA
A
= +125°C 1.5 0.5 nA
A
= −40°C 1 0.1 nA
A
Rev. A | Page 5 of 28
AD8226
ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 2 V step
G = 1 6 6 μs G = 10 6 6 μs G = 100 35 35 μs
G = 1000 350 350 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V Gain Error
G = 1 V
G = 5 to 1000 V Gain vs. Temperature
2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
T
G > 1 TA = −40°C to +125°C −100 ppm/°C
INPUT −VS = 0 V, +VS = 2.7 V to 36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range
3
T
T T Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40
OUTPUT
Output Swing RL = 10 kΩ to 1.35 V,
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Single-supply operation 2.2 36 2.2 36 V Quiescent Current TA = +25°C, −VS = 0 V, +VS = 2.7 V 325 400 325 400 μA T T T
TEMPERATURE RANGE −40 +125 −40 +125 °C
1
Input stage uses pnp transistors; therefore, input bias current always flows into the part.
2
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the section for more information. Input Voltage Range
= 0.8 V to 1.8 V 0.04 0.01% %
OUT
= 0.2 V to 2.5 V 0.3 0.1% %
OUT
= +85°C to +125°C 5 2 ppm/°C
A
= +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V
A
= −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V
A
= +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V
A
= −40°C to +125°C
T
A
= −40°C, −VS = 0 V, +VS = 2.7 V 250 325 250 325 μA
A
= +85°C, −VS = 0 V, +VS = 2.7 V 425 500 425 500 μA
A
= +125°C, −VS = 0 V, +VS = 2.7 V 475 550 475 550 μA
A
0.1 +V
− 0.1 0.1 +VS − 0.1 V
S
Rev. A | Page 6 of 28
AD8226

ABSOLUTE MAXIMUM RATINGS

Table 4.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Maximum Voltage at −IN or +IN −VS + 40 V
Minimum Voltage at −IN or +IN +VS − 40 V
REF Voltage ±VS
Storage Temperature Range −65°C to +150°C
Specified Temperature Range −40°C to +125°C
Maximum Junction Temperature 140°C
ESD
Human Body Model 1.5 kV Charge Device Model 1.5 kV Machine Model 100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for a device in free air.
Table 5. Thermal Resistance
Package θJA Unit
8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W

ESD CAUTION

Rev. A | Page 7 of 28
AD8226

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8226
1
–IN
2
R
G
3
R
G
4
+IN
TOP VIEW
(Not to S cale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input. 2, 3 RG Gain-Setting Pins. Place a gain resistor between these two pins. 4 +IN Positive Input. 5 −VS Negative Supply. 6 REF Reference. This pin must be driven by low impedance. 7 V
Output.
OUT
8 +VS Positive Supply.
8
+V
S
7
V
OUT
6
REF
5
–V
S
07036-002
Rev. A | Page 8 of 28
AD8226

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
N: 2203
160
140
120
100
HITS
80
60
40
20
0
–900 –600 –300 0 300 600 900
V
OSO
@ ±15V (µV)
MEAN: 35.7649 SD: 229.378
Figure 3. Typical Distribution of Output Offset Voltage
240
210
180
150
120
HITS
90
60
30
0
–9 –6 –3 0 3 6 9
V
OSO
DRIFT (µV)
MEAN: –0.57 SD: 1.5762
Figure 4. Typical Distribution of Output Offset Voltage Drift
250
200
150
HITS
100
50
0
–1.2
–0.9 –0.6 –0.3
07036-031
0 0.3 0.6 0.9 1.2
DRIFT (µV)
V
OSI
MEAN: 0.041 SD: 0.224
07036-034
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
180
150
120
90
HITS
60
30
0
07036-032
18
20 22 24
POSITIVE I
CURRENT @ ±15V (nA)
BIAS
MEAN: 21.5589 SD: 0.624
26
07036-035
Figure 7. Typical Distribution of Input Bias Current
350
300
250
200
HITS
150
100
50
0
–400
–200
V
OSI
0 200 400
@ RG PINS @ ±15V (µV)
Figure 5. Typical Distribution of Input Offset Voltage
MEAN: –3.67283 SD: 51.1
07036-033
Rev. A | Page 9 of 28
300
250
200
HITS
150
100
50
0
–0.9 –0.6 –0.3 0 0.3 0.6 0.9
V
@ ±15V (nA)
OSI
Figure 8. Typical Distribution of Input Offset Current
MEAN: 0.003 SD: 0.075
07036-036
Loading...
+ 19 hidden pages