Datasheet AD8226 Datasheet (ANALOG DEVICES)

Wide Supply Range, Rail-to-Rail

FEATURES

Gain set with 1 external resistor

Gain range: 1 to 1000 Input voltage goes below ground Inputs protected beyond supplies Very wide power supply range

Single supply: 2.2 V to 36 V

Dual supplies: ±1.35 V to ±18 V Bandwidth (G = 1): 1.5 MHz CMRR (G = 1): 90 dB minimum for BR models Input noise: 22 nV/√Hz Typical supply current: 350 μA Specified temperature: −40°C to +125°C 8-lead SOIC and MSOP packages

APPLICATIONS

Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems

Output Instrumentation Amplifier

AD8226

PIN CONFIGURATION

AD8226

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to S cale)

Figure 1.

Table 1. Instrumentation Amplifiers by Category

General Purpose

Zero Drift

Military Grade

AD8220 AD8231 AD620 AD627 AD8250 AD8221 AD8290 AD621 AD623 AD8251 AD8222 AD8293 AD524 AD8223 AD8253 AD8224 AD8553 AD526 AD8226 AD8228 AD8556 AD624 AD8227 AD8295 AD8557

1

Visit www.analog.com for the latest instrumentation amplifiers.

8

+V

7

V

OUT

6

REF

5

–V

Low Power

S

07036-001

1

High Speed PGA

GENERAL DESCRIPTION

The AD8226 is a low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain between 1 and 1000.

The AD8226 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range also includes the ability to go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The AD8226 operates on supplies ranging from ±1.35 V to ±18 V for dual supplies and 2.2 V to 36 V for single supply.

The robust AD8226 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the

AD8226 can handle voltages beyond the rails. For example, with a ±5 V supply, the part is guaranteed to withstand ±35 V at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection.

The AD8226 is perfect for multichannel, space-constrained industrial applications. Unlike other low cost, low power instrumentation amplifiers, the AD8226 is designed with a minimum gain of 1 and can easily handle ±10 V signals. With its MSOP package and 125°C temperature rating, the AD8226 thrives in tightly packed, zero airflow designs.

The AD8226 is available in 8-lead MSOP and SOIC packages, and is fully specified for −40°C to +125°C operation.

For a device with a similar package and performance as the AD8226 but with gain settable from 5 to 1000, consider using

AD8227.

the

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8226

REVISION HISTORY

7/09—Rev. 0 to Rev. A

Added BRZ and BRM Models .......................................... Universal

Changes to Features Section............................................................ 1

Changes to Table 1 ............................................................................ 1

Changes to General Description Section ...................................... 1

Changes to Gain vs. Temperature Parameter, Output Parameter,

and Operating Range Parameter, Table 2 ......................................... 4

Changes to Common-Mode Rejection Ratio (CMRR) Parameter

and to Input Offset, V

Parameter, Table 3 ........................................................................ 5

Changes to Gain vs. Temperature Parameter, Table 3 ................. 6

Changes to Gain Selection Section ............................................... 19

Changes to Reference Terminal Section and Input Voltage

Range Section .............................................................................. 20

Changes to Ordering Guide .......................................................... 25

1/09—Revision 0: Initial Version

, Average Temperature Coefficient

OSO

Gain Selection ............................................................................. 19

Reference Terminal .................................................................... 20

Input Voltage Range ................................................................... 20

Layout .......................................................................................... 20

Input Bias Current Return Path ............................................... 21

Input Protection ......................................................................... 22

Radio Frequency Interference (RFI) ........................................ 22

Applications Information .............................................................. 23

Differential Drive ....................................................................... 23

Precision Strain Gage ................................................................. 24

Driving an ADC ......................................................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. A | Page 2 of 28

AD8226

SPECIFICATIONS

+VS = +15 V, −VS = −15 V, V

Table 2.

ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR) VCM = −10 V to +10 V

CMRR with DC to 60 Hz

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

CMRR with DC at 5 kHz

G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB

NOIS E Total noise: eN = √(e

Voltage Noise 1 kHz

Input Voltage Noise, eNI 22 24 22 24 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p

G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p

VOLTAGE OFFSET Total offset voltage:

Input Offset, V

Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C Output Offset, V

Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 μV/°C Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V

G = 1 80 90 dB

G = 10 100 105 dB

G = 100 105 110 dB

G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current

T

Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C Input Offset Current TA = +25°C 1.5 0.5 nA T T

Average Temperature Coefficient TA = −40°C to +125°C 5 5 pA/°C

REFERENCE INPUT

RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %

DYNAMIC RESPONSE

Small-Signal −3 dB Bandwidth

G = 1 1500 1500 kHz

G = 10 160 160 kHz

G = 100 20 20 kHz

G = 1000 2 2 kHz

V

OSI

V

OSO

1

T

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

2

+ (eNO/G)2)

NI

= V

+ (V

V

OS

OSI

= ±5 V to ±15 V 200 100 μV

S

= ±5 V to ±15 V 1000 500 μV

S

= +25°C 5 20 27 5 20 27 nA

A

= +125°C 5 15 25 5 15 25 nA

A

= −40°C 5 30 35 5 30 35 nA

A

= +125°C 1.5 0.5 nA

A

= −40°C 2 0.5 nA

A

OSO

/G)

Rev. A | Page 3 of 28

AD8226

ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit

Settling Time 0.01% 10 V step

G = 1 25 25 μs G = 10 15 15 μs G = 100 40 40 μs

G = 1000 350 350 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V Gain Error V

G = 1 0.04 0.01 %

G = 5 to 1000 0.3 0.1 % Gain Nonlinearity V

G = 1 to 10 RL ≥ 2 kΩ 10 10 ppm

G = 100 RL ≥ 2 kΩ 75 75 ppm

G = 1000 RL ≥ 2 kΩ 750 750 ppm Gain vs. Temperature

2

G = 1 TA = −40°C to +85°C 5 1 ppm/°C

T

G > 1 TA = −40°C to +125°C −100 −100 ppm/°C

INPUT VS = ±1.35 V to +36 V

Input Impedance

Differential 0.8||2 0.8||2 GΩ||pF

Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range

3

T

T T Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V

OUTPUT

Output Swing

RL = 2 kΩ to Ground

T

RL = 10 kΩ to Ground

T

RL = 100 kΩ to Ground

T Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V Quiescent Current TA = +25°C 350 425 350 425 μA T T T

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

The input stage uses pnp transistors; therefore, input bias current always flows into the part.

2

The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

3

Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.

See the section for more information. Input Voltage Range

±10 V

OUT

= −10 V to +10 V

OUT

= 85°C to 125°C 5 2 ppm/°C

A

= +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V

A

= +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V

A

= −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V

A

= +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V

A

= +125°C −VS + 0.4 +VS – 1.0 −VS + 0.4 +VS – 1.0 V

A

= −40°C −VS + 1.2 +VS – 1.1 −VS + 1.2 +VS – 1.1 V

A

= +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V

A

= +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V

A

= −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V

A

= −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V

A

= −40°C 250 325 250 325 μA

A

= +85°C 450 525 450 525 μA

A

= +125°C 525 600 525 600 μA

A

Rev. A | Page 4 of 28

AD8226

+VS = 2.7 V, −VS = 0 V, V

Table 3.

ARZ, ARMZ BRZ, BRMZ

Parameter Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 1.7 V

CMRR with DC to 60 Hz

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

CMRR with DC at 5 kHz

G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB

NOISE Total noise: eN = √(e

Voltage Noise 1 kHz

Input Voltage Noise, eNI 22 24 22 24 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz

RTI f = 0.1 Hz to 10 Hz

G = 1 2.0 2.0 μV p-p G = 10 0.5 0.5 μV p-p

G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p

VOLTAGE OFFSET Total offset voltage: VOS = V

Input Offset, V

Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C Output Offset, V

Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 μV/°C Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V

G = 1 80 90 dB

G = 10 100 105 dB

G = 100 105 110 dB

G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current T T

Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C Input Offset Current TA = +25°C 1.5 0.5 nA T T

Average Temperature Coefficient TA =−40°C to +125°C 5 5 pA/°C

REFERENCE INPUT

RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %

DYNAMIC RESPONSE

Small-Signal −3 dB Bandwidth

G = 1 1500 1500 kHz

G = 10 160 160 kHz

G = 100 20 20 kHz

G = 1000 2 2 kHz

200 100 μV

OSI

1000 500 μV

OSO

1

T

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

2

+ (eNO/G2))

NI

+ (V

/G)

OSI

OSO

= +25°C 5 20 27 5 20 27 nA

A

= +125°C 5 15 25 5 15 25 nA

A

= −40°C 5 30 35 5 30 35 nA

A

= +125°C 1.5 0.5 nA

A

= −40°C 1 0.1 nA

A

Rev. A | Page 5 of 28

AD8226

ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit

Settling Time 0.01% 2 V step

G = 1 6 6 μs G = 10 6 6 μs G = 100 35 35 μs

G = 1000 350 350 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V Gain Error

G = 1 V

G = 5 to 1000 V Gain vs. Temperature

2

G = 1 TA = −40°C to +85°C 5 1 ppm/°C

T

G > 1 TA = −40°C to +125°C −100 ppm/°C

INPUT −VS = 0 V, +VS = 2.7 V to 36 V

Input Impedance

Differential 0.8||2 0.8||2 GΩ||pF

Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range

3

T

T T Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40

OUTPUT

Output Swing RL = 10 kΩ to 1.35 V,

Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Single-supply operation 2.2 36 2.2 36 V Quiescent Current TA = +25°C, −VS = 0 V, +VS = 2.7 V 325 400 325 400 μA T T T

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

Input stage uses pnp transistors; therefore, input bias current always flows into the part.

2

The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

3

Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.

See the section for more information. Input Voltage Range

= 0.8 V to 1.8 V 0.04 0.01% %

OUT

= 0.2 V to 2.5 V 0.3 0.1% %

OUT

= +85°C to +125°C 5 2 ppm/°C

A

= +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V

A

= −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V

A

= +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V

A

= −40°C to +125°C

T

A

= −40°C, −VS = 0 V, +VS = 2.7 V 250 325 250 325 μA

A

= +85°C, −VS = 0 V, +VS = 2.7 V 425 500 425 500 μA

A

= +125°C, −VS = 0 V, +VS = 2.7 V 475 550 475 550 μA

A

0.1 +V

− 0.1 0.1 +VS − 0.1 V

S

Rev. A | Page 6 of 28

AD8226

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage ±18 V

Output Short-Circuit Current Indefinite

Maximum Voltage at −IN or +IN −VS + 40 V

Minimum Voltage at −IN or +IN +VS − 40 V

REF Voltage ±VS

Storage Temperature Range −65°C to +150°C

Specified Temperature Range −40°C to +125°C

Maximum Junction Temperature 140°C

ESD

Human Body Model 1.5 kV Charge Device Model 1.5 kV Machine Model 100 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for a device in free air.

Table 5. Thermal Resistance

Package θJA Unit

8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W

ESD CAUTION

Rev. A | Page 7 of 28

AD8226

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8226

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to S cale)

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Negative Input. 2, 3 RG Gain-Setting Pins. Place a gain resistor between these two pins. 4 +IN Positive Input. 5 −VS Negative Supply. 6 REF Reference. This pin must be driven by low impedance. 7 V

Output.

OUT

8 +VS Positive Supply.

8

+V

S

7

V

OUT

6

REF

5

–V

S

07036-002

Rev. A | Page 8 of 28

AD8226

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.

N: 2203

160

140

120

100

HITS

80

60

40

20

0

–900 –600 –300 0 300 600 900

V

OSO

@ ±15V (µV)

MEAN: 35.7649 SD: 229.378

Figure 3. Typical Distribution of Output Offset Voltage

240

210

180

150

120

HITS

90

60

30

0

–9 –6 –3 0 3 6 9

V

OSO

DRIFT (µV)

MEAN: –0.57 SD: 1.5762

Figure 4. Typical Distribution of Output Offset Voltage Drift

250

200

150

HITS

100

50

0

–1.2

–0.9 –0.6 –0.3

07036-031

0 0.3 0.6 0.9 1.2

DRIFT (µV)

V

OSI

MEAN: 0.041 SD: 0.224

07036-034

Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100

180

150

120

90

HITS

60

30

0

07036-032

18

20 22 24

POSITIVE I

CURRENT @ ±15V (nA)

BIAS

MEAN: 21.5589 SD: 0.624

26

07036-035

Figure 7. Typical Distribution of Input Bias Current

350

300

250

200

HITS

150

100

50

0

–400

–200

V

OSI

0 200 400

@ RG PINS @ ±15V (µV)

Figure 5. Typical Distribution of Input Offset Voltage

MEAN: –3.67283 SD: 51.1

07036-033

Rev. A | Page 9 of 28

300

250

200

HITS

150

100

50

0

–0.9 –0.6 –0.3 0 0.3 0.6 0.9

V

@ ±15V (nA)

OSI

Figure 8. Typical Distribution of Input Offset Current

MEAN: 0.003 SD: 0.075

07036-036

AD8226

2.5 V

2.0

+0.02V, +2.0V

+1.35V, +1.9V

REF

= +1.35V

1.5

1.0

0.5

+0.02V, +1.3V

+0.02V, +0.3V

V

= 0V

REF

+2.68V, +1.2V

+2.4V, +0.8V

+2.68V, +0.3V

0

COMMON-MODE VOLTAGE (V)

–0.5

+0.02V, –0.4V

–1.0

–0.5 0 0.5 1.0 1.5

+1.35V, –0.4V

2.0

2.5 3.0

OUTPUT VOLTAGE (V)

Figure 9. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= +2.7 V, G = 1

S

07036-037

2.5

2.0

+0.02V, +2.0V

+1.35V, +1.9V

V

REF

= +1.35V

1.5

+0.02V, +1.3V

1.0

0.5

COMMON-MO DE VO LTAGE (V)

0

–0.5

–0.5 0 0.5 1.0 1.5

+0.02V, +0.4V

+0.02V, –0.3V

V

REF

= 0V

+1.35, –0.3V

+2.67V, +1.3V

+2.4V, +0.8V

+2.67V, +0.4V

2.0

2.5 3.0

OUTPUT VOLTAGE (V)

Figure 12. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= +2.7 V, G = 100

S

07036-040

5

+0.02V, +4.3V

4

3

+0.02V, +3.0V

2

+0.02V, +0.8V

1

COMMON-MODE VOLTAGE (V)

0

+0.02V, –0.4V

–1

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.55.0

+2.5V, +4.3V

V

REF

+2.5V, –0.4V

= 0V

V

+4.98V, +3.0V

+4.7V, +1.9V

+4.98V, +0.8V

REF

= +1.35V

OUTPUT VOLTAGE (V)

Figure 10. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

6

4

2

–4.97V, +1.8V

0

= +5 V, G = 1

S

0V, +4.3V

+4.96V, +1.8V

5

+0.02V, +4.3V

4

3

+0.02V, +3.0V

2

1

+0.02V, +0.7V

COMMON-MODE VOLTAGE (V)

0

07036-038

+0.02V, –0.3V

–1

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.55.0

V

REF

+2.5V, +4.2V

= 0V

+2.5V, –0.3.V

V

REF

+4.96V, +3.0V

+4.7V, +1.9V

+4.96V, +0.7V

= +2.5V

07036-041

OUTPUT VOLTAGE (V)

Figure 13. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

6

4

2

–4.96V, +1.7V

0

= +5 V, G = 100

S

0V, +4.2V

+4.96V, +1.7V

–2

COMMON-MO DE VO LTAGE (V)

–4.97V, –3.0V

–4

–6

–6 –4 –2 0 2

0V, –5.4V

+4.96V, –0.3V

4

OUTPUT VOLTAGE (V)

Figure 11. Input Common-Mode Voltage vs. Output Voltage,

Dual Supplies, V

= ±5 V, G = 1

S

07036-039

6

Rev. A | Page 10 of 28

–2

COMMON-MODE VOLTAGE (V)

–4.96V, –3.1V

–4

–6

–6 –4 –2 0 2

0V, –5.3V

+4.96V, –3.1V

4

OUTPUT VOLTAGE (V)

Figure 14. Input Common-Mode Voltage vs. Output Voltage,

Dual Supplies, V

= ±5 V, G = 100

S

07036-042

6

AD8226

20

15

10

+14.96V, +6.8V

5

–11.95V, +5.3V

0

COMMON-MODE VOLTAGE (V)

–5

–10

–14.96V, –7.9V

–11.95V, –6.4V

–15

–20

–20 –15 –10 –5 0

0V, +14.3V

0V, +11.3V

VS = ±12V

0V, –12.4V

0V, –15.4V

= ±15V

V

S

+11.95V, +5.3V

+11.95V, –6.4V

105

+14.94V, +6.8V

+14.94V, –7.9V

15 20

OUTPUT VOLTAGE ( V)

Figure 15. Input Common-Mode Voltage vs. Output Voltage,

Dual Supplies, V

= ±15 V, G = 1

S

07036-043

20

15

10

+14.95V, +6.7V

5

–11.95V, +5.2V

0

COMMON-MODE VOLTAGE (V)

–5

–10

–14.95V, –8.0V

–11.95V, –6.5V

–15

–20

–20 –15 –10 –5 0

0V, +14.2V

0V, +11.2V

VS = ±12V

0V, –12.3V

0V, –15.4V

= ±15V

V

S

+11.95V, +5.2V

+11.95V, –6.5V

105

+14.95V, +6.7V

+14.95V, –8.0V

15 20

OUTPUT VOLTAGE ( V)

Figure 18. Input Common-Mode Voltage vs. Output Voltage,

Dual Supplies, V

= ±15 V, G = 100

S

07036-046

2.25 0.6 VS = 2.7V G = 1

2.00 –V

= 0V

IN

1.75

V

OUT

1.50

1.25

OUTPUT VOLTAGE (V)

1.00

0.75

I

IN

0.50

0.25

0 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

INPUT VOLTAGE (V)

Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V

16 0.5

VS = ±15V

14

G = 1

12

–V

= 0V

IN

10

8

V

OUT

6 4

2 0

I

IN

–2 –4 –6

OUTPUT VOLTAGE (V)

–8 –10 –12 –14 –16

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

INPUT VOLTAGE (V)

Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V

0.5

0.4

0.3

0.2

0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6

0.4

0.3

0.2

0.1

0 –0.1

–0.2

–0.3

–0.4

–0.5

2.75 0.6 VS = 2.7V

2.50

G = 100 –V

= 0V

IN

2.25

V

OUT

2.00

1.75

1.50

1.25

1.00

INPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

0.75

I

IN

0.50

0.25

0 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

07036-044

INPUT VOLTAGE (V)

0.5

0.4

0.3

0.2

0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6

INPUT CURRENT (mA)

07036-047

Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V

16

VS = ±15V

14

G = 100

12

–V

= 0V

IN

10

8

V

OUT

6 4

2 0

I

IN

–2 –4

INPUT CURRENT (mA)

–6

OUTPUT VO LTAGE (V)

–8 –10 –12 –14 –16

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

07036-045

INPUT VOLTAGE ( V)

0.6

0.5

0.4

0.3

0.2

0.1 0

–0.1 –0.2 –0.3 –0.4 –0.5 –0.6

INPUT CURRENT (mA)

07036-048

Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V

Rev. A | Page 11 of 28

AD8226

30 29 28

27 26

25 24 23 22 21 20

INPUT BIAS CURRENT (nA)

19 18 17 16

–0.15V

+4.22V

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

COMMON-MODE VOLTAGE (V)

Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V

07036-049

160

140

GAIN = 1000

120

GAIN = 100

GAIN = 10

100

GAIN = 1

80

60

NEGATIVE PSRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

Figure 24. Negative PSRR vs. Frequency

07036-014

50

–15.13V

45

40 35 30 25 20 15 10

INPUT BIAS CURRENT (nA)

5 0

–5

–16 –12 –8 –4 0 4 8 12 16

COMMON-MODE VOLTAGE (V)

+14.18V

Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10 GAIN = 1

100

80

60

POSITIVE PSRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

Figure 23. Positive PSRR vs. Frequency, RTI

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

GAIN (dB)

10

GAIN = 1

0 –10

–20

–30

100 1k 10k 100k 1M 10M

07036-050

FREQUENCY (Hz)

VS = ±15V

07036-015

Figure 25. Gain vs. Frequency, VS = ±15 V

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

GAIN (dB)

10

GAIN = 1

0 –10

–20

–30

100 1k 10k 100k 1M 10M

07036-013

FREQUENCY (Hz)

VS = 2.7V

07036-016

Figure 26. Gain vs. Frequency, 2.7 V Single Supply

Rev. A | Page 12 of 28

AD8226

160

140

120

100

GAIN = 1000 GAIN = 100

GAIN = 10

GAIN = 1

BANDWIDTH

LIMITED

35

30

25

–IN BIAS CURRENT +IN BIAS CURRENT OFFSET CURRENT

VS = ±15V V

REF

150

= 0V

125

100

80

CMRR (dB)

60

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 27. CMRR vs. Frequency, RTI

120

GAIN = 1000

100

GAIN = 1

80

60

CMRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k

GAIN = 100

GAIN = 10

FREQUENCY (Hz)

BANDWIDTH

LIMITED

Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

20

15

INPUT BIAS CURRENT (nA)

10

5 –45 –30 –15 0 15 30 45 60 75 90 105 120 135

07036-017

TEMPERATURE ( °C)

75

50

INPUT OF FSET CURRENT (pA)

25

0

07036-012

Figure 30. Input Bias Current and Input Offset Current vs. Temperature

20

10

0

–10

–20

–30

–40

GAIN ERROR (µ V/V)

–50

–60

NORMALIZ E D AT 25°C

–70

–60 –40 –20 0 20 40 60 80 100 120 140

07036-018

–0.3ppm/°C

–0.4ppm/°C

TEMPERATURE (°C)

–0.6

ppm/°C

07036-051

Figure 31. Gain Error vs. Temperature, G = 1

3.0

2.5

2.0

1.5

1.0

0.5 0

–0.5 –1.0 –1.5 –2.0

CHANGE IN INPUT OFFSET VOLTAG E (µV)

–2.5 –3.0

0 102030405060708090100110120

WARM-UP TIME (Seconds)

Figure 29. Change in Input Offset Voltage vs. Warm-Up Time

07036-011

Rev. A | Page 13 of 28

20

10

–0.35ppm/°C

0

–10

CMRR (µV/V)

–20

–30

–40

0.2ppm/°C

REPRESENTATIVE DATA NORMALIZ E D AT 25°C

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

Figure 32. CMRR vs. Temperature, G = 1

07036-052

AD8226

V

+

S

–0.2

–0.4

–0.6

–0.8

–V

INPUT VOLTAGE (V)

–0.2 –0.4

REFERRED TO SUPPLY VOLTAGES

–0.6

–0.8

–40°C +25°C +85°C +105°C +125°C

S

2 4 6 8 10 12 14 16 18

SUPPLY VOLT AGE ( ±V

)

S

Figure 33. Input Voltage Limit vs. Supply Voltage

07036-053

15

10

–40°C

5

0

–5

OUTPUT VOLTAGE SWING (V)

–10

–15

100 1k 10k 100k

LOAD RESISTANCE (Ω)

+25°C +85°C +105°C +125°C

Figure 36. Output Voltage Swing vs. Load Resistance

07036-056

+

S

–0.1

–0.2

–0.3

–0.4

+0.4 +0.3

OUTPUT VOLTAGE SWING (V)

+0.2

REFERRED TO SUPPLY VOLTAGES

+0.1

–V

–40°C +25°C +85°C +105°C +125°C

S

2 4 6 8 10 12 14 16 18

SUPPLY VOLT AGE ( ±V

)

S

Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ

+

S

–0.2 –0.4 –0.6 –0.8 –1.0 –1.2

+1.2 +1.0 +0.8 +0.6

OUTPUT VOLTAGE SWING (V)

REFERRED TO SUPPLY VOLTAGES

+0.4 +0.2

–V

–40°C +25°C +85°C +105°C +125°C

S

2 4 6 8 10 12 14 16 18

SUPPLY VOLT AGE ( ±V

)

S

Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

+

S

–0.2

–0.4

–0.6

–0.8

+0.8

+0.6

OUTPUT VO LTAGE SWING (V)

+0.4

REFERRED TO SUPPLY VOLTAGES

+0.2

–V

07036-054

–40°C +25°C +85°C +105°C +125°C

S

10µ 100µ 1M 10M

OUTPUT CURRENT ( A)

07036-057

Figure 37. Output Voltage Swing vs. Output Current, G = 1

8

G = 1

6

4

2

0

–2

–4

NONLINEARITY (2ppm/DIV)

–6

–8

–10 –8 –6 –4 –2 0 2 4 6 8 10

07036-055

Figure 38. Gain Nonlinearity, G = 1, R

OUTPUT VOLTAGE (V)

≥ 2 kΩ

L

07036-019

Rev. A | Page 14 of 28

AD8226

8

G = 10

6

4

1k

2

0

–2

–4

NONLINEARITY (2ppm/DIV)

–6

–8

–10 –8 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ

80

G = 100

60

40

20

0

–20

–40

NONLINEARITY (20ppm/DIV)

–60

–80

–10 –8 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ

GAIN = 1

100

NOISE (nV/ Hz)

10

07036-020

GAIN = 10

GAIN = 100

GAIN = 1000

1 10 100 1k 10k 100k

BANDWIDTH

LIMITED

FREQUENCY (Hz)

07036-023

Figure 42. Voltage Noise Spectral Density vs. Frequency

GAIN = 1000, 200nV/DIV

GAIN = 1, 1µV/DIV

1s/DIV

07036-021

07036-024

Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000

800

G = 1000

600

400

200

0

–200

–400

NONLINEARITY (100ppm/DIV)

–600

–800

–10 –8 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ

07036-022

Rev. A | Page 15 of 28

1k

100

NOISE (fA/ Hz)

10

1 10 100 1k 10k

FREQUENCY (Hz)

Figure 44. Current Noise Spectral Density vs. Frequency

07036-058

AD8226

5V/DIV

15.46μs TO 0.01%

17.68µs TO 0.001%

0.002%/DIV

1s/DIV1.5pA/DIV

Figure 45. 0.1 Hz to 10 Hz Current Noise

30

VS= ±15V

27

24

21

18

15

12

9

OUTPUT VOLTAGE (V p-p)

6

VS= +5V

3

0

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 46. Large-Signal Frequency Response

07036-025

40µs/DIV

07036-061

Figure 48. Large-Signal Pulse Response and Settling Time,

G = 10, 10 V Step, V

5V/DIV

39.64μs TO 0.01%

58.04µs TO 0.001%

0.002%/DIV

07036-059

= ±15 V

S

100µs/DIV

07036-062

Figure 49. Large-Signal Pulse Response and Settling Time,

G = 100, 10 V Step, V

= ±15 V

S

5V/DIV

25.38μs TO 0.01%

26.02µs TO 0.001%

0.002%/DIV

40µs/DIV

Figure 47. Large-Signal Pulse Response and Settling Time,

G = 1, 10 V Step, V

= ±15 V

S

07036-060

Rev. A | Page 16 of 28

5V/DIV

349.6μs TO 0.01%

529.6µs TO 0.001%

0.002%/DIV

400µs/DIV

Figure 50. La rge-Sig nal Puls e Response and Settling Time,

G = 1000, 10 V Step, V

= ±15 V

S

07036-063

AD8226

20mV/DIV 4µs/DIV

Figure 51. Small-Signal Response, G = 1, R

20mV/DIV 4µs/DIV

Figure 52. Small-Signal Response, G = 10, R

= 10 kΩ, CL = 100 pF

L

= 10 kΩ, CL = 100 pF

L

07036-026

07036-027

20mV/DIV 20µs/DIV

Figure 53. Small-Signal Response, G = 100, R

20mV/DIV 100µs/DIV

Figure 54. Small-Signal Response, G = 1000, R

= 10 kΩ, CL = 100 pF

L

= 10 kΩ, CL = 100 pF

L

07036-028

07036-029

Rev. A | Page 17 of 28

AD8226

340

330

NO LOA D

RL = 47pF RL = 100pF

RL = 147pF

20mV/DIV

4µs/DIV

07036-030

Figure 55. Small-Signal Response with Various Capacitive Loads,

G = 1, R

= ∞

L

60

50

40

30

SETTLED TO 0.001%

20

SETTLING TIME (µs)

10

SETTLED TO 0.01%

320

310

SUPPLY CURRENT ( µ A)

300

290

0 2 4 6 8 1012141618

SUPPLY VOLTAGE (±V

)

S

Figure 57. Supply Current vs. Supply Voltage

07036-066

0

2

46810

12 14 16 18 20

STEP SIZE (V)

Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies

07036-064

Rev. A | Page 18 of 28

AD8226

V

THEORY OF OPERATION

+V

S

–V

S

R1

24.7kΩ

NODE 1

ESD AND

OVERVOLT A GE

+IN

PROTECTION

A1 A2

R

B

+

S

R

G

–V

V

BIAS

S

–V

R2

24.7kΩ

NODE 2

S

NODE 4NODE 3

Q2Q1

R

B

Figure 58. Simplified Schematic

ESD AND

OVERVOLTAGE

PROTECTION

R4

50kΩ

R5

50kΩ

–IN

R3

50kΩ

A3

R6

50kΩ

DIFFERENCE

AMPLIFIER STAGEGAIN STAGE

+V

S

V

OUT

+V

S

–V

S

REF

–V

S

07036-003

ARCHITECTURE

The AD8226 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 58 shows a simplified schematic of the AD8226.

The first stage works as follows: in order to maintain a constant voltage across the bias resistor R stant diode drop above the positive input voltage. Similarly, A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore, a replica of the differential input voltage is placed across the gain-setting resistor, R flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop up, is also still present.

The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal.

The transfer function of the AD8226 is

V

OUT

= G(V

IN+

− V

IN−

where:

G

1 +=

k49.4

R

G

, A1 must keep Node 3 a con-

B

. The current that

G

) + V

REF

GAIN SELECTION

Placing a resistor across the RG terminals sets the gain of the AD8226, which can be calculated by referring to Tab le 7 or by using the following gain equation:

k49.4

R

G

Table 7. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG (Ω) Calculated Gain

49.9 k 1.990

12.4 k 4.984

5.49 k 9.998

2.61 k 19.93

1.00 k 50.40 499 100.0 249 199.4 100 495.0

49.9 991.0

The AD8226 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the R to the AD8226 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal.

If a gain of 5 is required and minimal gain drift is important, consider using the AD8227. The AD8227 has a default gain of 5 that is set with internal resistors. Because all resistors are internal, the gain drift is extremely low (<5 ppm/°C maximum).

1

−=G

resistor should be added

G

Rev. A | Page 19 of 28

AD8226

GV

REFERENCE TERMINAL

The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8226 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +V

or −VS by more than 0.3 V.

S

For the best performance, source impedance to the REF terminal should be kept below 2 Ω. As shown in Figure 58, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional R can be computed by 2(50 k + R

)/(100 k + R

REF

).

REF

Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.

INCORRECT

AD8226

REF

V

Figure 59. Driving the Reference Pin

V

CORRECT

+

OP1177

–

AD8226

REF

07036-004

INPUT VOLTAGE RANGE

Figure 9 through Figure 15 and Figure 18 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The 3-op-amp architecture of the AD8226 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 58) experience a combination of a gained signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited.

For most applications, Figure 9 through Figure 15 and Figure 18 provide sufficient information to achieve a good design. For applications where a more detailed understanding is needed, Equation 1 to Equation 3 can be used to understand how the gain (G), common-mode input voltage (V voltage (V the constants, V

), and reference voltage (V

DIFF

, V

+LIMIT

, and V

−LIMIT

REF_LIMIT

These three formulas, along with the input and output range specifications in Tabl e 2 and Ta b le 3, set the operating boundaries of the part.

), differential input

CM

) interact. The values for

REF

, are shown in Tab le 8 .

V

CM

V

CM

GV

DIFF

2

Table 8. Input Voltage Range Constants for Various Temperatures

Temperature V

−40°C −0.55 V 0.8 V 1.3 V +25°C −0.35 V 0.7 V 1.15 V +85°C −0.15 V 0.65 V 1.05 V +125°C −0.05 V 0.6 V 0.9 V

Performance Across Temperature

The common-mode input range shifts upward with temperature. At cold temperatures, the part requires extra headroom from the positive supply, and operation near the negative supply has more margin. Conversely, hot temperatures require less headroom from the positive supply, but are the worst-case conditions for input voltages near the negative supply.

Recommendation for Best Performance

A typical part functions up to the boundaries described in this section. However, for best performance, designing with a few hundred millivolts extra margin is recommended. As signals approach the boundary, internal transistors begin to saturate, which can affect frequency and linearity performance.

If the application requirements exceed the boundaries, one solution is to apply less gain with the AD8226, and then apply additional gain later in the signal chain. Another option is to use the pin-compatible AD8227.

LAYOUT

To ensure optimum performance of the AD8226 at the PCB level, care must be taken in the design of the board layout. The AD8226 pins are arranged in a logical manner to aid in this task.

))((

DIFF

2

GV

))((

DIFF

2

))((

CM

S

++

VV

REF

2

−LIMIT

1

–IN

2

R

G

3

R

G

4

+IN

AD8226

TOP VIEW

(Not to S cale)

Figure 60. Pinout Diagram

VV

+−>−

S

LIMIT

−

VV

−+<+

V

(2)

LIMIT

+

−+<

VV

S

+LIMIT

8

+V

7

V

6

REF

5

–V

(1)

(3)

LIMITREF

_

V

S

OUT

S

07036-005

REF_LIMIT

Rev. A | Page 20 of 28

AD8226

V

Common-Mode Rejection Ratio Over Frequency

Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces.

Parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. If the board design has a component at the gain-setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible.

Power Supplies

A stable dc voltage should be used to power the instrumentation amplifier. Note that noise on the supply pins can adversely affect performance. For more information, see the PSRR performance curves in Figure 23 and Figure 24.

A 0.1 µF capacitor should be placed as close as possible to each supply pin. As shown in Figure 61, a 10 µF tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits.

+

S

REF

10µF

LOAD

V

OUT

07036-006

+IN

–IN

0.1µF

AD8226

0.1µF 10µF

–V

S

Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground

References

The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground.

INPUT BIAS CURRENT RETURN PATH

The input bias current of the AD8226 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 62.

INCORRECT

+V

S

AD8226

–V

S

TRANSFORMER

+V

S

AD8226

–V

S

THERMOCOUPLE

+V

S

C

AD8226

C

CAPACITIVEL Y CO UPLED

REF

–V

S

Figure 62. Creating an I

REF

f

HIGH-PASS

10MΩ

1

=

2πRC

CAPACITIVEL Y COUPLED

TRANSFORMER

THERMOCOUPLE

C

R

C

R

Path

BIAS

CORRECT

+V

S

AD8226

–V

S

+V

S

AD8226

–V

S

+V

S

AD8226

–V

S

REF

7036-007

Rev. A | Page 21 of 28

AD8226

V

INPUT PROTECTION

The AD8226 has very robust inputs and typically does not need additional input protection. Input voltages can be up to 40 V from the opposite supply rail. For example, with a +5 V positive supply and a −8 V negative supply, the part can safely withstand voltages from −35 V to 32 V. Unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 16, Figure 17, Figure 19, and Figure 20 show the behavior of the part under overvoltage conditions.

The rest of the AD8226 terminals should be kept within the supplies. All terminals of the AD8226 are protected against ESD.

For applications where the AD8226 encounters voltages beyond the allowed limits, external current-limiting resistors and lowleakage diode clamps such as the BAV199L, the FJH1100s, or the SP720 should be used.

RADIO FREQUENCY INTERFERENCE (RFI)

RF rectification is often a problem when amplifiers are used in applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter limits the input signal bandwidth according to the following relationship:

where C

≥ 10 CC.

D

uencyFilterFreq

=

DIFF

=

CM

1

D

1

RC

π2

C

)2(π2

CCR

+

C

+

S

R

4.02kΩ

R

4.02kΩ

C

1nF

C

D

10nF

C

1nF

0.1µF

R

G

0.1µF

+IN

AD8226

–IN

–V

10µF

V

OUT

REF

10µF

S

07036-008

Figure 63. RFI Suppression

CD affects the difference signal and CC affects the common-mode signal. Values of R and C Mismatch between the R × C

should be chosen to minimize RFI.

C

at the positive input and the R × CC

C

at the negative input degrades the CMRR of the AD8226. By using a value of C

that is one magnitude larger than C

D

, the effect of

C

the mismatch is reduced and performance is improved.

Rev. A | Page 22 of 28

AD8226

APPLICATIONS INFORMATION

DIFFERENTIAL DRIVE

+IN

V

BIAS

+

IN+

− V

+OUT

–OUT

IN−

07036-009

)

AD8226

–IN

REF

RECOMMENDED OP AMPS: AD8515, AD8641, AD820. RECOMMENDED R VALUES: 5kΩ to 20kΩ.

Figure 64. Differential Output Using an Op Amp

R

–

OP AMP

Figure 64 shows how to configure the AD8226 for differential output.

The differential output is set by the following equation:

V

DIFF_OUT

= V

OUT+

− V

= Gain × (V

OUT−

The common-mode output is set by the following equation:

V

CM_OUT

= (V

OUT+

− V

OUT−

)/2= V

BIAS

The advantage of this circuit is that the dc differential accuracy depends on the AD8226, not on the op amp or the resistors. In addition, this circuit takes advantage of the precise control that the AD8226 has of its output voltage relative to the reference voltage. Although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and therefore typically have little effect on overall system accuracy.

Tips for Best Differential Output Performance

For best ac performance, an op amp with at least a 2 MHz gain bandwidth and a 1 V/µs slew rate is recommended. Good choices for op amps are the AD8641, AD8515, and AD820.

Keep trace lengths from the resistors to the inverting terminal of the op amp as short as possible. Excessive capacitance at this node can cause the circuit to be unstable. If capacitance cannot be avoided, use lower value resistors.

For best linearity and ac performance, a minimum positive supply voltage (+V

) is required. Tab le 9 shows the minimum

S

supply voltage required for optimum performance. In this mode, V

indicates the maximum common-mode voltage expected

CM_MAX

at the input of the AD8226.

Table 9. Minimum Positive Supply Voltage

Temperature Equation

Less than −10°C +VS > (V

−10°C to 25°C +VS > (V More than 25°C +VS > (V

CM_MAX

+ V + V + V

)/2 + 1.4 V

BIAS

)/2 + 1.25 V

BIAS

)/2 + 1.1 V

BIAS

Rev. A | Page 23 of 28

AD8226

V

PRECISION STRAIN GAGE

The low offset and high CMRR over frequency of the AD8226 make it an excellent candidate for performing bridge measurements. The bridge can be connected directly to the inputs of the amplifier (see Figure 65).

5

10µF 0.1µF

350Ω

350Ω350Ω

Figure 65. Precision Strain Gage

+IN

+

R

AD8226

G

–

–IN

2.5V

07036-010

DRIVING AN ADC

Figure 66 shows several methods for driving an ADC. The

ADuC7026 microcontroller was chosen for this example because it

contains ADCs with an unbuffered, charge-sampling architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the ADC and amplifier to work correctly.

Option 1 shows the minimum configuration required to drive a charge-sampling ADC. The capacitor provides charge to the ADC sampling capacitor while the resistor shields the AD8226 from the capacitance. To keep the AD8226 stable, the RC time constant of the resistor and capacitor needs to stay above 5 µs. This circuit is mainly useful for lower frequency signals.

Option 2 shows a circuit for driving higher speed signals. It uses a precision op amp (AD8616) with relatively high bandwidth and output drive. This amplifier can drive a resistor and capacitor with a much higher time constant and is therefore suited for higher frequency applications.

Option 3 is useful for applications where the AD8226 needs to run off a large voltage supply but drive a single-supply ADC. In normal operation, the AD8226 output stays within the ADC range, and the AD8616 simply buffers it. However, in a fault condition, the output of the AD8226 may go outside the supply range of both the AD8616 and the ADC. This is not an issue in the circuit, however, because the 10 k resistor between the two amplifiers limits the current into the AD8616 to a safe level.

OPTION 1: DRIVING LOW FREQUENCY SIGNALS

3.3V

AD8226

3.3V

AD8226

+15V

AD8226

–15V

100Ω

REF

OPTION 2: DRIVING HIGH FREQ UE NCY SIG NALS

REF

OPTIO N 3: P ROTECTING ADC FROM LARGE VOLTAGES

10kΩ

REF

100nF

3.3V

AD8616

3.3V

AD8616

Figure 66. Driving an ADC

10Ω

10nF

10Ω

10nF

3.3V

AV

DD

ADC0

ADuC7026

ADC1

ADC2

AGND

07036-065

Rev. A | Page 24 of 28

AD8226

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8° 0°

0.80

0.60

0.40

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00 COPLANARITY

1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 67. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLI M E TERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8226ARMZ AD8226ARMZ-RL AD8226ARMZ-R7 AD8226ARZ AD8226ARZ-RL AD8226ARZ-R7 AD8226BRMZ AD8226BRMZ-RL AD8226BRMZ-R7 AD8226BRZ AD8226BRZ-RL AD8226BRZ-R7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 8-Lead MSOP RM-8 Y18

1

−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y18

1

−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y18

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

1

−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

1

−40°C to +125°C 8-Lead MSOP RM-8 Y19

1

−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y19

1

−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y19

1

−40°C to +125°C 8-Lead SOIC_N R-8

1

−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8

1

−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8

Rev. A | Page 25 of 28

AD8226

NOTES

Rev. A | Page 26 of 28

AD8226

NOTES

Rev. A | Page 27 of 28

AD8226

NOTES

Rev. A | Page 28 of 28

Datasheet AD8226 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

PIN CONFIGURATION

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ARCHITECTURE

GAIN SELECTION

REFERENCE TERMINAL

INPUT VOLTAGE RANGE

Performance Across Temperature

Recommendation for Best Performance

LAYOUT

Common-Mode Rejection Ratio Over Frequency

Power Supplies

References

INPUT BIAS CURRENT RETURN PATH

INPUT PROTECTION

RADIO FREQUENCY INTERFERENCE (RFI)

APPLICATIONS INFORMATION

DIFFERENTIAL DRIVE

Tips for Best Differential Output Performance

PRECISION STRAIN GAGE

DRIVING AN ADC

OUTLINE DIMENSIONS

ORDERING GUIDE