ANALOG DEVICES AD8195 Service Manual

V

www.BDTIC.com/ADI

HDMI/DVI Buffer with Equalization

FEATURES

1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input

4 TMDS channels per link

Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables

(20 m at 2.25 Gbps)
Preemphasized outputs
Fully buffered unidirectional inputs/outputs
50 Ω on-chip terminations
Low added jitter
Transmitter disable feature

Reduces power dissipation

Disables input termination

3 auxiliary buffered channels per link

Bidirectional buffered DDC lines (SDA and SCL)
Bidirectional buffered CEC line with integrated pull-up

resistors (27 kΩ)
Independently powered from +5 V of HDMI input

connector
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation

Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm × 6 mm)

APPLICATIONS

Front panel buffer for advanced television (HDTV) sets

GENERAL DESCRIPTION

The AD8195 is an HDMI™/DVI buffer featuring equalized
TMDS inputs and preemphasized TMDS outputs, ideal for
systems with long cable runs. The AD8195 includes bidirec­tional buffering for the DDC bus and bidirectional buffering
with integrated pull-up resistors for the CEC bus. The DDC
and CEC buffers are powered independently of the TMDS
buffers so that DDC/CEC functionality can be maintained
when the system is powered off.

The AD8195 is specified to operate over the −40°C to +85°C
temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

AD8195

FUNCTIONAL BLOCK DIAGRAM

PE_EN

TX_EN

COMP

PARALLEL

VTTI

4

+

IP[3:0]

IN[3:0]

VREF_IN

SCL_IN
SDA_IN

CEC_IN CEC_OUT

4

–

CONTROL

LOGIC

BUFFER

EQ

HIGH SPEED BUFFERED

LOW SPEED BUFFERED

BIDIRECTIO NAL

Figure 1.

TYPICAL APPLICATION

MEDIA CENTER

HDMI

RECEIVER

SET-TOP BOX

DVD PLAYER

Figure 2. Typical AD8195 Application for HDTV Sets

4:1 HDMI

SWITCH

BACK PANEL

CONNECT ORS

PRODUCT HIGHLIGHTS

1. Enables a fully HDMI 1.3a-compliant front panel input.

2. Supports data rates up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.

3. Input cable equalizer enables use of long cables; more than

20 meters (24 AWG) at data rates up to 2.25 Gbps.

4. Auxiliary buffer isolates and buffers the DDC bus and CEC

line for a single chip, fully HDMI 1.3a-compliant solution.

5. Auxiliary buffer is powered independently from the TMDS

link so that DDC/CEC functionality can be maintained
when the system is powered off.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD8195

4

4

PE

22

HDTV SET

AD8195

FRONT PANEL

CONNECTOR

+

–

AVCC

AMUXVCC

AVEE

VTTO

OP[3:0]

ON[3:0]

REF_OUT

SCL_OUT
SDA_OUT

GAME

CONSOLE

07049-001

07049-002

AD8195

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Typical Application ........................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

TMDS Performance Specifications ............................................ 3

Auxiliary Channel Performance Specifications........................ 4

Power Supply and Control Logic Specifications ...................... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation ..................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 12

Introduction ................................................................................ 12

Input Channels ........................................................................... 12

Output Channels ........................................................................ 12

Preemphasis ................................................................................ 13

Auxiliary Lines ............................................................................ 13

Applications Information .............................................................. 14

Front Panel Buffer for Advanced TV ....................................... 14

Cable Lengths and Equalization ............................................... 15

TMDS Output Rise/Fall Times ................................................. 15

PCB Layout Guidelines .............................................................. 15

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

8/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD8195

www.BDTIC.com/ADI

SPECIFICATIONS

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AMUXVCC = 5 V, VREF_IN = 5 V, VREF_OUT = 5 V, AVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

TMDS PERFORMANCE SPECIFICATIONS

Table 1.

Parameter Conditions/Comments Min Typ Max Unit
TMDS DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps
Bit Error Rate (BER) PRBS 223 − 1 10−9
Added Data Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1 31 ps p-p
Added Clock Jitter 1 ps rms
Differential Intrapair Skew At output 1 ps
Differential Interpair Skew At output 30 ps

TMDS EQUALIZATION PERFORMANCE

Receiver
Transmitter

TMDS INPUT CHARACTERISTICS

Input Voltage Swing Differential 150 1200 mV
Input Common-Mode Voltage (V

TMDS OUTPUT CHARACTERISTICS

High Voltage Level Single-ended high speed channel AVCC − 200 AVCC + 10 mV
Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV
Rise/Fall Time (20% to 80%)

TMDS TERMINATION

Input Termination Resistance Single-ended 50 Ω
Output Termination Resistance Single-ended 50 Ω

1

Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.

2

Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.

3

Output rise/fall time measurement excludes external components, such as HDMI connector or external ESD protection diodes. See the

section for more information.

1

Boost frequency = 1.125 GHz 12 dB

2

Boost frequency = 1.125 GHz 6 dB

) AVCC − 800 AVCC mV

ICM

3

DR = 2.25 Gbps 50 90 150 ps

Applications Information

Rev. 0 | Page 3 of 20

AD8195

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AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS

Table 2.

Parameter Conditions/Comments Min Typ Max Unit
DDC CHANNELS

Input Capacitance, C
Input Low Voltage, VIL 0.5 V
Input High Voltage, VIH 0.7 × VREF
Output Low Voltage, VOL I
Output High Voltage, VOH VREF
Rise Time 10% to 90%, no load 140 ns
Fall Time 90% to 10%, C
Leakage Input voltage = 5.0 V 10 μA

CEC CHANNEL

Input Capacitance, C

Input Low Voltage, VIL 0.8 V
Input High Voltage, VIH 2.0 V
Output Low Voltage, VOL 0.25 0.6 V
Output High Voltage, VOH 2.5 3.3 V
Rise Time

Fall Time

Pull-Up Resistance 27 kΩ
Leakage Off leakage test conditions

1

VREF is the voltage at the reference pin (VREF_IN for SCL_IN and SDA_IN, or VREF_OUT for SCL_OUT and SDA_OUT); nominally +5.0 V.

2

Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3b Section 8, Test ID 8-14: “Remove power (mains) from DUT. Connect CEC line

to 3.63 V via 27 kΩ ±5% resistor with ammeter in series. Measure CEC line leakage.”

DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 10 15 pF

AUX

AUX

1

VREF

= 5 mA 0.25 0.4 V

OL

= 400 pF 100 200 ns

LOAD

DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz,

5 25 pF

1

V

1

2 kΩ pull-up resistor from CEC_OUT to 3.3 V

10% to 90%, C
or C

= 7200 pF, R

LOAD

90% to 10%, C

= 7200 pF, R

or C

LOAD

= 1500 pF, R

LOAD

PULL-UP

= 1500pF, R

LOAD

PULL-UP

= 27 kΩ;

PULL-UP

= 3 kΩ

= 27 kΩ;

PULL-UP

= 3 kΩ

2

1.8 μA

50 100 μs

5 10 μs

V

POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

POWER SUPPLY

AVCC Operating range (3.3 V ± 10%) 3 3.3 3.6 V
AMUXVCC Operating range (5 V ± 10%) 4.5 5 5.5 V
VREF_IN, VREF_OUT 3 5.5 V

QUIESCENT CURRENT

AVCC Output disabled 20 40 mA
Output enabled, no preemphasis 32 50 mA
Output enabled, maximum preemphasis 66 80 mA
VTTI Input termination on 40 54 mA
VTTO Output termination on, no preemphasis 40 50 mA
Output termination on, maximum preemphasis 80 100 mA
VREF_IN 120 200 μA
VREF_OUT 120 200 μA

AMUXVCC 10 20 mA
POWER DISSIPATION
Output disabled 116 254 mW
Output enabled, no preemphasis 180 663 mW
Output enabled, maximum preemphasis 736 1047 mW
PARALLEL CONTROL INTERFACE TX_EN, PE_EN

Input High Voltage, VIH 2.4 V

Input Low Voltage, VIL 0.8 V

Rev. 0 | Page 4 of 20

AD8195

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ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVCC to AVEE 3.7 V
VTTI AVCC + 0.6 V
VTTO AVCC + 0.6 V
AMUXVCC 5.5 V
VREF_IN 5.5 V
VREF_OUT 5.5 V
Internal Power Dissipation 1.81 W
High Speed Input Voltage

High Speed Differential Input Voltage 2.0 V
Parallel Control Input Voltage

Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Junction Temperature 150°C
ESD, Human Body Model

Input Pins Only ±5 kV
All Other Pins ±3 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

AVCC − 1.4 V < V
AVCC + 0.6 V

AVEE − 0.3 V < V
AVCC + 0.6 V

<

IN

<

IN

THERMAL RESISTANCE

Table 5.

Package θJA θ

40-Lead LFCSP_VQ 36 5.0 °C/W

Unit

JC

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8195 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation,
it is necessary to observe the maximum power derating as
determined by the thermal resistance coefficients.

ESD CAUTION

Rev. 0 | Page 5 of 20

AD8195

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

40 SCL_IN

39 SDA_IN

38 CEC_IN

37 AVEE

36 VREF_IN

35 SCL_OUT

34 SDA_OUT

31 CEC_OUT

32 AMUXVCC

33 VREF_OUT

1IN0

PIN 1

2IP0

INDICAT OR

3IN1

4IP1

5VTTI

6IN2

7IP2

8IN3

9IP3

10AVCC

11ON0

NOTES

1. THE AD8195 LFCSP HAS AN EXPOSED PAD O N THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DI SSIPATI ON. THE PAD MUST BE
ELECTRICALLY CONNECT ED TO THE AVEE SUPPL Y PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.

(Not to Scale)

12OP0

13VTTO

AD8195

TOP VIEW

14ON1

15OP1

16AVCC

17ON2

19ON3

18OP2

30 AVCC

29 PE_EN

28 TX_EN

27 AVEE

26 AVCC

25 AVCC

24 AVEE

23 AVCC

22 AVCC

21 COMP

20OP3

07049-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1 IN0 HS I High Speed Input Complement.
2 IP0 HS I High Speed Input.
3 IN1 HS I High Speed Input Complement.
4 IP1 HS I High Speed Input.
5 VTTI Power Input Termination Supply. Nominally connected to AVCC.
6 IN2 HS I High Speed Input Complement.
7 IP2 HS I High Speed Input.
8 IN3 HS I High Speed Input Complement.
9 IP3 HS I High Speed Input.
10, 16, 22, 23, 25, 26, 30 AVCC Power Positive Analog Supply. 3.3 V nominal.
11 ON0 HS O High Speed Output Complement.
12 OP0 HS O High Speed Output.
13 VTTO Power Output Termination Supply. Nominally connected to AVCC.
14 ON1 HS O High Speed Output Complement.
15 OP1 HS O High Speed Output.
17 ON2 HS O High Speed Output Complement.
18 OP2 HS O High Speed Output.
19 ON3 HS O High Speed Output Complement.
20 OP3 HS O High Speed Output.
21 COMP Control Power-On Compensation Pin. Bypass to ground through a 10 μF capacitor.
24, 27, 37, Exposed Pad AVEE Power Negative Analog Supply. 0 V nominal.
28 TX_EN Control High Speed Output Enable Parallel Interface.
29 PE_EN Control High Speed Preemphasis Enable Parallel Interface.
31 CEC_OUT LS I/O CEC Output Side.
32 AMUXVCC Power Positive Auxiliary Buffer Supply. 5 V nominal.

Rev. 0 | Page 6 of 20