ANALOG DEVICES AD8192 Service Manual

2:1 HDMI/DVI Switch with

FEATURES

2 inputs, 1 output HDMI/DVI links
HDMI 1.3a receive and transmit compliant
±7 kV HBM ESD on HDMI input pins
4 TMDS channels per link

Supports 250 Mbps to 2.25 Gbps data rates and beyond
Supports 25 MHz to 225 MHz pixel clocks and beyond
Fully buffered unidirectional inputs/outputs
Switchable 50 Ω on-chip input terminations with

programmable or automatic control on channel switch
Equalized inputs and pre-emphasized outputs
Low added jitter
Output disable feature for reduced power dissipation
Switched output termination for building of larger arrays

Bidirectional and cascadable DDC buffers (SDA/SCL)

DDC bus logic level translation (3.3 V, 5 V)

Bidirectional and cascadable CEC buffer with integrated

pull-up resistors (27 kΩ)

Hot plug detect pulse low on channel switch
Standards compatible: DVI, HDMI 1.3a, HDCP, I

2

Serial (I

C slave) control interface

56-lead, 8 mm × 8 mm LFCSP, RoHS-compliant package

APPLICATIONS

Front panel buffer for advanced television (HDTV) sets
Standalone HDMI switcher
Multiple input displays
Projectors
A/V receivers
Set-top boxes

2

C

Equalization and DDC/CEC Buffers

AD8192

FUNCTIONAL BLOCK DIAGRAM

RESET

I2C_SDA
I2C_SCL

I2C_ADDR

VTTI

IP_A[3:0]
IN_A[3:0]

IP_B[3:0]
IN_B[3:0]

VTTI

DDC_A[1:0]

DDC_B[1:0]

HPD_A

HPD_B

SET-TOP BOX

SERIAL INTERFACE

CONFIG

INTERFACE

+

–

+

–

4

4

4

4

2

2

LOW SPEED

DVEE

CONTROL

LOGIC

SWITCH

CORE

EQ

HIGH SPEED BUFFERED

SWITCH

CORE

BIDIRECT IONAL

Figure 1.

TYPICAL APPLICATION

HDMI

RECEIVER

AD8192

Figure 2. Typical Application for HDTV Sets

BUFFERED

HDTV SET

AD8192

PE

+

4

–

4

2

DVD PLAYER

AVCC
DVCC
AMUXVCC
AVEE
DVEE
VREF_AB
VREF_COM

VTTO

OP[3:0]
ON[3:0]

DDC_COM[1:0]

CEC_O/ICEC_I/O

07050–001

07050-002

GENERAL DESCRIPTION

The AD8192 is a complete HDMI™/DVI link switch featuring
equalized TMDS inputs and pre-emphasized TMDS outputs
ideal for systems with long cable runs. The TMDS outputs can
be set to a high impedance state to reduce the power dissipation
and/or allow the construction of larger arrays using the wire­OR technique. The AD8192 includes bidirectional buffering for
the DDC bus and CEC line, with integrated pull-up resistors for
the CEC line. The AD8192 is available in a space-saving, 56-lead
LFCSP surface-mount, lead-free plastic package specified to
operate over the −40°C to +85°C temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to chan ge without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. Fully HDMI 1.3a transmit and receive compliant.

2. Supports data rates up to 2.25 Gbps, enabling greater than

1080p HDMI formats with deep color (12-bit) and UXGA
(1600 × 1200) DVI resolutions.

3. Input cable equalizer enables use of long cables; more than

20 m (24 AWG) at data rates up to 2.25 Gbps.

4. Auxiliary switch isolates and buffers the DDC bus and the

CEC line, improving total system capacitance limit.

5. Hot plug detect (HPD) signal is pulsed low on link switch.

6. Manually or automatically switched input terminations.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD8192

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Typical Application ........................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

Input Channels ............................................................................ 12

Output Channels ........................................................................ 12

Switching Mode .......................................................................... 13

Pre-Emphasis .............................................................................. 13

Auxiliary Multiplexer ................................................................. 14

DDC Logic Levels ....................................................................... 14

Input/Output Mapping Control ............................................... 14

Serial Control Interface .................................................................. 15

Reset ............................................................................................. 15

Write Procedure .......................................................................... 15

Read Procedure ........................................................................... 16

Configuration Registers ................................................................. 17

High Speed Device Modes Register ......................................... 18

Auxiliary Device Modes Register ............................................. 18

Receiver Settings Register ......................................................... 18

Input Termination Control Register ........................................ 18

Receive Equalizer Register ........................................................ 18

Transmitter Settings Register .................................................... 19

Source Sign Control Register .................................................... 19

Source A Input/Output Mapping Register .............................. 19

Source B Input/Output Mapping Register .............................. 19

Applications Information .............................................................. 20

Pinout ........................................................................................... 20

Cable Lengths and Equalization ............................................... 21

TMDS Output Rise/Fall Times ................................................. 21

Front Panel Buffer for Advanced TV ....................................... 21

HDMI Switcher .......................................................................... 21

Cascading Multiple Devices ...................................................... 21

PCB Layout Guidelines .............................................................. 22

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

5/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8192

SPECIFICATIONS

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, VREF_AB = 5 V, VREF_COM = 5 V,
AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless
otherwise noted.

Table 1. TMDS Performance Specifications

Parameter Conditions/Comments Min Typ Max Unit

TMDS DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per

Channel
Bit Error Rate (BER) PRBS 223 − 1 10−9
Added Data Jitter

Added Clock Jitter 1 ps (rms)
Differential Intrapair Skew At output 1 ps
Differential Interpair Skew At output 30 ps

TMDS EQUALIZATION PERFORMANCE

Receiver (Highest Setting)
Transmitter (Highest Setting)

1

2

TMDS INPUT CHARACTERISTICS

Input Voltage Swing Differential 150 1200 mV
Input Common-Mode Voltage (V

TMDS OUTPUT CHARACTERISTICS

High Voltage Level Single-ended high speed channel AVCC − 200 AVCC + 10 mV
Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV
Rise/Fall Time (20% to 80%)

3

TMDS TERMINATION

Input Termination Resistance Single-ended 50 Ω
Output Termination Resistance Single-ended 50 Ω

1

Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.

2

Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.

3

Output rise/fall time measurement excludes external components such as HDMI connector or external ESD protection diodes. See Applications Information section for

more information.

NRZ 2.25 Gbps

DR ≤ 2.25 Gbps, PRBS 2

7

− 1, no equalization

23 ps (p-p)

Boost frequency = 1.125 GHz 12 dB
Boost frequency = 1.125 GHz 6 dB

) AVCC − 800 AVCC mV

ICM

DR = 2.25 Gbps 50 90 150 ps

Table 2. Auxiliary Channel Performance Specifications

Parameter Symbol Conditions/Comments Min Typ Max Unit
DDC CHANNELS

Input Capacitance C

DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 10 15 pF

AUX

Input Low Voltage VIL 0.5 V
Input High Voltage VIH 0.7 × VREF1 V
Output Low Voltage VOL I
Output High Voltage VOH VREF

= 5 mA 0.4 V

OL

1

V

Rise Time 10% to 90%, no capacitive load 140 ns
Fall Time 90% to 10%, C

= 400 pF 100 200 ns

LOAD

Leakage 10 μA

CEC CHANNEL

Input Capacitance C

DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 5 25 pF

AUX

Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.0 V
Output Low Voltage VOL R

= 3 kΩ to +3.3 V 0.6 V

PULLUP

Output High Voltage, VOH 2.5 AVCC V

Rev. 0 | Page 3 of 28

AD8192

Parameter Symbol Conditions/Comments Min Typ Max Unit

Rise Time

10% to 90%, C
7200 pF, R

Fall Time

90% to 10%, C
7200 pF, R

Leakage

Off-leakage test conditions from HDMI Compliance Test

PULLUP

PULLUP

= 1500 pF, R

LOAD

= 3 kΩ

= 1500 pF, R

LOAD

= 3 kΩ

= 27 kΩ; or C

PULLUP

= 27 kΩ; or C

PULLUP

LOAD

LOAD

=

=

Specification Test ID: 8-14

HOT PLUG DETECT

Output Low Voltage VOL R

1

VREF refers to the voltage at the VREF_AB or VREF_COM pins. VREF should be at the same supply voltage as that to which the external pull-up resistors are connected.

= 800 Ω to +5 V 0.4 V

PULLUP

Table 3. Power Supply and Control Logic Specifications

Parameter Conditions/Comments Min Typ Max Unit

POWER SUPPLY

AVCC Operating range (3.3 V ± 5%) 3.135 3.3 3.465 V
AMUXVCC Operating range (5 V ± 10%) 4.5 5 5.5 V
VREF_AB 3 5 5.5 V
VREF_COM 3 5 5.5 V

QUIESCENT CURRENT

AVCC Outputs disabled 40 45 mA
AVCC Outputs enabled, no pre-emphasis 60 70 mA
AVCC Outputs enabled, maximum pre-emphasis 100 120 mA
VTTI Input termination on

1

40 54 mA
VTTO Outputs enabled, output termination on 40 50 mA
Output termination on, maximum pre-emphasis 80 100 mA
DVCC 10 15 mA
VREF_AB 1 10 μA
VREF_COM 1 10 μA
AMUXVCC 10 20 mA

POWER DISSIPATION
Outputs disabled 215 318 mW

Outputs enabled, no pre-emphasis 545 765 mW
Outputs enabled, maximum pre-emphasis 881 1200 mW

I2C® AND LOGIC INPUTS

2

Input High Voltage, VIH Serial interface 2.4 V
Input Low Voltage, VIL Serial interface 0.8 V

I2C AND LOGIC OUTPUTS

Output Low Voltage, VOL Serial interface, IOL = +3 mA 0.4 V

1

Assumes that the unselected HDMI/DVI link is deactivated through the hot plug detect line, as required by the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.

2

The AD8192 is an I2C slave and its control interface is based on the 3.3 V I2C bus specification.

50 100 μs

5 10 μs

1.8 μA

Rev. 0 | Page 4 of 28

AD8192

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVCC to AVEE 3.7 V
DVCC to DVEE 3.7 V
DVEE to AVEE ±0.3 V
VTTI AVCC + 0.6 V
VTTO AVCC + 0.6 V
AMUXVCC 5.5 V
VREF_AB 5.5 V
VREF_COM 5.5 V
Internal Power Dissipation 2.41 W
High Speed Input Voltage AVCC − 1.4 V < VIN < AVCC + 0.6 V
High Speed Differential

Input Voltage
Low Speed Input Voltage DVEE − 0.3 V < VIN < AMUXVCC + 0.6 V
I2C Logic Input Voltage DVEE − 0.3 V < VIN < DVCC + 0.6 V
Storage Temperature

Range
Operating Temperature

Range
Junction Temperature 150°C
ESD HBM Input Pins Only ±7 kV
ESD HBM All Other Pins ±1.5 kV

2.0 V

−65°C to +125°C

−40°C to +85°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a four-layer JEDEC circuit board for surface-mount
packages. θ

is specified for the exposed pad soldered to the

JC

circuit board with no airflow.

Table 5. Thermal Resistance

Model θJA θJC Unit

56-Lead LFCSP 27 2.1 °C/W

ESD CAUTION

Rev. 0 | Page 5 of 28

AD8192

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PD_A

DDC_COM051VREF_AB52DVEE53CEC_I/O54H

50

AD8192

TOP VIEW

(Not to Scale)

1

DDC_B046CEC_O/I47AMUXVCC48VREF_COM49DDC_COM

DDC_B143HPD_B

44

45

42
41
40
39
38
37
36
35
34
33
32
31
30
29

AVCC
IN_A0
IP_A0
AVEE
IN_A1
IP_A1

VTTI
IN_A2
IP_A2
AVCC
IN_A3
IP_A3
AVEE

I2C_ADDR

0

DDC_A156DDC_A

55

PIN 1

1

INDICATO R

2
3
4
5
6
7
8

9
10
11
12
13
14

AVCC
IP_B3
IN_B3
AVEE
IP_B2
IN_B2
VTTI
IP_B1
IN_B1
AVCC
IP_B0
IN_B0
AVEE
I2C_SDA

16

15

ON0

DVCC

NOTES

1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICAL LY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO

MEET THERMAL SPECIFICATIONS.

21

17

19

20

22

23

24

25

26

27

18

OP0

OP1

ON1

ON2

VTTO

DVCC

28

OP2

OP3

SCL

ON3

_

VTTO

C

RESET

I2

07050-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1, 10, 33, 42 AVCC Power Positive Analog Supply. 3.3 V nominal.
2 IN_A0 HS I/O High Speed Input Complement.
3 IP_A0 HS I/O High Speed Input.
4, 13, 30, 39, ePAD AVEE Power Negative Analog Supply. 0 V nominal.
5 IN_A1 HS I/O High Speed Input Complement.
6 IP_A1 HS I/O High Speed Input.
7, 36 VTTI Power Input Termination Supply. Nominally connected to AVCC.
8 IN_A2 HS I/O High Speed Input Complement.
9 IP_A2 HS I/O High Speed Input.
11 IN_A3 HS I/O High Speed Input Complement.
12 IP_A3 HS I/O High Speed Input.
14 I2C_ADDR Control I2C Address LSB.
15, 21 DVCC Power Positive Digital Power Supply. 3.3 V nominal.
16 ON0 HS I/O High Speed Output Complement.
17 OP0 HS I/O High Speed Output.
18, 24 VTTO Power Output Termination Supply. Nominally connected to AVCC.
19 ON1 HS I/O High Speed Output Complement.
20 OP1 HS I/O High Speed Output.
22 ON2 HS I/O High Speed Output Complement.
23 OP2 HS I/O High Speed Output.
25 ON3 HS I/O High Speed Output Complement.
26 OP3 HS I/O High Speed Output.
27

RESET

Control Configuration Registers Reset. Normally pulled to AVCC.
28 I2C_SCL Control I2C Clock.
29 I2C_SDA Control I2C Data.
31 IN_B0 HS I/O High Speed Input Complement.
32 IP_B0 HS I/O High Speed Input.
34 IN_B1 HS I/O High Speed Input Complement.
35 IP_B1 HS I/O High Speed Input.

Rev. 0 | Page 6 of 28

AD8192

Pin No. Mnemonic Type

1

Description

37 IN_B2 HS I/O High Speed Input Complement.
38 IP_B2 HS I/O High Speed Input.
40 IN_B3 HS I/O High Speed Input Complement.
41 IP_B3 HS I/O High Speed Input.
43 HPD_B LS O Hot Plug Detect Output.
44 DDC_B1 LS I/O Display Data Channel Input/Output.
45 DDC_B0 LS I/O Display Data Channel Input/Output.
46 CEC_O/I LS I/O Consumer Electronics Control Output/Input.
47 AMUXVCC Power Positive Auxiliary Switch Supply. 5 V typical.
48 VREF_COM Reference Positive Auxiliary Switch Supply Common Side.
49 DDC_COM1 LS I/O Display Data Channel Common Input/Output.
50 DDC_COM0 LS I/O Display Data Channel Common Input/Output.
51 VREF_AB Reference Positive Auxiliary Switch Supply Source Side.
52 DVEE Power Negative Digital and Auxiliary Switch Power Supply. 0 V nominal.
53 CEC_I/O LS I/O Consumer Electronics Control Input/Output.
54 HPD_A LS O Hot Plug Detect Output.
55 DDC_A1 LS I/O Display Data Channel Input/Output.
56 DDC_A0 LS I/O Display Data Channel Input/Output.

1

HS = high speed, LS = low speed, I = input, O = output.

Rev. 0 | Page 7 of 28

AD8192

V

V

V

V

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

DIGITAL

PATTERN

GENERATOR

AD8192

EVALUATIO N

BOARD

SMA COAX CABLE

SERIAL DATA

ANALYZER

REFERENCE EYE DI AGRAM AT TP1

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 5. Rx Eye Diagram at TP2 (Cable = 2 m, 30 AWG)

TP1 TP2 TP3

Figure 4. Test Circuit Diagram for Rx Eye Diagrams

250mV/DI

07050-005

Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 2 m, 30 AWG)

0.125UI/DI V AT 2.25Gbps

07050-004

07050-007

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 6. Rx Eye Diagram at TP2 (Cable = 20 m, 24 AWG)

07050-006

250mV/DI

0.125UI/DI V AT 2.25Gbps

07050-008

Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 m, 24 AWG)

Rev. 0 | Page 8 of 28

AD8192

V

V

V

V

TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

REFERENCE EYE DI AGRAM AT TP1

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 10. Tx Eye Diagram at TP2, PE = 0 dB

DIGITAL

PATTERN

GENERATOR

SMA COAX CABLE

AD8192

EVALUATION

BOARD

TP1 TP2 TP3

Figure 9. Test Circuit Diagram for Tx Eye Diagrams

250mV/DI

07050-010

Figure 12. Tx Eye Diagram at TP3, PE = 0 dB (Cable = 2 m, 24 AWG)

SERIAL DATA

ANALYZER

0.125UI/DI V AT 2.25Gbps

07050-009

07050-012

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 11. Tx Eye Diagram at TP2, PE = 6 dB

07050-011

250mV/DI

0.125UI/DI V AT 2.25Gbps

Figure 13. Tx Eye Diagram at TP3, PE = 6 dB (Cable = 10 m, 24 AWG)

07050-013

Rev. 0 | Page 9 of 28