ANALOG DEVICES AD8159 Service Manual

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3.2 Gbps

FEATURES

Port level 2:1 mux/1:2 demux Each port consists of 4 lanes Each lane runs from dc to 3.2 Gbps, independent

of the other lanes

Compensates over 40 inches of FR4 at 3.2 Gbps through

o levels of input equalization, or four levels of output

tw

pre-emphasis Accepts ac- or dc-coupled differential CML inputs Low deterministic jitter, typically 20 ps p-p Low random jitter, typically 1 ps rms BER < 10 On-chip termination Reversible inputs and outputs on one port Unicast or bicast on 1:2 demux function Port level loopback capability Single lane switching capability

3.3 V core supply Flexible I/O supply down to 2.5 V Low power, typically 1 W in basic configuration 100-pin TQFP_EP

−40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch SONET OC48/SDH16 and lower data rates XAUI (10 Gigabit Ethernet) over backplane Gigabit Ethernet over backplane Fibre channel 1.06 Gbps and 2.125 Gbps over backplane Infiniband over backplane PCI-Express over backplane

GENERAL DESCRIPTION

The AD8159 is an asynchronous, protocol agnostic, quad-lane 2:1 switch with a total of 12 differential PECL/CML-compatible inputs and 12 differential CML outputs. The operation of this product is optimized for NRZ signaling with data rates up to

3.2 Gbps per lane. Each lane offers two levels of input equalization and four levels of output pre-emphasis.

-16

Quad Buffer Mux/Demux

AD8159

FUNCTIONAL BLOCK DIAGRAM

EQUALIZATION

Figure 1.

TRANSMIT

PRE-

EMPHASIS

EQ

RECEIVE

I/O

CROSS-

OVER

SWITCH

CONTROL

LOGIC

OUT_C[3:0]/ IN_C[3:0]

IN_C[3:0]/ OUT_C[3:0]

LB_A LB_B LB_C PE_A[1:0] PE_B[1:0] PE_C[1:0] EQ_A EQ_B EQ_C SEL[3:0] BICAST REVERSE_C

RECEIVE

EQUALIZATION

IN_A[3:0]

IN_B[3:0]

OUT_A[3:0]

OUT_B[3:0]

EQ

TRANSMIT

PRE-

EMPHASIS

AD8159

2:1

1:2

QUAD

2:1

MULTIPLEXER/

1:2

DEMULTIPLEXER

The main application of the AD8159 is to support redundancy on both the backplane side and the line interface side of a serial link. The device has unicast and bicast capability, so it is configurable to support either 1 + 1 or 1:1 redundancy.

The AD8159 supports reversing the output and input pins on o

ne of its ports, which helps to connect two ASICs with

opposite pinouts.

05611-001

The AD8159 consists of four multiplexers and four demultip

lexers, one per lane. Each port is a 4-lane link, and each lane runs up to a 3.2 Gbps data rate independent of the other lanes. The lanes are switched independently using the four select pins,

The AD8159 is also used for testing high speed serial links by

uplicating incoming data and sending it to the destination port

d and to test equipment simultaneously.

SEL[3:0]; each select pin controls one lane of the port. The AD8159 has low latency and very low lane-to-lane skew.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8159

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REVISION HISTORY

4/06—Rev. 0 to Rev. A

Changes to Applications Section .................................................... 1

Changes to Table 5.......................................................................... 15

Updates to Outline Dimensions ...................................................22

Changes to Ordering Guide.......................................................... 22

Input Equalization (EQ) and Output Pre-Emphasis (PE).... 15

Loopback ..................................................................................... 16

Port C Reverse (Crossover) Capability.................................... 17

Applications..................................................................................... 18

Interfacing to the AD8159............................................................. 19

Termination Structures.............................................................. 19

Input Compliance....................................................................... 19

Output Compliance ................................................................... 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

9/05—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD8159

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SPECIFICATIONS

VCC = +3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration,1 data rate= 3.2 Gbps, input common-mode voltage = 2.7 V, differential input swing = 800 mV p-p, @ T

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Data Rate/Channel (NRZ) DC 3.2 Gbps Deterministic Jitter Data rate = 3.2 Gbps; see Figure 21 20 ps p-p Random Jitter RMS; see Figure 24 1 ps Propagation Delay Input to output 600 ps Lane-to-Lane Skew 100 ps Switching Time 5 ns Output Rise/Fall Time 20% to 80% 100 ps

INPUT CHARACTERISTICS

Input Voltage Swing Differential, V Input Voltage Range Common mode, VID = 800 mV p-p;3 see Figure 25 VEE + 1.8 VCC + 0.3 V Input Bias Current 4 μA Input Capacitance 2 pF

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential, PE = 0 800 mV p-p Output Voltage Range Single-ended absolute voltage level; see Figure 26 VCC − 1.6 VCC + 0.6 V Output Current Port A/B, PE_A/B = 0 16 mA Port C, PE_C = 0 20 mA Port A/B, PE_A/B = 3 28 mA Port C, PE_C = 3 32 mA Output Capacitance 2 pF

TERMINATION CHARACTERISTICS

Resistance Differential 90 100 110 Ω Temperature Coefficient 0.15 Ω/°C

POWER SUPPLY

Operating Range

V

CC

Supply Current

I

CC

I

= I

+ I

TTO

TTOI

+ I

I/O

Supply Current

I

CC

I

= I

+ I

TTO

TTOI

+ I

I/O

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C θJA Still air 29 °C/W θJB Still air 16 °C/W θJC Still air 13 °C/W

LOGIC INPUT CHARACTERISTICS

Input High (VIH) 2.4 VCC V Input Low (VIL) VEE 0.8 V

1

Bicast off, loopback off on all ports, pre-emphasis off on all ports, equalization set to minimum on all ports.

2

V

= input common-mode voltage.

ICM

3

VID = input differential peak-to-peak voltage swing.

= +25°C, unless otherwise noted.

A

VEE = 0 V 3.0 3.3 3.6 V Basic configuration1, dc-coupled inputs/outputs, 400 mV I/O

swings (800 mV p-p differential), 50 Ω far end terminations

+ I

TTI

TTIO

BICAST = 1, PE = 3 on all ports, dc-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 Ω far end

+ I

TTI

TTIO

terminations

= VCC − 0.6 V;2 see Figure 22 200 2000 mV p-p

ICM

175 mA 144 mA

255 mA 352 mA

Rev. A | Page 3 of 24

AD8159

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating VCC to VEE 3.7 V V

V

TTI

V

TTIO

V

TTO

V

TTOI

Internal Power Dissipation Differential Input Voltage 2.0 V Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range Lead Temperature

+ 0.6 V

CC

+ 0.6 V

CC

+ 0.6 V

CC

+ 0.6 V

CC

4.26 W

−65°C to +125°C 300°C

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 4 of 24

AD8159

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CC

EE

TTOI

EE

CC

EE

TTIO

EE

V

OIP_C098OIN_C097V

OIP_C195OIN_C194V

OIP_C292OIN_C291V

OIP_C389OIN_C388V

IOP_C086ION_C085V

IOP_C183ION_C182V

100

99

96

93

90

87

84

IOP_C280ION_C279V

81

IOP_C377ION_C376V

78

CC

1

NC

V

CC

V

EE

V

EE

V

EE

PE_A0

PE_A1

PE_B0

PE_B1

PE_C0

PE_C1

REVERSE_C

V

CC

ON_A3

OP_A3

V

EE

ON_A2

OP_A2

V

TTO

ON_A1

OP_A1

V

EE

ON_A0

OP_A0

V

CC

NC = NO CONNE CT

NOTES

1. THE AD8159 TQFP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS IN HEAT DISS IPATIO N. THE ePAD M UST BE ELE CTRICALL Y CONNECTE D TO THE V TO MEET THERMAL SPECIFICATIONS.

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

EE

CC

V

IP_A3

IN_A3

TTI

V

IP_A2

IN_A2

IN_A1

34

IP_A1

AD8159

TOP VIEW

(Not to Scale)

35

36

EE

V

IN_A0

37

38

39

40

41

42

43

44

45

46

47

48

EE

CC

V

IP_A0

OP_B3

ON_B3

OP_B2

ON_B2

EE

TTO

V

OP_B1

ON_B1

ON_B0

SUPPLY PLANE IN ORDER

EE

75

V

CC

74

EQ_A

73

EQ_B

72

EQ_C

71

SEL3

70

SEL2

69

SEL1

68

SEL0

67

LB_C

66

LB_B

65

LB_A

64

BICAST

63

V

CC

62

IP_B0

61

IN_B0

60

V

EE

59

IP_B1

58

IN_B1

57

V

TTI

56

IP_B2

55

IN_B2

54

V

EE

53

IP_B3

52

IN_B3

51

V

CC

49

50

CC

V

OP_B0

05611-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 NC N/A No connect 2, 13, 25, 26, 38, 50, 51, 63, 75, 76, 88, 100 VCC Power Positive supply 3 to 5, 16, 22, 29, 35, 41, 47, 54, 60, 79, 85, 91, 97 V 6 PE_A0 Control 7 PE_A1 Control 8 PE_B0 Control 9 PE_B1 Control 10 PE_C0 Control 11 PE_C1 Control 12 REVERSE_C Control 14 ON_A3 I/O 15 OP_A3 I/O 17 ON_A2 I/O 18 OP_A2 I/O 19, 44 V 20 ON_A1 I/O 21 OP_A1 I/O 23 ON_A0 I/O 24 OP_A0 I/O

Power Negative supply

EE

Pre-emphasis control for Port A (LSB) Pre-emphasis control for Port A (MSB) Pre-emphasis control for Port B (LSB) Pre-emphasis control for Port B (MSB) Pre-emphasis control for Port C (LSB) Pre-emphasis control for Port C (MSB) Reverse inputs and outputs on Port C High speed output complement High speed output High speed output complement High speed output

Power Port A and Port B output termination supply

TTO

High speed output complement High speed output High speed output complement High speed output

27 IN_A3 I/O High speed input complement

Rev. A | Page 5 of 24

AD8159

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Pin No. Mnemonic Type Description

28 IP_A3 I/O High speed input 30 IN_A2 I/O High speed input complement 31 IP_A2 I/O High speed input 32, 57 V 33 IN_A1 I/O High speed input complement 34 IP_A1 I/O High speed input 36 IN_A0 I/O High speed input complement 37 IP_A0 I/O High speed input 39 ON_B3 I/O High speed output complement 40 OP_B3 I/O High speed output 42 ON_B2 I/O High speed output complement 43 OP_B2 I/O High speed output 45 ON_B1 I/O High speed output complement 46 OP_B1 I/O High speed output 48 ON_B0 I/O High speed output complement 49 OP_B0 I/O High speed output 52 IN_B3 I/O High speed input complement 53 IP_B3 I/O High speed input 55 IN_B2 I/O High speed input complement 56 IP_B2 I/O High speed input 58 IN_B1 I/O High speed input complement 59 IP_B1 I/O High speed input 61 IN_B0 I/O High speed input complement 62 IP_B0 I/O High speed input 64 BICAST Control Bicast enable 65 LB_A Control Loopback enable for Port A 66 LB_B Control Loopback enable for Port B 67 LB_C Control Loopback enable for Port C 68 SEL0 Control

69 SEL1 Control 70 SEL2 Control 71 SEL3 Control 72 EQ_C Control Equalization control for Port C

73 EQ_B Control Equalization control for Port B 74 EQ_A Control Equalization control for Port A 77 ION_C3 I/O High speed input/output complement 78 IOP_C3 I/O High speed input/output 80 ION_C2 I/O High speed input/output complement 81 IOP_C2 I/O High speed input/output 82 V 83 ION_C1 I/O High speed input/output complement 84 IOP_C1 I/O High speed input/output 86 ION_C0 I/O High speed input/output complement 87 IOP_C0 I/O High speed input/output 89 OIN_C3 I/O High speed output/input complement 90 OIP_C3 I/O High speed output/input 92 OIN_C2 I/O High speed output/input complement 93 OIP_C2 I/O High speed output/input 94 V 95 OIN_C1 I/O High speed output/input complement 96 OIP_C1 I/O High speed output/input 98 OIN_C0 I/O High speed output/input complement 99 OIP_C0 I/O High speed output/input

Power Port A and Port B input termination supply

TTI

/B select for Lane 0

A

/B select for Lane 1

A

/B select for Lane 2

A

/B select for Lane 3

A

Power Port C input/output termination supply

TTIO

Power Port C output/input termination supply

TTOI

Rev. A | Page 6 of 24

AD8159

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TYPICAL PERFORMANCE CHARACTERISTICS

VCC = +3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration, data rate = 3.2 Gbps, input common-mode voltage = 2.7 V, differential input swing = 800 mV p-p, T

Note: All graphs were generated using the setup shown in Figure 32, unless otherwise specified.

= 25°C, unless otherwise noted.

A

0

–2

–4

–6

–8

150mV/DIV

39.0625ps/DIV

Figure 3. Output Port A Eye Diagram 3.2 Gbps

Input Port A or Input Port C

150mV/DIV

39.0625ps/DIV

Figure 4. Output Port B Eye Diagram

Input Port B

or Input Port C

05611-003

05611-004

–10

–12

BIT ERROR RATE (Decades)

–14

–16

0 1.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

TIME (Unit Interval)

Figure 6. Output Port A Bathtub Curve 3.2 Gbps

0

–2

–4

–6

–8

–10

–12

BIT ERROR RATE (Decades)

–14

–16

0 1.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

TIME (Unit Interval)

Figure 7. Output Port B Bathtub Curve 3.2 Gbps

0

05611-006

05611-007

–2

–4

–6

–8

150mV/DIV

39.0625ps/DIV

Figure 5. Output Port C Eye Diagram 3.2 Gbps

Input Port A

or Input Port B

05611-005

–10

–12

BIT ERROR RATE (Decades)

–14

–16

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

01

Figure 8. Output Port C Bathtub Curve 3.2 Gbps

Rev. A | Page 7 of 24

TIME (Unit Interval)

05611-008

.0

AD8159

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150mV/DIV

39.0625ps/DIV

Figure 9. Eye Diagram over Backplane

(18

” FR4 + 2 GbX Connectors), PE = 0

150mV/DIV

Figure 10. Eye Diagram over Backplane

(30

” FR4 + 2 GbX Connectors), PE = 0

39.0625ps/DIV

05611-009

05611-044

150mV/DIV

39.0625ps/DIV

Figure 12. Eye Diagram over Backplane

(18

” FR4 + 2 GbX Connectors), PE = 1

150mV/DIV

Figure 13. Eye Diagram over Backplane

(30” FR4 + 2 GbX Connectors), PE = 2

39.0625ps/DIV

05611-012

05611-013

150mV/DIV

39.0625ps/DIV

Figure 11. Eye Diagram over Backplane

(36

” FR4 + 2 GbX Connectors), PE = 0

05611-011

150mV/DIV

39.0625ps/DIV

Figure 14. Eye Diagram over Backplane

(36

” FR4 + 2 GbX Connectors), PE = 3

Rev. A | Page 8 of 24

05611-014

ANALOG DEVICES AD8159 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS