ANALOG DEVICES AD8156 Service Manual
6.25 Gbps, 4 × 4,
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FEATURES
4 × 4, fully differential, nonblocking array
Configurable for dual 2 × 2 operation
DC to 6.25 Gbps per channel, NRZ data rate
Programmable input equalization compensates for over 40”
of FR-4 a
Multicast and broadcast modes of operation
Programmable output swing
100 mV p-p to 1.6 V p-p differential
Power supply: 3.3 V (±10%)
Low power
No EQ: 400 mW typical
Maximum EQ: 700 mW typical
Inputs: ac-coupled or dc-coupled
Wide set of dc-coupled input standards
3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL
Control: LVTTL- or LVCMOS-compatible
Low additive jitter: 25 ps p-p typical
Low random jitter: 0.8 ps rms
Integrated 50 Ω termination impedance at inputs/outputs
Individual output disable for power savings
49-ball, 8 mm × 8 mm BGA, 1 mm pitch
t 6.25 Gbps
Digital Crosspoint Switch with EQ
AD8156
FUNCTIONAL BLOCK DIAGRAM
IN0P/N
IN1P/N
IN2P/N
IN3P/N
CS
RST
UPD
WE
RE
MODE
D[3:0]
A[3:0]
INPUT
RECEIVE RS
CONTROL
4
4
LOGIC
INPUT
EQUALIZATION
EQ
EQ
EQ
EQ
Figure 1.
AD8156
4 × 4
SWITCH
OUTPUT
DRIVERS
OUT0P/N
OUT1P/N
OUT2P/N
OUT3P/N
06305-001
APPLICATIONS
Backplane equalization
SONET/SDH
Gigabit Ethernet
XAUI
Fibre Channel
GENERAL DESCRIPTION
The AD8156, a member of the Xstream line of products, is a
high speed, fully differential, digital crosspoint switch. The part
can function as a 4 × 4 crosspoint switch with double-latched
memory, allowing simultaneous updates, or as a dual 2 × 2 with
direct output control. The AD8156 has low power dissipation,
typically 700 mW on 3.3 V with all outputs and input equalizers
active. It operates at any data rate from dc to 6.25 Gbps per port.
Each input channel on the AD8156 has a programmable input
qualizer to compensate for signal loss over a backplane.
e
The AD8156 high speed inputs are compatible with both ac-
upled and dc-coupled 3.3 V, 2.5 V, or 1.8 V CML, as well as
co
3.3 V LVPECL data levels. The control interface is LVTTL- and
LVCMOS-compatible at 3.3 V. All input and output termination
resistors are integrated for ease of layout and to minimize
impedance mismatch. Input equalization and unused outputs
can be individually disabled to minimize power dissipation.
The AD8156 is packaged in a 49-ball, 8 mm × 8 mm, BGA
ackage with a 1 mm ball pitch. It operates over the industrial
p
temperature range of −40°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD8156
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Timing Specifications .................................................................. 4
Timing Diagrams.............................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Cir c ui t ...................................................................................... 12
Theory of Operation ...................................................................... 13
4 × 4 Mode................................................................................... 13
Dual 2 × 2 Mode......................................................................... 13
Input Equalization...................................................................... 14
Control Interface Description....................................................... 15
Control Pins................................................................................ 15
Address Pins, A[3:0] Inputs...................................................... 16
Data Pins, D[3:0] Inputs/Outputs............................................ 16
Control Interface Levels ............................................................ 16
Programming Examples ................................................................ 17
Dual 2 × 2 Mode (MODE Pin = 1)
Programming Examples............................................................ 17
4 × 4 Mode (MODE Pin = 0) Programming Examples ........ 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8156
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SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V
= V
TTI
V
= 1 V p-p differential, TA = 25°C, unless otherwise noted.
IN
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Data Rate NRZ data 6.25 Gbps
Deterministic Jitter Data date < 6.25 Gbps 25 ps p-p
Random Jitter 0.8 ps rms
Propagation Delay t
Propagation Delay Match 50 ps
Output Fall Time t
Output Rise Time tR Differential, 20% to 80% 75 ps
INPUT CHARACTERISTICS
Input Voltage Swing V
Input Voltage Range Single-ended VEE + 1.5 V
Input Voltage Range V
Input Termination R
OUTPUT CHARACTERISTICS
Output Voltage Swing V
Output Voltage Range Common-mode VEE + 1.6 V
Output Termination R
POWER SUPPLY
VCC Operating Range V
Supply Current I
I
I
I
I
Power Dissipation
All outputs on, no equalization 400 mW
All outputs and equalizers on 700 mW
THERMAL CHARACTERISTICS
Operating Temperature Range −40 85 °C
LOGIC INPUT CHARACTERISTICS VCC = 3.3 V dc
Input V
Input V
1
ICC supply current excludes input and output termination currents. Currents at V
output structure with separate termination supplies, all of the output and input current is drawn from V
2
Power dissipation includes power due to 800 mV p-p differential input and output voltages; this is the true representation of power dissipated on and used by the
chip at an 800 mV p-p differential signal level.
= VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223−1,
TTO
PD
F
IN
CM
IN
OUT
OUT
CC
1
CC
1
CC
1
CC
TTI
2
High 2.0 V
IN
Low 0 0.8 V
IN
TTO
All disabled 60 mW
Input to output 1000 ps
Differential, 20% to 80% 75 ps
Differential 200 2000 mV p-p
V
V
Common-mode VEE + 1.6 V
CC
CC
Single-ended 50 Ω
Differential, programmable 50 800 1850 mV p-p
CC
V
Single-ended 50 Ω
VEE = 0 V 3.0 3.3 3.6 V
All disabled 19 mA
All outputs on, no equalization 67 mA
All outputs and equalizers on 141 mA
800 mV differential swing 32 mA
800 mV differential swing 32 mA
V
and V
TTI
CC
count in power dissipation, but are not included in ICC. Note that in a CML
TTO
and the termination resistors, not from Vcc.
TTI
Rev. 0 | Page 3 of 20
AD8156
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TIMING SPECIFICATIONS
V
= V
TTI
V
= 1 V p-p differential, TA = 25°C, unless otherwise noted.
IN
Table 2.
Parameter Symbol Min Typ Max Unit
FIRST RANK WRITE CYCLE
CS to WE Setup Time
Address Setup Time t
Data Setup Time t
WE to CS Hold Time
Address Hold Time t
Data Hold Time t
WE Pulse Width
SECOND RANK UPDATE CYCLE
CS to UPD Setup Time
UPD to CS Hold Time
Output Enable t
Output Switch t
Output Disable t
UPD Pulse Width
TRANSPARENT WRITE AND UPDATE CYCLE
Output Enable t
Output Toggle t
Output Disable t
SECOND RANK READBACK CYCLE
CS to RE Setup Time
RE to CS Hold Time
ADDR from RE
DATA from RE
Access Time t
RE to Read Disable
ASYNCHRONOUS RESET
Output Disable t
RST Pulse Width
= VCC = 3.3 V, VEE = 0 V, RL = 50 Ω, differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223 − 1,
TTO
t
t
t
t
t
t
t
t
t
t
t
t
CSW
ASW
DSW
CHW
AHW
DHW
WP
CSU
CHU
UOE
UOT
UOD
UW
WOE
WOT
WOD
CSR
CHR
RHA
RDE
AA
RDD
TOD
TW
0 ns
0 ns
1 ns
0 ns
0 ns
0 ns
10 ns
0 ns
0 ns
20 ns
10 ns
20 ns
10 ns
35 50 ns
25 45 ns
25 45 ns
0 ns
0 ns
5 ns
15 ns
15 30 ns
50 ns
10 25 ns
10 ns
Rev. 0 | Page 4 of 20
AD8156
A
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TIMING DIAGRAMS
CS
WE
[3:0]
D[3:0]
t
CSW
t
ASW
t
DSW
t
WP
t
AHW
t
DHW
t
CHW
06305-002
Figure 2. First Rank Write Cycle
CS
UPD
OUTxN/P
ENABLE
OUTxN/P
DISABLE
OUTxN/P
TOGGLE
t
UOD
t
UOT
t
UW
t
CHU
06305-003
t
CSU
t
UOE
Figure 3. Second Rank Update Cycle
Rev. 0 | Page 5 of 20
AD8156
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CS
UPD
WE
OUTxN/P
ENABLE
OUTxN/P
DISABLE
OUTxN/P
TOGGLE
t
WOE
t
WOD
t
WOT
Figure 4. Transparent Write and Update Cycle
t
WHU
06305-004
CS
RE
ADDR[3:0]
DATA[3:0]
ADDR1 ADDR2
t
CSR
t
RDE
t
AA
DATA2DATA1
t
RHA
t
CHR
t
RDD
06305-005
Figure 5. Second Rank Readback Cycle
RST
OUTxN/P
DISABLE
t
TOD
t
TW
06305-006
Figure 6. Asynchronous Reset
Rev. 0 | Page 6 of 20
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