ANALOG DEVICES AD8153 Service Manual

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3.2 Gbps

FEATURES

Single lane 2:1 mux/1:2 demux

3.2 Gbps to dc data rates Compensates over 40 inches of FR4 at 3.2 Gbps through

Two levels of input equalization, or

Four levels of output pre-emphasis Operates with ac- or dc-coupled differential I/O Low deterministic jitter, typically 16 ps p-p Low random jitter, typically 500 fs rms On-chip terminations Unicast or bicast on 1:2 demux function Loopback capability on all ports

3.3 V core supply Flexible I/O supply Low power, typically 200 mW in basic configuration 32-lead LFCSP package

−40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch SONET OC48/SDH16 and lower data rates Gigabit Ethernet over backplane Fibre Channel 1.06 Gbps and 2.12 Gbps over backplane Serial RapidIO PCI Express Gen 1 Infiniband over backplane

1

Single Buffered Mux/Demux Switch

AD8153

FUNCTIONAL BLOCK DIAGRAM

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

EQ

CONTROL

LOGIC

OUTPUT C

INPUT C

SEL BICAST LB_A LB_B LB_C MODE RESETB EQ_A/(SCL) EQ_B/(SDA) EQ_C PE_A/(I2C_A[0]) PE_B/(I2C_A[1]) PE_C/(I2C_A[2])

INPUT A

INPUT B

OUTPUT A

OUTPUT B

RECEIVE

EQUALIZATION

EQ

TRANSMIT

PRE-EMPHASIS

2:1 MULTIPLEXER/

1:2 DEMULTIPLEXE R

AD8153

Figure 1.

06393-001

GENERAL DESCRIPTION

The AD8153 is an asynchronous, protocol agnostic, single-lane 2:1 switch with three differential CML inputs and three differential CML outputs. The AD8159, another member of the Xstream line of products, is suitable for similar applications that require more than one lane.

The AD8153 is optimized for NRZ signaling with data rates of up to 3.2 Gbps per port. Each port offers two levels of input equalization and four levels of output pre-emphasis.

The device consists of a 2:1 multiplexer and a 1:2 demultiplexer. There are three operating modes: pin mode, serial mode, and mixed mode. In pin mode, lane switching, equalization, and pre-emphasis are controlled exclusively using external pins. In serial mode, an I

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

2

C interface is used to control the device and to

provide access to advanced features, such as additional preemphasis settings and output disable. In mixed mode, the user

2

accesses the advanced features using I

C, but controls lane

switching using the external pins.

The main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. The device has unicast and bicast capability, so it is capable of supporting either 1 + 1 or 1:1 redundancy.

Using a mixture of bicast and loopback modes, the AD8153 can also be used to test high speed serial links by duplicating the incoming data and transmitting it to the destination port and test equipment simultaneously.

1

Two ports active with no pre-emphasis.

AD8153

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REVISION HISTORY

4/07—Revision 0: Initial Version.

Rev. 0 | Page 2 of 24

AD8153

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SPECIFICATIONS

VCC = V pattern, V

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Data Rate/Channel (NRZ) DC 3.2 Gbps Deterministic Jitter Data rate = 3.2 Gbps, high EQ 16 ps p-p Random Jitter RMS, high EQ 500 fs Propagation Delay Input to output 640 ps Lane-to-Lane Skew 55 ps Switching Time 5 ns Output Rise/Fall Time 20% to 80% 85 ps

INPUT CHARACTERISTICS

Input Voltage Swing Differential 200 2000 mV p-p Input Voltage Range Common mode, VID = 800 mV p-p VEE + 1.0 VCC + 0.3 V Input Capacitance 2 pF

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential, @ dc 700 800 900 mV p-p Output Voltage Range Single-ended absolute voltage level Vcc − 1.6 Vcc + 0.6 V Output Current No pre-emphasis 16 mA Output Current Maximum pre-emphasis, all ports 28 mA Output Capacitance 2 pF

TERMINATION CHARACTERISTICS

Resistance Differential 100 Ω Temperature Coefficient 0.1 Ω/°C

POWER SUPPLY

Operating Range

Supply Current

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C θJA Still air 30.0 °C/W

LOGIC INPUT CHARACTERISTICS

Input High (VIH) 2.4 VCC V Input Low (VIL) VEE 0.8 V

1

VID: Input differential voltage swing.

= V

TTI

V

CC

V

TTI

V

TTO

= 3.3 V, VEE = 0 V, RL = 50 Ω, two outputs active with no pre-emphasis, data rate = 3.2 Gbps, ac-coupled, PRBS7 test

TTO

= 800 mV p-p, TA = 25°C, unless otherwise noted.1

ID

VEE = 0 V 3.0 3.3 3.6 V

= 0 V VCC V

EE

= 0 V VCC V

EE

Two outputs active, no pre-emphasis, 400 mV I/O swings

I

CC

I

= I

+ I

I/O

TTO

TTI

(800 mV p-p differential)

Three outputs active, maximum pre-emphasis, 400 mV

I

CC

I

= I

+ I

I/O

TTO

TTI

I/O swings (800 mV p-p differential)

27 31 35 mA 26 32 39 mA

53 58 63 mA 74 84 95 mA

Rev. 0 | Page 3 of 24

AD8153

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I2C TIMING SPECIFICATIONS

SDA

t

BUF

SPSrS

06393-006

SCL

SU;STO

t

r

t

HD;STA

HIGH

t

f

Figure 2. I

t

SU;STA

2

C Timing Diagram

t

HD;DAT

SU;DAT

t

f

t

LOW

t

HD;STA

t

r

t

SP

t

Table 2.

Parameter Symbol Min Max Unit

SCL Clock Frequency f Hold Time for a Start Condition t Set-up Time for a Repeated Start Condition t Low Period of the SCL Clock t High Period of the SCL Clock t Data Hold Time t Data Set-Up Time t Rise Time for Both SDA and SCL t Fall Time for Both SDA and SCL t Set-Up Time for Stop Condition t Bus Free Time Between a Stop Condition and a Start Condition t Capacitance for Each I/O Pin C

0 400+ kHz

SCL

HD;STA

SU;STA

LOW

HIGH

HD;DAT

SU;DAT

r

f

SU;STO

BUF

i

0.6 – μs

1.3 – μs

0.6 – μs 0 – μs 10 – ns 1 300 ns 1 300 ns

0.6 – μs 1 – ns 5 7 pF

Rev. 0 | Page 4 of 24

AD8153

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating VCC to VEE 3.7 V V

V

TTI

V

TTO

Internal Power Dissipation Differential Input Voltage 2.0 V Logic Input Voltage V Storage Temperature Range Lead Temperature Junction Temperature

+ 0.6 V

CC

+ 0.6 V

CC

4.1 W

− 0.3V < V

EE

−65°C to +125°C 300°C 150°C

< VCC + 0.6 V

IN

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

AD8153

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

)

E_C/(I2C_A[2])

OPC

INC

PE_A/(I2C_A[0]

IPC

29

31

30

PIN 1 INDICATOR

AD8153

TOP VIEW

11

12

10

PB

VCC

O

ONB

ONC

PE_B/(I2C_A[1])

P

28

27

26

25

24 MODE 23 RESETB 22 SEL 21 BICAST 20 LB_A 19 LB_B 18 LB_C 17 EQ_A/(SCL )

15

16

14

13

IPB

INB

EQ_C

EQ_B/(SDA)

06393-002

VEE

32

1VCC 2VTTO 3ONA 4OPA 5VTTI 6INA 7IPA 8VEE

9

VCC

NOTE EPAD NEEDS TO BE ELECTRICALLY CONNECTED TO VEE.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

1, 9, 12 VCC Power Positive Supply. 2 VTTO Power Output Termination Supply. 3 ONA I/O High Speed Output Complement. 4 OPA I/O High Speed Output. 5 VTTI Power Input Termination Supply. 6 INA I/O High Speed Input Complement. 7 IPA I/O High Speed Input. 8, 32, EPAD VEE Power Negative Supply. 10 ONB I/O High Speed Output Complement. 11 OPB I/O High Speed Output. 13 INB I/O High Speed Input Complement. 14 IPB I/O High Speed Input. 15 EQ_C Control Port C Input Equalization Control. 16 EQ_B/(SDA) Control Port B Input Equalization Control/(I2C Data when MODE = 1). 17 EQ_A/(SCL) Control Port A Input Equalization Control/(I2C Clock when MODE = 1). 18 LB_C Control Port C Loopback Enable. 19 LB_B Control Port B Loopback Enable. 20 LB_A Control Port A Loopback Enable. 21 BICAST Control Bicast Enable. 22 SEL Control A/B Select. 23 RESETB Control Configuration Registers Reset. 24 MODE Control Configuration Mode. 1 for Serial/Mixed Mode, 0 for Pin Mode. 25 PE_C/(I2C_A[2]) Control Port C Pre-Emphasis Control/(I2C Slave Address Bit 2 when MODE = 1). 26 PE_B/(I2C_A[1]) Control Port B Pre-Emphasis Control/(I2C Slave Address Bit 1 when MODE = 1). 27 ONC I/O High Speed Output Complement. 28 OPC I/O High Speed Output. 29 PE_A/(I2C_A[0]) Control Port A Pre-Emphasis Control/(I2C Slave Address Bit 0 when MODE = 1). 30 INC I/O High Speed Input Complement. 31 IPC I/O High Speed Output.

Rev. 0 | Page 6 of 24

AD8153

V

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TYPICAL PERFORMANCE CHARACTERISTICS

VCC = V PRBS7 test pattern, V

TTI

= V

=3.3 V, VEE = 0 V, RL = 50 Ω, two outputs active with no pre-emphasis, high EQ, data rate = 3.2 Gbps, ac-coupled,

TTO

= 800 mV p-p, TA = 25°C, unless otherwise noted.

ID

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

Figure 4. Standard Test Circuit (No Channel)

INPUT PIN

AD8153

AC COUPLED EVALUATION

OUTPUT

BOARD

50Ω CABLES

2 2

50Ω

TP2TP1

OSCILLOSCOPE

HIGH-SPEED

SAMPLING

06393-014

150mV/DI

40ps/DIV

Figure 5. 3.2 Gbps Input Eye

(TP1 from

Figure 4)

06393-021

150mV/DI

40ps/DIV

Figure 6. 3.2 Gbps Output Eye, No Channel

(TP2 from

Figure 4)

06393-022

Rev. 0 | Page 7 of 24

AD8153

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DATA OUT

PATTERN

150mV/DI

40ps/DIV

REFERENCE EYE DI AGRAM AT TP1

150mV/DI

GENERATOR

40ps/DIV

Figure 8. 3.2 Gbps Input Eye, 20 Inch FR4 Input Channel

(TP2 from

Figure 7)

50Ω CABLES

2 2

FR4 TEST BACKPLANE

DIFFERENTIAL STRIPLINE TRACES

TP1

8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT

TRACE LENGT HS = 20 INCHES, 40 INCHES

Figure 7. Input Equalization Test Circuit

06393-024

50Ω CABLES

2 2

150mV/DI

TP2

INPUT

OUTPUT

AD8153

AC COUPLED EVALUATION

BOARD

50Ω CABLES

2 2

40ps/DIV

50Ω

TP3

SAMPLING

OSCILLOSCOPE

HIGH-

SPEED

Figure 10. 3.2 Gbps Output Eye, 20 Inch FR4 Input Channel, High EQ

(TP3 from

Figure 7)

06393-015

06393-026

150mV/DI

40ps/DIV

Figure 9. 3.2 Gbps Input Eye, 40 Inch FR4 Input Channel

(TP2 from

Figure 7)

06393-025

150mV/DI

Figure 11. 3.2 Gbps Output Eye, 40 Inch FR4 Input Channel, High EQ

(TP3 from

Rev. 0 | Page 8 of 24

40ps/DIV

Figure 7)

06393-027

ANALOG DEVICES AD8153 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

I2C TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS