ANALOG DEVICES AD 8137 YRZ Datasheet

Differential ADC Driver

AD8137

Rev. E

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the property of their res pective owners.

Fax: [phone] ©2004–2012 Analog Devices, Inc. All rights reserved.

04771-0-001

–IN

1

V

OCM

2

V

S+

3

+OUT

4

+IN

8

PD

7

V

S–

6

–OUT

5

AD8137

R

G

= 1kΩ

V

O, dm

= 0.1V p-p

FREQUENCY (MHz)

NORMALIZED CLOSED-LOOP GAIN (dB)

3
2
1

0

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0.1 1 10 100 1000

04771-0-002

G = 5

G = 10

G = 1

G = 2

Data Sheet

FEATURES

Fully differential
Extremely low power with power-down feature

2.6 mA quiescent supply current @ 5 V
450 µA in power-down mode @ 5 V

High speed

110 MHz large signal 3 dB bandwidth @ G = 1

450 V/µs slew rate
12-bit SFDR performance @ 500 kHz
Fast settling time: 100 ns to 0.02%
Low input offset voltage: ±2.6 mV max
Low input offset current: 0.45 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential

operation
Rail-to-rail output
Adjustable output common-mode voltage
Externally adjustable gain
Wide supply voltage range: 2.7 V to 12 V
Available in small SOIC package
Qualified for automotive applications

Low Cost, Low Power,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

ADC drivers
Automotive vision and safety systems
Automotive infotainment systems
Portable instrumentation
Battery-powered applications
Single-ended-to-differential converters
Differential active filters
Video amplifiers
Level shifters

GENERAL DESCRIPTON

The AD8137 is a low cost differential driver with a rail-to-rail
output that is ideal for driving ADCs in systems that are sensitive
to power and cost. The AD8137 is easy to apply, and its internal
common-mode feedback architecture allows its output common­mode voltage to be controlled by the voltage applied to one pin.
The internal feedback loop also provides inherently balanced
outputs as well as suppression of even-order harmonic distortion
products. Fully differential and single-ended-to-differential gain
configurations are easily realized by the AD8137. External
feedback networks consisting of four resistors determine the

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

closed-loop gain of the amplifier. The power-down feature is
beneficial in critical low power applications.

The AD8137 is manufactured on Analog Devices, Inc.,
proprietary second-generation XFCB process, enabling it to
achieve high levels of performance with very low power
consumption.

The AD8137 is available in the small 8-lead SOIC package and
3 mm × 3 mm LFCSP package. It is rated to operate over the
extended industrial temperature range of −40°C to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

Figure 2. Small Signal Response for Various Gains

AD8137 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Descripton .......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

Maximum Power Dissipation ..................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 11

REVISION HISTORY

7/12—Rev. D to Rev. E

Changes to Features Section and Applications Section ............... 1

Added AD8137W ............................................................... Universal

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 29

Added Automotive Products Section .......................................... 29

7/10—Rev. C to R e v. D

Changes to Power-Down Section, Added Figure 68,

Renumbered Subsequent Figures ................................................. 24

Changes to Ordering Guide .......................................................... 27

12/09—Rev. B to Rev. C

Changes to Product Title, Applications Section, and General

Description Section .......................................................................... 1

Changes to Input Resistance Parameter Unit, Table 3 ................. 5

Added EPAD Mnemonic/Description, Table 6 ............................ 7

Added Figure 61; Renumbered Sequentially .............................. 17

Moved Test Circuits Section .......................................................... 18

Changes to Power Down Section ................................................. 24

Updated Outline Dimensions ....................................................... 26

7/05—Rev. A to Rev. B

Changes to Ordering Guide .......................................................... 24

Test Circuits ..................................................................................... 21

Theory of Operation ...................................................................... 22

Applications Information .............................................................. 23

Analyzing a Typical Application with Matched RF and RG

Networks ...................................................................................... 23

Estimating Noise, Gain, and Bandwith with Matched

Feedback Networks .................................................................... 23

Driving an ADC with Greater than 12-Bit Performance ...... 27

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 30

Automotive Products ................................................................. 30

8/04—Rev. 0 to R e v. A.

Added 8-Lead LFCSP ......................................................... Universal

Changes to Layout .............................................................. Universal

Changes to Product Title and Figure 1 ........................................... 1

Changes to Specifications ................................................................. 3

Changes to Absolute Maximum Ratings ........................................ 6

Changes to Figure 4 and Figure 5 .................................................... 7

Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48,

and Figure 58; Renumbered Sequentially ...................................... 7

Changes to Figure 32 ...................................................................... 12

Changes to Figure 40 ...................................................................... 13

Changes to Figure 55 ...................................................................... 16

Changes to Table 7 and Figure 63................................................. 18

Changes to Equation 19 ................................................................. 19

Changes to Figure 64 and Figure 65............................................. 20

Changes to Figure 66 ...................................................................... 22

Added Driving an ADC with Greater Than 12-Bit

Performance Section ...................................................................... 22

Changes to Ordering Guide .......................................................... 24

Updated Outline Dimensions ....................................................... 24

5/04—Revision 0: Initial Version

Rev. E | Page 2 of 32

Data Sheet AD8137

Parameter

Conditions

Min

Typ

Max

Unit

DIFFERENTIAL INPUT PERFORMANCE

Dynamic Performance

V

= 2 V p-p, fC = 2 MHz

76 dB

Input Characteristics

Output Current

20 mA

V

to V

PERFORMANCE

V

Dynamic Performance

AD8137W only: T

−28 +28

mV

SPECIFICATIONS

VS = ±5 V, V

Table 1.

= 0 V (@ 25°C, differential gain = 1, R

OCM

= RF = RG = 1 kΩ, unless otherwise noted, T

L, dm

MIN

to T

= −40°C to +125°C).

MAX

−3 dB Small Signal Bandwidth V
AD8137W only: T

−3 dB Large Signal Bandwidth V
AD8137W only: T
Slew Rate V
Settling Time to 0.02% V
Overdrive Recovery Time G = 2, V

= 0.1 V p-p 64 76 MHz

O, dm

63 MHz

MIN-TMAX

= 2 V p-p 79 110 MHz

O, dm

79 MHz

MIN-TMAX

= 2 V step 450 V/µs

O, dm

= 3.5 V step 100 Ns

O, dm

= 12 V p-p triangle wave 85 Ns

I, dm

Noise/Harmonic Performance

SFDR V

= 2 V p-p, fC = 500 kHz 90 dB

O, dm

O, dm

Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz
Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz

DC Performance

Input Offset Voltage VIP = VIN = V
AD8137W only: T
Input Offset Voltage Drift T
Input Bias Current T

MIN

MIN

to T
to T

= 0 V −2.6 ±0.7 +2.6 mV

OCM

−5.0 +5.0 mV

MIN-TMAX

3 µV/°C

MAX

0.5 1.0 µA

MAX

Input Offset Current 0.1 0.45 µA
AD8137W only: T

0.45 µA

MIN-TMAX

Open-Loop Gain 91 dB

Input Common-Mode Voltage Range −4 +4 V
AD8137W only: T

−4 +4 V

MIN-TMAX

Input Resistance Differential 800 KΩ
Common-mode 400 KΩ
Input Capacitance Common-mode 1.8 pF
CMRR ΔV

AD8137W only: T

= ±1 V 66 79 dB

ICM

66 dB

MIN-TMAX

Output Characteristics

Output Voltage Swing Each single-ended output, R
AD8137W only: T

MIN-TMAX

= 1 kΩ VS− + 0.55 VS+ − 0.55 V

L, dm

VS− + 0.55 VS+ − 0.55 V

Output Balance Error f = 1 MHz −64 dB

OCM

O, cm

OCM

−3 dB Bandwidth V
Slew Rate V

Gain 0.992 1.000 1.008 V/V
AD8137W only: T
V

Input Characteristics

OCM

Input Voltage Range −4 +4 V

AD8137W only: T

Input Resistance 35 kΩ

Input Offset Voltage −28 ±11 +28 mV

Input Voltage Noise f = 100 kHz to 1 MHz 18 nV/√Hz

= 0.1 V p-p 58 MHz

O, cm

= 0.5 V p-p 63 V/µs

O, cm

0.990 1.008 V/V

MIN-TMAX

−4

MIN-TMAX

+4 V

MIN-TMAX

Rev. E | Page 3 of 32

AD8137 Data Sheet

Parameter

Conditions

Min

Typ

Max

Unit

AD8137W only: T

900

µA

Input Bias Current 0.3 1.1 µA
AD8137W only: T
CMRR ΔV

O, dm

/ΔV

OCM

, ΔV
AD8137W only: T
Power Supply

Operating Range +2.7 ±6 V
AD8137W only: T
Quiescent Current 3.2 3.60 mA
AD8137W only: T
Quiescent Current, Disabled Power-down = low 750 900 µA

PSRR ΔVS = ±1 V 79 91 dB
AD8137W only: T

PD Pin

Threshold Voltage VS− + 0.7 VS− + 1.7 V
AD8137W only: T
Input Current Power-down = high/low 150/210 170/240 µA
AD8137W only: T

OPERATING TEMPERATURE RANGE −40 +125 °C

1.1 µA

MIN-TMAX

= ±0.5 V 62 75 dB

OCM

62 dB

MIN-TMAX

+2.7 ±6 V

MIN-TMAX

3.65 mA

MIN-TMAX

MIN-TMAX

79 dB

MIN-TMAX

VS− + 0.7 VS− + 1.7 V

MIN-TMAX

180/245 µA

MIN-TMAX

Rev. E | Page 4 of 32

Data Sheet AD8137

AD8137W only: T

61

MHz

DC Performance

Input Resistance

Differential

800 kΩ

Output Voltage Swing

Each single-ended output, R

= 1 kΩ

VS− + 0.45

VS+ − 0.45

V

Gain

0.980

1.000

1.020

V/V

Input Offset Voltage

−25

±7.5

+25

mV

VS = 5 V, V

Table 2.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE

Dynamic Performance

−3 dB Small Signal Bandwidth V

−3 dB Large Signal Bandwidth V
AD8137W only: T
Slew Rate V
Settling Time to 0.02% V
Overdrive Recovery Time G = 2, V

Noise/Harmonic Performance

SFDR V
V
Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz
Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz

= 2.5 V (@ 25°C, differential gain = 1, R

OCM

= RF = RG = 1 kΩ, unless otherwise noted, T

L, dm

= 0.1 V p-p 63 75 MHz

O, dm

MIN-TMAX

= 2 V p-p 76 107 MHz

O, dm

76 MHz

MIN-TMAX

= 2 V step 375 V/µs

O, dm

= 3.5 V step 110 ns

O, dm

= 7 V p-p triangle wave 90 ns

I, dm

= 2 V p-p, fC = 500 kHz 89 dB

O, dm

= 2 V p-p, fC = 2 MHz 73 dB

O, dm

MIN

to T

= −40°C to +125°C).

MAX

Input Offset Voltage VIP = VIN = V
AD8137W only: T
Input Offset Voltage Drift T
Input Bias Current T

MIN

MIN

to T
to T

= 0 V −2.7 ±0.7 +2.7 mV

OCM

−5.0 +5.0 mV

MIN-TMAX

3 µV/°C

MAX

0.5 0.9 µA

MAX

Input Offset Current 0.1 0.45 µA
AD8137W only: T

0.45 µA

MIN-TMAX

Open-Loop Gain 89 dB

Input Characteristics

Input Common-Mode Voltage Range 1 4 V
AD8137W only: T

1 4 V

MIN-TMAX

Common-mode 400 kΩ
Input Capacitance Common-mode 1.8 pF
CMRR ΔV
AD8137W only: T

= ±1 V 64 90 dB

ICM

64 dB

MIN-TMAX

Output Characteristics

L, dm

AD8137W only: T

VS− + 0.45 VS+ − 0.45 V

MIN-TMAX

Output Current 20 mA
Output Balance Error f = 1 MHz −64 dB

V

to V

OCM

V

OCM

PERFORMANCE

O, cm

Dynamic Performance

−3 dB Bandwidth V
Slew Rate V

= 0.1 V p-p 60 MHz

O, cm

= 0.5 V p-p 61 V/µs

O, cm

AD8137W only: T

V

Input Characteristics

OCM

Input Voltage Range 1 4 V
AD8137W only: T
Input Resistance 35 kΩ

AD8137W only: T

0.975 1.020 V/V

MIN-TMAX

1 4 V

MIN-TMAX

−25 +25 mV

MIN-TMAX

Rev. E | Page 5 of 32

AD8137 Data Sheet

AD8137W only: T

62

dB

Quiescent Current, Disabled

Power-down = low

450

600

µA

Parameter Conditions Min Typ Max Unit

Input Voltage Noise f = 100 kHz to 5 MHz 18 nV/√Hz
Input Bias Current 0.25 0.9 µA
AD8137W only: T
CMRR ΔV

O, dm

/ΔV

OCM

, ΔV

Power Supply

Operating Range +2.7 ±6 V
AD8137W only: T
Quiescent Current 2.6 2.8 mA
AD8137W only: T

0.9 µA

MIN-TMAX

= ±0.5 V 62 75 dB

OCM

MIN-TMAX

+2.7 ±6 V

MIN-TMAX

2.8 mA

MIN-TMAX

AD8137W only: T

600 µA

MIN-TMAX

PSRR ΔVS = ±1 V 79 91 dB
AD8137W only: T

PD Pin

79 dB

MIN-TMAX

Threshold Voltage VS− + 0.7 VS− + 1.5 V
AD8137W only: T

VS− + 0.7 VS− + 1.5 V

MIN-TMAX

Input Current Power-down = high/low 50/110 60/120 µA
AD8137W only: T

60/125 µA

MIN-TMAX

OPERATING TEMPERATURE RANGE −40 +125 °C

Rev. E | Page 6 of 32

Data Sheet AD8137

AD8137W only: T

58

MHz

DC Performance

AD8137W only: T

0.4

µA

Input Resistance

Differential

800 kΩ

Output Voltage Swing

Each single-ended output, R

= 1 kΩ

VS− + 0.37

VS+ − 0.37

V

Gain

0.960

1.00

1.040

V/V

Input Offset Voltage

−25

±5.5

+25

mV

VS = 3 V, V

Table 3.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE

Dynamic Performance

−3 dB Small Signal Bandwidth V

−3 dB Large Signal Bandwidth V
AD8137W only: T
Slew Rate V
Settling Time to 0.02% V
Overdrive Recovery Time G = 2, V

Noise/Harmonic Performance

SFDR V
V
Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz
Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz

= 1.5 V (@ 25°C, differential gain = 1, R

OCM

= RF = RG = 1 kΩ, unless otherwise noted, T

L, dm

= 0.1 V p-p 61 73 MHz

O, dm

MIN-TMAX

= 2 V p-p 62 93 MHz

O, dm

62 MHz

MIN-TMAX

= 2 V step 340 V/µs

O, dm

= 3.5 V step 110 Ns

O, dm

= 5 V p-p triangle wave 100 Ns

I, dm

= 2 V p-p, fC = 500 kHz 89 dB

O, dm

= 2 V p-p, fC = 2 MHz 71 dB

O, dm

MIN

to T

= −40°C to +125°C).

MAX

Input Offset Voltage VIP = VIN = V
AD8137W only: T
Input Offset Voltage Drift T
Input Bias Current T

MIN

MIN

to T
to T

= 0 V −2.75 ±0.7 +2.75 mV

OCM

−5.25 +5.25 mV

MIN-TMAX

3 µV/°C

MAX

0.5 0.9 µA

MAX

Input Offset Current 0.1 0.4 µA

MIN-TMAX

Open-Loop Gain 87 dB

Input Characteristics

Input Common-Mode Voltage Range 1 2 V
AD8137W only: T

1 2 V

MIN-TMAX

Common-mode 400 kΩ
Input Capacitance Common-mode 1.8 pF
CMRR ΔV
AD8137W only: T

= ±1 V 64 80 dB

ICM

64 dB

MIN-TMAX

Output Characteristics

L, dm

AD8137W only: T

VS− + 0.37 VS+ − 0.37 V

MIN-TMAX

Output Current 20 mA
Output Balance Error f = 1 MHz −64 dB

V

to V

OCM

V

OCM

PERFORMANCE

O, cm

Dynamic Performance

−3 dB Bandwidth V
Slew Rate V

= 0.1 V p-p 61 MHz

O, cm

= 0.5 V p-p 59 V/µs

O, cm

AD8137W only: T

V

Input Characteristics

OCM

Input Voltage Range 1.0 2.0 V
AD8137W only: T
Input Resistance 35 kΩ

AD8137W only: T
Input Voltage Noise f = 100 kHz to 5 MHz 18 nV/√Hz
Input Bias Current 0.3 0.7 µA
AD8137W only: T

0.955 1.040 V/V

MIN-TMAX

1.0 2.0 V

MIN-TMAX

−25 +25 mV

MIN-TMAX

0.7 µA

MIN-TMAX

Rev. E | Page 7 of 32

AD8137 Data Sheet

AD8137W only: T

+2.7 ±6

V

AD8137W only: T

78

dB

Parameter Conditions Min Typ Max Unit

CMRR ΔV
AD8137W only: T

Power Supply

Operating Range +2.7 ±6 V

Quiescent Current 2.3 2.5 mA
AD8137W only: T
Quiescent Current, Disabled Power-down = low 345 460 µA
AD8137W only: T
PSRR ΔVS = ±1 V 78 90 dB

PD Pin

Threshold Voltage VS− + 0.7 VS− + 1.5 V
AD8137W only: T
Input Current Power-down = high/low 8/65 10/70 µA
AD8137W only: T

OPERATING TEMPERATURE RANGE −40 +125 °C

/ΔV

, ΔV

O, dm

OCM

= ±0.5 V 62 74 dB

OCM

62 dB

MIN-TMAX

MIN-TMAX

2.5 mA

MIN-TMAX

460 µA

MIN-TMAX

MIN-TMAX

VS− + 0.7 VS− + 1.5 V

MIN-TMAX

10/75 µA

MIN-TMAX

Rev. E | Page 8 of 32

Data Sheet AD8137

Junction Temperature

150°C

–40 –20–10–30 0 10 20 30 40 50 60 70 80 90 100110120

3.0

MAXIMUM POWER DISSIPATION (W)

1.0

1.5

0.5

2.0

2.5

0

AMBIENT TEMPERATURE (°C)

SOIC-8

LFCSP

04771-0-022

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 12 V
V

OCM

VS+ to VS−
Power Dissipation See Figure 3
Input Common-Mode Voltage VS+ to VS−
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I

). The load current consists of differential

S

and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.

Airflow reduces θ

. In addition, more metal directly in contact

JA

with the package leads from metal traces, through holes, ground,
and power planes reduces the θ

JA

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W) and 8-lead LFCSP (θ
standard 4-layer board. θ

values are approximations.

JA

) is the sum of the

D

) times the

S

.

= 70°C/W) on a JEDEC

JA

Table 5. Thermal Resistance

Package Type θJA θJC Unit

8-Lead SOIC/2-Layer 157 56 °C/W
8-Lead SOIC/4-Layer 125 56 °C/W
8-Lead LFCSP/4-Layer 70 56 °C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8137 package
is limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the AD8137. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices, potentially causing failure.

) on

J

Figure 3. Maximum Power Dissipation vs.

Ambient Temperature for a 4-Layer Board

ESD CAUTION

Rev. E | Page 9 of 32

AD8137 Data Sheet

04771-0-001

–IN

1

V

OCM

2

V

S+

3

+OUT

4

+IN

8

PD

7

V

S–

6

–OUT

5

AD8137

1

−IN

Inverting Input.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

2 V

OCM

An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to
the V

pin, provided the operation of the amplifier remains linear.

OCM

3 VS+ Positive Power Supply Voltage.
4 +OUT Positive Side of the Differential Output.
5 −OUT Negative Side of the Differential Output.
6 VS− Negative Power Supply Voltage.
7

PD

Power Down.

8 +IN Noninverting Input.
EPAD Exposed paddle may be connected to either ground plane or power plane.

Rev. E | Page 10 of 32

Data Sheet AD8137

R

G

= 1kΩ

V

O, dm

= 0.1V p-p

FREQUENCY (MHz)

NORMALIZED CLOSED-LOOP GAIN (dB)

3
2
1

0

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0.1 1 10 100 1000

04771-0-002

G = 5

G = 10

G = 1

G = 2

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

–12

1 10 100 1000

04771-0-003

VS = ±5

VS = +5

VS = +3

3
2
1

0

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

V

O, dm

= 0.1V p-p

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

3
2
1
0

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

1 10 100 1000

04771-0-006

V

O, dm

= 0.1V p-p

T = –40°C

T = +125°C

T = +85°C

T = +25°C

FREQUENCY (MHz)

NORMALIZED CLOSED-LOOP GAIN (dB)

3
2
1

0

–12

–11

–10

–9

–

8

–7

–6

–5

–4

–3

–2

–1

0.1 1 10 100 1000

04771-0-004

G = 10

G = 1

G = 2

G = 5

RG= 1kΩ
V

O, dm

= 2.0V p-p

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

4
3
2
1
0

–11

–

10

–9

–8

–7

–6

–5

–4

–3

–2

–1

1 10 100 1000

04771-0-005

V

O, dm

= 2.0V p-p

VS = ±5

VS = +5

V

S

= +3

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

4
3
2
1

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1 10 100 1000

04771-0-007

T = +85°C

T = +125°C

T = –40°C

T = +25°C

V

O, dm

= 2.0V p-p

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, differential gain = 1, RG = RF = R
Figure 60 for the definition of terms.

= 1 kΩ, VS = 5 V, TA = 25°C, V

L, dm

= 2.5V. Refer to the basic test circuit in

OCM

Figure 5. Small Signal Frequency Response for Various Gains

Figure 6. Small Signal Frequency Response for Various Power Supplies

Figure 8. Large Signal Frequency Response for Various Gains

Figure 9. Large Signal Frequency Response for Various Power Supplies

Figure 7. Small Signal Frequency Response at Various Temperatures

Figure 10. Large Signal Frequency Response at Various Temperatures

Rev. E | Page 11 of 32

AD8137 Data Sheet

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

3
2
1
0

–1

–3
–4

–2

–5
–6
–7
–8

–10
–11

–9

–

12

1 10 100 1000

04771-0-041

V

O, dm

= 0.1V p-p

R

L, dm

= 2kΩ

R

L, dm

= 1kΩ

R

L, dm

= 500Ω

1 10 100 1000

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

V

O, dm

= 0.1V p-p

3
2
1

0

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

04771-0-008

C

F

= 2pF

CF= 1pF

C

F

= 0pF

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

2
1

0
–1
–2

–4
–5

–3

–6
–7
–8
–9

–11
–12

–10

–13

1 10 100 1000

04771-0-042

V

O, dm

= 0.1V p-p

V

OCM

= 1V

V

OCM

= 4V

V

OCM

= 2.5V

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

3

2

1

0
–1

–3
–4

–2

–5
–6
–7
–8

–10
–11

–9

–12

1 10 100 1000

04771-0-043

V

O, dm

= 2V p-p

R

L, dm

= 2kΩ

R

L, dm

= 1kΩ

R

L, dm

= 500Ω

1 10 100 1000

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

V

O, dm

= 2.0V p-p

3
2
1

0

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

04771-0-009

CF= 2pF

CF= 1pF

C

F

= 0pF

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

3

2

1

0
–1

–3
–4

–2

–5
–6
–7
–8

–10
–11

–9

–12

1 10 100 1000

04771-0-044

2V p-p

0.5V p-p

0.1V p-p

1V p-p

Figure 11. Small Signal Frequency Response for Various Loads

Figure 12. Small Signal Frequency Response for Various C

F

Figure 14. Large Signal Frequency Response for Various Loads

Figure 15. Large Signal Frequency Response for Various C

F

Figure 13. Small Signal Frequency Response at Various V

OCM

Rev. E | Page 12 of 32

Figure 16. Frequency Response for Various Output Amplitudes

Data Sheet AD8137

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

4
3
2
1

–3

–2

–1

0

–7

–6

–5

–4

–11

–10

–9

–8

1 10 100

1000

04771-0-037

G = 1
V

S

= ±5V

V

O, dm

= 0.1V p-p

R

F

= 500Ω

R

F

= 2kΩ

RF = 1kΩ

FREQUENCY (MHz)

DISTORTION (dBc)

–65

–70

–80

–75

–85

–90

–95

–100

–105

0.1 1 10

04771-0-045

V

S

= ±5V

V

S

= +5V

V

S

= +3V

G = 1
V

O, dm

= 2V p-p

V

O, dm

(V p-p)

DISTORTION (dBc)

–50

–60

–65

–70

–55

–75

–80

–85

–90
–95

–100

0.25 1.25 2.25 3.25 4.25 5.25 7.25 8.256.25 9.25

04771-0-027

F

C

= 500kHz
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE

V

S

= +5V

VS = +5V

VS = +3V

V

S

= +3V

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

4
3
2
1

–3

–2

–1

0

–7

–6

–5

–4

–11

–10

–9

–8

1

10 100 1000

04771-0-036

G = 1
V

O, dm

= 2V p-p

R

F

= 500Ω

R

F

= 2kΩ

RF = 1kΩ

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–70

–60

–50

–80

–90

–

100

–110

0.1 1 10

04771-0-063

V

S

= ±5V

V

S

= +5V

V

S

= +3V

G = 1
V

O, dm

= 2V p-p

V

O, dm

(V p-p)

DISTORTION (dBc)

–50

–60

–65

–70

–55

–75

–80

–85

–90
–95

–100

0.25 1.25 2.25 3.25 4.25 5.25 7.25 8.256.25 9.25

04771-0-026

V

S

= +5V

V

S

= +5V

VS = +3V

VS = +3V

FC = 2MHz
SECOND HARMONICSOLID

LINE

THIRDHARMONIC DASHED LINE

Figure 17. Small Signal Frequency Response for Various R

F

Figure 18. Second Harmonic Distortion vs. Frequency and Supply Voltage

Figure 20. Large Signal Frequency Response for Various R

F

Figure 21. Third Harmonic Distortion vs. Frequency and Supply Voltage

Figure 19. Harmonic Distortion vs. Output Amplitude and Supply,

F

= 500 kHz

C

= 2 MHz

C

Figure 22. Harmonic Distortion vs. Output Amplitude and Supply, F

Rev. E | Page 13 of 32

AD8137 Data Sheet

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-032

V

O, dm

= 2V p-p

R

L, dm

= 200Ω

R

L, dm

= 1kΩ

R

L, dm

= 500Ω

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-034

G = 2

G = 5

G = 1

V

O, dm

= 2V p-p

R

G

= 1kΩ

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-030

V

O, dm

= 2V p-p

G = 1

R

F

= 500Ω

R

F

= 2kΩ

RF = 1kΩ

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-033

V

O, dm

= 2V p-p

R

L, dm

= 200Ω

R

L, dm

= 1kΩ

R

L, dm

= 500Ω

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-035

V

O, dm

= 2V p-p

R

G

= 1kΩ

G = 5

G = 1

G = 2

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

–110

0.1 1 10

04771-0-031

V

O, dm

= 2V p-p

G = 1

R

F

= 500Ω

R

F

= 2kΩ

RF = 1kΩ

Figure 23. Second Harmonic Distortion at Various Loads

Figure 24. Second Harmonic Distortion at Various Gains

Figure 26. Third Harmonic Distortion at Various Loads

Figure 27. Third Harmonic Distortion at Various Gains

Figure 25. Second Harmonic Distortion at Various RF

Rev. E | Page 14 of 32

Figure 28. Third Harmonic Distortion at Various RF

Data Sheet AD8137

V

OCM

(V)

DISTORTION (dBc)

–50

–60

–80

–70

–100

–90

–110

0.5 1.0 1.5 2.52.0 3.5 4.03.0 4.5

04771-0-028

FC = 500kHz
V

O, dm

= 2V p-p
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE

FREQUENCY (Hz)

INPUT VOLTAGE NOISE (nV/√Hz)

100

10

1

10 100 1k 10k 100k 1M 10M 100M

04771-0-046

FREQUENCY (MHz)

CMRR (dB)

20

–20

–10

0

10

–50

–30

–40

–70

–60

–80

1 10 100

04771-0-013

V

IN, cm

= 0.2V p-p

INPUT CMRR = ∆V

O, cm/

∆V

IN, cm

V

OCM

(V)

DISTORTION (dBc)

–50

–60

–70

–80

–90

–100

–110

0.5 0.7 0.9 1.31.1 1.5 1.7 2.32.11.9 2.5

04771-0-029

F

C

= 500kHz

V

O, dm

= 2V p-p
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE

FREQUENCY (Hz)

V

OCM

NOISE (nV/√Hz)

1000

100

10

1

10 100 1k 10k 100k 1M 10M 100M

04771-0-047

FREQUENCY (MHz)

V

OCM

CMRR (dB)

–10

–30

–20

–50

–40

–70

–60

–80

1 10 100

04771-0-012

V

O, cm

= 0.2V p-p

V

OCM

CMRR = ∆V

O, dm/∆VOCM

Figure 29. Harmonic Distortion vs. V

, VS = 5 V

OCM

Figure 30. Input Voltage Noise vs. Frequency

Figure 32. Harmonic Distortion vs. V

OCM

, VS = 3 V

Figure 33. V

Voltage Noise vs. Frequency

OCM

Figure 31. CMRR vs. Frequency

Figure 34. V

CMRR vs. Frequency

OCM

Rev. E | Page 15 of 32

AD8137 Data Sheet

TIME (ns)

VOLTAGE (V)

8

2

4

6

0

–4

–2

–6

–8

04771-0-016

250ns/DIV

INPUT

×

2

OUTPUT

G = 2

TIME (ns)

V

O, dm

(mV)

100

50

25

75

0

–25

–50

–75

–100

04771-0-015

10ns/DIV

V

O, dm

= 100mV p-p

CF = 0pF

C

F

= 1pF

TIME (ns)

V

O, dm

(V)

100

50

25

75

0

–50

–25

–75

–100

04771-0-039

20ns/DIV

RS = 111, CL= 5pF

RS = 60.4, C

L

= 15pF

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.5

1.0

04771-0-040

AMPLITUDE (V)

ERROR (V) 1DIV = 0.02%

C

F

= 0pF

V

O, dm

= 3.5V p-p

ERROR = V

O, dm

- INPUT

T

SETTLE

= 110ns

50ns/DIV

V

O, dm

INPUT

TIME (ns)

2V p-p

1V p-p

TIME (ns)

V

O, dm

(V)

1.5

1.0

–0.5

0

0.5

–1.0

–1.5

04771-0-014

C

F

= 0pF

C

F

= 1pF

C

F

= 0pF

C

F

= 1pF

20ns/DIV

TIME (ns)

V

O, dm

(V)

1.5

0.5

1.0

0

–0.5

–1.0

–1.5

04771-0-038

20ns/DIV

R

S

= 111, CL= 5pF

R

S

= 60.4, CL= 15pF

Figure 35. Overdrive Recovery

Figure 36. Small Signal Transient Response for Various Feedback

Capacitances

Figure 38. Settling Time (0.02%)

Figure 39. Large Signal Transient Response for Various Feedback

Capacitances

Figure 37. Small Signal Transient Response for Various Capacitive Loads

Figure 40. Large Signal Transient Response for Various Capacitive Loads

Rev. E | Page 16 of 32

Data Sheet AD8137

FREQUENCY (MHz)

PSRR (dB)

–5

–25

–35

–15

–45

–65

–55

–85

–75

0.1 1 10 100

04771-0-011

PSRR = ∆V

O, dm/∆VS

–PSRR

+PSRR

1 10 100 1000

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

V

O, dm

= 0.1V p-p

1
0

–1
–2

–14

–13

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

04771-0-010

VS = +3

V

S

= +5

V

S

= ±5

700

–700

–600

–500

–400

–300

–200

–100

0

100

200

300

400

500

600

200 1k 10k

04771-0-049

RESISTIVE LOAD (Ω)

SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)

VS+– V

OP

VON– V

S–

VS = +3V

V

S

= +5V

FREQUENCY (MHz)

OUTPUT IMPEDANCE (Ω)

1000

100

10

1

0.1

0.01

0.01 1001010.1

04771-0-061

TIME (ns)

V

O, cm

(V)

4.0

3.0

3.5

2.5

1.5

2.0

1.0

04771-0-050

20ns/DIV

2V p-p

1V p-p

320

350

–330

–325

–320

–315

–310

–305

–300

345

340

335

330

325

–40 –20 0 20 40 60 80 100 120

04771-0-065

TEMPERATURE (°C)

V

OP

SWING FROM RAIL (mV)

V

ON

SWING FROM RAIL (mV)

VON– VS–

VS+ – V

OP

Figure 42. V

Figure 41. PSRR vs. Frequency

Small Signal Frequency Response for Various Supply Voltages

OCM

Figure 44. Single-Ended Output Impedance vs. Frequency

Figure 45. V

Large Signal Transient Response

OCM

Figure 43. Output Saturation Voltage vs. Output Load

Figure 46. Output Saturation Voltage vs. Temperature

Rev. E | Page 17 of 32

AD8137 Data Sheet

–0.3

0.3

–15

10

5

0

5

10

15

0.2

0.1

0

–0.1

–0.2

–40 –20 0 20 40 60 80 100 120

04771-0-052

TEMPERATURE (°

C)

V

OS, dm

(mV)

V

OS, cm

(mV)

V

OS, cm

V

OS, dm

V

ACM

(V)

INPUT BIAS CURRENT (µA)

1.2

1.0

0.6

0.8

0.4

0.2

–0.2

0

–0.4

0.50 1.50 2.50 3.50 4.50

04771-0-059

0.10

0.40

–3

–2

–1

0

1

2

3

0.35

0.30

0.25

0.20

0.15

–40 –20 0 20 40 60 80 100 120

04771-0-053

TEMPERATURE (°C)

I

BIAS

(µA)

I

OS

(nA)

I

BIAS

I

OS

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

2.60

2.55

2.45

2.40

2.50

2.35

2.30
–40 0 20–20 40 80 10060 120

04771-0-051

V

OCM

(V)

I

V

OCM

(µA)

70�

50

30

10

–10

–30

–50

–70

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

4.0 4.5 5.0

04771-0-056

–0.5

–0.1

–0.2

–0.3

–0.4

–40 –20 0 20 40 60 80 100 120

04771-0-054

TEMPERATURE (°C)

V

OCM

CURRENT (µA)

Figure 47. Offset Voltage vs. Temperature

Figure 48. Input Bias Current vs. Input Common-Mode Voltage, V

ACM

Figure 50. Supply Current vs. Temperature

Figure 51. V

Bias Current vs. V

OCM

Input Voltage

OCM

Figure 49. Input Bias and Offset Current vs. Temperature

Rev. E | Page 18 of 32

Figure 52. V

Bias Current vs. Temperature

OCM

Data Sheet AD8137

V

OCM

V

O, cm

5

4

2

3

0

1

–1

–4

–3

–2

–5

–5 –4 –3 –2 –1 43210 5

04771-0-060

VS = +3V

V

S

= +5V

VS = ±5V

PD VOLTAGE (V)

PD CURRENT (µA)

40�

20

0

–20

–40

–60

–80

–100

–120

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

5.0

04771-0-057

PD VOLTAGE (V)

SUPPLY CURRENT (mA)

3

2

1

0

–1

–2

–3

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

04771-0-058

IS+

I

S

–

PD

–2.0V

–0.5V

V

O, dm

2µs/DIV

VS = ±

2.5V

G = 1 (R

F

= RG = 1kΩ)

R

L, dm

= 1kΩ

INPUT = 1Vp-p @ 1MHz

TIME (µs)

SUPPLY CURRENT (mA)

1.5

1.0

0.5

–0.5

0

–1.0

–1.5

04771-0-066

TIME (ns)

SUPPLY CURRENT (mA)

3.6

3.2

2.8

2.0

2.4

0.8

1.2

1.6

0.4

0

04771-0-024

100ns/DIV

PD (0.8V TO 1.5V)

TIME (ns)

SUPPLY CURRENT (mA)

3.4

3.0

2.6

2.2

1.8

1.4

1.0

0.6

0.2

04771-0-025

40ns/DIV

PD (1.5V TO 0.8V)

Figure 53. V

O, cm

vs. V

Input Voltage

OCM

Figure 56. Power-Down Transient Response

Figure 54. PD Current vs. PD Voltage

Figure 55. Supply Current vs. PD Voltage

Figure 57. Power-Down Turn-On Time

Figure 58. Power-Down Turn-Off Time

Rev. E | Page 19 of 32

AD8137 Data Sheet

04771-071

0

5

10

15

20

25

–5 –4 –3 –2 –1 0 1 2 3 4 5

SUPPLY CURRENT (mA)

POWER-DOWN VOLTAGE (V)

VS = ±5V
V

OCM

= 0V

G = +1

Figure 59. Supply Current vs. Power-Down Voltage

Rev. E | Page 20 of 32

Data Sheet AD8137

AD8137

+

–

52.3Ω

52.3Ω

R

L, dm

1kΩ V

O, dm

+

–

V

OCM

R

F

C

F

R

F

V

TEST

TEST
SIGNAL
SOURCE

50Ω

50Ω

04771-0-023

R

G

= 1kΩ

R

G

= 1kΩ

C

F

MIDSUPPLY

AD8137

+

–

52.3Ω

52.3Ω

R

L, dm

V

O, dm

+

–

R

F

= 1kΩ

R

F

= 1kΩ

R

S

R

S

V

TEST

TEST
SIGNAL
SOURCE

50Ω

50Ω

04771-0-062

C

L, dm

RG= 1kΩ

RG= 1kΩ

V

OCM

MIDSUPPLY

TEST CIRCUITS

Figure 60. Basic Test Circuit

Figure 61. Capacitive Load Test Circuit, G = 1

Rev. E | Page 21 of 32

AD8137 Data Sheet

–OUT +IN

A

CM

V

OCM

C

C

C

C

CP +OUT–IN CN

04771-0-017

C

m

C

g

BW×π=

2

FREQUENCY (MHz)

100

80

–60

–40

–20

0

20

40

60

–120

–100

–80

–200

–180

–160

–140

0.0001 0.010.001 0.1 1 10 100

04771-0-021

OPEN-LOOP GAIN (dB)

PHASE (DEGREES)

THEORY OF OPERATION

The AD8137 is a low power, low cost, fully differential voltage
feedback amplifier that features a rail-to-rail output stage,
common-mode circuitry with an internally derived common­mode reference voltage, and bias shutdown circuitry. The amplifier
uses two feedback loops to separately control differential and
common-mode feedback. The differential gain is set with external
resistors as in a traditional amplifier, and the output common­mode voltage is set by an internal feedback loop, controlled by
an external V
arbitrarily the output common-mode voltage level without
affecting the differential gain of the amplifier.

input. This architecture makes it easy to set

OCM

Figure 62. Block Diagram

From Figure 62, the input transconductance stage is an H-bridge
whose output current is mirrored to high impedance nodes CP
and CN. The output section is traditional H-bridge driven circuitry
with common emitter devices driving nodes +OUT and −OUT.
The 3 dB point of the amplifier is defined as

where:
gm is the transconductance of the input stage.

C

is the total capacitance on node CP/CN (capacitances CP

C

and CN are well matched).

For the AD8137, the input stage g
capacitance C

is 3.5 pF, setting the crossover frequency of the

C

is ~1 mA/V and the

m

amplifier at 41 MHz. This frequency generally establishes an
amplifier’s unity gain bandwidth, but with the AD8137, the
closed-loop bandwidth depends upon the feedback resistor
value as well (see Figure 17). The open-loop gain and phase
simulations are shown in Figure 63.

Rev. E | Page 22 of 32

Figure 63. Open-Loop Gain and Phase

In Figure 62, the common-mode feedback amplifier ACM
samples the output common-mode voltage, and by negative
feedback forces the output common-mode voltage to be equal
to the voltage applied to the V

input. In other words, the

OCM

feedback loop servos the output common-mode voltage to the
voltage applied to the V
sets the V

level to approximately midsupply; therefore, the

OCM

input. An internal bias generator

OCM

output common-mode voltage is set to approximately midsupply
when the V

input is left floating. The source resistance of the

OCM

internal bias generator is large and can be overridden easily by an
external voltage supplied by a source with a relatively small output
resistance. The V

input can be driven to within approximately

OCM

1 V of the supply rails while maintaining linear operation in the
common-mode feedback loop.

The common-mode feedback loop inside the AD8137 produces
outputs that are highly balanced over a wide frequency range
without the requirement of tightly matched external components,
because it forces the signal component of the output common­mode voltage to be zeroed. The result is nearly perfectly balanced
differential outputs of identical amplitude and exactly 180°
apart in phase.

Data Sheet AD8137

04771-0-055

+

–

V

AP

V

AN

V

ON

V

OP

–

+

V

O, dm

R

L, dm

AD8137

C

F

R

F

R

G

R

G

C

F

R

F

V

IP

V

OCM

V

IN

2

,

ONOP

cmO

VVV+

=

dmO

cmO

V

V

BalanceOutput

,

,

∆

∆

=

2

, dmO

OCMOP

V

VV +=

2

, dmO

OCMON

V

VV −=

APPLICATIONS INFORMATION

ANALYZING A TYPICAL APPLICATION WITH
MATCHED R

Typical Connection and Definition of Terms

Figure 64 shows a typical connection for the AD8137, using
matched external R
terminals of the AD8137, V
junctions. An external reference voltage applied to the V
terminal sets the output common-mode voltage. The two
output terminals, V
in a balanced fashion in response to an input signal.

The differential output voltage is defined as

V

O, dm

Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as

Output Balance

Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feedback
loop that forces the signal component of the output common­mode toward zero, resulting in the near perfectly balanced
differential outputs of identical amplitude and are exactly 180°
out of phase. The output balance performance does not require
tightly matched external components, nor does it require that
the feedback factors of each loop be equal to each other. Low
frequency output balance is ultimately limited by the mismatch
of an on-chip voltage divider.

AND RG NETWORKS

F

networks. The differential input

F/RG

and VAN, are used as summing

AP

OCM

and VON, move in opposite directions

OP

Figure 64. Typical Connection

= VOP − VON (1)

(2)

Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential
mode voltage:

(3)

The differential negative feedback drives the voltages at the summing
junctions V

V

and VAP to be essentially equal to each other.

AN

= VAP (4)

AN

The common-mode feedback loop drives the output common­mode voltage, sampled at the midpoint of the two internal
common-mode tap resistors in Figure 62, to equal the voltage
set at the V

terminal. This ensures that

OCM

(5)

and

(6)

ESTIMATING NOISE, GAIN, AND BANDWITH WITH MATCHED FEEDBACK NETWORKS

Estimating Output Noise Voltage and Bandwidth

The total output noise is the root-sum-squared total of several
statistically independent sources. Because the sources are
statistically independent, the contributions of each must be
individually included in the root-sum-square calculation. Tab le 7
lists recommended resistor values and estimates of bandwidth
and output differential voltage noise for various closed-loop
gains. For most applications, 1% resistors are sufficient.

Table 7. Recommended Values of Gain-Setting Resistors and
Voltage Gain for Various Closed-Loop Gains

3 dB Bandwidth

Gain RG (Ω) RF (Ω)

(MHz)

1 1 k 1 k 72 18.6
2 1 k 2 k 40 28.9
5 1 k 5 k 12 60.1
10 1 k 10 k 6 112.0

Total Output
Noise (nV/√Hz)

Rev. E | Page 23 of 32

AD8137 Data Sheet











+=

G

F

n

R

R

vVo_n 11

( )

F

n

RiVo_n =2











=

G

F

G

R

R

TRVo_n k43

F

TRVo_n k44 =

F

ONAP

G

AP

IP

R

VV

R

VV −

=

−










+

==

G

F

G

OPAPAN

RR

R

VVV

i

G

F

dmO,

ONOP

V

R

R

VVV ==−

G

F

G

RRR+

≡β

( )















×

+

+















+

×

+

OCM

G

F

GINIP

G

F

F

V

RR

R

VV

RR

R

2

2

INIP

ICM

VVV+

≡

)(2

1

F

G

F

G

IN

RR

R

R

R

+

−

=

The differential output voltage noise contains contributions
from the AD8137’s input voltage noise and input current noise
as well as those from the external feedback networks.

The contribution from the input voltage noise spectral density
is computed as

Feedback Factor Notation

When working with differential drivers, it is convenient to
introduce the feedback factor β, which is defined as

(14)

, or equivalently, vn/β (7)

where v

is defined as the input-referred differential voltage

n

noise. This equation is the same as that of traditional op amps.

The contribution from the input current noise of each input is
computed as

(8)

where i

is defined as the input noise current of one input. Each

n

input needs to be treated separately because the two input currents
are statistically independent processes.

The contribution from each R

is computed as

G

(9)

This result can be intuitively viewed as the thermal noise of
each R

multiplied by the magnitude of the differential gain.

G

The contribution from each R

is computed as

F

(10)

Voltage Gain

The behavior of the node voltages of the single-ended-to­differential output topology can be deduced from the signal
definitions and Figure 64. Referring to Figure 64, C
setting V

= 0, one can write:

IN

= 0 and

F

(11)

(12)

Solving the previous two equations and setting V
the gain relationship for V

O, dm/Vi

.

to Vi gives

IP

(13)

An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to V
setting V
V

IN, dm

= 0. For a balanced differential input, the gain from

IP

to V

is also equal to RF/RG, where V

O, dm

= VIP − VIN.

IN, dm

IN

and

This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.

Input Common-Mode Voltage

The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Because V

and VAP are

AN

essentially equal to each other, they are both equal to the amplifier’s
input common-mode voltage. Their range is indicated in the
specifications tables as input common-mode range. The voltage
at V

and VAP for the connection diagram in Figure 64 can be

AN

expressed as

V

= VAP = V

AN

ACM

=

(15)

where V

is the common-mode voltage present at the amplifier

ACM

input terminals.

Using the β notation, Equation (15) can be written as

= βV

V

ACM

+ (1 − β)V

OCM

(16)

ICM

or equivalently,

= V

V

where V

ACM

ICM

+ β(V

ICM

is the common-mode voltage of the input signal,

OCM

− V

) (17)

ICM

that is

For proper operation, the voltages at V

and VAP must stay

AN

within their respective linear ranges.

Calculating Input Impedance

The input impedance of the circuit in Figure 64 depends on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input
signals, the differential input impedance (R

= 2RG (18)

R

IN, dm

For a single-ended signal (for example, when V
and the input signal drives V

), the input impedance becomes

IP

) is simply

IN, dm

IN

is grounded

(19)

Rev. E | Page 24 of 32

Data Sheet AD8137

04771-0-018

GND

V

REF

V

REFA

ADR525A

2.5V SHUNT

REFERENCE

AD7450A

VIN+

V

IN

–

VDD

AD8137

+

–

8

V

REFB

2.5V

2
1

6

3

4

5

V

OCM

1kΩ

1kΩ 1kΩ

2.5kΩ

1kΩ

5V

50Ω

50Ω

V

IN

1.0nF

1.0nF

0.1µF

0.1µF

+1.88V
+1.25VV

ACM WITH

V

REFB

= 0

+0.63V

+2.5V
GND
–2.5V

04771-0-019

V

IN

0V TO 5V

AD8137

+

–

8
2
1

6

3

4

5

V

OCM

1kΩ

1kΩ

5V

1kΩ 1kΩ

10kΩ

0.1µF

0.1µF

0.1µF

10µF

+

AD8031

+

–

0.1µF

5V

ADR525A

2.5V SHUNT

REFERENCE

TO
AD7450A
V

REF

)MHz72(,

3

×

+

=

−

F

G

G

dmO,dB

RR

R

Vf

Figure 65. AD8137 Driving AD7450A, 12-Bit ADC

The input impedance of a conventional inverting op amp
configuration is simply R

; however, it is higher in Equation 19

G

because a fraction of the differential output voltage appears at
the summing junctions, V
bootstraps the voltage across the input resistor R

and VAP. This voltage partially

AN

, leading to

G

the increased input resistance.

Input Common-Mode Swing Considerations

In some single-ended-to-differential applications, when using a
single-supply voltage, attention must be paid to the swing of the
input common-mode voltage, V

Consider the case in Figure 65, where V
about a baseline at ground and V

.

ACM

is 5 V p-p swinging

IN

is connected to ground.

REFB

The input signal to the AD8137 is originating from a source
with a very low output resistance.

The circuit has a differential gain of 1.0 and β = 0.5. V
amplitude of 2.5 V p-p and is swinging about ground. Using the
results in Equation 16, the common-mode voltage at the inputs of
the AD8137, V

, is a 1.25 V p-p signal swinging about a baseline

ACM

of 1.25 V. The maximum negative excursion of V

0.63 V, which exceeds the lower input common-mode voltage limit.

One way to avoid the input common-mode swing limitation is
to bias V
swinging about a baseline at 2.5 V, and V
low-Z 2.5 V source. V

and V

IN

at midsupply. In this case, VIN is 5 V p-p

REF

is connected to a

REF

now has an amplitude of 2.5 V p-p and

ICM

is swinging about 2.5 V. Using the results in Equation 17, V
is calculated to be equal to V
V

ICM

common-mode voltage limits of the AD8137. Another benefit
seen by this example is that because V
wasted common-mode current flows. Figure 66 illustrates a way
to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.

swings from 1.25 V to 3.75 V, which is well within the input

because V

ICM

OCM

OCM

= V

ICM

in this case is

ACM

= V

. Therefore,

ICM

= V

ACM

has an

ACM

, no

ICM

Rev. E | Page 25 of 32

Figure 66. Low-Z Bias Source

Another way to avoid the input common-mode swing limitation
is to use dual power supplies on the AD8137. In this case, the
biasing circuitry is not required.

Bandwidth vs. Closed-Loop Gain

The 3 dB bandwidth of the AD8137 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can
be estimated as

(20)

or equivalently, β(72 MHz).

This estimate assumes a minimum 90° phase margin for the
amplifier loop, a condition approached for gains greater than 4.
Lower gains show more bandwidth than predicted by the equation
due to the peaking produced by the lower phase margin.

AD8137 Data Sheet











+

=

G

G

F

IO

R

RR

VVo_e

1

( )

F

IO

G

F

F

G

G

G

F

IO

RI

RR

RR

R

RR

IVo_e =











+











+

=2

Estimating DC Errors

Primary differential output offset errors in the AD8137 are due
to three major components: the input offset voltage, the offset
between the V

and VAP input currents interacting with the

AN

feedback network resistances, and the offset produced by the
dc voltage difference between the input and output common­mode voltages in conjunction with matching errors in the
feedback network.

The first output error component is calculated as

, or equivalently as VIO/β (21)

where V

is the input offset voltage.

IO

The second error is calculated as

(22)

where I

is defined as the offset between the two input bias

IO

currents.

The third error voltage is calculated as

− V

Vo_e3 = Δenr × (V

ICM

) (23)

OCM

where Δenr is the fractional mismatch between the two feedback
resistors.

The total differential offset error is the sum of these three error
sources.

Additional Impact of Mismatches in the Feedback Networks

The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the R

F/RG

feed­back networks are mismatched. The mismatch, however, causes
a gain error proportional to the feedback network mismatch.

Ratio-matching errors in the external resistors degrade the
ability to reject common-mode signals at the V

and VIN input

AN

terminals, similar to a four resistor, difference amplifier made
from a conventional op amp. Ratio-matching errors also produce a
differential output component that is equal to the V

OCM

input
voltage times the difference between the feedback factors (βs).
In most applications using 1% resistors, this component amounts
to a differential dc offset at the output that is small enough to
be ignored.

Driving a Capacitive Load

A purely capacitive load reacts with the bondwire and pin
inductance of the AD8137, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance. The resistor and load
capacitance forms a first-order, low-pass filter; therefore, the
resistor value should be as small as possible. In some cases, the
ADCs require small series resistors to be added on their inputs.

Figure 37 and Figure 40 illustrate transient response vs. capacitive
load and were generated using series resistors in each output
and a differential capacitive load.

Layout Considerations

Standard high speed PCB layout practices should be adhered
to when designing with the AD8137. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.

To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to
the summing nodes should be removed. Small amounts of stray
summing-node capacitance cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.

Terminating a Single-Ended Input

Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line
termination. In analog applications, a matched resistive termination
is generally placed at the load end of the line. This section deals
with how to properly terminate a single-ended input to the AD8137.

The input resistance presented by the AD8137 input circuitry
is seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and is easier,
especially considering the fact that standard resistor values are
generally used.

Rev. E | Page 26 of 32

Data Sheet AD8137

AD8137

+

–

8
2
1

6

3

4

0V

2V p-p

R

T

52.3Ω

5

+

–

V

OCM

1kΩ

1.02kΩ
1kΩ

1kΩ

0.1µF

0.1µF

+5V

–5V

V

IN

SIGNAL
SOURCE

50Ω

04771-0-020

50kΩ

5kΩ

150kΩ

REF APD

–V

S

+V

S

+V

S

Q1 Q2

04771-072

Figure 67 shows the AD8137 in a unity-gain configuration, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.

Figure 67. AD8137 with Terminated Input

The 52.3 Ω termination resistor, RT, in parallel with the 1 kΩ
input resistance of the AD8137 circuit, yields an overall input
resistance of 50 Ω that is seen by the signal source. To have
matched feedback loops, each loop must have the same R
has the same R

. In the input (upper) loop, RG is equal to the 1 kΩ

F

if it

G

resistor in series with the (+) input plus the parallel combination
of R

and the source resistance of 50 Ω. In the upper loop, RG is

T

therefore equal to 1.03 kΩ. The closest standard value is 1.02 kΩ
and is used for R

in the lower loop.

G

Things become more complicated when it comes to determining
the feedback resistor values. The amplitude of the signal source
generator V

is two times the amplitude of its output signal when

IN

terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude
is produced by a 4 V p-p amplitude from V
equivalent circuit of the signal source and R
calculating the closed-loop gain because R

. The Thevenin

S

must be used when

T

in the upper loop is

G

split between the 1 kΩ resistor and the Thevenin resistance
looking back toward the source. The Thevenin voltage of the
signal source is greater than the signal source output voltage
when terminated in 50 Ω because R
than 50 Ω. In this case, R

is 52.3 Ω and the Thevenin voltage

T

must always be greater

T

and resistance are 2.04 V p-p and 25.6 Ω, respectively.

Now the upper input branch can be viewed as a 2.04 V p-p
source in series with 1.03 kΩ. Because this is to be a unity-gain
application, a 2 V p-p differential output is required, and R

F

must therefore be 1.03 kΩ × (2/2.04) = 1.01 kΩ ≈ 1 kΩ.

This example shows that when R
the gain reduction produced by the increase in R
cancelled by the increase in the Thevenin voltage caused by R

and RG are large compared to RT,

F

is essentially

G

T

being greater than the output resistance of the signal source. In
general, as R
R

needs to be increased to compensate for the increase in RG.

F

When generating the typical performance characteristics data,
the measurements were calibrated to take the effects of the
terminations on closed-loop gain into account.

and RG become smaller in terminated applications,

F

Rev. E | Page 27 of 32

Power-Down

The AD8137 features a PD pin that can be used to minimize the
quiescent current consumed when the device is not being used.
PD

is asserted by applying a low logic level to Pin 7. The threshold
between high and low logic levels is nominally 1.1 V above the
negative supply rail. See

The AD8137

PD

enables the amplifier for normal operation. The AD8137

Tabl e 1 to Table 3 for the threshold limits.

pin features an internal pull-up network that

PD

pin can be left floating (that is, no external connection is
required) and does not require an external pull-up resistor to
ensure normal on operation (see Figure 68).

Do not connect the

PD

pin directly to VS+ in ±5 V applications.
This can cause the amplifier to draw excessive supply current
(see Figure 59) and may induce oscillations and/or stability
issues.

PD

Figure 68.

Pin Circuit

DRIVING AN ADC WITH GREATER THAN 12-BIT PERFORMANCE

Because the AD8137 is suitable for 12-bit systems, it is desirable
to measure the performance of the amplifier in a system with
greater than 12-bit linearity. In particular, the effective number
of bits (ENOB) is most interesting. The AD7687, 16-bit, 250 KSPS
ADC performance makes it an ideal candidate for showcasing
the 12-bit performance of the AD8137.

For this application, the AD8137 is set in a gain of 2 and driven
single-ended through a 20 kHz band-pass filter, while the output
is taken differentially to the input of the AD7687 (see Figure 69).
This circuit has mismatched R
dc offset at the differential output. It is included as a test circuit to
illustrate the performance of the AD8137. Actual application
circuits should have matched feedback networks.

For an AD7687 input range up to −1.82 dBFS, the AD8137 power
supply is a single 5 V applied to V
increase the AD7687 input range to −0.45 dBFS, the AD8137
supplies are increased to +6 V and −1 V. In both cases, the V
pin is biased with 2.5 V and the
supplies are decoupled with 0.1 µF capacitors. Figure 70 and
Figure 71 show the performance of the −1.82 dBFS setup and the

−0.45 dBFS setup, respectively.

impedances and, therefore, has a

G

with VS− tied to ground. To

S+

OCM

PD

pin is left floating. All voltage

AD8137 Data Sheet

AD8137

+

–

1nF

1nF

V

OCM

V

S

–

V

S

+

V+

1.0kΩ

1.0kΩ

20kHz

33Ω

33Ω

04771-0-067

499Ω

499Ω

+2.5

AD7687

GND

V

DD

V

IN

GND

BPF

FREQUENCY (kHz)

AMPLITUDE (dB OF FULL SCALE)

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130
–140
–150
–160

–170

0 4020 60 12010080 140

04771-0-068

THD = –93.63dBc
SNR = 91.10dB
SINAD = 89.74dB
ENOB = 14.6

FREQUENCY (kHz)

AMPLITUDE (dB OF FULL SCALE)

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130

–140
–150

–160

0 4020 60 12010080 140

04771-0-069

THD = –91.75dBc
SNR = 91.35dB
SINAD = 88.75dB
ENOB = 14.4

Figure 69. AD8137 Driving AD7687, 16-Bit 250 KSPS ADC

Figure 70. AD8137 Performance on Single 5 V Supply, −1.82 dBFS

Figure 71. AD8137 Performance on +6 V, −1 V Supplies, −0.45 dBFS

Rev. E | Page 28 of 32

Data Sheet AD8137

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

012407-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

45°

8°
0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

4

1

8 5

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)
BSC

6.20 (0.2441)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

TOP VIEW

8

1

5

4

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.55

1.45

1.35

1.84

1.74

1.64

0.203 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.50

0.40

0.30

COMPLIANT

TO

JEDEC STANDARDS MO-229-WEED

12-07-2010-A

PIN 1
INDICATOR
(R 0.15)

OUTLINE DIMENSIONS

Figure 72. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-13)

Dimensions shown in millimeters

Rev. E | Page 29 of 32

AD8137 Data Sheet

AD8137YCPZ-R2

–40°C to +125°C

8-Lead Lead Frame Chip Scale Package (LFCSP_WD)

CP-8-13

HFB#

ORDERING GUIDE

1, 2

Model

AD8137YR −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8137YR-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8137YRZ −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8137YRZ-REEL −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
AD8137YRZ-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8

AD8137YCPZ-REEL –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 HFB#
AD8137YCPZ-REEL7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 HFB#
AD8137WYCPZ-R7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 H2G
AD8137YCP-EBZ LFCSP Evaluation Board
AD8137YR-EBZ SOIC Evaluation Board

1

Z = RoHS Compliant Part; # denotes that RoHS part may be top or bottom marked.

2

W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD8137W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.

Temperature Range Package Description Package Option Branding

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Data Sheet AD8137

NOTES

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AD8137 Data Sheet

©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D04771-0-7/12(E)

Rev. E | Page 32 of 32