Datasheet AD8129 Datasheet (Analog Devices)

Low Cost 270 MHz

AD8129/

AD8130

1

2

3

4

+IN

–IN

–V

S

+V

S

PD

OUT

REF

FB

8

7

6

5

+

a

Differential Receiver Amplifiers

AD8129/AD8130

FEATURES High Speed

AD8130: 270 MHz, 1090 V/s @ G = 1 AD8129: 200 MHz, 1060 V/s @ G = 10

High CMRR

94 dB Min, DC to 100 kHz 80 dB Min @ 2 MHz

70 dB @ 10 MHz High Input Impedance: 1 M Differential Input Common-Mode Range 10.5 V Low Noise

AD8130: 12.5 nV/√Hz

AD8129: 4.5 nV/√Hz Low Distortion, 1 V p-p @ 5 MHz:

AD8130, –79 dBc Worst Harmonic @ 5 MHz

AD8129, –74 dBc Worst Harmonic @ 5 MHz User-Adjustable Gain

No External Components for G = 1 Power Supply Range +4.5 V to 12.6 V Power-Down

APPLICATIONS High Speed Differential Line Receiver Differential-to-Single-Ended Converter High Speed Instrumentation Amp Level-Shifting

data transmission. The AD8129 and AD8130 are differentialto-single-ended amplifiers with extremely high CMRR at high frequency. Therefore, they can also be effectively used as high-speed instrumentation amps or for converting differential signals to single-ended signals.

The AD8129 is a low noise, high gain (10 or greater) version intended for applications over very long cables where signal attenuation is significant. The AD8130 is stable at a gain of one and can be used for those applications where lower gains are required. Both have user adjustable gain to help compensate for losses in the transmission line. The gain is set by the ratio of two resistor values. The AD8129 and AD8130 have very high input impedance on both inputs regardless of the gain setting.

The AD8129 and AD8130 have excellent common-mode rejec-

GENERAL DESCRIPTION

The AD8129 and AD8130 are designed as receivers for the transmission of high-speed signals over twisted-pair cables to work with the AD8131 or AD8132 drivers. Either can be used for analog or digital video signals and for high-speed

120

110

100

90

80

70

CMRR – dB

60

50

40

30

10k 100k 1M 10M 100M

FREQUENCY – Hz

tion (70 dB @ 10 MHz) allowing the use of low cost unshielded twisted-pair cables without fear of corruption by external noise sources or crosstalk.

The AD8129 and AD8130 have a wide power supply range from single 5 V supply to ±12 V, allowing wide common-mode and differential-mode voltage ranges while maintaining signal integrity. The wide common-mode voltage range will enable the driver receiver pair to operate without isolation transformers in many systems where the ground potential difference between drive and receive locations is many volts. The AD8129 and AD8130 have considerable cost and performance improvements over op amps and other multi-amplifier receiving solutions.

Figure 1. AD8129 CMRR vs. Frequency

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 2. Typical Connection Configuration

CONNECTION DIAGRAM

(Top View)

SO-8 (R) and Micro_SO-8 (RM)

+V

S

V

R

F

–V

S

V

IN

R

G

V

= VIN [1+(RF/RG)]

OUT

PD

OUT

AD8129/AD8130–SPECIFICATIONS

5 V SPECIFICATIONS

otherwise noted. T

MIN

to T

= –40C to +85C, unless otherwise noted.)

MAX

(AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 5 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF, unless

Model AD8129A AD8130A Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth V

Bandwidth for 0.1 dB Flatness V Slew Rate V Settling Time V Rise and Fall Time V Output Overdrive Recovery 30 40 ns

≤ 0.3 V p-p 175 200 240 270 MHz

OUT

V

= 2 V p-p 170 190 140 155 MHz

OUT

≤ 0.3 V p-p, SOIC/µSOIC 30/50 45 MHz

OUT

= 2 V p-p, 25% to 75% 925 1060 950 1090 V/µs

OUT

= 2 V p-p, 0.1% 20 20 ns

OUT

≤ 1 V p-p, 10% to 90% 1.7 1.4 ns

OUT

NOISE/DISTORTION

Second Harmonic/Third Harmonic V

IMD V Output IP3 V Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.5 nV/√Hz

= 1 V p-p, 5 MHz –74/–84 –79/–86 dBc

OUT

V

= 2 V p-p, 5 MHz –68/–74 –74/–81 dBc

OUT

V

= 1 V p-p, 10 MHz –67/–81 –74/–80 dBc

OUT

V

= 1 V p-p, 10 MHz –61/–70 –74/–76 dBc

OUT

= 2 V p-p, 10 MHz –67 –70 dBc

OUT

= 2 V p-p, 10 MHz 25 26 dBm

OUT

Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz Differential Gain Error AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω 0.3 0.13 % Differential Phase Error AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω 0.1 0.15 Degrees

INPUT CHARACTERISTICS

Common-Mode Rejection Ratio DC to 100 kHz, VCM = –3 V to +3.5 V 94 110 90 110 dB

VCM = 1 V p-p @ 2 MHz 80 80 dB

VCM = 1 V p-p @ 10 MHz 70 70 dB CMRR with V Common-Mode Voltage Range V Differential Operating Range ±0.5 ±2.5 V

= 1 V p-p VCM = 2 V p-p @ 1 kHz, V

OUT

– V

= 0 V ±3.5 ±3.8 V

+IN

–IN

= ±0.5 V dc 100 83 dB

OUT

Differential Clipping Level ±0.6 ± 0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ

Common-Mode 4 4 MΩ Capacitance Differential 3 3 pF

Common-Mode 4 4 pF

DC PERFORMANCE

Closed-Loop Gain Error V

Open-Loop Gain V Gain Nonlinearity V Input Offset Voltage 0.2 0.8 0.4 1.8 mV

Input Offset Voltage vs. Supply +VS = +5 V, –VS = –4.5 V to –5.5 V –90 –84 –78 –74 dB

= ±1 V, RL ≥ 150 Ω±0.4 ± 1.5 ±0.15 ±0.6 %

OUT

T

to T

MIN

MAX

= ±1 V 88 74 dB

OUT

= ±1 V 250 200 ppm

OUT

T

to T

MIN

to T

MAX

T

20 10 ppm/°C

220µV/°C

1.4 3.5 mV

–VS = –5 V, +VS = +4.5 V to +5.5 V –94 –86 –80 –74 dB Input Bias Current (+IN, –IN) ±0.5 ± 2 ±0.5 ±2 µA Input Bias Current (REF, FB) ±1 ± 3.5 ±1 ±3.5 µA

T

to T

Input Offset Current (+IN, –IN, REF, FB) ±0.08 ± 0.4 ± 0.08 ± 0.4 µA

MIN

T

MIN

(+IN, –IN, REF, FB) 5 5 nA/°C

MAX

to T

MAX

0.2 0.2 nA/°C

OUTPUT PERFORMANCE

Voltage Swing R Output Current 40 40 mA

= 150 Ω/1 kΩ 3.6/4.0 3.6/4.0 ±V

LOAD

Short Circuit Current To Common –60/+55 –60/+55 mA

T

to T

MIN

Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF

MAX

–240 –240 µA/°C

POWER SUPPLY

Operating Voltage Range Total Supply Voltage ±2.25 ± 12.6 ± 2.25 ±12.6 V Quiescent Supply Current 10.8 11.6 10.8 11.6 mA

T

to T

MIN

PD ≤ V

IL

PD ≤ VIL, T

MAX

MIN

to T

MAX

36 36 µA/°C

0.68 0.85 0.68 0.85 mA 11mA

PD PIN

V

IH

V

IL

I

IH

I

IL

Input Resistance PD ≤ +VS – 3 V 12.5 12.5 kΩ

PD = Min V PD = Max V

IH

IL

+VS – 1.5 +VS – 1.5 V

+VS – 2.5 +VS – 2.5 V –30 –30 µA –50 –50 µA

PD ≥ +VS – 2 V 100 100 kΩ

Enable Time 0.5 0.5 µs

OPERATING TEMPERATURE RANGE –40 +85 –40 +125 °C

Specifications subject to change without notice.

–2–

REV. A

AD8129/AD8130

12 V SPECIFICATIONS

unless otherwise noted. T

MIN

to T

MAX

(AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 12 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF,

= –40C to +85C, unless otherwise noted.)

Model AD8129A AD8130A Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth V

Bandwidth for 0.1 dB Flatness V Slew Rate V Settling Time V Rise and Fall Time V Output Overdrive Recovery 40 40 ns

≤ 0.3 V p-p 175 200 250 290 MHz

OUT

V

= 2 V p-p 170 195 150 175 MHz

OUT

≤ 0.3 V p-p, SOIC/µSOIC 50/70 110 MHz

OUT

= 2 V p-p, 25% to 75% 935 1070 960 1100 V/µs

OUT

= 2 V p-p, 0.1% 20 20 ns

OUT

≤ 1 V p-p, 10% to 90% 1.7 1.4 ns

OUT

NOISE/DISTORTION

Second Harmonic/Third Harmonic V

IMD V Output IP3 V Input Voltage Noise (RTI) f ≥ 10 kHz 4.6 13 nV/√Hz

= 1 V p-p, 5 MHz –71/–84 –79/–86 dBc

OUT

V

= 2 V p-p, 5 MHz –65/–74 –74/–81 dBc

OUT

V

= 1 V p-p, 10 MHz –65/–82 –74/–80 dBc

OUT

V

= 2 V p-p, 10 MHz –59/–70 –74/–74 dBc

OUT

= 2 V p-p, 10 MHz –67 –70 dBc

OUT

= 2 V p-p, 10 MHz 25 26 dBm

OUT

Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz Differential Gain Error AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω 0.3 0.13 % Differential Phase Error AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω 0.1 0.2 Degrees

INPUT CHARACTERISTICS

Common-Mode Rejection Ratio DC to 100 kHz, VCM = ± 10 V 92 105 88 105 dB

VCM = 1 V p-p @ 2 MHz 80 80 dB

VCM = 1 V p-p @ 10 MHz 70 70 dB CMRR with V Common-Mode Voltage Range V Differential Operating Range ±0.5 ±2.5 V

= 1 V p-p VCM = 4 V p-p @ 1 kHz, V

OUT

– V

= 0 V ±10.3 ± 10.5 V

+IN

–IN

= ±0.5 V dc 93 80 dB

OUT

Differential Clipping Level ±0.6 ± 0.75 ± 0.85 ± 2.3 ±2.8 ± 3.3 V Resistance Differential 1 6 MΩ

Common-Mode 4 4 MΩ Capacitance Differential 3 3 pF

Common-Mode 4 4 pF

DC PERFORMANCE

Closed-Loop Gain Error V

Open-Loop Gain V Gain Nonlinearity V Input Offset Voltage 0.2 0.8 0.4 1.8 mV

Input Offset Voltage vs. Supply +VS = +12 V, –VS = –11.0 V to –13.0 V –88 –82 –77 –70 dB

= ± 1 V, RL ≥ 150 Ω±0.8 ±1.8 ± 0.15 ± 0.6 %

OUT

T

to T

MIN

MAX

= ± 1 V 87 73 dB

OUT

= ± 1 V 250 200 ppm

OUT

T

to T

MIN

to T

MAX

T

20 10 ppm/°C

220µV/°C

1.4 3.5 mV

–VS = –12 V, +VS = +11.0 V to +13.0 V –92 –84 –88 –70 dB Input Bias Current (+IN, –IN) ±0.25 ±2 ±0.25 ±2 µA Input Bias Current (REF, FB) ±0.5 ±3.5 ± 0.5 ±3.5 µA

T

to T

Input Offset Current (+IN, –IN, REF, FB) ±0.08 ±0.4 ± 0.08 ±0.4 µA

MIN

T

MIN

(+IN, –IN, REF, FB) 2.5 2.5 nA/°C

MAX

to T

MAX

0.2 0.2 nA/°C

OUTPUT PERFORMANCE

Voltage Swing R Output Current 40 40 mA

= 700 Ω±10.8 ±10.8 V

LOAD

Short Circuit Current To Common –60/+55 –60/+55 mA

T

to T

MIN

Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF

MAX

–240 –240 µA/°C

POWER SUPPLY

Operating Voltage Range Total Supply Voltage ±2.25 ± 12.6 ± 2.25 ±12.6 V Quiescent Supply Current 13 13.9 13 13.9 mA

T

to T

MIN

PD ≤ V

IL

PD ≤ VIL, T

MAX

MIN

to T

MAX

43 43 µA/°C

0.73 0.9 0.73 0.9 mA

1.1 1.1 mA

PD PIN

V

IH

V

IL

I

IH

I

IL

Input Resistance PD ≤ +VS – 3 V 3 3 kΩ

PD = Min V

PD = Max V

IH

IL

+VS – 1.5 +VS – 1.5 V

+VS – 2.5 +VS – 2.5 V –30 –30 µA –50 –50 µA

PD ≥ +VS – 2 V 100 100 kΩ Enable Time 0.5 0.5 µs

OPERATING TEMPERATURE RANGE –40 +85 –40 +85 °C

Specifications subject to change without notice.

REV. A

–3–

AD8129/AD8130–SPECIFICATIONS

5 V SPECIFICATIONS

unless otherwise noted. T

MIN

(AD8129 G = 10, AD8130 G = 1, TA = 25C, +VS = 5 V, –VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 k, CL = 2 pF

to T

= –40C to +85C, unless otherwise noted.)

MAX

Model AD8129A AD8130A Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth V

Bandwidth for 0.1 dB Flatness V Slew Rate V Settling Time V Rise and Fall Time V Output Overdrive Recovery 20 30 ns

≤ 0.3 V p-p 160 185 220 250 MHz

OUT

V

= 1 V p-p 160 185 180 205 MHz

OUT

≤ 0.3 V p-p, SOIC/µSOIC 25/40 25 MHz

OUT

= 2 V p-p, 25% to 75% 810 930 810 930 V/µs

OUT

= 2 V p-p, 0.1% 20 20 ns

OUT

≤ 1 V p-p, 10% to 90% 1.8 1.5 ns

OUT

NOISE/DISTORTION

Second Harmonic/Third Harmonic V

IMD V Output IP3 V Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.3 nV/√Hz

= 1 V p-p, 5 MHz –68/–75 –72/–79 dBc

OUT

V

= 2 V p-p, 5 MHz –62/–64 –65/–71 dBc

OUT

= 1 V p-p, 10 MHz –63/–70 –60/–62 dBc

V

OUT

V

= 2 V p-p, 10 MHz –56/–58 –68/–68 dBc

OUT

= 2 V p-p, 10 MHz –67 –70 dBc

OUT

= 2 V p-p, 10 MHz 25 26 dBm

OUT

Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz Differential Gain Error AD8130, G = 2, NTSC 100 IRE, R Differential Phase Error AD8130, G = 2, NTSC 100 IRE, RL ≥ 150 Ω 0.1 0.15 Degrees

≥ 150 Ω 0.3 0.13 %

L

INPUT CHARACTERISTICS

Common-Mode Rejection Ratio DC to 100 kHz, VCM = 1.5 V to 3.5 V 86 96 86 96 dB

VCM = 1 V p-p @ 1 MHz 80 80 dB

VCM = 1 V p-p @ 10 MHz 70 70 dB CMRR with V Common-Mode Voltage Range V Differential Operating Range ± 0.5 ± 2.5 V

= 1 V p-p VCM = 1 V p-p @ 1 kHz, V

OUT

+IN

– V

= 0 V 1.25 to 3.7 1.25 to 3.8 V

–IN

= ±0.5 V dc 80 72 dB

OUT

Differential Clipping Level ±0.6 ± 0.75 ±0.85 ± 2.3 ±2.8 ± 3.3 V Resistance Differential 1 6 MΩ

Common-Mode 4 4 MΩ Capacitance Differential 3 3 pF

Common-Mode 4 4 pF

DC PERFORMANCE

Closed-Loop Gain Error V

Open-Loop Gain V Gain Nonlinearity V Input Offset Voltage 0.2 0.8 0.4 1.8 mV

Input Offset Voltage vs. Supply +VS = 5 V, –VS = –0.5 V to +0.5 V –88 –80 –74 –70 dB

= ± 1 V, RL ≥ 150 Ω±0.25 ±1.25 ±0.1 ± 0.6 %

OUT

T

to T

MIN

MAX

= ± 1 V 86 71 dB

OUT

= ± 1 V 250 200 ppm

OUT

T

to T

MIN

to T

MAX

T

20 20 ppm/°C

220µV/°C

1.4 3.5 mV

–VS = 0 V, +VS = +4.5 V to +5.5 V –100 –86 –90 –76 dB Input Bias Current (+IN, –IN) ±0.5 ±2 ±0.5 ± 2 µA Input Bias Current (REF, FB) ±1 ± 3.5 ±1 ± 3.5 µA

T

to T

Input Offset Current (+IN, –IN, REF, FB) ±0.08 ±0.4 ± 0.08 ±0.4 µA

MIN

T

MIN

(+IN, –IN, REF, FB) 5 5 nA/°C

MAX

to T

MAX

0.2 0.2 nA/°C

OUTPUT PERFORMANCE

Voltage Swing R Output Current 35 35 mA

≥ 150 Ω 1.1 3.9 1.1 3.9 V

LOAD

Short Circuit Current To Common –60/+55 –60/+55 mA

T

to T

MIN

Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF

MAX

–240 –240 µA/°C

POWER SUPPLY

Operating Voltage Range Total Supply Voltage ±2.25 ± 12.6 ± 2.25 ±12.6 V Quiescent Supply Current 9.9 10.6 9.9 10.6 mA

T

to T

MIN

PD ≤ V

IL

PD ≤ VIL, T

MAX

MIN

to T

MAX

33 33 µA/°C

0.65 0.85 0.65 0.85 mA 11mA

PD PIN

V

IH

V

IL

I

IH

I

IL

Input Resistance PD ≤ +VS – 3 V 12.5 12.5 kΩ

PD = Min V PD = Max V

IH

IL

+VS – 1.5 +VS – 1.5 V

+VS – 2.5 +VS – 2.5 V –30 –30 µA –50 –50 µA

PD ≥ +VS – 2 V 100 100 kΩ

Enable Time 0.5 0.5 µs

OPERATING TEMPERATURE RANGE –40 +85 –40 +125 °C

Specifications subject to change without notice.

–4–

REV. A

AD8129/AD8130

AD8129/

AD8130

1

2

3

4

+IN

–IN

–V

S

+V

S

PD

OUT

REF

FB

8

7

6

5

+

ABSOLUTE MAXIMUM RATINGS

1, 2

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . Refer to Figure 3

Input Voltage (Any Input) . . . . . . . –V

Differential Input Voltage (AD8129) Differential Input Voltage (AD8129)

– 0.3 V to +VS + 0.3 V

S

3

VS ≥ ± 11.5 V . . . ± 0.5 V

3

VS < ± 11.5 V . . . ± 6.2 V

Differential Input Voltage (AD8130) . . . . . . . . . . . . . . . ± 8.4 V

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2

Thermal Resistance measured on SEMI standard 4-layer board. 8-Lead SOIC: θJA= 121°C/W; 8-Lead Micro_SO: θJA = 142°C/W

3

Refer to Applications section, Extreme Operating Condition, and Power Dissipation.

1.75

1.50

1.25

1.00

0.75

MICRO_SO

0.50

SOIC

CONNECTION DIAGRAM

(Top View)

SO-8 (R) and Micro_SO-8 (RM)

MAXIMUM POWER DISSIPATION (W)

0.25

0 –40 –30 –20–10 0 10 20 30 40 50 60 70 80 90 100 110120

AMBIENT TEMPERATURE (C)

Figure 3. Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8129/AD8130 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD8129/AD8130

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Branding

AD8129AR –40ºC to +85ºC 8-Lead SOIC SO-8 AD8129AR-REEL –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel AD8129AR-REEL7 –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel AD8129ARZ AD8129ARZ-REEL AD8129ARZ-REEL7 AD8129ARM –40ºC to +85ºC 8-Lead Micro_SO RM-8 HQA AD8129ARM-REEL –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HQA AD8129ARM-REEL7 –40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HQA AD8129ARMZ AD8129ARMZ-REEL AD8129ARMZ-REEL7 AD8130AR AD8130AR-REEL AD8130AR-REEL7 AD8130ARZ AD8130ARZ-REEL AD8130ARZ-REEL7 AD8130ARM AD8130ARM-REEL AD8130ARM-REEL7 AD8130ARMZ AD8130ARMZ-REEL AD8130ARMZ-REEL7

1

Pb-free part; # indicates lead-free, may be top or bottom marked.

2

Operating temperature range for ± 5 V or +5 V operation is –40°C to +125°C.

1

2

1, 2

2

1, 2

–40ºC to +85ºC 8-Lead SOIC SO-8 –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel

–40ºC to +85ºC 8-Lead Micro_SO RM-8 HQA# –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HQA#

1

–40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HQA# –40ºC to +85ºC 8-Lead SOIC SO-8 –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel –40ºC to +85ºC 8-Lead SOIC SO-8 –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel –40ºC to +85ºC 8-Lead Micro_SO RM-8 HPA –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HPA –40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HPA –40ºC to +85ºC 8-Lead Micro_SO RM-8 HPA# –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HPA#

1, 2

–40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HPA#

–6–

REV. A

Typical Performance Characteristics–AD8129/AD8130

AD8130 Frequency Response Characteristics

(G = 1, RL = 1 k, CL = 2 pF, V

3

V

= 0.3V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

TPC 1. AD8130 Frequency Response vs. Supply, V

VS = 5V

10 100 400

FREQUENCY – MHz

= 0.3 V p-p

OUT

= 0.3 V p-p, TA = 25C, unless otherwise noted.)

OUT

V

S

= 12V

V

S

= 2.5V

3

V

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

OUT

= 1V p-p

FREQUENCY – MHz

TPC 2. AD8130 Frequency Response vs. Supply, V

OUT

VS = 5V

10 100 300

= 1 V p-p

V

S

= 12V

V

S

= 2.5V

3

V

= 2V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

FREQUENCY – MHz

= 2.5V

V

S

VS = 5V

VS = 12V

10 100 300

TPC 3. AD8130 Frequency Response vs. Supply, V

= 2 V p-p

OUT

6

VS = 5V

5

4

3

2

1

0

GAIN – dB

–1

–2

–3

–4

1

FREQUENCY – MHz

C

= 20pF

L

CL = 10pF

= 5pF

C

L

CL = 2pF

10 100 300

TPC 4. AD8130 Frequency Response vs. Load Capacitance

3

RL = 150

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

VS = 2.5V

VS = 5V

= 12V

V

S

10 100 400

FREQUENCY – MHz

TPC 7. AD8130 Frequency Response vs. Supply, RL = 150

Ω

0.7

0.6

0.5

0.4

0.3

0.2

0.1

GAIN – dB

0.0

–0.1

–0.2

–0.3

1

RL = 1k

V

= 2.5V

S

VS = 5V

= 12V

V

S

10 100 300

FREQUENCY – MHz

TPC 5. AD8130 Fine Scale Response vs. Supply, RL = 1 k

3

G = 2

= 0.3V p-p

V

2

OUT

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

Ω

VS = 2.5V

VS = 5V

= 12V

V

S

10 100 300

FREQUENCY – MHz

TPC 8. AD8130 Frequency Response vs. Supply, G = 2, V

= 0.3 V p-p

OUT

0.5 RL = 150

0.4

0.3

0.2

0.1

0.0

–0.1

GAIN – dB

–0.2

–0.3

–0.4

–0.5

1

V

= 2.5V

S

VS = 5V

= 12V

V

S

10 100 300

FREQUENCY – MHz

TPC 6. AD8130 Fine Scale Response

= 150

vs. Supply, R

3

G = 2

= 2V p-p

V

2

OUT

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

L

FREQUENCY – MHz

Ω

VS = 2.5V

VS = 5V

= 12V

V

S

10 100 300

TPC 9. AD8130 Frequency Response vs. Supply, G = 2, V

= 2 V p-p

OUT

REV. A

–7–

AD8129/AD8130

3

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1

RF = RG = 750

RF = RG = 499

RF = RG = 250

G = 2 VS = 5V

10 100 300

FREQUENCY – MHz

RF = RG = 1k

TPC 10. AD8130 Frequency Response for Various RF/R

3

G = 2

2

= 150

R

L

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

FREQUENCY – MHz

VS = 2.5V

VS = 5V

VS = 12V

10 100

G

TPC 13. AD8130 Frequency Response vs. Supply, G = 2, RL = 150

Ω

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

1

G = 2 R

= 1k

L

FREQUENCY – MHz

VS = 2.5V

VS = 5V

VS = 12V

10 100

TPC 11. AD8130 Fine Scale Response vs. Supply, G = 2, R

0.3 V

= 2V p-p

OUT

0.2

0.1

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

0.1

VS = 2.5V

VS = 5V, 12V

= 1 k

Ω

L

VS = 2.5V

G = 10

11030

FREQUENCY – MHz

VS = 5V

VS = 12V

G = 5

TPC 14. AD8130 Fine Scale Response vs. Supply, G = 5, G = 10, V

= 2 V p-p

OUT

0.3 G = 2

0.2

= 150

R

0.1

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

1

L

VS = 2.5V

VS = 5V

VS = 12V

10 100

FREQUENCY – MHz

TPC 12. AD8130 Fine Scale Response vs. Supply, G = 2, RL = 150

3

V

= 2V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

0.1

VS = 12V

VS = 5V, 12V

VS = 2.5V

1

FREQUENCY – MHz

Ω

G = 5

G = 10

10 100

TPC 15. AD8130 Frequency Response vs. Supply, G = 5, G = 10, V

= 2 V p-p

OUT

3

RL = 150

2

1

0

–1

G = 10

–2

–3

GAIN – dB

–4

–5

–6

–7

0.1

VS = 2.5V

VS = 5V, 12V

1

FREQUENCY – MHz

VS = 5V, 12V

G = 5

10 100

TPC 16. AD8130 Frequency Response vs. Supply, G = 5, G = 10, RL = 150

Ω

12

0dB = 1V RMS

6

0

–6

–12

–18

–24

–30

OUTPUT VOLTAGE – dBV

–36

–42

VS = 5V

–48

10

FREQUENCY – MHz

100 400

TPC 17. AD8130 Frequency Response for Various Output Levels

–8–

50

1

8

4

5

R

F

0

499

8.06k

4.99k

R

F

499

2k

549

R

G

GR

1 2 5

10

TEK P6245

FET PROBE

6

RLC

G

–

TPC 18. AD8130 Basic Frequency Response Test Circuit

REV. A

L

AD8129 Frequency Response Characteristics

(G = 10, RL = 1 k, CL = 2 pF, V

3

V

= 0.3V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

VS = 2.5V

10 100

FREQUENCY – MHz

= 0.3 V p-p, TA = 25C, unless otherwise noted.)

OUT

3

V

= 1V p-p

VS = 5V

VS = 12V

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

VS = 2.5V

10 100

FREQUENCY – MHz

VS = 12V

VS = 5V

AD8129/AD8130

3

V

= 2V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

VS = 2.5V

VS = 5V

VS = 12V

10 100

FREQUENCY – MHz

TPC 19. AD8129 Frequency Response vs. Supply, V

4

VS = 5V

3

2

1

0

–1

–2

GAIN – dB

–3

–4

–5

–6

1 300

= 0.3 V p-p

OUT

CL = 20pF C

= 10pF

L

C

= 5pF

L

C

= 2pF

L

10 100

FREQUENCY – MHz

TPC 22. AD8129 Frequency Response vs. Load Capacitance

3

RL = 150

2

1

0

–1

–2

GAIN – dB

–3

–4

–5

–6

–7

10

VS = 2.5V

VS = 5V

VS = 12V

100 300

FREQUENCY – MHz

TPC 25. AD8129 Frequency Response vs. Supply, RL = 150

Ω

TPC 20. AD8129 Frequency Response vs. Supply, V

0.5 RL = 1k

0.4

0.3

0.2

0.1

0

–0.1

GAIN – dB

–0.2

–0.3

–0.4

–0.5

1 300

= 1 V p-p

OUT

VS = 2.5V

VS = 5V

VS = 12V

10 100

FREQUENCY – MHz

TPC 23. AD8129 Fine Scale Response

= 1 k

vs. Supply, R

3

G = 20

= 0.3V p-p

V

2

OUT

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

Ω

L

VS = 2.5V

10 100

FREQUENCY – MHz

VS = 5V, 12V

TPC 26. AD8129 Frequency Response vs. Supply, G = 20, V

= 0.3 V p-p

OUT

TPC 21. AD8129 Frequency Response vs. Supply, V

0.3 RL = 150

0.2

0.1

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

1 300

= 2 V p-p

OUT

VS = 2.5V

VS = 5V

VS = 12V

10 100

FREQUENCY – MHz

TPC 24. AD8129 Fine Scale Response vs. Supply, RL = 150

3

G = 20

= 2V p-p

V

2

OUT

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

Ω

VS = 5V, 12V

VS = 2.5V

10 100

FREQUENCY – MHz

TPC 27. AD8129 Frequency Response vs. Supply, G = 20, V

= 2 V p-p

OUT

REV. A

–9–

AD8129/AD8130

0.8

G = 10

0.6 VS = 5V

0.4

0.2

SOIC

0

–0.2

0.2

GAIN – dB

SOIC

0

–0.2

–0.4

–0.6

1 10 100 300

2k/221

909/100

499/54.9

909/100

2k/221

FREQUENCY – MHz

TPC 28. AD8129 Fine Scale Response

µ

vs. SOIC and

3

G = 20 R

2

L

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

1 300

SOIC for Various RF/R

= 150

VS = 5V, 12V

VS = 2.5V

10 100

FREQUENCY – MHz

TPC 31. AD8129 Frequency Response

= 150

vs. Supply, G = 20, R

L

Ω

0.2 G = 20

0.1

= 1k

R

L

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

–0.8

1

VS = 12V

VS = 2.5V

10 30

FREQUENCY – MHz

TPC 29. AD8129 Fine Scale Response vs. Supply

G

0.2

V

= 2V p-p

OUT

0.1

0

–0.1

–0.2

–0.3

–0.4

GAIN – dB

–0.5

–0.6

–0.7

–0.8

0.1

G = 100

VS = 2.5V

VS = 5V

VS = 12V

110

FREQUENCY – MHz

TPC 32. AD8129 Fine Scale Response vs. Supply, G = 50, G = 100, V

= 2 V p-p

OUT

VS = 5V

VS = 12V

G = 50

0.3 G = 20

0.2

R

= 150

L

0.1

0

–0.1

–0.2

–0.3

GAIN – dB

–0.4

–0.5

–0.6

–0.7

0.1 30 FREQUENCY – MHz

VS = 5V, 12V

VS = 2.5V

110

TPC 30. AD8129 Fine Scale Response vs. Supply

3

V

= 2V p-p

OUT

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

0.1 50

G = 100

VS = 2.5V

VS = 5V

VS = 12V

110

FREQUENCY – MHz

G = 50

TPC 33. AD8129 Frequency Response vs. Supply, G = 50, G = 100, V

= 2 V p-p

OUT

3

RL = 150

2

1

0

–1

–2

–3

GAIN – dB

–4

–5

–6

–7

0.1 50

G = 100

VS = 2.5V

VS = 5V

VS = 12V

110

FREQUENCY – MHz

G = 50

TPC 34. AD8129 Frequency Response vs. Supply, G = 50, G = 100,

= 150

R

L

Ω

12

0dB = 1V RMS

6

0

–6

–12

–18

–24

–30

OUTPUT VOLTAGE – dBV

–36

–42

VS = 5V

–48

10

FREQUENCY – MHz

100 400

TPC 35. AD8129 Frequency Response for Various Output Levels

–10–

1

8

50

4

5

R

2k 2k 2k 2k

R

F

221 105

41.2

R

G

GR

10 20 50

100

20

G

TEK P6245

FET PROBE

6

RLC

TPC 36. AD8129 Basic Frequency Response Test Circuit

REV. A

L

AD8130 Harmonic Distortion Characteristics

(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)

–60

V

= 1V p-p

OUT

–66

VS = 12V

–72

–78

HD2 – dBc

G = 1

–84

–90

VS = 12V

G = 2

1

FREQUENCY – MHz

VS = 5V

10 40

TPC 37. AD8130 Second Harmonic Distortion vs. Frequency

–54

V

= 2V p-p

OUT

–60

–66

–72

HD2 – dBc

–78

V

= 12V

S

G = 2

–84

1

VS = 5V

FREQUENCY – MHz

TPC 38. AD8130 Second Harmonic Distortion vs. Frequency

G = 1

= 5V

V

S

G = 1

= 12V

V

S

10 40

AD8129/AD8130

–55

fC = 5MHz

–61

–67

–73

HD2 – dBc

–79

–85

–91

0.5

TPC 39. AD8130 Second Harmonic Distortion vs. Output Voltage

VS = 12V

VS = 5V

G = 1

V

= 12V

S

VS = 5V

G = 2

110

V

– V p-p

OUT

–51

V

–57

–63

–69

–75

HD3 – dBc

–81

–87

–93

–99

1

= 1V p-p

OUT

VS = 12V

G = 1

G = 2

VS = 5V

FREQUENCY – MHz

G = 1

VS = 5V

G = 1

VS = 12V

10 40

TPC 40. AD8130 Third Harmonic Distortion vs. Frequency

–43

VS = 2.5V

–49

–55

–61

HD2 – dBc

–67

–73

G = 1

–79

1

V

OUT

G = 2

FREQUENCY – MHz

G = 1

= 2V p-p

V

= 1V p-p

OUT

10 40

TPC 43. AD8130 Second Harmonic Distortion vs. Frequency

–45

V

= 2V p-p

–51

–57

–63

–69

HD3 – dBc

–75

G = 1

–81

–87

–93

1

OUT

VS = 5V

G = 2, VS = 12V

G = 2, VS = 5V

VS = 12V

G = 2

10 40

FREQUENCY – MHz

TPC 41. AD8130 Third Harmonic Distortion vs. Frequency

–42

VS = 2.5V

–48

–54

–60

V

= 2V p-p

OUT

–66

–72

HD3 – dBc

–78

–84

–90

–96

1

G = 2

G = 1

G = 2

V

= 1V p-p

OUT

FREQUENCY – MHz

10 40

G = 1

TPC 44. AD8130 Third Harmonic Distortion vs. Frequency

–46

f

= 5MHz

C

–52

–58

–64

–70

HD3 – dBc

–76

–82

–88

–94

0.5

V

= 12V

S

V

= 5V

S

G = 1

110

V

– V p-p

OUT

G = 2

VS = 12V

VS = 5V

TPC 42. AD8130 Third Harmonic Distortion vs. Output Voltage

–46

–52

–58

–64

–70

HD – dBc

–76

–82

–88

–94

0

VS = 2.5V

= 5MHz

f

C

G = 1, HD2

G = 2, HD2

0.5 1.0 1.5 2.0 2.5 3.0 V

OUT

G = 1, HD3

– V p-p

G = 2, HD3

G = 2, HD2

G = 2, HD3

TPC 45. AD8130 Harmonic Distortion vs. Output Voltage

REV. A

–11–

AD8129/AD8130

AD8129 Harmonic Distortion Characteristics

(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)

–51

V

= 1V p-p

OUT

–57

–63

–69

HD2 – dBc

–75

–81

–87

1

G = 10,

= 5V

V

S

G = 10,

= 12V

V

S

G = 20,

= 5V

V

S

FREQUENCY – MHz

10 40

G = 20,

= 12V

V

S

TPC 46. AD8129 Second Harmonic Distortion vs. Frequency

–42

V

= 2V p-p

OUT

–48

–54

–60

–66

HD2 – dBc

–72

–78

–84

1

G = 20, V

= 12V

S

G = 10,

= 12V

V

S

G = 20, V

S

FREQUENCY – MHz

TPC 47. AD8129 Second Harmonic Distortion vs. Frequency

G = 10

G = 20

G = 10, V

= 5V

S

= 5V

10 40

–50

fC = 5MHz

–56

–62

G = 10,

= 12V

V

S

–68

HD2 – dBc

–74

–80

–86

0.5

G = 20,

= 12V

V

S

1 10

V

– V p-p

OUT

G = 20,

= 5V

V

S

G = 10,

= 5V

V

S

TPC 48. AD8129 Second Harmonic Distortion vs. Output Voltage

–54

V

= 1V p-p

OUT

–60

–66

–72

–78

HD3 – dBc

–84

–90

–96

G = 20,

V

= 5V

S

1 10 40

FREQUENCY – MHz

G = 10,

= 5V

V

S

G = 10,

= 12V

V

S

G = 20,

= 12V

V

S

TPC 49. AD8129 Third Harmonic Distortion vs. Frequency

–44

VS = 2.5V

–50

–56

–62

G = 20

HD2 – dBc

–68

–74

–80

1

V

= 2V p-p

OUT

V

G = 10

FREQUENCY – MHz

10 40

OUT

= 1V p-p

TPC 52. AD8129 Second Harmonic Distortion vs. Frequency

–45

V

= 2V p-p

–51

–57

–63

G = 10,

–69

V

HD3 – dBc

–75

–81

–87

1

OUT

= 12V

S

G = 10,

= 5V

V

S

FREQUENCY – MHz

G = 10,

= 5V

V

S

G = 10,

= 12V

V

S

G = 20,

= 5V

V

S

G = 20, V

= 12V

S

10 40

TPC 50. AD8129 Third Harmonic Distortion vs. Frequency

–42

VS = 2.5V

–48

–54

–60

G = 20

–66

HD3 – dBc

–72

–78

–84

–90

1

FREQUENCY – MHz

= 2V p-p

V

OUT

V

OUT

G = 10

10 40

= 1V p-p

TPC 53. AD8129 Third Harmonic Distortion vs. Frequency

–48

–54

–60

–66

–72

HD3 – dBc

–78

–84

–90

–96

0.5

fC = 5MHz

110

V

G = 10, V

S

OUT

= 5V

G = 20,

= 12V

V

S

– V p-p

G = 10,

= 12V

V

S

G = 20,

V

= 5V

S

TPC 51. AD8129 Third Harmonic Distortion vs. Output Voltage

–50

VS = 2.5V

= 5MHz

f

C

–56

–62

–68

HD – dBc

–74

–80

–86

G = 20

HD3

G = 10

HD2

G = 10

HD3

0.5 1.0 1.5 2.0 2.5 3.0

0

V

– V p-p

OUT

G = 20

HD2

TPC 54. AD8129 Harmonic Distortion vs. Output Voltage

–12–

REV. A

AD8129/AD8130

–39

–45

–51

–57

–63

–69

DISTORTION – dBc

–75

–81

–87

–5

G = 1 V

= 2V p-p

OUT

= 5V

V

S

= 1k

R

L

= 5MHz

f

C

HD2

HD3

–4 –3 –2 –1 0 1

VCM – V

2 345

TPC 55. AD8130 Harmonic Distortion vs. Common-Mode Voltage

–36

–42

–48

–54

–60

DISTORTION – dBc

–66

–72

–78

–5

G = 10

= 2V p-p

V

OUT

= 5V

V

S

= 1k

R

L

f

= 5MHz

C

HD2

–4 –3 –2 –1 0 1

V

– V

CM

HD3

2 345

TPC 58. AD8129 Harmonic Distortion vs. Common-Mode Voltage

–61

–67

–73

–79

–85

DISTORTION – dBc

–91

–97

100

G = 1

= 5MHz

f

C

V

RL – 

HD3 = 5V

S

V

= 1V p-p

OUT

HD2

VS = 2.5V

HD2

V

= 5V, 12V

S

HD3

= 12V

V

S

HD3

= 2.5V

V

S

1k

TPC 56. AD8130 Harmonic Distortion vs. Load Resistance

–48

–54

–60

–66

–72

DISTORTION – dBc

–78

–84

VS = 2.5V

–90

100

G = 10 f

= 5MHz

C

V

S

V

S

HD3

HD2

= 12V

= 5V

RL – 

V

OUT

= 1V p-p

VS = 2.5V V

= 12V

S

V

= 5V

S

1k

TPC 59. AD8129 Harmonic Distortion vs. Load Resistance

–50

–56

–62

–68

–74

DISTORTION – dBc

–80

–86

100

G = 1

= 5MHz

f

C

HD3

= 2.5V

V

S

V

S

HD2

= 2.5V

HD3

V

= 5V, 12V

S

RL – 

V

= 2V p-p

OUT

HD2

= 5V, 12V

V

S

1k

TPC 57. AD8130 Harmonic Distortion vs. Load Resistance

–44

–50

–56

–62

–68

DISTORTION – dBc

–74

–80

100

G = 10

= 5MHz

f

C

VS = 2.5V

VS = 5V

HD3

RL – 

V

= 2V p-p

OUT

VS = 2.5V

= 12V

V

S

V

= 5V

S

VS = 12V

1k

TPC 60. AD8129 Harmonic Distortion vs. Load Resistance

V

CM

200

1:2

R

G

MINI CIRCUITS:

f

# T4 – 6T, # TC4 – 1W,

ⱕ 10MHz

C

f

C

⬎ 10MHz

R

F

GR

1 2

499 10 20

R

0

2k 2k

R

L

F

G

– 499 221 105

TPC 61. AD8129/AD8130 Basic Distortion Test Circuit, V

= 0 V Unless

CM

Otherwise Noted

REV. A

100

10

C

L

1.0

CURRENT NOISE – pA/ Hz

0.1 100 1k 10k

10 100k

FREQUENCY – Hz

1M 10M

TPC 62. AD8129/AD8130 Input Current Noise vs. Frequency

100

AD8130

10

AD8129

VOLTA G E NOISE – nV/ Hz

1.0 100 1k 10k

10 100k

FREQUENCY – Hz

1M 10M

TPC 63. AD8129/AD8130 Input Voltage Noise vs. Frequency

–13–

AD8129/AD8130

–30

–40

–50

–60

–70

–80

–90

–100

COMMON-MODE REJECTION – dB

–110

–120

VS = 2.5V

= 5V, 12V

V

S

100k 1M 10M

10k 100M

FREQUENCY – Hz

TPC 64. AD8130 Common-Mode Rejection vs. Frequency

–30

–40

–50

–60

–70

VS = 2.5V

–80

–90

–100

COMMON-MODE REJECTION – dB

–110

–120

100k 1M 10M

10k 100M

FREQUENCY – Hz

VS = 5V, 12V

TPC 67. AD8129 Common-Mode Rejection vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

V

= 12V

S

–80

POWER SUPPLY REJECTION – dB

–90

–100

1k

10k 100k 1M 10M 100M

= 5V

V

S

VS = 2.5V

FREQUENCY – Hz

TPC 65. AD8130 Positive Power Supply Rejection vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

VS = 12V

–80

POWER SUPPLY REJECTION – dB

–90

–100

= 2.5V

V

S

VS = 5V

10k 100k 1M 10M 100M

1k

FREQUENCY – Hz

TPC 68. AD8129 Positive Power Supply Rejection vs. Frequency

0

–10

–20

–30

–40

–50

–60

VS = 2.5V

–70

–80

POWER SUPPLY REJECTION – dB

–90

–100

V

= 5V

S

1k

= 12V

V

S

10k 100k 1M 10M 100M

FREQUENCY – Hz

TPC 66. AD8130 Negative Power Supply Rejection vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

–80

POWER SUPPLY REJECTION – dB

–90

–100

VS = 5V

VS = 12V

VS = 2.5V

1k

10k 100k 1M 10M 100M

FREQUENCY – Hz

TPC 69. AD8129 Negative Power Supply Rejection vs. Frequency

80

70

60

50

40

30

20

OPEN-LOOP GAIN – dB

10

1k

0

–10

1k

10k 100k 1M 10M 100M 300M

GAIN

+

–

+

–

1k

V

IN

FREQUENCY – Hz

1k

PHASE

V

OUT

2pF

φ

= 58

M

TPC 70. AD8130 Open Loop Gain and Phase vs. Frequency

90

180

135

90

45

0

80

70

60

50

40

30

OPEN-LOOP GAIN – dB

20

PHASE MARGIN – Degrees

10

0

1k

TPC 71. AD8129 Open Loop Gain and Phase vs. Frequency

GAIN

V

OUT

2pF

1k

100

1k

V

IN

10k 100k 1M 10M 100M 300M

FREQUENCY – Hz

φM = 56

–14–

PHASE

100

180

10

135

90

45

PHASE MARGIN – Degrees

0

100m

OUTPUT IMPEDANCE – 

10m

1m

1

1k

TPC 72. Closed-Loop Output Impedance vs. Frequency

= 5V

V

S

AD8130, G = 1

AD8129, G = 10

10k 100k 1M 10M 100M

FREQUENCY – Hz

REV. A

AD8130 Transient Response Characteristics

(G = 1, RL = 1 k, CL = 2 pF, VS = 5 V, TA = 25C, unless otherwise noted.)

V

= 1V p-p

OUT

= 2.5V

V

S

V

OUT

V

S

= 1V p-p

= 5V

AD8129/AD8130

V

= 1V p-p

OUT

= 12V

V

S

250mV

5.00ns

TPC 73. AD8130 Transient Response, V

= ±2.5 V, V

S

VS = 2.5V

VS = 12V

50mV

OUT

VS = 5V

= 1 V p-p

V

OUT

= 0.2V p-p

5.00ns

TPC 76. AD8130 Transient Response vs. Supply, V

= 0.2 V p-p

OUT

250mV

5.00ns

TPC 74. AD8130 Transient Response, V

= ±5 V, V

S

VS = 2.5V

250mV

OUT

VS = 5V

VS = 12V

= 1 V p-p

V C

OUT

= 5pF

L

= 1V p-p

5.00ns

TPC 77. AD8130 Transient Response

vs. Supply, V

= 1 V p-p, CL = 5 pF

OUT

250mV

5.00ns

TPC 75. AD8130 Transient Response, VS = ±12 V, V

VS = 2.5V

VS = 12V

500mV

OUT

VS = 5V

= 1 V p-p

V C

OUT

= 5pF

L

5.00ns

= 2V p-p

TPC 78. AD8130 Transient Response

vs. Supply, V

= 2 V p-p, CL = 5 pF

OUT

CL = 10pF

50mV

CL = 5pF

CL = 2pF

V

= 0.2V

OUT

p-p

10.0ns

TPC 79. AD8130 Transient Response vs. Load Capacitance, V

= 0.2 V p-p

OUT

REV. A

2V p-p

1V p-p

0.5V p-p

500mV

5.00ns

TPC 80. AD8130 Transient Response vs. Output Amplitude,

= 0.5 V p-p, 1 V p-p, 2 V p-p

V

OUT

–15–

4V p-p

2V p-p

1V p-p

1.00V

5.00ns

TPC 81. AD8130 Transient Response vs. Output Amplitude, V

= 1 V p-p, 2 V p-p, 4 V p-p

OUT

AD8129/AD8130

V

= 1V p-p

OUT

G = 2

VS = 5V, CL = 10pF

V

OUT

G = 2

= 2V p-p

VS = 5V

V

OUT

= 8V p-p

CL = 10pF

G = 2

V

S

= 5V

VS = 5V, CL = 2pF

250mV

5.00ns

TPC 82. AD8130 Transient Response vs. Load Capacitance, V

= 1 V p-p,

OUT

G = 2

V

IN

V

OUT

1.00V

5.00ns

TPC 85. AD8130 Transient Response with +3 V Common-Mode Input

VS = 12V

500mV

5.00ns

TPC 83. AD8130 Transient Response vs. Supply, V

1.00V

= 2 V p-p, G = 2

OUT

V

IN

V

OUT

5.00ns

TPC 86. AD8130 Transient Response with –3 V Common-Mode Input

CL = 2pF

2.00V

5.00ns

TPC 84. AD8130 Transient Response vs. Load Capacitance, V

V

= 10V p-p

OUT

2.50V

= 8 V p-p

OUT

G = 2

= 12V

V

S

5.00ns

TPC 87. AD8130 Transient Response,

= 10 V p-p, G = 2, VS = ±12 V

V

OUT

G = 5

= 5V

V

4V p-p

2V p-p

1.00V

S

= 10pF

C

L

10.0ns

1V p-p

TPC 88. AD8130 Transient Response vs. Output Amplitude

V

OUT

2.00V

= 8V p-p

G = 5

= 5V

V

S

= 10pF

C

L

10.0ns

TPC 89. AD8130 Transient Response, V

= 8 V p-p, G = 5, VS = ±5 V

OUT

V

OUT

= 20V p-p

5.00V

G = 5

= 12V

V

S

= 10pF

C

L

10.0ns

TPC 90. AD8130 Transient Response,

= 20 V p-p, G = 5, VS = ±12 V

V

OUT

–16–

REV. A

AD8129 Transient Response Characteristics

(G = 10, RF = 2 k, RG = 221 , RL = 1 k, CL = 1 pF, VS = 5 V, TA = 25C, unless otherwise noted.)

V

VS = 2.5V

V

OUT

= 1V p-p

VS = 5V

OUT

= 1V p-p

AD8129/AD8130

VS = 12V

V

OUT

= 1V p-p

250mV

5.00ns

TPC 91. AD8129 Transient Response, VS = ±2.5 V, V

VS = 5V

VS = 12V

100mV

= 1 V p-p

OUT

VS = 2.5V

V

OUT

= 0.4V p-p

5.00ns

TPC 94. AD8129 Transient Response vs. Supply, V

= 0.4 V p-p

OUT

250mV

5.00ns

TPC 92. AD8129 Transient Response, VS = ±5 V, V

VS = 5V

250mV

OUT

VS = 2.5V

VS = 12V

= 1 V p-p

V

OUT

C

L

= 1V p-p

= 5pF

5.00ns

TPC 95. AD8129 Transient Response vs. Supply, V

= 1 V p-p, CL = 5 pF

OUT

250mV

5.00ns

TPC 93. AD8129 Transient Response, V

= ±12 V, V

S

VS = 2.5V

VS = 12V

500mV

OUT

VS = 5V

= 1 V p-p

V

OUT

C

= 5pF

L

5.00ns

= 2V p-p

TPC 96. AD8129 Transient Response

vs. Supply, V

= 2 V p-p, CL = 5 pF

OUT

CL = 5pF

CL = 10pF

CL = 2pF

100mV

V

OUT

= 0.4V p-p

5.00ns

TPC 97. AD8129 Transient Response vs. Load Capacitance, V

= 0.4 V p-p

OUT

REV. A

VO = 2V p-p

VO = 1V p-p

V

= 0.5V p-p

O

500mV

5.00ns

TPC 98. AD8129 Transient Response vs. Output Amplitude, V

= 0.5 V p-p, 1 V p-p, 2 V p-p

OUT

–17–

VO = 4V p-p

V

= 2V p-p

O

1.00V

VO = 1V p-p

5.00ns

TPC 99. AD8129 Transient Response vs. Output Amplitude,

= 1 V p-p, 2 V p-p, 4 V p-p

V

OUT

AD8129/AD8130

V

= 1V p-p

OUT

G = 20

= 20pF

C

L

V

OUT

= 2V p-p

G = 20

= 20pF

C

L

V

OUT

= 8V p-p

G = 20 C

= 20pF

L

250mV

5.00ns

TPC 100. AD8129 Transient Response, V

= 1 V p-p, VS = ±2.5 V to ±12 V

OUT

V

IN

V

OUT

1.00V

5.00ns

TPC 103. AD8129 Transient Response with +3.5 V Common-Mode Input

500mV

5.00ns

TPC 101. AD8129 Transient Response, V

= 2 V p-p, VS = ±5 V

OUT

V

OUT

V

IN

TPC 104. AD8129 Transient Response with –3.5 V Common-Mode Input

2.00V

5.00ns

TPC 102. AD8129 Transient Response, V

= 8 V p-p, VS = ±5 V

OUT

V

OUT

= 10V p-p

2.50V

G = 20

= 12V

V

S

= 20pF

C

L

5.00ns

TPC 105. AD8129 Transient Response, V

= 10 V p-p, G = 20

OUT

G = 50

= 5V

V

4V p-p

2V p-p

1.00V

S

= 20pF

C

L

12.5ns

1V p-p

TPC 106. AD8129 Transient Response vs. Output Amplitude, V

= 1 V p-p,

OUT

2 V p-p, 4 V p-p

V

OUT

= 8V p-p

2.00V

G = 50

= 5V

V

S

= 20pF

C

L

12.5ns

TPC 107. AD8129 Transient Response,

= 8 V p-p, G = 50, VS = ±5 V

V

OUT

V

= 20V p-p

OUT

5.00V

G = 50

= 12V

V

S

= 10pF

C

L

12.5ns

TPC 108. AD8129 Transient Response, V

= 20 V p-p, G = 50, VS = ±12 V

OUT

–18–

REV. A

AD8129/AD8130

23

20

17

14

SUPPLY CURRENT – mA

11

–5 –4 –3 –2 –1 0 1 2 3 4 5

DIFFERENTIAL INPUT – V

G = 1 V

= 5V

S

TPC 109. AD8130 DC Power Supply Current vs. Differential Input Voltage

G = 1

= 5V

V

S

= 1k

R

L

0.005%/DIV

GAIN NONLINEARITY –

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

OUTPUT VOLTAGE – V

37

31

25

19

SUPPLY CURRENT – mA

13

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

DIFFERENTIAL INPUT – V

G = 10 V

= 10V

S

TPC 110. AD8129 DC Power Supply Current vs. Differential Input Voltage

G = 1

= 5V

V

S

= 1k

R

L

GAIN NONLINEARITY – 0.08%/DIV

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

OUTPUT VOLTAGE – V

3.0

–1.0

DIFFERENTIAL INPUT – V

–2.0

–3.0

2.0

1.0

0.0

–50

V

= 100mV AC @ 1kHz

OUT

–35 –20 –5 10 25 40 55 70 85 100

TEMPERATURE – C

AD8130

AD8129

AD8130

TPC 111. AD8129/AD8130 Input Differential Voltage Range vs. Temperature, 1% Gain Compression

4

3

VS = 5V

2

1

– V

0

OUT

V

–1

–2

–3

–4

–5 –4 –3 –2 –1 0 1 2 3 4 5

DIFFERENTIAL INPUT – V

TPC 112. AD8130 Gain Nonlinearity,

= 2 V p-p

V

OUT

G = 10

= 5V

V

S

= 1k

R

L

0.005%/DIV

GAIN NONLINEARITY –

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

OUTPUT VOLTAGE – V

TPC 115. AD8129 Gain Nonlinearity,

= 2 V p-p

V

OUT

TPC 113. AD8130 Gain Nonlinearity, V

= 5 V p-p

OUT

G = 10

= 12V

V

S

= 1k

R

L

0.2%/DIV

GAIN NONLINEARITY –

–5 –4 –3 –2 –1 0 1 2 3 4 5

OUTPUT VOLTAGE – V

TPC 116. AD8129 Gain Nonlinearity,

= 10 V p-p

V

OUT

TPC 114. AD8130 Differential Input Clipping Level

8

6

VS = 10V

4

2

0

–2

–4

OUTPUT VOLTAGE – V

–6

–8

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

DIFFERENTIAL INPUT – V

TPC 117. AD8129 Differential Input Clipping Level

REV. A

–19–

AD8129/AD8130

15

14

13

12

11

SUPPLY CURRENT – mA

10

9

05 30

10 15 20 25

TOTAL SUPPLY VOLTAGE – V

TPC 118. Quiescent Power Supply Current vs. Total Supply Voltage

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

INPUT COMMON-MODE – V

1.50

1.25

1.00

AD8129

V

= 5V

S

–50 –35 –20 –5 10 25 40 55 70 85 100

AD8130

V

= 100mV

OUT

AC AT 1kHz

AD8129

TEMPERATURE – C

AD8130

TPC 121. Common-Mode Voltage Range vs. Temperature, Typical 1% Gain Compression

17

16

15

14

13

12

11

10

SUPPLY CURRENT – mA

9

8

7

–50

–35 –20 –5 10 25 40 55 70 85 100

VS = 12V

VS = 2.5V

TEMPERATURE – C

VS = 5V

TPC 119. Quiescent Power Supply Current vs. Temperature

4.00

3.75

3.50

3.25 VS = 5V

3.00

V

2.75

–3.00

–3.25

INPUT COMMON-MODE – V

–3.50

–3.75

–4.00

–35 –20 –5 10 25 40 55 70 85 100

–50

= 100mV

OUT

AC AT 1kHz

TEMPERATURE – C

AD8130

AD8129

AD8130AD8129

TPC 122. Common-Mode Voltage Range vs. Temperature, Typical 1% Gain Compression

0.60

I

0.45

0.30

INPUT BIAS CURRENT – A

0.15 –35 –20 –5 10 25 40 55 70 85 100

–50

B

I

OS

TEMPERATURE – C

40

30

20

10

TPC 120. Input Bias Current and Input Offset Current vs. Temperature

11.0

10.5

10.0 VS = 12V

9.5

9.0

V

8.5

–9.0

–9.5

INPUT COMMON-MODE – V

–10.0

–10.5

–11.0

–35 –20 –5 10 25 40 55 70 85 100

–50

= 100mV

OUT

AC AT 1kHz

TEMPERATURE – C

AD8130

AD8129

AD8130AD8129

TPC 123. Common-Mode Voltage Range vs. Temperature, Typical 1% Gain Compression

INPUT OFFSET CURRENT – nA

4.0

3.5 SOURCING

3.0

+100C –40C +25C

2.0

OUTPUT VOLTAGE – V

SINKING

1.5

1.0

510152025303540

0

OUTPUT CURRENT – mA

V

= 5V

S

V

= 100mV

OUT

AC AT 1kHz

TPC 124. Output Voltage Range vs. Output Current, Typical 1% Gain Compression

4.0

3.5

3.0 +100C –40C +25C

–3.0

OUTPUT VOLTAGE – V

–3.5

–4.0

510152025303540

0

OUTPUT CURRENT – mA

VS = 5V

V

= 100mV

OUT

AC AT 1kHz

TPC 125. Output Voltage Range vs. Output Current, Typical 1% Gain Compression

–20–

11

10

9

+100C –40C +25C

–9

OUTPUT VOLTAGE – V

–10

–11

510152025303540

0

OUTPUT CURRENT – mA

VS = 12V

V

= 100mV

OUT

AC AT 1kHz

TPC 126. Output Voltage Range vs. Output Current, Typical 1% Gain Compression

REV. A

AD8129/AD8130

THEORY OF OPERATION

The AD8129/AD8130 use an architecture called active feedback which differs from that of conventional op amps. The most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op amp’s single pair. Typically for the active-feedback architecture, one of these input pairs is driven by a differential input signal, while the other is used for the feedback. This active stage in the feedback path is where the term “active feedback” is derived.

The active feedback architecture offers several advantages over a conventional op amp in several types of applications. Among these are excellent common-mode rejection, wide input commonmode range and a pair of inputs that are high-impedance and totally balanced in a typical application. In addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it totally independent of the signal input. This eliminates any interaction between the feedback and input circuits, which traditionally causes problems with CMRR in conventional differential-input op amp circuits.

Another advantage is the ability to change the polarity of the gain merely by switching the differential inputs. A high inputimpedance inverting amplifier can be made. Besides a high input impedance, a unity-gain inverter with the AD8130 will have a noise gain of unity. This will produce lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity gain inverter.

The two differential input stages of the AD8129/AD8130 are each transconductance stages that are well matched. These stages convert the respective differential input voltages to internal currents. The currents are then summed and converted to a voltage, which is buffered to drive the output. The compensation capacitor is in the summing circuit.

When the feedback path is closed around the part, the output will drive the feedback input to that voltage which causes the internal currents to sum to zero. This occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is zero.

In a closed-loop application, a conventional op amp will have its differential input voltage driven to near zero under nontransient conditions. The AD8129/AD8130 generally will have differential input voltages at each of its input pairs, even under equilibrium conditions. As a practical consideration, it is necessary to internally limit the differential input voltage with a clamp circuit.

Thus, the input dynamic ranges are limited to about 2.5 V for the AD8130 and 0.5 V for the AD8129 (see Specification section for more detail). For this and other reasons, it is not recommended to reverse the input and feedback stages of the AD8129/AD8130, even though some apparently normal functionality might be observed under some conditions.

A few simple circuits can illustrate how the active feedback architecture of the AD8129/AD8130 operates.

Op Amp Configuration

If only one of the input stages of the AD8129/AD8130 is used, it will function very much like a conventional op amp. (See Figure 4.) Classical inverting and noninverting op amps circuits can be created, and the basic governing equations will be the same as for a conventional op amp. The unused input pins form the second input and should be shorted together and tied to ground or some midsupply voltage when they are not used.

+V

0.1F

10F

+

V

IN

+

R

F

R

G

PD +

–V

V

S

V

OUT

0.1F10F

Figure 4. With both inputs grounded, the feedback stage functions like an op amp: V

= VIN (1 + RF/RG). NOTE: This

OUT

circuit is provided to demonstrate device operation. It is not suggested to use this circuit in place of an op amp.

With the unused pair of inputs shorted, there is no differential voltage between them. This dictates that the differential input voltage of the used inputs will also be zero for closed-loop applications. Since this is the governing principle of conventional op amp circuits, an active feedback amplifier can function as a conventional op amp under these conditions.

Note that this circuit is presented only for illustration purposes, to show the similarities of the active feedback architecture functionality to conventional op amp functionality. If it is desired to design a circuit that can be created from a conventional op amp, it is recommended to choose a conventional op amp whose specifications are better suited to that application. These op amp principles are the basis for offsetting the output as described in the Output Offset/Level Translator section.

REV. A

–21–

AD8129/AD8130

APPLICATIONS

Basic Gain Circuits

The gain of the AD8129/AD8130 can be set with a pair of feedback resistors. The basic configuration is shown in Figure 5. The gain equation is the same as that of a conventional op amp: G = 1 + R

can be set to zero (short circuit), and RG can be removed.

R

F

. For unity gain applications using the AD8130,

F/RG

(See Figure 6.) The AD8129 is compensated to operate at gains of 10 and higher, so shorting the feedback path to obtain unity gain will cause oscillation.

+V

AD8129/

AD8130

+

V

IN

R

G

PD

+

–V

S

R

F

–V

Figure 5. Basic Gain Circuit: V

+V

S

0.1F10F

+V

0.1F

10F

V

OUT

= VIN (1 + RF/RG)

OUT

AD8130

10F

0.1F

PD

–V

S

–V

+V

S

0.1F10F

V

OUT

V

IN

+

Figure 6. An AD8130 with Unity Gain

The input signal can be applied either differentially or singleendedly—all that matters is the magnitude of the differential signal between the two inputs. For single-ended input applications, applying the signal to the +IN with –IN grounded will create a noninverting gain, while reversing these connections will create an inverting gain. Since the two inputs are highimpedance and matched, both of these conditions will provide the same high input impedance. Thus, an advantage of the active feedback architecture is the ability to make a high-inputimpedance, inverting op amp. If conventional op amps are used, a high impedance buffer followed by an inverting stage is needed. This requires two op amps.

Twisted-Pair Cable, Composite Video Receiver with Equalization Using an AD8130

The AD8130 has excellent common-mode rejection at its inputs. This makes it an ideal candidate for a receiver for signals that are transmitted over long distances on twisted-pair cables. Category 5 type cables are now very common in office settings and are extensively used for data transmission. These same cables can also be used for the analog transmission of signals like video.

These long cables will pick up noise from the environment they pass through. This noise will not favor one conductor over another, and will therefore be a common-mode signal. A receiver that rejects the common-mode signal on the cable can greatly enhance the signal-to-noise ratio performance of the link.

The AD8130 is also very easy to use as a differential receiver, because the differential inputs and the feedback inputs are entirely separate. This means that there is no interaction of the feedback network and the termination network as there would be in conventional op amp-type receivers.

Another issue to be dealt with on long cables is the attenuation of the signal at longer distances. This attenuation is a function of frequency and increases as roughly as the square root of frequency.

For good fidelity of video circuits, the overall frequency response of the transmission channel should be flat versus frequency. Since the cable attenuates the high frequencies, a frequency-selective boost circuit can be used to undo this effect. These circuits are called equalizers.

An equalizer uses frequency-dependent elements (Ls and Cs) in order to create a frequency response that is the opposite of the rest of the channel’s response in order to create an overall flat response. There are many ways to create such circuits, but a common technique is to put the frequency-selective elements in the feedback path of an op amp circuit. The AD8130 in particular makes this easier than other circuits, because, once again, the feedback path is totally independent of the input path and there is no interaction.

The circuit in Figure 7 was developed as a receiver/equalizer for transmitting composite video over 300 m of Category 5 cable. This cable has an attenuation of approximately 20 dB at 10 MHz for 300 m. At 100 MHz, the attenuation is approximately 60 dB. (See Figure 8.)

+V

100

200pF

AD8130

R

G

499

+

1k

V

100

IN

R1

C1

+V

PD

S

–V

S

R

F

0.1F

–V

0.1F

V

OUT

10F

–22–

Figure 7. An Equalizer Circuit for Composite Video Transmission over 300 m of Category 5 Cable

REV. A

20

10

–10

–20

–30

–40

–50

–60

–70

–80

FREQUENCY – Hz

I/O RESPONSE

0

10k 100k 1M 10M 100M

10

0

–10

–20

–30

–40

I/O RESPONSE

–50

–60

–70

–80

10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 8. Transmission Response of 300 m of Category 5 Cable

The feedback network is between Pins 6 and 5 and from Pin 5 to ground. C1 and R

create a corner frequency of about 800 kHz.

F

The gain increases to provide about 15 dB of boost at 8 MHz. The response of this circuit is shown in Figure 9.

20

10

0

–10

–20

–30

–40

I/O RESPONSE

–50

–60

–70

–80

10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 9. Frequency Response of Equalizer Circuit

It is difficult to come up with the exact component values via strictly mathematical means, because the equations for the cable attenuation are approximate and have functions that are not simply related to the responses of RC networks. The method used in this design was to approximate the required response via graphical means from the frequency response, and then select components that would approximate this response. The circuit was then built and measured, and finally adjusted to obtain an acceptable response—in this case flat to 9 MHz to within approximately 1 dB. (See Figure 10.)

REV. A

AD8129/AD8130

Figure 10. Combined Response of Cable Plus Equalizer

Output Offset/Level Translator

The circuit in Figure 6 has the reference input (Pin 4) tied to ground, which produces a ground-referenced output signal. If it is desired to offset the output voltage from ground, the REF input can be used. (See Figure 11). The level V output with unity gain.

+V

V

OFFSET

V

IN

AD8130

+

PD

+

–V

+V

S

0.1F10F

0.1F

V

Figure 11. The voltage applied to Pin 4 adds to the unitygain output voltage produced by VIN.

If the circuit has a gain higher than unity, the gain has to be factored in. If R

is connected to ground, the voltage applied to

G

REF will be multiplied by the gain of the circuit and appear at the output; just like a noninverting conventional op amp, This situation is not always desirable and one may want V appear at the output with unity gain.

One way to accomplish this is to drive both REF and R the desired offset signal. (See Figure 12.) Superposition can be used to solve this circuit. First break the connection between V V R

and RG. With RG grounded the gain from Pin 4 to

OFFSET

will be 1 + RF/RG. With Pin 4 grounded, the gain though

OUT

to V

G

is –RF/RG. The sum of these is +1. If V

OUT

from a low-impedance source, this will work fine. However, if the delivered offset voltage is derived from a high-impedance source, like a voltage divider, its impedance will affect the gain equation. This makes the circuit more complicated as it creates an interaction between the gain and offset voltage.

–23–

OFFSET

= V

OUT

10F

IN +VOFFSET

appears at the

OFFSET

with

G

is delivered

REF

to

AD8129/AD8130

+V

AD8129/

AD8130

+

PD

+

–V

R

F

–V

V

OFFSET

V

IN

R

G

Figure 12. In this circuit, V

+V

S

OFFSET

0.1F

0.1F10F

with unity gain. This circuit works well if the V

10F

V

=

OUT

 (1+ RF/RG) +V

V

IN

OFFSET

appears at the output

OFFSET

Source Impedance is low.

A way around this is to apply the offset voltage to a voltage divider whose attenuation factor matches the gain of the amplifier, and then apply this voltage to the high-impedance REF input. This circuit will first divide the desired offset voltage by the gain, and the amplifier will multiply it back up to unity. (See Figure 13.)

+V

AD8129/

V

OFFSET

AD8130

V

IN

R

F

R

G

R

+

R

G

+V

PD

S

–V

S

F

0.1F10F

–V

0.1F

V V

10F

=

OUT

 (1+RF/RG) + V

IN

OFFSET

Figure 13. Adding an attenuator at the offset input causes it to appear at the output with unity gain.

Resistorless Gain-of-Two

The voltage applied to the REF input (Pin 4) can also be a high bandwidth signal. If a unity-gain AD8130 has both +IN and REF driven with the same signal, there will be unity gain from

and unity gain from V

V

IN

. Thus, the circuit will have a gain

REF

of two, and requires no resistors. (See Figure 14.)

+V

V

IN

AD8130

+

PD

+V

S

–V

S

0.1F

10F

V

OUT

Summer

A general summing circuit can be made by the above technique. A unity-gain configured AD8130 has one signal applied to +IN, while the other signal is applied to REF. The output will be the sum of the two input signals. (See Figure 15.)

+V

AD8130

V1

V2

+

PD

+V

–V

S

–V

S

0.1F10F

0.1F

V

OUT

10F

= V1 + V2

Figure 15. A Summing Circuit that is Noninverting with High Input Impedance

This circuit offers several advantages over a conventional op amp inverting summing circuit. First, the inputs are both highimpedance and the circuit is noninverting. It would require significant additional circuitry to make an op amp summing circuit that has high input impedance and is noninverting.

Another advantage is that the AD8130 circuit still preserves the full bandwidth of the part. In a conventional summing circuit, the noise gain is increased for every additional input, so the bandwidth response decreases accordingly. By this technique, four signals can be summed by applying them to two AD8130s, and then summing the two outputs by a third AD8130.

Cable-Tap Amplifier

It is often desirable to have a video signal drive several different pieces of equipment. However, the cable should only be terminated once at its end point, so it is not appropriate to have a termination at each device. A “loop-through” connection allows a device to tap the video signal while not disturbing it by any excessive loading.

Such a connection, also referred to as a cable-tap amplifier, can be simply made with an AD8130. (See Figure 16.) The circuit is configured with unity gain, and if no output offset is desired, the REF pin is grounded. The negative differential input is connected directly to the shield of the cable (or an associated connector) at the point at which it wants to be “tapped.”

+V

AD8130

75

0.1F

+

PD

+V

S

–V

S

10F

V

OUT

0.1F10F

–V

Figure 14. Gain-of-Two Connections with No Resistors

VIDEO

IN

75

–V

0.1F10F

Figure 16. The AD8130 can tap the video signal at any point along the cable without loading the signal.

–24–

REV. A

AD8129/AD8130

V

IN

AGILENT

HSMS 2822

1

2

3

V

OUT

0.1F10F

–V

+V

0.1F

10F

–V

S

PD

+V

S

+

V

IN

AD8129

The center conductor connects to the positive differential input of the AD8130. The amplitude of the video signal at this point is unity, because it is between the two termination resistors. The AD8130 provides a high impedance to this signal, so it does not disturb it. A buffered, unity-gain version of the video signal appears at the output.

Power-Down

The AD8129/AD8130 have a power-down pin that can be used to lower the quiescent current when the amplifier is not being used. A logic low level on the PD pin will cause the part to power down.

Since there is no “Ground” pin on the AD8129/AD8130, there is no logic reference to interface to standard logic levels. For this reason, the reference level for the PD input is +V AD8129/AD8130 are run with +V

= 5 V, there will be direct

S

. If the

S

compatibility with logic families. However, if +VS is higher than this, a level-shift circuit will be needed to interface to conventional logic levels. A simple level-shifting circuit that is compatible with common logic families is presented in Figure 17.

+V

S

LOW=

POWER-DOWN

4.99k

1k

2N2222 OR EQ

3

PD

AD8129/

AD8130

7

+V

S

Figure 17. Circuit that Shifts the Logic Level when +VS Is Not Equal to Approximately 5 V

Extreme Operating Conditions

The AD8129/AD8130 are designed to provide high performance over a wide range of supply voltages. However, there are some extremes of operating conditions that have been observed to produce non-optimal results. One of these conditions occurs when the AD8130 is operated at unity gain with low supply voltage—less than approximately ±4 V.

At unity gain, the output drives FB directly. At supplies of ±V

S

less than approximately ±4 V and unity gain, the voltage on FB can be driven by the output too close to the rail for the circuit to stay properly biased. This can lead to a parasitic oscillation.

A way to prevent this is to limit the input signal swing with clamp diodes. Common silicon junction signal diodes like the 1N4148 have a forward bias of approximately 0.7 V when about 1 mA of current flow through them. Two series pairs of such diodes connected antiparallel across the differential inputs can be used to clamp the input signal and prevent this condition. It should be noted that the REF input can also shift the output signal, so this technique will only work when REF is at ground or close to it. (See Figure 18.)

+V

V

IN

V

IN

1N4148

AD8130

0.1F

+

PD

+V

–V

S

–V

S

0.1F10F

10F

V

OUT

Figure 18. Clamping Diodes at the Input Limit the Input Swing Amplitude

Another problem can occur with the AD8129 operating at supply voltage of greater than or equal to ±12 V. The architecture causes the supply current to increase as the input differential voltage increases. If the AD8129 differential inputs are overdriven too far, excessive current can flow in the device and potentially cause permanent damage.

A practical means to prevent this from occurring is to differentially clamp the inputs with a pair of antiparallel Schottky diodes. (See Figure 19.) These diodes have a lower forward voltage of approximately 0.4 V. If the differential voltage across the inputs is restricted to these conditions, no excess current will be drawn by the AD8129 under these operating conditions.

If the supply voltage is restricted to less than ±11 V, the internal clamping circuit will limit the differential voltage and excessive supply current will not be drawn. The external clamp circuit is not needed.

Figure 19. Schottky Diodes Across the Inputs Limits the Input Differential Voltage

In both circuits, the input series resistors function to limit the current through the diodes when they are forward-biased. As a practical matter, these resistors need to be matched to the degree that the CMRR needs to be preserved at high frequency. These resistor will have minimal effect on the CMRR at low frequency.

REV. A

–25–

AD8129/AD8130

Power Dissipation

The AD8129/AD8130 can operate with supply voltages from +5 V to ±12 V. The major reason for such a wide supply range is to provide a wide input common-mode range for systems that might require this. This would be encountered when significant common-mode noise couples into the input path. For applications that do not require a wide input or output dynamic range, it is recommended to operate with lower supply voltages.

The AD8129/AD8130 is also available in a very small Micro_SO-8 package. This has higher thermal impedance than larger packages and will operate at a higher temperature with the same amount of power dissipation. Certain operating conditions that are within the specification range of the parts can cause excess power dissipation. Caution should be exercised.

The power dissipation is a function of several operating conditions. These include the supply voltage, the input differential voltage, the output load and the signal frequency.

A basic starting point is to calculate the quiescent power dissipation with no signal and no differential input voltage. This is just the product of the total supply voltage and the quiescent operating current. The maximum operating supply voltage is 26.4 V and the quiescent current is 13 mA. This causes a quiescent power dissipation of 343 mW. For the Micro_SO package, the

θ

specification is 142°C/W. So the quiescent power will cause

JA

about a 49°C rise above ambient in the Micro_SO package.

The current consumption is also a function of the differential input voltage. (See TPCs 109 and 110.) This current should be added on to the quiescent current and then multiplied by the total supply voltage to calculate the power.

The AD8129/AD8130 can directly drive loads of as low as 100 Ω, such as a terminated 50 Ω cable. The worst-case power dissipation in the output stage occurs when the output is at midsupply. As an example, for a 12 V supply and the output driving a 250 Ω load to ground, the maximum power dissipation in the output will occur when the output voltage is 6 V.

The load current will be 6 V/250 Ω = 24 mA. This same current will flow through the output across a 6 V drop from +V will dissipate 144 mW. For the Micro_SO-8 package, this causes a temperature rise of 20°C above ambient. Although this is a worstcase number, it is apparent that this can be a considerable additional amount of power dissipation.

Several changes can be made to alleviate this. One is to use the standard SO-8 package. This will lower the thermal impedance to 121°C/W, which is a 15% improvement. Next is to use a lower supply voltage unless absolutely necessary.

Finally, do not use the AD8129/AD8130 to directly drive a heavy load when it is operating on high supply voltages. It is best to use a second op amp after the output stage. Some of the gain can be shifted to this stage so that the signal swing at the output of the AD8129/AD8130 is not too large.

Layout, Grounding and Bypassing

The AD8129/AD8130 are very high-speed parts that can be sensitive to the PCB environment in which they have to operate. Realizing their superior specifications requires attention to various details of standard high-speed PCB design practice.

The first requirement is for a good solid ground plane that covers as much of the board area around the AD8129/AD8130 as possible. The only exception to this is that the ground plane around the FB pin should be kept a few mm away, and ground should be removed from inner layers and the opposite side of the board under this pin. This will minimize the stray capacitance on this node and help preserve the gain flatness versus frequency.

The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high-frequency ceramic chip capacitors should be used. This bypassing should be done with a capacitance value of 0.01 µF to 0.1 µF for each supply. Further away, low frequency bypassing should be provided with 10 µF tantalum capacitors from each supply to ground.

The signal routing should be short and direct in order to avoid parasitic effects. Where possible, signals should be run over ground planes to avoid radiating, or to avoid being susceptible to other radiation sources.

. This

S

–26–

REV. A

0.1574 (4.00)

0.1497 (3.80)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

85

0.2440 (6.20)

0.2284 (5.80)

41

AD8129/AD8130

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)

SEATING

0.0500 (1.27) BSC

PLANE

0.122 (3.10)

0.114 (2.90)

85

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

PLANE

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

8-Lead Micro_SO

(RM-8)

0.199 (5.05)

0.187 (4.75)

41

0.043 (1.09)

0.037 (0.94)

0.0098 (0.25)

0.0075 (0.19)

0.011 (0.28)

0.003 (0.08)

0.0196 (0.50)

0.0099 (0.25)

8

0.0500 (1.27)

0

0.0160 (0.41)

0.120 (3.05)

0.112 (2.84)

33 27

 45

0.028 (0.71)

0.016 (0.41)

REV. A

–27–

AD8129/AD8130

Revision History

Location Page

3/05—Data Sheet changed from REV. 0 to REV. A

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Replaced Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

C02464–0–3/05(A)

–28–

REV. A

Datasheet AD8129 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

ORDERING GUIDE

THEORY OF OPERATION

Op Amp Configuration

APPLICATIONS

Basic Gain Circuits

Output Offset/Level Translator

Resistorless Gain-of-Two

Summer

Cable-Tap Amplifier

Power-Down

Extreme Operating Conditions

Power Dissipation

Layout, Grounding and Bypassing

OUTLINE DIMENSIONS

Revision History