ANALOG DEVICES AD8108, AD8109 Service Manual

325 MHz, 8 × 8 Buffered Video

EATURES

8 × 8 high speed nonblocking switch arrays

AD8108: G = 1

AD8109: G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple 8 × 8 arrays

to create larger switch arrays
Output disable allows connection of multiple devices
Pin-compatible with AD8110/AD8111 16 × 8 switch arrays
For 16 × 16 arrays see AD8116
Complete solution

Buffered inputs

Eight output amplifiers

AD8108 (G = 1)
AD8109 (G = 2)

Drives 150 Ω loads
Excellent video performance

60 MHz 0.1 dB gain flatness

0.02%/0.02° differential gain/differential phase error
= 150 Ω)

(R

L

Excellent ac performance

−3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)

Slew rate: 400 V/μs (AD8108), 480 V/μs (AD8109)
Low power of 45 mA
Low all hostile crosstalk of −83 dB @ 5 MHz
Reset pin allows disabling of all outputs (connected through

a capacitor to ground provides power-on reset capability)
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including

Composite video (NTSC, PAL, S, SECAM)

Component video (YUV, RGB)

Compressed video (MPEG, Wavelet)

3-level digital video (HDB3)

GENERAL DESCRIPTION

The AD8108/AD8109 are high speed 8 × 8 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
250 MHz and channel switch times of less than 25 ns with 1%
settling. With −83 dB of crosstalk and −98 dB isolation (@5 MHz),
the AD8108/AD8109 are useful in many high speed applications.
The differential gain and differential phase of better than 0.02%

Crosspoint Switches

AD8108/AD8109

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

CLK

DATA IN

UPDATE

CE

RESET

AD8108/AD8109

8 INPUTS

Figure 1. Functional Block Diagram

and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,
make the AD8108/AD8109 ideal for video signal switching.

The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral­leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of 1, while the AD8109
offers a gain of 2. They operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control allowing updating of an individual output without
re-programming the entire array.

The AD8108/AD8109 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of −40°C to +85°C.

D0 D1 D2 D3

32-BIT SHIFT REGISTER

WITH 4-BIT

PARALLEL LOADING

32

PARALLEL LATCH

32

DECODE

8  4:8 DECODERS

OUTPUT
BUFFER

64

G = +1
G = +2

SWITCH
MATRIX

SET INDIVIDUAL

OR RESET ALL

OUTPUTS
TO "OFF"

8

ENABLE/DISABLE

A0
A1
A2

DATA
OUT

8 OUTPUTS

01068-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD8108/AD8109

TABLE OF CONTENTS

AD8108/AD8109—Specifications ................................................. 3

Power-On

....................................................................... 19

RESET

Timing Characteristics (Serial) .................................................. 5

Timing Characteristics (Parallel) ............................................... 6

Absolute Maximum Ratings............................................................ 8

Maximum Power Dissipation ..................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics........................................... 11

I/O Schematics................................................................................ 17

Theory of Operation ...................................................................... 18

Applications.................................................................................18

REVISION HISTORY

9/05—Rev. A to Rev. B

Updated Format.................................................................. Universal

Change to Absolute Maximum Ratings..........................................8

Changes to Maximum Power Dissipation Section........................8

Change to Figure 4 ............................................................................8

Updated Outline Dimensions........................................................30

Changes to Ordering Guide...........................................................30

Gain Selection............................................................................. 19

Creating Larger Crosspoint Arrays.......................................... 20

Multichannel Video ................................................................... 21

Crosstalk ...................................................................................... 22

PCB Layout...................................................................................... 24

Evaluation Board ............................................................................ 28

Control the Evaluation Board from a PC................................ 28

Overshoot of PC Printer Ports’ Data Lines............................. 28

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

1/02—Rev. 0 to Rev. A

Universal change in nomenclature from MQFP to LQFP .............

Comment added to OUTLINE DIMENSIONS ..........................27

Revision 0: Initial Version

Rev. B | Page 2 of 32

AD8108/AD8109

AD8108/AD8109—SPECIFICATIONS

VS = ±5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit Reference

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p, RL = 150 Ω 240/150 325/250

2 V p-p, RL = 150 Ω 140/160 MHz

Propagation Delay 2 V p-p, RL = 150 Ω 5
Slew Rate 2 V Step, RL = 150 Ω 400/480 V/µs
Settling Time 0.1%, 2 V Step, RL = 150 Ω 40

Gain Flatness 0.05 dB, 200 mV p-p, RL = 150 Ω 60/50

0.05 dB, 2 V p-p, RL = 150 Ω 60/50

0.1 dB, 200 mV p-p, RL = 150 Ω 70/65

0.1 dB, 2 V p-p, RL = 150 Ω 80/50

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, RL = 1 kΩ 0.01
NTSC or PAL, RL = 150 Ω 0.02
Differential Phase Error NTSC or PAL, RL = 1 kΩ 0.01
NTSC or PAL, RL = 150 Ω 0.02
Crosstalk, All Hostile f = 5 MHz 83/85

f = 10 MHz 76/83

Off Isolation, Input-Output

f = 10 MHz, R
one channel

=150 Ω,

L

93/98

Input Voltage Noise 0.01 MHz to 50 MHz 15

DC PERFORMANCE

Gain Error RL = 1 kΩ 0.04/0.1 0.07/0.5 %
R

= 150 Ω 0.15/0.25 %

L

Gain Matching No load, channel-channel 0.02/1.0 %
R

= 1 kΩ, channel-channel 0.09/1.0 %

L

Gain Temperature Coefficient 0.5/8 ppm/°C

OUTPUT CHARACTERISTICS

Output Impedance DC, enabled 0.2 Ω

Disabled 10/0.001 MΩ

Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8108 only 1/NA µA
Output Voltage Range No load ±2.5 ±3 V
Output Current 20 40 mA
Short-Circuit Current 65 mA

MHz

Figure 1,
Figure 13

Figure 1,
Figure 13

ns

ns

Figure 15,
Figure 18

MHz

Figure 1,
Figure 13

MHz

Figure 1,
Figure 13

MHz

Figure 1,
Figure 13

MHz

Figure 1,
Figure 13

%
%
Degrees
Degrees
dB

Figure 8,
Figure 14

dB

Figure 8,
Figure 14

dB

Figure 23,
Figure 29

nV/√Hz Figure 20,

Figure 26

Figure 24,
Figure 30

Figure 21,
Figure 27

Rev. B | Page 3 of 32

AD8108/AD8109

Parameter Conditions Min Typ Max Unit Reference

INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) 5 20 mV

Temperature coefficient 12 µV/°C

Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any switch configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per output selected 2 5 µA

SWITCHING CHARACTERISTICS

Enable On Time 60 ns
Switching Time, 2 V Step

UPDATE to 1% settling

50%

25 ns

Switching Transient (Glitch) Measured at output 20/30 mV p-p

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 33 mA
AVCC, outputs disabled 10 mA
AVEE, outputs enabled, no load 33 mA
AVEE, outputs disabled 10 mA
DVCC 10 mA
Supply Voltage Range ±4.5 to ±5.5
PSRR f = 100 kHz 73/78

f = 1 MHz 55/58

V
dB

dB

OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 to +85
θ

JA

Operating (still air) 48

°C
°C/W

Figure 35,
Figure 41

Figure 36,
Figure 42

Figure 22,
Figure 28

Figure 19,
Figure 25

Rev. B | Page 4 of 32

AD8108/AD8109

TIMING CHARACTERISTICS (SERIAL)

Table 2. Timing Characteristics

Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t
CLK Pulse Width t
Serial Data Hold Time t
CLK Pulse Separation, Serial Mode t
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode t
Propagation Delay, UPDATE to Switch On or Off

1

2

3

4

t

5

t

6

7

–
Data Load Time, CLK = 5 MHz, Serial Mode –
CLK, UPDATE Rise and Fall Times
RESET Time

–

– 200

Table 3. Logic Levels

V

IH

RESET, SER/PAR
CLK, DATA IN,

CE, UPDATE

V

IL

RESET, SER/PAR
CLK, DATA IN,

CE, UPDATE

V

OH

V

OL

DATA OUT DATA OUT

I

IH

RESET, SER/PAR
CLK, DATA IN,

CE, UPDATE

I

RESET, SER/PAR
CLK, DATA IN,

CE, UPDATE

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min

20
100
20
100
0
50

IL

ns
ns
ns
ns
ns

ns
180 ns
8 ns

6.4

µs
100 ns

I

OH

ns

I

OL

DATA OUT DATA OUT

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

t

1

0

t1t

1

OUT7 (D3)

0

2

3

t

7

t

4

LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE

OUT7 (D2)

TRANSFER DATA FROM SERIAL

Figure 2. Timing Diagram, Serial Mode

OUT00 (D0)

t

5

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

t

6

01068-002

Rev. B | Page 5 of 32

AD8108/AD8109

T

TIMING CHARACTERISTICS (PARALLEL)

Table 4. Timing Characteristics

Parameter Symbol Min Typ Max Unit

Data Setup Time t
CLK Pulse Width t
Data Hold Time t
CLK Pulse Separation t
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time

1

2

3

4

t

5

t

6

–
–
– 200

Table 5. Logic Levels

V

IH

RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2

CE, UPDATE

V

IL

RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2

CE, UPDATE

V

OH

V

OL

DATA OUT DATA OUT

I

IH

RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2

CE, UPDATE

I

RESET SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2

CE, UPDATE

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min

20
100
20
100
0
50

IL

ns
ns
ns
ns
ns

ns
8 ns
100 ns

I

OH

ns

I

OL

DATA OUT DATA OUT

CLK

D0–D3
A0–A2

1 = LATCHED

0 = TRANSPAREN

UPDATE

t

1

0

t

1

1

0

2

t

3

Figure 3. Timing Diagram, Parallel Mode

t

4

t5t

6

01068-003

Rev. B | Page 6 of 32

AD8108/AD8109

A

Table 6. Operation Truth Table

/

SER

UPDATE

CE

CLK DATA IN DATA OUT

1 X X X X X X No change in logic.
0 1

0 1

f

f

Data

i

D0 … D3,
A0 … A2

Data

i-32

NA in parallel
mode

0 0 X X… X 1 X

X X X X X 0 X

D0

PARALLEL DAT

(OUTPUT ENABLE)

SER/PAR

DATA IN

(SERIAL)

D1
D2
D3

S

D1

Q

D0

D
CLK

S

D1

Q

Q

DQ

D0

CLK

RESET

1 0

1 1

S

D1

DQ

Q

D0

CLK

PAR

Operation/Comment

The data on the serial DATA IN line is loaded into serial register. The
first bit clocked into the serial register appears at DATA OUT 32 clocks
later.

The data on the parallel data lines, D0 to D3, are loaded into the
32-bit serial shift register location addressed by A0 to A2.

Data in the 32-bit shift register transfers into the parallel latches that
control the switch array. Latches are transparent.

Asynchronous operation. All outputs are disabled. Remainder of logic
is unchanged.

S

D1

Q

D0

DQ

CLK

S

D1

DQ

Q

D0

CLK

S

D1

Q

D0

DQ

CLK

S

D1

Q

D0

DQ
CLK

S

D1

Q

D0

DQ
CLK

S

D1

Q

D0

DQ
CLK

S

D1

Q

Q

D
CLK

DATA
OUT

D0

CLK

CE

RESET

OUT0 EN

OUT1 EN

OUT2 EN

A0

OUT3 EN

A1

OUT4 EN

A2

OUT5 EN

3 TO 8 DECODER

OUT6 EN

OUT7 EN

LE

OUT0

LE
OUT0

B1

D

Q

D

B0

Q

LE

OUT0

D

B2

Q

LE
OUT0

EN

D

QCLR

D

LE
OUT1

B0

Q

DECODE

64

LE

OUT6

D

EN

QCLR

LE
OUT7

B0

D

Q

LE

OUT7

D

B1

Q

OUTPUT ENABLESWITCH MATRIX

LE

OUT7

B2

8

D

Q

LE
OUT7

EN

D

QCLR

01068-011

Figure 4. Logic Diagram

Rev. B | Page 7 of 32

AD8108/AD8109

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage 12.0 V
Internal Power Dissipation

1

AD8108/AD8109 80-Lead Plastic LQFP (ST) 2.6 W
Input Voltage ±V
Output Short-Circuit Duration

S

Observe power
derating curves

Storage Temperature Range

1

Specification is for device in free air (TA = 25°C):

80-lead plastic LQFP (ST): θ

2

Maximum reflow temperatures are to JEDEC industry standard J-STD-020.

2

= 48°C/W.

JA

−65°C to +125°C

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8108/AD8109 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 125°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 125°C for an extended
period can result in device failure.

While the AD8108/AD8109 are internally short-circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (125°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 5.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

5.0

4.0

3.0

2.0

1.0

MAXIMUM POWER DISSIPATION (Ω)

0

–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70

Figure 5. Maximum Power Dissipation vs. Temperature

AMBIENT TEMPERATURE (°C)

TJ = 125°C

90

01068-004

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 8 of 32

AD8108/AD8109

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND79DVCC78NC77NC76NC75NC74NC73NC72NC71NC70NC69NC68NC67NC66NC65NC64NC63DVCC62DGND61RESET

80

IN00

AGND

IN01

AGND

IN02

AGND

IN03

AGND

IN04

AGND

IN05

AGND

IN06

AGND

IN07

AGND

AVEE

AVCC

AVCC07

OUT07

1

PIN 1

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

AD8108/AD8109

TOP VIEW

(Not to Scale)

28

29

30

31

32

33

34

35

36

37

38

60

CE

59

DATA OUT

58

CLK

57

DATA IN

56

UPDATE

55

SER/PAR

54

A0

53

A1

52

A2

51

D0

50

D1

49

D2

48

D3

47

NC

46

AGND

45

AVEE

44

AVCC

43

AVCC00

42

AGND00

41

OUT00

39

40

NC = NO CONNECT

AGND07

OUT06

AVEE06/07

OUT05

AGND06

AVCC05/06

AGND06

OUT04

AVEE04/05

OUT03

AGND04

AVCC03/04

AGND03

AVEE02/03

OUT02

OUT01

AGND02

AVCC01/02

AGND01

AVEE00/01

01068-005

Figure 6. Pin Configuration

Rev. B | Page 9 of 32

AD8108/AD8109

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3, 5, 7, 9, 11, 13, 15 INxx Analog Inputs. xx = Channels 00 through 07.
57 DATA IN Serial Data Input, TTL Compatible.
58 CLK Clock, TTL Compatible. Falling edge triggered.
59 DATA OUT Serial Data Output, TTL Compatible.
56 UPDATE

61
60
55
41, 38, 35, 32, 29, 26, 23, 20 OUTyy Analog Outputs. yy = Channels 00 through 07.
2, 4, 6, 8, 10, 12, 14, 16, 46 AGND Analog Ground for Inputs and Switch Matrix.
63, 79 DVCC 5 V for Digital Circuitry

62, 80 DGND Ground for Digital Circuitry
17, 45 AVEE −5 V for Inputs and Switch Matrix.
18, 44 AVCC +5 V for Inputs and Switch Matrix.
42, 39, 36, 33, 30, 27, 24, 21 AGNDxx Ground for Output Amp. xx = Output Channels 00 through 07. Must be connected.
43, 37, 31, 25, 19 AVCCxx/yy +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
40, 34, 28, 22 AVEExx/yy −5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
54 A0 Parallel Data Input, TTL Compatible (output select LSB).
53 A1 Parallel Data Input, TTL Compatible (output select).
52 A2 Parallel Data Input, TTL Compatible (output select MSB).
51 D0 Parallel Data Input, TTL Compatible (input select LSB).
50 D1 Parallel Data Input, TTL Compatible (input select).
49 D2 Parallel Data Input, TTL Compatible (input select MSB).
48 D3 Parallel Data Input, TTL Compatible (output enable).
47, 64 to 78 NC No Connect.

RESET
CE
SER/PAR

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data
latched when high.

Disable Outputs, Active Low.
Chip Enable, Enable Low. Must be low to clock in and latch data.
Selects Serial Data Mode, Low or Parallel, High. Must be connected.

Rev. B | Page 10 of 32