ANALOG DEVICES AD8105 Service Manual

600 MHz, 32 × 16 Buffered

FEATURES

High channel count, 32 × 16 high speed, nonblocking

switch array Differential or single-ended operation Differential G = +1 (AD8104) or G = +2 (AD8105) Pin compatible with Flexible power supplies

Single +5 V supply, or dual ±2.5 V supplies Serial or parallel programming of switch array High impedance output disable allows connection of

multiple devices with minimal loading on output bus Excellent video performance

>50 MHz 0.1 dB gain flatness

0.05% differential gain error (R

0.05° phase error (R

Excellent ac performance

Bandwidth: 600 MHz

Slew rate: 1800 V/μs

Settling time: 2.5 ns to 1% Low power of 1.7 W Low all hostile crosstalk

< −70 dB @ 5 MHz

< −40 dB @ 600 MHz Reset pin allows disabling of all outputs (connected through

a capacitor to ground provides power-on reset capability) 304-ball BGA package (31 mm × 31 mm)

AD8117/AD8118, 32 × 32 switch arrays

= 150 Ω)

L

= 150 Ω)

L

SER/PAR

WE

CLK

DATA IN

UPDATE

RESET

32 INPUT PAIRS

Analog Crosspoint Switch

AD8104/AD8105

FUNCTIONAL BLOCK DIAGRAM

D0 D1 D2 D3 D4 D5 VDD DGND

AD8104/ AD8105

1

0

INPUT

RECEIVER

G = +1* G = +2**

192-BIT SHIFT REGISTER

WITH 6-BIT

PARALLEL LOADING

96

PARALLEL LATCH

96

DECODE

16 × 6:32 DECODERS

512

OUTPUT BUFFER

SWITCH MATRIX

NO

CONNECT

16

G = +1

96

ENABLE/DISABLE

A0 A1 A2 A3

DATA OUT

SET INDIVIDUAL, OR

RESET ALL OUTPUTS TO OFF

22

16 OUTPUT PAIRS

APPLICATIONS

Routing of high speed signals including

RGB and component video routing

KVM

Compressed video (MPEG, wavelet)

Data communications

GENERAL DESCRIPTION

The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint switch matrices. They offer 600 MHz bandwidth and slew rate of 1800 V/µs for high resolution computer graphics (RGB) signal switching. With less than −70 dB of crosstalk and −90 dB isolation (@ 5 MHz), the AD8104/AD8105 are useful in many high speed applications. The 0.1 dB flatness, which is greater than 50 MHz, makes the AD8104/AD8105 ideal for composite video switching.

The AD8104/AD8105 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus. The AD8104 has a differential gain of +1,

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

*AD8104 ONLY

**AD8105 ONLY

VPOS VNEG VOCM

Figure 1.

while the AD8105 has a differential gain of +2 for ease of use in back-terminated load applications. They operate as fully differential devices or can be configured for single-ended operation. Either a single +5 V supply or dual ±2.5 V supplies can be used, while consuming only 340 mA of idle current with all outputs enabled. The channel switching is performed via a double-buffered, serial digital control (which can accommodate daisy-chaining of several devices), or via a parallel control, allowing updating of an individual output without reprogramming the entire array.

The AD8104/AD8105 are packaged in a 304-ball BGA package and are available over the extended industrial temperature range of −40°C to +85°C.

06612-001

AD8104/AD8105

REVISION HISTORY

6/07—Revision 0: Initial Version

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Truth Table and Logic Diagram ............................................... 13

I/O Schematics................................................................................ 15

Typical Performance Characteristics........................................... 17

Theory of Operation ...................................................................... 25

Applications Information.............................................................. 26

Programming.............................................................................. 26

Operating Modes........................................................................ 27

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Rev. 0 | Page 2 of 36

AD8104/AD8105

SPECIFICATIONS

VS = ±2.5 V at TA = 25°C, R

Table 1.

AD8104/AD8105 Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p, typical channel 2 V p-p, typical channel 420/525 MHz Gain Flatness 0.1 dB, 200 mV p-p 100/50 MHz

0.1 dB, 2 V p-p 70/50 MHz Propagation Delay 2 V p-p 1.3 ns Settling Time 1%, 2 V step 2.5 ns Slew Rate 2 V step, peak 1800 V/µs 2 V step, 10% to 90% 1500 V/µs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, RL = 150 Ω 0.05 % Differential Phase Error NTSC or PAL, RL = 150 Ω 0.05 Degrees Crosstalk, All Hostile f = 5 MHz −80/−70 dB f = 10 MHz −72/−68 dB f = 100 MHz −48/−50 dB f = 600 MHz −40/−50 dB Off Isolation, Input-to-Output f = 10 MHz, one channel −90 dB Input Voltage Noise 0.1 MHz to 50 MHz 45/53 nV/√Hz

DC PERFORMANCE

Voltage Gain Differential +1/+2 V/V Gain Error ±1 % No load ±1 ±3 % Gain Matching Channel-to-channel ±1 % Differential Offset ±5 ±25 mV Common-Mode Offset ±25 ±90 mV

OUTPUT CHARACTERISTICS

Output Impedance DC, enabled 0.1 Ω Disabled, differential 30 kΩ Output Disable Capacitance Disabled 4 pF Output Leakage Current Disabled 1 µA Output Voltage Range No load 2.8 3.8 V p-p V

Input Range V

OCM

V Output Swing Limit Single-ended output −1.3 +1.3 V Output Current Maximum operating signal 30 mA

INPUT CHARACTERISTICS

Input Voltage Range Common mode, V Differential 2/1 V Common-Mode Rejection Ratio f = 10 MHz 48 dB Input Capacitance Any switch configuration 2 pF Input Resistance Differential 5 kΩ Input Offset Current 1 A V

Input Bias Current 64 µA

OCM

V

Input Impedance 4 kΩ

OCM

= 200 Ω, V

L, diff

= 0 V, differential I/O mode, unless otherwise noted.

OCM

= 2 V p-p −0.5 +0.8 V

OUT, diff

= 2.8 V p-p −0.25 +0.6 V

OUT, diff

= 2 V p-p −2 +2 V

IN, diff

600 MHz

Rev. 0 | Page 3 of 36

AD8104/AD8105

AD8104/AD8105 Parameter Conditions Min Typ Max Unit

SWITCHING CHARACTERISTICS

Enable On Time 50% update to 1% settling 100 ns Switching Time, 2 V Step 50% update to 1% settling 100 ns Switching Transient (Glitch) Differential 40 mV p-p

POWER SUPPLIES

Supply Current VPOS, outputs enabled, no load 340 420 mA VPOS, outputs disabled 210 240 mA VNEG, outputs enabled, no load 340 420 mA VNEG, outputs disabled 210 240 mA VDD, outputs enabled, no load 1.2 mA Supply Voltage Range 4.5 to 5.5 V

PSRR VNEG, VPOS, f = 1 MHz 85 dB VOCM, f = 1 MHz 75 dB OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 to +85 °C

θJA Operating (still air) 14 °C/W

θJC Operating (still air) 1 °C/W

Rev. 0 | Page 4 of 36

AD8104/AD8105

TIMING CHARACTERISTICS (SERIAL MODE)

Specifications subject to change without notice.

Table 2.

Limit Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 40 ns

t

CLK Pulse Width Serial Data Hold Time t3 50 ns CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid Propagation Delay, UPDATE to Switch On or Off RESET Pulse Width RESET Time

1

WE

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

0

1

0

t1t

1

OUT15 (D5)

0

1

0

t

2

3

t

7

t

4

Figure 2. Timing Diagram, Serial Mode

50 ns

2

t

150 ns

4

t

10 ns

5

t

90 ns

6

t

120 ns

7

100 ns 60 ns 200 ns

LOAD DATA INT O SERIAL REGISTER ON FALLING EDGE

OUT15 (D4) OUT0 (D0)

t

5

TRANSFER DATA FROM SERIAL

REGISTE R TO PARAL LEL

LATCHES DURING LOW L EV E L

t

6

06612-002

Table 3. Logic Levels

VIH VIL V

RESET,

/PAR, CLK,

SER DATA IN, UPDATE

,

RESET

/PAR, CLK,

SER DATA IN, UPDATE

2.0 V min 0.6 V max

1

See Figure 15.

V

OH

DATA OUT DATA OUT

VDD − 0.3 V min

DGND +

0.5 V max

I

OL

I

IH

1

RESET

/PAR, CLK,

SER DATA IN, UPDATE

1 μA max –1 μA min −1 mA max 1 mA min

Rev. 0 | Page 5 of 36

I

IL

1

,

RESET SER DATA IN, UPDATE

,

/PAR, CLK,

I

OH

DATA OUT DATA OUT

OL

AD8104/AD8105

TIMING CHARACTERISTICS (PARALLEL MODE)

Specifications subject to change without notice.

Table 4.

Limit Parameter Symbol Min Typ Max Unit

Parallel Data Setup Time t1 80 ns

t

WE Pulse Width Parallel Data Hold Time t3 150 ns WE Pulse Separation WE to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off RESET Pulse Width RESET Time

WE

D0 TO D5 A0 TO A3

1 = LATCHED

0 = TRANSPARENT

UPDATE

t

1

0

t1t

1

0

2

3

t

4

Figure 3. Timing Diagram, Parallel Mode

110 ns

2

t

90 ns

4

t

10 ns

5

t

90 ns

6

100 ns 60 ns 200 ns

t

5

6

06612-003

Table 5. Logic Levels

VIH VIL V

RESET, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0,

A1, A2, A3, UPDATE

RESET, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0,

A1, A2, A3, UPDATE

V

OH

I

OL

DATA OUT DATA OUT

I

IH

RESET1, SER/PAR, WE, D0, D1, D2, D3, D4,

D5, A0, A1, A2, A3, UPDATE

I

IL

RESET1, SER/PAR, WE, D0, D1, D2, D3, D4, D5, A0, A1,

A2, A3,

UPDATE

I

OH

OL

DATA OUT DATA OUT

2.0 V min 0.6 V max Disabled Disabled 1 µA max –1 µA min Disabled Disabled

1

See Figure 15.

Rev. 0 | Page 6 of 36

AD8104/AD8105

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Supply Voltage

6 V

(VPOS – VNEG)

Digital Supply Voltage

6 V

(VDD – DGND)

Ground Potential Difference

+0.5 V to −2.5 V

(VNEG – DGND)

Maximum Potential Difference

8 V

(VDD – VNEG)

Common-Mode Analog Input

VNEG to VPOS

Voltage Differential Analog Input Voltage ±2 V Digital Input Voltage VDD Output Voltage

(VPOS − 1 V) to (VNEG + 1 V)

(Disabled Analog Output) Output Short-Circuit Duration Momentary Output Short-Circuit Current 80 mA Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

300°C

(Soldering, 10 sec) Junction Temperature 150°C

POWER DISSIPATION

The AD8104/AD8105 are operated with ±2.5 V or +5 V supplies and can drive loads down to 100 , resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature.

Packaged in a 304-ball BGA, the AD8104/AD8105 junction-toambient thermal impedance (θ reliability, the maximum allowed junction temperature of the die should not exceed 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. The following curve shows the range of allowed internal die power dissipations that meet these conditions over the −40°C to +85°C ambient temperature range. When using Tabl e 6 , do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors.

8

) is 14°C/W. For long-term

JA

TJ = 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC θJB ψJT ψJB Unit

304-Ball BGA 14 1 6.5 0.6 5.7 °C/W

7

6

MAXIMUM POWER (W)

5

4

25 35 45 55 65 75

15 85

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

06612-004

Rev. 0 | Page 7 of 36

AD8104/AD8105

AA

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

VPOS

A

VPOS

B

VPOS

C

VPOS

IN16

D

VNEG

IN17

IP16

E

VNEG

IP17

IN18

F

VNEG

IN19

IP18

G

VNEG

IP19

IN20

H

VNEG

IN21

IP20

J

VNEG

IP21

IN22

K

VPOS

IN23

IP22

L

VPOS

IP23

IN24

M

VPOS

IN25

IP24

N

VNEG

IP25

IN26

P

VNEG

IN27

IP26

R

VNEG

IP27

IN28

T

VNEG

IN29

IP28

U

VNEG

IP29

IN30

V

VNEG

IN31

IP30

W

VPOS

IP31

VPOS

Y

VPOS

B

VPOS

C

NC

VPOS

VNEG

VOCM

VDD

DGND

RESET

WE

D5

D4

D3

D2

D1

D0

VDD

DGND

VOCM

VNEG

VPOS

ON15

NC

VNEG

VOCM

VNEG

ON14

OP15

NC

VNEG

OP14

ON13

NC

VNEG

ON12

OP13

NC

VNEG

NC NC NC NC NC N C NC NC NC

NC

NC NC NC NC NC N C NC NC NC

VNEG

VNEG VPO S VPOS VPOS VNEG VNEG VNEG VNEG VNEG

VNEG

VNEG VPO S VPOS VPOS VNEG VNEG VNEG VNEG VNEG

AD8104/AD8105

BOTTOM VIEW

(Not to Scale)

VNEG

OP12

ON11

VNEG VPO S VPOS VPOS VNEG VNEG VNEG VNEG VNEG

VNEG

VNEG VPO S VPOS VPOS VNEG VNEG VNEG VNEG VNEG

ON10

OP10 O N8 OP8 ON6 OP6 ON4 OP4 ON2 O P2

OP11 ON9 OP9 ON7 OP7 ON5 OP5 ON3 OP3 ON1

NC

VNEG

VOCM

VNEG

ON0

OP1

NC

VPOS

VNEG

VOCM

VDD

DGND

DATA

OUT

CLK

DATA

IN

SER/ PAR

DGND

A3

A2

A1

A0

VDD

DGND

VOCM

VNEG

VPOS

OP0

VPOS

VNEG

VPOS

VNEG

VPOS

IP0

IN0

IP2

IN2

IP4

IN4

IP6

IN6

IP8

IN8

IP10

IN10

IP12

IN12

IP14

IN14

VPOS

IP1

IN1

IP3

IN3

IP5

IN5

IP7

IN7

IP9

IN9

IP11

IN11

IP13

IN13

IP15

IN15

VPOS

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 5. Package Bottom View

Rev. 0 | Page 8 of 36

6612-005

AD8104/AD8105

VPOS

NC

AA

AB

AC

VPOS

VNEG

VOCM

VDD

DGND

DATA

OUT

CLK

DATA

IN

SER/

PAR

DGND

A3

A2

A1

A0

VDD

DGND

VOCM

VNEG

VPOS

OP0

VPOS

NC

VNEG

VOCM

VNEG

ON0

OP1

AD8104/AD8105

TOP VIEW

(Not to Scale)

A

VPOS

IP0

IN0

IP2

IN2

IP4

IN4

IP6

IN6

IP8

IN8

IP10

IN10

IP12

IN12

IP14

IN14

VPOS

VNEG

VPOS

VNEG

VPOS

B

VPOS

C

VPOS

D

IP1

E

IN1

F

IP3

G

IN3

H

IP5

J

IN5

K

IP7

L

IN7

M

IP9

N

IN9

P

IP11

R

IN11

T

IP13

U

IN13

V

IP15

W

IN15

Y

VPOS

NC

VNEG

OP14

ON13

NC

VNEG

VOCM

VNEG

ON14

OP15

NCNCNCNCNCNCNCNCNC

NC

VNEG

OP12

ON11

NC

VNEG

ON12

OP13

NCNCNCNCNCNCNCNCNC

VNEG

VNEGVPOSVPOSVPO SVNEGVNEGVNEGVNEGVNEG

VNEG

VNEGVPOSVPOSVPO SVNEGVNEGVNEGVNEGVNEG

VNEG

VNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEG

VNEG

VNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEG

ON10

OP10ON8OP8ON6OP6ON4OP4ON2OP2

OP11ON9OP9ON7OP7ON5OP5ON3OP3ON1

VPOS

NC

VPOS

VNEG

VOCM

VDD

DGND

RESET

WE

D5

D4

D3

D2

D1

D0

VDD

DGND

VOCM

VNEG

VPOS

ON15

21 22 232019181716151413121110987654321

VPOS

VNEG

VPOS

VNEG

VPOS

IN17

IP17

IN19

IP19

IN21

IP21

IN23

IP23

IN25

IP25

IN27

IP27

IN29

IP29

IN31

IP31

VPOS

IN16

IP16

IN18

IP18

IN20

IP20

IN22

IP22

IN24

IP24

IN26

IP26

IN28

IP28

IN30

IP30

VPOS

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

Table 8. Ball Grid Description

Ball No. Mnemonic Description A1 VPOS Analog Positive Power Supply. A2 VPOS Analog Positive Power Supply. A3 VPOS Analog Positive Power Supply. A4 NC No Connect. A5 NC No Connect. A6 NC No Connect. A7 NC No Connect. A8 NC No Connect. A9 NC No Connect. A10 NC No Connect. A11 NC No Connect. A12 NC No Connect. A13 NC No Connect. A14 NC No Connect.

Figure 6. Package Top View

Ball No. Mnemonic Description A15 NC No Connect. A16 NC No Connect. A17 NC No Connect. A18 NC No Connect. A19 NC No Connect. A20 VPOS Analog Positive Power Supply. A21 VPOS Analog Positive Power Supply. A22 VPOS Analog Positive Power Supply. A23 VPOS Analog Positive Power Supply. B1 VPOS Analog Positive Power Supply. B2 VPOS Analog Positive Power Supply. B3 VPOS Analog Positive Power Supply. B4 VPOS Analog Positive Power Supply. B5 NC No Connect.

Rev. 0 | Page 9 of 36

2322212019181716151413121110987654321

6612-006

AD8104/AD8105

Ball No. Mnemonic Description B6 NC No Connect. B7 NC No Connect. B8 NC No Connect. B9 NC No Connect. B10 NC No Connect. B11 NC No Connect. B12 NC No Connect. B13 NC No Connect. B14 NC No Connect. B15 NC No Connect. B16 NC No Connect. B17 NC No Connect. B18 NC No Connect. B19 NC No Connect. B20 NC No Connect. B21 VPOS Analog Positive Power Supply. B22 VPOS Analog Positive Power Supply. B23 VPOS Analog Positive Power Supply. C1 VPOS Analog Positive Power Supply. C2 VPOS Analog Positive Power Supply. C3 VPOS Analog Positive Power Supply. C4 VPOS Analog Positive Power Supply. C5 VNEG Analog Negative Power Supply. C6 VNEG Analog Negative Power Supply. C7 VNEG Analog Negative Power Supply. C8 VNEG Analog Negative Power Supply. C9 VNEG Analog Negative Power Supply. C10 VNEG Analog Negative Power Supply. C11 VPOS Analog Positive Power Supply. C12 VPOS Analog Positive Power Supply. C13 VPOS Analog Positive Power Supply. C14 VNEG Analog Negative Power Supply. C15 VNEG Analog Negative Power Supply. C16 VNEG Analog Negative Power Supply. C17 VNEG Analog Negative Power Supply. C18 VNEG Analog Negative Power Supply. C19 VNEG Analog Negative Power Supply. C20 VPOS Analog Positive Power Supply. C21 VPOS Analog Positive Power Supply. C22 VPOS Analog Positive Power Supply. C23 VPOS Analog Positive Power Supply. D1 VPOS Analog Positive Power Supply. D2 IP0 Input Number 0, Positive Phase. D3 VPOS Analog Positive Power Supply. D4 VNEG Analog Negative Power Supply. D5 VOCM

D6 VNEG Analog Negative Power Supply. D7 VNEG Analog Negative Power Supply. D8 VNEG Analog Negative Power Supply. D9 VNEG Analog Negative Power Supply. D10 VNEG Analog Negative Power Supply. D11 VPOS Analog Positive Power Supply.

Output Common-Mode Reference Supply.

Ball No. Mnemonic Description D12 VPOS Analog Positive Power Supply. D13 VPOS Analog Positive Power Supply. D14 VNEG Analog Negative Power Supply. D15 VNEG Analog Negative Power Supply. D16 VNEG Analog Negative Power Supply. D17 VNEG Analog Negative Power Supply. D18 VNEG Analog Negative Power Supply. D19 VOCM

D20 VNEG Analog Negative Power Supply. D21 VPOS Analog Positive Power Supply. D22 VPOS Analog Positive Power Supply.

D23 IN16 Input Number 16, Negative Phase. E1 IP1 Input Number 1, Positive Phase. E2 IN0 Input Number 0, Negative Phase. E3 VNEG Analog Negative Power Supply. E4 VOCM

E20 VOCM

E21 VNEG Analog Negative Power Supply. E22 IN17 Input Number 17, Negative Phase. E23 IP16 Input Number 16, Positive Phase. F1 IN1 Input Number 1, Negative Phase. F2 IP2 Input Number 2, Positive Phase. F3 VNEG Analog Negative Power Supply. F4 VDD Logic Positive Power Supply. F20 VDD Logic Positive Power Supply. F21 VNEG Analog Negative Power Supply. F22 IP17 Input Number 17, Positive Phase. F23 IN18 Input Number 18, Negative Phase. G1 IP3 Input Number 3, Positive Phase. G2 IN2 Input Number 2, Negative Phase. G3 VNEG Analog Negative Power Supply. G4 DGND Logic Negative Power Supply. G20 DGND Logic Negative Power Supply. G21 VNEG Analog Negative Power Supply. G22 IN19 Input Number 19, Negative Phase. G23 IP18 Input Number 18, Positive Phase. H1 IN3 Input Number 3, Negative Phase. H2 IP4 Input Number 4, Positive Phase. H3 VNEG Analog Negative Power Supply. H4 DATA OUT Control Pin: Serial Data Out. H20

H21 VNEG Analog Negative Power Supply. H22 IP19 Input Number 19, Positive Phase. H23 IN20 Input Number 20, Negative Phase. J1 IP5 Input Number 5, Positive Phase. J2 IN4 Input Number 4, Negative Phase. J3 VNEG Analog Negative Power Supply. J4

J20

RESET

CLK UPDATE

Output Common-Mode Reference Supply.

Control Pin: Second Rank Data Reset.

Control Pin: Serial Data Clock. Control Pin: Second Rank Write Strobe.

Rev. 0 | Page 10 of 36

AD8104/AD8105

Ball No. Mnemonic Description J21 VNEG Analog Negative Power Supply. J22 IN21 Input Number 21, Negative Phase. J23 IP20 Input Number 20, Positive Phase. K1 IN5 Input Number 5, Negative Phase. K2 IP6 Input Number 6, Positive Phase. K3 VNEG Analog Negative Power Supply. K4 DATA IN Control Pin: Serial Data In. K20 K21 VNEG Analog Negative Power Supply. K22 IP21 Input Number 21, Positive Phase. K23 IN22 Input Number 22, Negative Phase. L1 IP7 Input Number 7, Positive Phase. L2 IN6 Input Number 6, Negative Phase. L3 VPOS Analog Positive Power Supply. L4 L20 D5 Control Pin: Input Address Bit 5. L21 VPOS Analog Positive Power Supply. L22 IN23 Input Number 23, Negative Phase. L23 IP22 Input Number 22, Positive Phase. M1 IN7 Input Number 7, Negative Phase. M2 IP8 Input Number 8, Positive Phase. M3 VPOS Analog Positive Power Supply. M4 DGND Logic Negative Power Supply M20 D4 Control Pin: Input Address Bit 4. M21 VPOS Analog Positive Power Supply. M22 IP23 Input Number 23, Positive Phase. M23 IN24 Input Number 24, Negative Phase. N1 IP9 Input Number 9, Positive Phase. N2 IN8 Input Number 8, Negative Phase. N3 VPOS Analog Positive Power Supply. N4 A3 Control Pin: Output Address Bit 3. N20 D3 Control Pin: Input Address Bit 3. N21 VPOS Analog Positive Power Supply. N22 IN25 Input Number 25, Negative Phase. N23 IP24 Input Number 24, Positive Phase. P1 IN9 Input Number 9, Negative Phase. P2 IP10 Input Number 10, Positive Phase. P3 VNEG Analog Negative Power Supply. P4 A2 Control Pin: Output Address Bit 2. P20 D2 Control Pin: Input Address Bit 2. P21 VNEG Analog Negative Power Supply. P22 IP25 Input Number 25, Positive Phase. P23 IN26 Input Number 26, Negative Phase. R1 IP11 Input Number 11, Positive Phase. R2 IN10 Input Number 10, Negative Phase. R3 VNEG Analog Negative Power Supply. R4 A1 Control Pin: Output Address Bit 1. R20 D1 Control Pin: Input Address Bit 1. R21 VNEG Analog Negative Power Supply. R22 IN27 Input Number 27, Negative Phase. R23 IP26 Input Number 26, Positive Phase. T1 IN11 Input Number 11, Negative Phase.

WE

SER/PAR

Control Pin: First Rank Write Strobe.

Control Pin: Serial/Parallel Mode Select.

Ball No. Mnemonic Description T2 IP12 Input Number 12, Positive Phase. T3 VNEG Analog Negative Power Supply. T4 A0 Control Pin: Output Address Bit 0. T20 D0 Control Pin: Input Address Bit 0. T21 VNEG Analog Negative Power Supply. T22 IP27 Input Number 27, Positive Phase. T23 IN28 Input Number 28, Negative Phase.

U1 IP13 Input Number 13, Positive Phase. U2 IN12 Input Number 12, Negative Phase. U3 VNEG Analog Negative Power Supply. U4 VDD Logic Positive Power Supply. U20 VDD Logic Positive Power Supply. U21 VNEG Analog Negative Power Supply. U22 IN29 Input Number 29, Negative Phase. U23 IP28 Input Number 28, Positive Phase.

V1 IN13 Input Number 13, Negative Phase. V2 IP14 Input Number 14, Positive Phase. V3 VNEG Analog Negative Power Supply. V4 DGND Logic Negative Power Supply. V20 DGND Logic Negative Power Supply. V21 VNEG Analog Negative Power Supply. V22 IP29 Input Number 29, Positive Phase. V23 IN30 Input Number 30, Negative Phase. W1 IP15 Input Number 15, Positive Phase. W2 IN14 Input Number 14, Negative Phase. W3 VNEG Analog Negative Power Supply. W4 VOCM

W20 VOCM

W21 VNEG Analog Negative Power Supply. W22 IN31 Input Number 31, Negative Phase. W23 IP30 Input Number 30, Positive Phase. Y1 IN15 Input Number 15, Negative Phase. Y2 VPOS Analog Positive Power Supply. Y3 VPOS Analog Positive Power Supply. Y4 VNEG Analog Negative Power Supply. Y5 VOCM

Y6 VNEG Analog Negative Power Supply. Y7 VNEG Analog Negative Power Supply. Y8 VNEG Analog Negative Power Supply. Y9 VNEG Analog Negative Power Supply. Y10 VNEG Analog Negative Power Supply. Y11 VPOS Analog Positive Power Supply. Y12 VPOS Analog Positive Power Supply. Y13 VPOS Analog Positive Power Supply. Y14 VNEG Analog Negative Power Supply. Y15 VNEG Analog Negative Power Supply. Y16 VNEG Analog Negative Power Supply. Y17 VNEG Analog Negative Power Supply. Y18 VNEG Analog Negative Power Supply.

Output Common-Mode Reference Supply.

Rev. 0 | Page 11 of 36

ANALOG DEVICES AD8105 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS (SERIAL MODE)

TIMING CHARACTERISTICS (PARALLEL MODE)

ABSOLUTE MAXIMUM RATINGS

POWER DISSIPATION

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS