ANALOG DEVICES AD8065, AD8066 Service Manual

High Performance, 145 MHz

V

FEATURES

Qualified for automotive applications
FET input amplifier
1 pA input bias current
Low cost
High speed: 145 MHz, −3 dB bandwidth (G = +1)
180 V/μs slew rate (G = +2)
Low noise

7 nV/√Hz (f = 10 kHz)

0.6 fA/√Hz (f = 10 kHz)
Wide supply voltage range: 5 V to 24 V
Single-supply and rail-to-rail output
Low offset voltage 1.5 mV maximum
High common-mode rejection ratio: −100 dB
Excellent distortion specifications
SFDR −88 dBc @ 1 MHz
Low power: 6.4 mA/amplifier typical supply current
No phase reversal
Small packaging: SOIC-8, SOT-23-5, and MSOP-8

GENERAL DESCRIPTION

The AD8065/AD80661 FastFET™ amplifiers are voltage feedback
amplifiers with FET inputs offering high performance and ease
of use. The AD8065 is a single amplifier, and the AD8066 is a
dual amplifier. These amplifiers are developed in the Analog
Devices, Inc. proprietary XFCB process and allow exceptionally
low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as
very high input impedance.

With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of applications.
For added versatility, the amplifiers also contain rail-to-rail outputs.

Despite the low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02%
and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/μs, excellent distortion (SFDR
of −88 dBc @ 1 MHz), extremely high common-mode rejection
of −100 dB, and a low input offset voltage of 1.5 mV maximum
under warmed up conditions. The AD8065/AD8066 operate
using only a 6.4 mA/amplifier typical supply current and are
capable of delivering up to 30 mA of load current.

1

Protected by U. S. Patent No. 6,262,633.

FastFET Op Amps

AD8065/AD8066

APPLICATIONS

Automotive driver assistance systems
Photodiode preamps
Filters
A/D drivers
Level shifting
Buffering

CONNECTION DIAGRAMS

OUT

–V

+IN

S

AD8065

1

2

3

TOP VIEW

(Not to Scale)

+V

5

S

4

–IN

AD8066

1

V

OUT1

2

–IN1

3

+IN1 –IN2

–V

4

S

TOP VIEW

(Not to Scale)

Figure 1.

The AD8065/AD8066 are high performance, high speed, FET
input amplifiers available in small packages: SOIC-8, MSOP-8,
and SOT-23-5. They are rated to work over the industrial
temperature range of −40°C to +85°C.

The AD8065WARTZ-REEL7 is fully qualified for automotive
applications. It is rated to operate over the extended temperature
range (−40°C to +105°C), up to a maximum supply voltage
range of +

5V only.

24

21

G = +10

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

10.1 10 100 1000
FREQUENCY (MHz)

Figure 2. Small Signal Frequency Response

AD8065

1

NC

27

–IN

3

+IN

–V

4

S

TOP VIEW

(Not to Scale)

8

+V

S

7

V

OUT2

6

5

+IN2

V

= 200mV p-p

O

8

NC

+V

6

V
NC

5

OUT

S

02916-E-001

02916-E-002

Rev. J

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2010 Analog Devices, Inc. All rights reserved.

AD8065/AD8066

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Connection Diagrams ...................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Specifications ±5 V ........................................................................... 4

Specifications ±12 V ......................................................................... 6

Specifications +5 V ........................................................................... 7

Absolute Maximum Ratings ............................................................ 9

Maximum Power Dissipation ..................................................... 9

Output Short Circuit .................................................................... 9

ESD Caution .................................................................................. 9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 17

Theory of Operation ...................................................................... 20

Closed-Loop Frequency Response ........................................... 20

Noninverting Closed-Loop Frequency Response .................. 20

Inverting Closed-Loop Frequency Response ......................... 20

Wideband Operation ................................................................. 21

Input Protection ......................................................................... 21

Thermal Considerations ............................................................ 22

Input and Output Overload Behavior ..................................... 22

Layout, Grounding, and Bypassing Considerations .................. 23

Power Supply Bypassing ............................................................ 23

Grounding ................................................................................... 23

Leakage Currents ........................................................................ 23

Input Capacitance ...................................................................... 23

Output Capacitance ................................................................... 23

Input-to-Output Coupling ........................................................ 24

Wideband Photodiode Preamp ................................................ 24

High Speed JFET Input Instrumentation Amplifier.............. 25

Video Buffer ................................................................................ 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 28

Automotive Products ................................................................. 28

Rev. J | Page 2 of 28

AD8065/AD8066

REVISION HISTORY

8/10—Rev. I to Rev. J

Changes to Features Section, Applications Section, and General

Description Section ........................................................................... 1

Change to Table 1 .............................................................................. 4

Change to Table 3 .............................................................................. 7

Changes to Table 4 ............................................................................ 9

Changes to Figure 9 ......................................................................... 10

Changes to Inverting Closed-Loop Frequency Response

Section .............................................................................................. 20

Moved Leakage Currents Section, Input Capacitance Section,

and Output Capacitance Section ................................................... 23

Moved Input-to-Input Coupling Section, Wideband

Photodiode Preamp Section, and Figure 59 ................................ 24

Changes to Table 5 .......................................................................... 25

Moved Figure 60 and High Speed JFET Input Instrumentation

Amplifier Section ............................................................................ 25

Updated Outline Dimensions ........................................................ 27

Changes to Ordering Guide ........................................................... 28

Added Automotive Products Section ........................................... 28

3/09—Rev. H to Rev. I

Changes to High Speed JFET Input Instrumentation Amplifier

Section .............................................................................................. 23

Updated Outline Dimensions ........................................................ 24

9/08—Rev. G to Rev. H

Deleted Usable Range Parameter, Table 1 ...................................... 3

Deleted Usable Range Parameter, Table 2 ...................................... 4

Deleted Usable Range Parameter, Table 3 ...................................... 5

Changes to Layout ............................................................................. 6

Changes to Input and Output Overload Behavior Section ........ 19

Changes to Table 5 Expressions Column ..................................... 22

1/06—Rev. F to Rev. G

Changes to Ordering Guide ........................................................... 26

12/05—Rev. E to Rev. F

Updated Format ................................................................. Universal

Changes to Features .......................................................................... 1

Changes to General Description ..................................................... 1

Changes to Figure 22 through Figure 27 ...................................... 11

Updated Outline Dimensions ........................................................ 25

Changes to Ordering Guide ........................................................... 26

2/04—Rev. D to Rev. E.

Updated Format ................................................................ Universal

Updated Figure 56 ......................................................................... 21

Updated Outline Dimensions ...................................................... 25

Updated Ordering Guide ............................................................. 26

11/03—Rev. C to Rev. D.

Changes to Features ......................................................................... 1

Changes to Connection Diagrams ................................................. 1

Updated Ordering Guide ................................................................ 5

Updated Outline Dimensions ...................................................... 22

4/03—Rev. B to Rev. C.

Added SOIC-8 (R) for the AD8065 ............................................... 4

2/03—Rev. A to Rev. B.

Changes to Absolute Maximum Ratings....................................... 4

Changes to Test Circuit 10 ........................................................... 14

Changes to Test Circuit 11 ........................................................... 15

Changes to Noninverting Closed-Loop Frequency Response 16

Changes to Inverting Closed-Loop Frequency Response ....... 16

Updated Figure 6 .......................................................................... 18

Changes to Figure 7 ...................................................................... 19

Changes to Figure 10 .................................................................... 21

Changes to Figure 11 .................................................................... 22

Changes to High Speed JFET Instrumentation Amplifier ...... 22

Changes to Video Buffer .............................................................. 22

8/02—Rev. 0 to Rev. A.

Added AD8066 .................................................................. Universal

Added SOIC-8 (R) and MSOP-8 (RM) ......................................... 1

Edits to General Description .......................................................... 1

Edits to Specifications ...................................................................... 2

New Figure 2 ..................................................................................... 5

Changes to Ordering Guide ............................................................ 5

Edits to TPCs 18, 25, and 28 ........................................................... 8

New TPC 36 ................................................................................... 11

Added Test Circuits 10 and 11 .................................................... 14

MSOP (RM-8) Added .................................................................. 23

Rev. J | Page 3 of 28

AD8065/AD8066

SPECIFICATIONS ±5 V

@ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065)

AD8065WARTZ only: T

MIN

− T

88 MHz

MAX

G = +1, VO = 0.2 V p-p (AD8066) 100 120 MHz

G = +2, VO = 0.2 V p-p 50 MHz

G = +2, VO = 2 V p-p 42 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz

Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns

Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns

Slew Rate G = +2, VO = 4 V step 130 180 V/μs

AD8065WARTZ only: T

MIN

− T

155 V/μs

MAX

Settling Time to 0.1% G = +2, VO = 2 V step 55 ns
G = +2, VO = 8 V step 205 ns
NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −88 dBc

f

f

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 8 V p-p −73 dBc

C

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 0.6 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.02 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.02 Degrees
DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC package 0.4 1.5 mV

AD8065WARTZ only: T

MIN

− T

2.6 mV

MAX

Input Offset Voltage Drift 1 17 μV/°C

AD8065WARTZ only: T

MIN

− T

17 μV/°C

MAX

Input Bias Current SOIC package 2 6 pA

T

MIN

to T

25 125 pA

MAX

Input Offset Current 1 10 pA

T

MIN

to T

1 125 pA

MAX

Open-Loop Gain VO = ±3 V, RL = 1 kΩ 100 113 dB

AD8065WARTZ only: T

MIN

− T

100 dB

MAX

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −5 to +1.7 −5.0 to +2.4 V
AD8065WARTZ only: T

MIN

− T

−5 to +1.7 V

MAX

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB
V
AD8065WARTZ only: T

= −1 V to +1 V (SOT-23) −82 −91 dB

CM

− T

MIN

−82 dB

MAX

100 145 MHz

Rev. J | Page 4 of 28

AD8065/AD8066

Parameter Conditions Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −4.88 to +4.90 −4.94 to +4.95 V
AD8065WARTZ only: T
R

= 150 Ω −4.8 to +4.7 V

L

Output Current VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA
Short-Circuit Current 90 mA
Capacitive Load Drive 30% overshoot G = +1 20 pF

POWER SUPPLY

Operating Range 5 24 V
AD8065WARTZ only: T
Quiescent Current per Amplifier 6.4 7.2 mA
AD8065WARTZ only: T
Power Supply Rejection Ratio ±PSRR −85 −100 dB
AD8065WARTZ only: T

MIN

MIN

MIN

MIN

− T

−4.88 to +4.90 V

MAX

− T

5 10 V

MAX

− T

7.2 mA

MAX

− T

−85 dB

MAX

Rev. J | Page 5 of 28

AD8065/AD8066

SPECIFICATIONS ±12 V

@ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz

G = +1, VO = 0.2 V p-p (AD8066) 100 115 MHz

G = +2, VO = 0.2 V p-p 50 MHz

G = +2, VO = 2 V p-p 40 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz

Input Overdrive Recovery G = +1, −12.5 V to +12.5 V 175 ns

Output Overdrive Recovery G = −1, −12.5 V to +12.5 V 170 ns

Slew Rate G = +2, VO = 4 V step 130 180 V/μs

Settling Time to 0.1% G = +2, VO = 2 V step 55 ns
G = +2, VO = 10 V step 250 ns
NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −100 dBc
f
f

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 1 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.03 Degrees
DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC package 0.4 1.5 mV

Input Offset Voltage Drift 1 17 μV/°C

Input Bias Current SOIC package 3 7 pA

T

Input Offset Current 2 10 pA

T

Open-Loop Gain VO = ±10 V, RL = 1 kΩ 103 114 dB
INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −12 to +8.5 −12.0 to +9.5 V

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB
V
OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 V

R

Output Current VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30 mA

Short-Circuit Current 120 mA

Capacitive Load Drive 30% overshoot G = +1 25 pF
POWER SUPPLY

Operating Range 5 24 V

Quiescent Current per Amplifier 6.6 7.4 mA

Power Supply Rejection Ratio ±PSRR −84 −93 dB

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 10 V p-p −85 dBc

C

to T

MIN

MIN

CM

= 350 Ω −11.25 to +11.5 V

L

25 pA

MAX

to T

2 pA

MAX

= −1 V to +1 V (SOT-23) −82 −91 dB

Rev. J | Page 6 of 28

AD8065/AD8066

SPECIFICATIONS +5 V

@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 125 155 MHz
AD8065WARTZ only: T
G = +1, VO = 0.2 V p-p (AD8066) 110 130 MHz
G = +2, VO = 0.2 V p-p 50 MHz
G = +2, VO = 2 V p-p 43 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 6 MHz
Input Overdrive Recovery Time G = +1, −0.5 V to +5.5 V 175 ns
Output Recovery Time G = −1, −0.5 V to +5.5 V 170 ns
Slew Rate G = +2, VO = 2 V step 105 160 V/μs
AD8065WARTZ only: T
Settling Time to 0.1% G = +2, VO = 2 V step 60 ns

NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −65 dBc
f

= 5 MHz, G = +2, VO = 2 V p-p −50 dBc

C

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 22 dBm
Input Voltage Noise f = 10 kHz 7 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.13 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.16 Degrees

DC PERFORMANCE

Input Offset Voltage V

= 1.0 V, SOIC package 0.4 1.5 mV

CM

AD8065WARTZ only: T
Input Offset Voltage Drift 1 17 μV/ºC
AD8065WARTZ only: T
Input Bias Current SOIC package 1 5 pA
T

MIN

to T

25 125 pA

MAX

Input Offset Current 1 5 pA
T

MIN

to T

1 125 pA

MAX

Open-Loop Gain VO = 1 V to 4 V (AD8065) 100 113 dB
AD8065WARTZ only: T

V

= 1 V to 4 V (AD8066) 90 103 dB

O

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF
Differential Input Impedance 1000 || 4.5 GΩ || pF
Input Common-Mode Voltage Range
FET Input Range
AD8065WARTZ only: T
Common-Mode Rejection Ratio VCM = 0.5 V to 1.5 V −74 −100 dB

V

= 1 V to 2 V (SOT-23) −78 −91 dB

CM

AD8065WARTZ only: T
OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 V
AD8065WARTZ only: T
R

= 150 Ω 0.07 to 4.83 V

L

Output Current VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA
Short-Circuit Current 75 mA
Capacitive Load Drive 30% overshoot G = +1 5 pF

− T

MIN

MIN

MIN

MIN

MIN

90 MHz

MAX

− T

123 V/μs

MAX

− T

2.6 mV

MAX

− T

17 μV/ºC

MAX

− T

100 dB

MAX

0 to 1.7 0 to 2.4 V

− T

MIN

MIN-TMAX

MIN

0 to 1.7 V

MAX

−76 dB

− T

0.1 to 4.85 V

MAX

Rev. J | Page 7 of 28

AD8065/AD8066

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range 5 24 V

AD8065WARTZ only: T

Quiescent Current per Amplifier 5.8 6.4 7.0 mA

AD8065WARTZ only: T

Power Supply Rejection Ratio ±PSRR −78 −100 dB

AD8065WARTZ only: T

MIN

MIN

MIN

− T

5 10 V

MAX

− T

7.0 mA

MAX

− T

−78 dB

MAX

Rev. J | Page 8 of 28

AD8065/AD8066

(

)

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 26.4 V
Power Dissipation See Figure 3
Common-Mode Input Voltage VEE − 0.5 V to VCC + 0.5 V
Differential Input Voltage 1.8 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C

AD8065WARTZ Only −40°C to +105°C

Lead Temperature

300°C

(Soldering, 10 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

RMS output voltages should be considered. If R
V

−, as in single-supply operation, then the total drive power is

S

V

× I

.

S

OUT

If the rms signal levels are indeterminate, then consider the
worst case, when V

()

D

In single-supply operation with R
is V

= VS/2.

OUT

2.0

1.5
MSOP-8

1.0

= VS/4 for RL to midsupply.

OUT

2

()

V

4/

S

IVP

+×=

SS

SOT-23-5

R

L

referenced to VS−, worst case

L

SOIC-8

is referenced to

L

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction temperature

) on the die. The plastic encapsulating the die locally reaches

(T

J

the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8065/AD8066.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.

The still air thermal properties of the package and PCB (θ
ambient temperature (T
package (P

) determine the junction temperature of the die.

D

), and total power dissipated in the

A

The junction temperature can be calculated by

T

= TA + (PD × θJA)

J

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I

). Assuming the load (RL) is referenced to

S

midsupply, then the total drive power is V

/2 × I

S

) times the

S

OUT

which is dissipated in the package and some in the load (V
I

). The difference between the total drive power and the load

OUT

power is the drive power dissipated in the package.

D

⎛

()

D

S

IVP

⎜

SS

2

⎝

OUT

R

V

OUT

⎞

−

⎟

R

L

L

⎠

VV

×+×=

−+=

2

JA

, some of

OUT

PowerLoadPowerDriveTotalPowerQuiescentP

),

×

0.5

MAXIMUM POWER DISSIPATION (W)

0

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

200–40 –20–60 40 60 80 100

Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduce
the θ

. Care must be taken to minimize parasitic capacitances

JA

at the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC (125°C/W),
SOT-23 (180°C/W), and MSOP (150°C/W) packages on a
JEDEC standard 4-layer board. θ

values are approximations.

JA

OUTPUT SHORT CIRCUIT

Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.

ESD CAUTION

02916-E-003

Rev. J | Page 9 of 28