ANALOG DEVICES AD8065, AD8066 Service Manual

High Performance, 145 MHz

V

FEATURES

Qualified for automotive applications FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, −3 dB bandwidth (G = +1) 180 V/μs slew rate (G = +2) Low noise

7 nV/√Hz (f = 10 kHz)

0.6 fA/√Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV maximum High common-mode rejection ratio: −100 dB Excellent distortion specifications SFDR −88 dBc @ 1 MHz Low power: 6.4 mA/amplifier typical supply current No phase reversal Small packaging: SOIC-8, SOT-23-5, and MSOP-8

GENERAL DESCRIPTION

The AD8065/AD80661 FastFET™ amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use. The AD8065 is a single amplifier, and the AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. proprietary XFCB process and allow exceptionally low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as very high input impedance.

With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and a bandwidth of 145 MHz, the AD8065/AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs.

Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/μs, excellent distortion (SFDR of −88 dBc @ 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065/AD8066 operate using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current.

1

Protected by U. S. Patent No. 6,262,633.

FastFET Op Amps

AD8065/AD8066

APPLICATIONS

Automotive driver assistance systems Photodiode preamps Filters A/D drivers Level shifting Buffering

CONNECTION DIAGRAMS

OUT

–V

+IN

S

AD8065

1

2

3

TOP VIEW

(Not to Scale)

+V

5

S

4

–IN

AD8066

1

V

OUT1

2

–IN1

3

+IN1 –IN2

–V

4

S

TOP VIEW

(Not to Scale)

Figure 1.

The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP-8, and SOT-23-5. They are rated to work over the industrial temperature range of −40°C to +85°C.

The AD8065WARTZ-REEL7 is fully qualified for automotive applications. It is rated to operate over the extended temperature range (−40°C to +105°C), up to a maximum supply voltage range of +

5V only.

24

21

G = +10

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 2. Small Signal Frequency Response

AD8065

1

NC

27

–IN

3

+IN

–V

4

S

TOP VIEW

(Not to Scale)

8

+V

S

7

V

OUT2

6

5

+IN2

V

= 200mV p-p

O

8

NC

+V

6

V NC

5

OUT

S

02916-E-001

02916-E-002

Rev. J

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8065/AD8066

REVISION HISTORY

8/10—Rev. I to Rev. J

Changes to Features Section, Applications Section, and General

Description Section ........................................................................... 1

Change to Table 1 .............................................................................. 4

Change to Table 3 .............................................................................. 7

Changes to Table 4 ............................................................................ 9

Changes to Figure 9 ......................................................................... 10

Changes to Inverting Closed-Loop Frequency Response

Section .............................................................................................. 20

Moved Leakage Currents Section, Input Capacitance Section,

and Output Capacitance Section ................................................... 23

Moved Input-to-Input Coupling Section, Wideband

Photodiode Preamp Section, and Figure 59 ................................ 24

Changes to Table 5 .......................................................................... 25

Moved Figure 60 and High Speed JFET Input Instrumentation

Amplifier Section ............................................................................ 25

Updated Outline Dimensions ........................................................ 27

Changes to Ordering Guide ........................................................... 28

Added Automotive Products Section ........................................... 28

3/09—Rev. H to Rev. I

Changes to High Speed JFET Input Instrumentation Amplifier

Section .............................................................................................. 23

Updated Outline Dimensions ........................................................ 24

9/08—Rev. G to Rev. H

Deleted Usable Range Parameter, Table 1 ...................................... 3

Deleted Usable Range Parameter, Table 2 ...................................... 4

Deleted Usable Range Parameter, Table 3 ...................................... 5

Changes to Layout ............................................................................. 6

Changes to Input and Output Overload Behavior Section ........ 19

Changes to Table 5 Expressions Column ..................................... 22

1/06—Rev. F to Rev. G

Changes to Ordering Guide ........................................................... 26

12/05—Rev. E to Rev. F

Updated Format ................................................................. Universal

Changes to Features .......................................................................... 1

Changes to General Description ..................................................... 1

Changes to Figure 22 through Figure 27 ...................................... 11

Updated Outline Dimensions ........................................................ 25

Changes to Ordering Guide ........................................................... 26

2/04—Rev. D to Rev. E.

Updated Format ................................................................ Universal

Updated Figure 56 ......................................................................... 21

Updated Outline Dimensions ...................................................... 25

Updated Ordering Guide ............................................................. 26

11/03—Rev. C to Rev. D.

Changes to Features ......................................................................... 1

Changes to Connection Diagrams ................................................. 1

Updated Ordering Guide ................................................................ 5

Updated Outline Dimensions ...................................................... 22

4/03—Rev. B to Rev. C.

Added SOIC-8 (R) for the AD8065 ............................................... 4

2/03—Rev. A to Rev. B.

Changes to Absolute Maximum Ratings....................................... 4

Changes to Test Circuit 10 ........................................................... 14

Changes to Test Circuit 11 ........................................................... 15

Changes to Noninverting Closed-Loop Frequency Response 16

Changes to Inverting Closed-Loop Frequency Response ....... 16

Updated Figure 6 .......................................................................... 18

Changes to Figure 7 ...................................................................... 19

Changes to Figure 10 .................................................................... 21

Changes to Figure 11 .................................................................... 22

Changes to High Speed JFET Instrumentation Amplifier ...... 22

Changes to Video Buffer .............................................................. 22

8/02—Rev. 0 to Rev. A.

Added AD8066 .................................................................. Universal

Added SOIC-8 (R) and MSOP-8 (RM) ......................................... 1

Edits to General Description .......................................................... 1

Edits to Specifications ...................................................................... 2

New Figure 2 ..................................................................................... 5

Changes to Ordering Guide ............................................................ 5

Edits to TPCs 18, 25, and 28 ........................................................... 8

New TPC 36 ................................................................................... 11

Added Test Circuits 10 and 11 .................................................... 14

MSOP (RM-8) Added .................................................................. 23

Rev. J | Page 3 of 28

AD8065/AD8066

SPECIFICATIONS ±5 V

@ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065)

AD8065WARTZ only: T

MIN

− T

88 MHz

MAX

G = +1, VO = 0.2 V p-p (AD8066) 100 120 MHz

G = +2, VO = 0.2 V p-p 50 MHz

G = +2, VO = 2 V p-p 42 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz

Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns

Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns

Slew Rate G = +2, VO = 4 V step 130 180 V/μs

AD8065WARTZ only: T

MIN

− T

155 V/μs

MAX

Settling Time to 0.1% G = +2, VO = 2 V step 55 ns G = +2, VO = 8 V step 205 ns NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −88 dBc

f

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 8 V p-p −73 dBc

C

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 0.6 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.02 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.02 Degrees DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC package 0.4 1.5 mV

AD8065WARTZ only: T

MIN

− T

2.6 mV

MAX

Input Offset Voltage Drift 1 17 μV/°C

AD8065WARTZ only: T

MIN

− T

17 μV/°C

MAX

Input Bias Current SOIC package 2 6 pA

T

MIN

to T

25 125 pA

MAX

Input Offset Current 1 10 pA

T

MIN

to T

1 125 pA

MAX

Open-Loop Gain VO = ±3 V, RL = 1 kΩ 100 113 dB

AD8065WARTZ only: T

MIN

− T

100 dB

MAX

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −5 to +1.7 −5.0 to +2.4 V AD8065WARTZ only: T

MIN

− T

−5 to +1.7 V

MAX

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB V AD8065WARTZ only: T

= −1 V to +1 V (SOT-23) −82 −91 dB

CM

− T

MIN

−82 dB

MAX

100 145 MHz

Rev. J | Page 4 of 28

AD8065/AD8066

Parameter Conditions Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −4.88 to +4.90 −4.94 to +4.95 V AD8065WARTZ only: T R

= 150 Ω −4.8 to +4.7 V

L

Output Current VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA Short-Circuit Current 90 mA Capacitive Load Drive 30% overshoot G = +1 20 pF

POWER SUPPLY

Operating Range 5 24 V AD8065WARTZ only: T Quiescent Current per Amplifier 6.4 7.2 mA AD8065WARTZ only: T Power Supply Rejection Ratio ±PSRR −85 −100 dB AD8065WARTZ only: T

MIN

− T

−4.88 to +4.90 V

MAX

− T

5 10 V

MAX

− T

7.2 mA

MAX

− T

−85 dB

MAX

Rev. J | Page 5 of 28

AD8065/AD8066

SPECIFICATIONS ±12 V

@ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz

G = +1, VO = 0.2 V p-p (AD8066) 100 115 MHz

G = +2, VO = 0.2 V p-p 50 MHz

G = +2, VO = 2 V p-p 40 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz

Input Overdrive Recovery G = +1, −12.5 V to +12.5 V 175 ns

Output Overdrive Recovery G = −1, −12.5 V to +12.5 V 170 ns

Slew Rate G = +2, VO = 4 V step 130 180 V/μs

Settling Time to 0.1% G = +2, VO = 2 V step 55 ns G = +2, VO = 10 V step 250 ns NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −100 dBc f f

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 1 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.03 Degrees DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC package 0.4 1.5 mV

Input Offset Voltage Drift 1 17 μV/°C

Input Bias Current SOIC package 3 7 pA

T

Input Offset Current 2 10 pA

T

Open-Loop Gain VO = ±10 V, RL = 1 kΩ 103 114 dB INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −12 to +8.5 −12.0 to +9.5 V

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB V OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 V

R

Output Current VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30 mA

Short-Circuit Current 120 mA

Capacitive Load Drive 30% overshoot G = +1 25 pF POWER SUPPLY

Operating Range 5 24 V

Quiescent Current per Amplifier 6.6 7.4 mA

Power Supply Rejection Ratio ±PSRR −84 −93 dB

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 10 V p-p −85 dBc

C

to T

MIN

CM

= 350 Ω −11.25 to +11.5 V

L

25 pA

MAX

to T

2 pA

MAX

= −1 V to +1 V (SOT-23) −82 −91 dB

Rev. J | Page 6 of 28

AD8065/AD8066

SPECIFICATIONS +5 V

@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 125 155 MHz AD8065WARTZ only: T G = +1, VO = 0.2 V p-p (AD8066) 110 130 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, VO = 2 V p-p 43 MHz Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 6 MHz Input Overdrive Recovery Time G = +1, −0.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −0.5 V to +5.5 V 170 ns Slew Rate G = +2, VO = 2 V step 105 160 V/μs AD8065WARTZ only: T Settling Time to 0.1% G = +2, VO = 2 V step 60 ns

NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −65 dBc f

= 5 MHz, G = +2, VO = 2 V p-p −50 dBc

C

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 22 dBm Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 0.6 fA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.13 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.16 Degrees

DC PERFORMANCE

Input Offset Voltage V

= 1.0 V, SOIC package 0.4 1.5 mV

CM

AD8065WARTZ only: T Input Offset Voltage Drift 1 17 μV/ºC AD8065WARTZ only: T Input Bias Current SOIC package 1 5 pA T

MIN

to T

25 125 pA

MAX

Input Offset Current 1 5 pA T

MIN

to T

1 125 pA

MAX

Open-Loop Gain VO = 1 V to 4 V (AD8065) 100 113 dB AD8065WARTZ only: T

V

= 1 V to 4 V (AD8066) 90 103 dB

O

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF Differential Input Impedance 1000 || 4.5 GΩ || pF Input Common-Mode Voltage Range FET Input Range AD8065WARTZ only: T Common-Mode Rejection Ratio VCM = 0.5 V to 1.5 V −74 −100 dB

V

= 1 V to 2 V (SOT-23) −78 −91 dB

CM

AD8065WARTZ only: T OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 V AD8065WARTZ only: T R

= 150 Ω 0.07 to 4.83 V

L

Output Current VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA Short-Circuit Current 75 mA Capacitive Load Drive 30% overshoot G = +1 5 pF

− T

MIN

90 MHz

MAX

− T

123 V/μs

MAX

− T

2.6 mV

MAX

− T

17 μV/ºC

MAX

− T

100 dB

MAX

0 to 1.7 0 to 2.4 V

− T

MIN

MIN-TMAX

MIN

0 to 1.7 V

MAX

−76 dB

− T

0.1 to 4.85 V

MAX

Rev. J | Page 7 of 28

AD8065/AD8066

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range 5 24 V

AD8065WARTZ only: T

Quiescent Current per Amplifier 5.8 6.4 7.0 mA

AD8065WARTZ only: T

Power Supply Rejection Ratio ±PSRR −78 −100 dB

AD8065WARTZ only: T

MIN

− T

5 10 V

MAX

− T

7.0 mA

MAX

− T

−78 dB

MAX

Rev. J | Page 8 of 28

AD8065/AD8066

(

)

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 26.4 V Power Dissipation See Figure 3 Common-Mode Input Voltage VEE − 0.5 V to VCC + 0.5 V Differential Input Voltage 1.8 V Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C

AD8065WARTZ Only −40°C to +105°C

Lead Temperature

300°C

(Soldering, 10 sec)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RMS output voltages should be considered. If R V

−, as in single-supply operation, then the total drive power is

S

V

× I

.

S

OUT

If the rms signal levels are indeterminate, then consider the worst case, when V

()

D

In single-supply operation with R is V

= VS/2.

OUT

2.0

1.5 MSOP-8

1.0

= VS/4 for RL to midsupply.

OUT

2

()

V

4/

S

IVP

+×=

SS

SOT-23-5

R

L

referenced to VS−, worst case

L

SOIC-8

is referenced to

L

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature

) on the die. The plastic encapsulating the die locally reaches

(T

J

the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/AD8066. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure.

The still air thermal properties of the package and PCB (θ ambient temperature (T package (P

) determine the junction temperature of the die.

D

), and total power dissipated in the

A

The junction temperature can be calculated by

T

= TA + (PD × θJA)

J

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V quiescent current (I

). Assuming the load (RL) is referenced to

S

midsupply, then the total drive power is V

/2 × I

S

) times the

S

OUT

which is dissipated in the package and some in the load (V I

). The difference between the total drive power and the load

OUT

power is the drive power dissipated in the package.

D

⎛

()

D

S

IVP

⎜

SS

2

⎝

OUT

R

V

OUT

⎞

−

⎟

R

L

⎠

VV

×+×=

−+=

2

JA

, some of

OUT

PowerLoadPowerDriveTotalPowerQuiescentP

),

×

0.5

MAXIMUM POWER DISSIPATION (W)

0

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

200–40 –20–60 40 60 80 100

Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the θ

. Care must be taken to minimize parasitic capacitances

JA

at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section.

Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC (125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W) packages on a JEDEC standard 4-layer board. θ

values are approximations.

JA

OUTPUT SHORT CIRCUIT

Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure.

ESD CAUTION

02916-E-003

Rev. J | Page 9 of 28

AD8065/AD8066

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, V

24

21

G = +10

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 4. Small Signal Frequency Response for Various Gains

6

VO = 200mV p-p G = +1

4

2

0

GAIN (dB)

–2

V

S

V

= ±12V

= +5V

S

= 200mV p-p

V

O

= 2 V p-p, Temperature = 25°C.

OUT

02916-E-004

V

= ±5V

S

6.9 RL = 150

G = +2

Ω

= 0.2V p-p

V

OUT

= 0.7V p-p

V

OUT

V

= 1.4V p-p

OUT

FREQUENCY (MHz)

6.8

6.7

6.6

6.5

6.4

GAIN (dB)

6.3

6.2

6.1

6.0

5.9

0.1 101 100

Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)

9

VO = 200mV p-p G = +2

8

7

6

GAIN (dB)

5

VS = +5V

= ±12V

V

S

V

= ±5V

S

02916-E-007

–4

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 5. Small Signal Frequency Response for Various Supplies

(See Figure 42)

2

VO = 2V p-p G = +1

1

0

–1

= ±12V

–2

GAIN (dB)

–3

–4

–5

10.1 10 100 1000

V

S

FREQUENCY (MHz)

V

= ±5V

S

Figure 6. Large Signal Frequency Response for Various Supplies

(See Figure 42)

4

3

02916-E-005

10.1 10 100 1000 FREQUENCY (MHz)

02916-E-008

Figure 8. Small Signal Frequency Response for Various Supplies

(See Figure 43)

8

= 2V p-p

V

O

G = +2

7

6

5

4

GAIN (dB)

3

2

1

0

02916-E-006

VS = +5V

V

= ±12V

S

10.1 10 100 1000 FREQUENCY (M Hz )

V

= ±5V

S

02916-009

Figure 9. Large Signal Frequency Response for Various Supplies

(See Figure 43)

Rev. J | Page 10 of 28

AD8065/AD8066

9

VO = 200mV p-p G = +1

6

3

C

L

C

L

= 25pF

= 20pF

C R

L SNUB

= 25pF

= 20Ω

8

6

4

2

C

= 5pF

L

C

= 55pF

L

CL = 25pF

0

GAIN (dB)

–3

–6

–9

10.1 10 100 1000 FREQUENCY (MHz)

Figure 10. Small Signal Frequency Response for Various C

8

6

G = +2

4

2

0

GAIN (dB)

–2

–4

–6

–8

V

OUT

V

OUT

10.1 10 100 1000 FREQUENCY (MHz)

= 2V p-p

= 4V p-p

C

= 5pF

L

V

OUT

LOAD

= 0.2V p-p

(See Figure 42)

Figure 11. Frequency Response for Various Output Amplitudes

(See Figure 43)

14

VO = 200mV p-p

12

G = +2

R

10

8

6

4

GAIN (dB)

2

0

–2

–4

= RG = 1kΩ,

R

F

R

= 500Ω,

S

= 3.3pF

C

F

10.1 10 100 1000 FREQUENCY (MHz)

= RG = 1kΩ,

F

= 500Ω

R

S

R

= RG = 500Ω,

F

R

= 250Ω

S

= RG = 500Ω,

R

F

= 250Ω,

R

S

= 2.2pF

C

F

Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)

0

GAIN (dB)

–2

–4

VO = 200mV p-p

–6

G = +2

–8

02916-E-010

Figure 13. Small Signal Frequency Response for Various C

8

7

6

5

4

GAIN (dB)

3

2

VO = 200mV p-p

1

G = +2

0

02916-E-011

Figure 14. Small Signal Frequency Response for Various R

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

0.01 0.1 1 10 100 1000

02916-E-012

10.1 10 100 1000 FREQUENCY (MHz)

(See Figure 43)

LOAD

RL = 100Ω

RL = 1kΩ

10.1 10 100 1000 FREQUENCY (MHz)

(See Figure 43)

LOAD

PHASE

GAIN

FREQUENCY (MHz)

120

60

0

–60

–120

–180

02916-E-013

02916-E-014

PHASE (DEGREES)

02916-E-015

Figure 15. Open-Loop Response

Rev. J | Page 11 of 28

AD8065/AD8066

–30

–40

G = +2

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

0.1 101 100

Figure 16. Harmonic Distortion vs. Frequency for Various Loads

–30

–40

G = +2 V

S

F = 1MHz

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

01234 6 105 789 1211 1413 15

Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V

50

45

HD2 RL = 150Ω

HD2 RL = 1kΩ

HD3 RL = 1kΩ

HD3 RL = 150Ω

FREQUENCY (MHz)

(See Figure 43)

= ±12V

HD2 RL = 150Ω

HD3 RL = 150Ω

HD2 RL = 300Ω

HD3 RL = 300Ω

OUTPUT AMPLITUDE (V p-p)

(See Figure 43)

RL = 100Ω

VS = ±12V

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

0.1 101 100

02916-E-016

HD2 G = +1

FREQUENCY (MHz)

HD2 G = +2

HD3 G = +2

HD3 G = +1

02916-E-019

Figure 19. Harmonic Distortion vs. Frequency for Various Gains

(See Figure 42 and Figure 43)

–20

VS = ±12V

–30

G = +2

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

–120

0.1 1.0 10.0

02916-E-017

HD2 VO = 10V p-p

HD3 VO = 10V p-p

HD2 VO = 20V p-p

HD3 VO = 20V p-p

FREQUENCY (MHz)

HD2 VO = 2V p-p

HD3 VO = 2V p-p

02916-E-020

Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes

(See Figure 43)

100

40

VS = ±5V

35

30

25

INTERCEPT POINT (dBm)

20

15

VS = +5V

110

FREQUENCY (MHz)

02916-E-018

Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage

Rev. J | Page 12 of 28

10

NOISE (nV/ Hz)

1

100k10k100 1k10 1M 10M 100M 1G

FREQUENCY (Hz)

02916-E-021

Figure 21. Voltage Noise

AD8065/AD8066

G = +1

CL = 20pF

CL = 5pF

G = +1

50mV/DIV

25ns/DIV

Figure 22. Small Signal Transient Response 5 V Supply (See Figure 42)

G = +1 VS = ±12V

2V/DIV

V

OUT

V

OUT

V

= 10V p-p

= 4V p-p

= 2V p-p

OUT

50ns/DIV

Figure 23. Large Signal Transient Response (See Figure 42)

G = –1

= ±5V

V

S

02916-022

02916-023

50mV/DIV

25ns/DIV

Figure 25. Small Signal Transient Response ±5 V (See Figure 42)

G = +2

5µs

VS = ±12V

50ns/DIV

2V/DIV

V

OUT

V

OUT

= 10V p-p

= 2V p-p

Figure 26. Large Signal Transient Response (See Figure 43)

G = +1 V

= ±5V

S

02916-025

02916-026

2.0V/DIV

100ns/DIV

Figure 24. Output Overdrive Recovery (See Figure 44)

02916-024

Rev. J | Page 13 of 28

2.0V/DIV

100ns/DIV

Figure 27. Input Overdrive Recovery (See Figure 42)

02916-027

AD8065/AD8066

+0.1%

–0.1%

–5

–10

–15

–20

INPUT BIAS CURRENT (pA)

–25

–30

0.3

0.2

0.1

VIN = 140mV/DIV

V

– 2V

OUT

IN

t = 0

2mV/DIV

Figure 28. Long-Term Settling Time (See Figure 49)

0

–I

+I

45 5525 35 65 75 85

TEMPERATURE (°C)

Figure 29. Input Bias Current vs. Temperature

VS = +5V

0

VS = ±5V

64μs/DIV

b

VIN= 500mV/DIV

+0.1%

2mV/DIV

t = 0

V

OUT

10ns/DIV

– 2V

IN

02916-E-031

–0.1%

02916-E-028

Figure 31. 0.1% Short-Term Settling Time (See Figure 49)

42 36 30 24

(μA)

18

b

I

12

6 0

10

–I

5

b

0

–5

–10

(pA)

b

I

–15 –20 –25

–30

–12 8–2–100–8 2–6 4–4

02916-E-029

+I

b

COMMON-MODEVOLTAGE (V)

+I

b

–I

b

FET INPUT STAGE BJT INPUT STAGE

10 12

6

02916-E-032

Figure 32. Input Bias Current vs. Common-Mode Voltage Range

(See the Input and Output Overload Behavior Section)

40

35

30

25

20

N = 299 SD = 0.388 MEAN = –0.069

–0.1

OFFSET VOLTAGE (mV)

–0.2

–0.3

–14 –10–12 –8–6–4 0 8–2 2 4 6 10 12 14

COMMON-MODE VOLTAGE (V)

Figure 30. Input Offset Voltage vs. Common-Mode Voltage

VS = ±12V

02916-E-030

Rev. J | Page 14 of 28

15

10

5

0 –2.0 2.0–1.5 –1.0 –0.5 0 0.5 1.0 1.5

INPUT OFFSET VOLTAGE (mV)

Figure 33. Input Offset Voltage

02916-E-033

AD8065/AD8066

–30

100

–40

–50

–60

–70

CMRR (dB)

VS = ±12V

–80

–90

–100

0.1 101 100

VS = ±5V

FREQUENCY (MHz)

Figure 34. CMRR vs. Frequency (See Figure 46)

0.30

0.25 VCC– V

OH

0.20

0.15

0.10

VOL– V

0.05

OUTPUT SATURATION VOLTAGE (V)

EE

10

1

0.1

OUTPUT IMPEDANCE (Ω)

0.01

0

02916-E-034

10k 100k100 1k 1M 10M 100M

FREQUENCY (Hz)

G = +2

G = +1

02916-E-037

Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)

80

70

VCC– V

OH

60

50

40

OUTPUT SATURATION VOLTAGE (mV)

VOL– V

EE

0

1002030

I

(mA)

LOAD

Figure 35. Output Saturation Voltage vs. Output Load Current

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

0.01 0.1 1 10 100 1000

–PSRR

+PSRR

FREQUENCY (MHz)

Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)

40

02916-E-035

CROSSTALK (dB)

02916-E-036

30

45 5525 35 65 75 85

TEMPERATURE (°C)

Figure 38. Output Saturation Voltage vs. Temperature

0

VIN = 2V p-p

–10

G = +1

–20

–30

–40

–50

–60

–70

–80

–90

0.1 101 100

B TO A

A TO B

FREQUENCY (MHz)

Figure 39. Crosstalk vs. Frequency (See Figure 51)

02916-E-038

02916-E-039

Rev. J | Page 15 of 28

AD8065/AD8066

6.60

6.55

6.50

6.45

6.40

6.35

SUPPLY CURRENT (mA)

6.30

6.25

VS = ±5V

VS = +5V

020–40 –20 40 60 80

TEMPERATURE (°C)

Figure 40. Quiescent Supply Current vs. Temperature for Various

Supply Voltages

VS = ±12V

125

120

115

110

105

100

95

OPEN-LOOP GAIN (dB)

90

85

80

02916-E-040

VS = +5V

VS = ±5V

1002030

I

LOAD

VS = ±12V

(mA)

40

02916-E-041

Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages

Rev. J | Page 16 of 28

AD8065/AD8066

TEST CIRCUITS

SOIC-8 Pinout

+V

CC

4.7μF

+V

CC

4.7μF

V

IN

49.9Ω

499Ω 499Ω

24.9Ω

AD8065

–V

Figure 42. G = +1

+V

2.2pF

0.1μF

2.2pF

V

IN

49.9Ω

SNUB

1kΩ

FET PROBE

C

LOAD

02916-E-042

R

0.1μF

4.7μF

EE

499Ω 499Ω

AD8065

249Ω

–V

0.1μF

FET PROBE

0.1μF

4.7μF

EE

1kΩ

02916-E-044

Figure 44. G = −1

CC

4.7μF

0.1μF

24.9Ω

+V

CC

4.7μF

0.1μF

SNUB

1kΩ

FET PROBE

C

LOAD

AD8065

02916-E-043

NETWORK ANALYZER S22

0.1μF

4.7μF

–V

EE

02916-E-045

Figure 45. Output Impedance G = +1

AD8065

V

IN

49.9Ω

249Ω

0.1μF

4.7μF

–V

EE

R

Figure 43. G = +2

Rev. J | Page 17 of 28

AD8065/AD8066

499Ω 499Ω

V

IN

49.9Ω 499Ω

499Ω

+V

CC

AD8065

4.7μF

0.1μF

FET PROBE

1kΩ

24.9Ω

AD8065

49.9Ω

0.1μF

V

IN

1V p-p

+V

CC

FET PROBE

1kΩ

Figure 46. CMRR

+V

CC

499Ω 499Ω

249Ω

AD8065

–V

EE

Figure 47. Output Impedance G = +2

4.7μF

–V

EE

4.7μF

0.1μF

NETWORK ANALYZER

0.1μF

4.7μF

S22

4.7μF

–V

02916-E-046

EE

02916-E-048

Figure 48. Positive PSRR

+V

CC

4.7μF

0.1μF

2.2pF

249Ω

49.9Ω

499Ω

AD8065

–V

EE

0.1μF

4.7μF

976Ω

TO SCOPE

49.9Ω

02916-E-049

499Ω

V

IN

02916-E-047

Figure 49. Settling Time

Rev. J | Page 18 of 28

AD8065/AD8066

V

2.2pF

499Ω

5V

4.7μF

0.1μF

AD8065

Figure 52. Single Supply

FET PROBE

1kΩ

1.5V

02916-E-052

24.9Ω

V

IN

1V p-p

+V

CC

4.7μF

0.1μF

AD8065

49.9Ω

–V

EE

Figure 50. Negative PSRR

1kΩ

24.9Ω

FET PROBE

499Ω

1.5V

V

IN

02916-E-050

249Ω

49.9Ω

1.5V

+5V

24.9Ω

4.7μF

0.1μF

FET PROBE

AD8066

1kΩ

RECEIVE SIDE

AD8066

IN

49.9Ω

DRIVE SIDE

0.1μF 1kΩ

4.7μF

–5V

02916-E-051

Figure 51. Crosstalk—AD8066

Rev. J | Page 19 of 28

AD8065/AD8066

THEORY OF OPERATION

The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar (XFCB) process, resulting in an outstanding combination of precision and speed. The supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles commonmode signals from below the negative supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply.

With voltage noise of 7 nV/√Hz and −88 dBc distortion for 1 MHz, 2 V p-p signals, the AD8065/AD8066 are a great choice for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capability of the AD8065/AD8066 also make them useful in video applications.

CLOSED-LOOP FREQUENCY RESPONSE

The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 53. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown.

R

F

NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE

Solving for the transfer function

()

RRf

V

where f

2

O

=

()

V

I

is the frequency where the amplifier’s open-loop

crossover

F

G

+×π

F

G

2

crossover

RfsRR

××π++

G

gain equals 0 db

At dc

V +

O

V

I

RR

F

G

=

R

G

Closed-loop −3 dB frequency

R

G

ff

×=

crossover

3dB

−

RR

+

F

G

INVERTING CLOSED-LOOP FREQUENCY RESPONSE

Rf

crossover

2

R

crossover

G

+

RR

××π−

F

RfRRs

××π++

G

GF

2

()

F

G

R

F

−=

R

G

At dc

V

O

=

V

I

V

O

V

I

Closed-loop −3 dB frequency

ff

−3

×=

crossoverdB

R

F

R

G

A

V

80

60

40

OPEN-LOOP GAIN (A) (dB)

20

0

E

I

0.01 100

Figure 53. Open-Loop Gain vs. Frequency and Basic Connections

V

O

A = (2π×f

0.1 101 FREQUENCY (MHz)

Rev. J | Page 20 of 28

crossover

)/s

R

V

G

I

V

A

E

f

crossover

= 65MHz

V

O

02916-E-053

AD8065/AD8066

The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (R

+ RG )/RG. This simple model is

F

accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp.

R

F

R

G

V

I

+VOS–

V

I

A

b

R

S

–

I

b

+

O

02916-E-054

Figure 54. Voltage Feedback Amplifier DC Errors

Figure 54 shows a voltage feedback amplifier’s dc errors. For both inverting and noninverting configurations

()

O

×=

RIerrorV

b

The voltage error due to I

+

RR

⎛ ⎜

S

⎝

and Ib– is minimized if RS = RF || RG

b+

⎞

F

G

⎟

R

G

⎠

+×−

VRI

F

b

−+

+

RR

⎛ ⎜

OS

⎝

F

G

R

G

(though with the AD8065 input currents at typically less than 20 pA over temperature, this is likely not a concern). To include common-mode and power supply rejection effects, total V

can be

OS

modeled

nom

V

PSR

VV

OSOS

V

is the offset voltage specified at nominal conditions,

OS

nom

is the change in power supply from nominal conditions,

ΔV

S

PSR is the power supply rejection, ΔV

++=

CMS

CMR

is the change in common-

CM

ΔΔ

V

mode voltage from nominal conditions, and CMR is the commonmode rejection.

WIDEBAND OPERATION

Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of +1, +2, and −1. Source impedance at the summing junction (R response with the amplifier’s input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 Ω to 1 kΩ are recommended, because they do not unduly load down the amplifier, and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (C

) in parallel with the feedback resistor, as

F

illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier.

For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance.

|| RG) forms a pole in the amplifier’s loop

F

⎞ ⎟

⎠

Actual distortion performance depends on a number of variables:

• The closed-loop gain of the application

• Whether it is inverting or noninverting

• Amplifier loading

• Signal frequency and amplitude

• Board layout

Also see Figure 16 to Figure 20. The lowest distortion is obtained with the AD8065 used in low gain inverting applications, because this eliminates common-mode effects. Higher closedloop gains result in worse distortion performance.

INPUT PROTECTION

The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation.

Excessive power dissipation through the protection devices destroys or degrades the performance of the amplifier. Differential voltages greater than 0.7 V result in an input current of approximately (|V series with the inputs.

For input voltages beyond the positive supply, the input current is approximately (V the input current is about (V amplifier are to be subjected to sustained differential voltages greater than 0.7 V, or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (R

(| V+–V

RI>

FOR LARGE | V

V

I

− V−| 0.7 V)/RI, where RI is the resistance in

+

− VCC − 0.7)/RI. Beyond the negative supply,

I

− VEE + 0.7)/RI. If the inputs of the

I

), as shown in Figure 55.

I

| – 0.7V)

–

30mA

+–V–

|

AD8065

R

I

(V

I–VEE

R

>

I

30mA

(V

I–VEE

>

R

I

30mA FOR V SUPPLY VOLTAGES

V

O

Figure 55. Current-Limiting Resistor

– 0.7V)

+ 0.7V)

BEYOND

I

02916-E-055

Rev. J | Page 21 of 28

AD8065/AD8066

THERMAL CONSIDERATIONS INPUT AND OUTPUT OVERLOAD BEHAVIOR

With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT-23-5 (thermal resistance of 160°C/W). V

OS

temperature drift is trimmed to guarantee a maximum drift of 17 μV/°C, so it can change up to 0.425 mV due to warm-up effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.

increases by a factor of 1.7 for every 10°C rise in temperature.

I

b

is close to five times higher at 24 V supplies as opposed to a

I

b

single 5 V supply. Heavy loads increase power dissipation and raise the chip

junction temperature as described in the Maximum Power Dissipation section. Care should be taken not to exceed the rated power dissipation of the package.

R1

A simplified schematic of the AD8065/AD8066 input stage is shown in Figure 56. This shows the cascoded N-channel JFET input pair, the ESD and other protection diodes, and the auxiliary NPN input stage that eliminates any phase inversion behavior. When the common-mode input voltage to the amplifier is driven to within approximately 3 V of the positive power supply, the input JFET’s bias current turns off and the bias of the NPN pair turns on, taking over control of the amplifier. The NPN differential pair now sets the amplifier’s offset, and the input bias current is now in the range of several tens of microamps. This behavior is shown in Figure 32. Normal operation resumes when the common-mode voltage goes below the 3 V from the positive supply threshold.

The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a ±5 V supply is shown in Figure 24.

V

CC

R5

TO REST OF AMP

V

THRESHOLD

V

N

Q2 Q5

D1

R6

R3

Q1 Q6

D3 D4

S

R2 R8

D2

Q3

Q4

R4

I

T1

R7

I

T2

S

–V

VBIAS

V

P

Q7

EE

02916-E-056

Figure 56. Simplified Input Stage

Rev. J | Page 22 of 28

AD8065/AD8066

V

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

POWER SUPPLY BYPASSING

Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise.

Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 μF (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 μF tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board at the supply inputs.

GROUNDING

A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create unwanted voltage noise.

The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical.

LEAKAGE CURRENTS

Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs sets up leakage currents through the PC board insulator, for example, 1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the

inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board.

Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. Also, low absorption materials, such as Teflon® or ceramic, could be necessary in some instances.

INPUT CAPACITANCE

Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance reduces the input impedance at high frequencies, in turn increasing the amplifier’s gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board.

OUTPUT CAPACITANCE

To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect:

• As shown in Figure 57, put a small value resistor (R

series with the output to isolate the load capacitor from the amp’s output stage. A good value to choose is 20 Ω (see Figure 10).

• Increase the phase margin with higher noise gains or add

a pole with a parallel resistor and capacitor from −IN to the output.

RS= 20Ω

AD8065

I

Figure 57. Output Isolation Resistor

) in

S

V

O

C

L

02916-E-057

Rev. J | Page 23 of 28

AD8065/AD8066

I

PHOTO

C

S

V

B

RSH= 1011Ω

CF+C

S

Figure 58. Wideband Photodiode Preamp

INPUT-TO-OUTPUT COUPLING

To minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs.

WIDEBAND PHOTODIODE PREAMP

Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is

RI

×

V

where I

PHOTO

=

OUT

+

1

is the output current of the photodiode, and the

PHOTO

parallel combination of R The stable bandwidth attainable with this preamp is a function

of R

, the gain bandwidth product of the amplifier, and the total

F

capacitance at the amplifier’s summing junction, including C and the amplifier input capacitance. R produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding C loop transmission that compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin (f

F

RsC

FF

and CF sets the signal bandwidth.

F

and the total capacitance

F

creates a 0 in the

F

) is defined by

(45)

S

C

F

R

F

C

M

C

D

C

M

R

F

V

O

02916-E-058

The frequency response in this case shows about 2 dB of peaking and 15% overshoot. Doubling C

and cutting the

F

bandwidth in half results in a flat frequency response with about 5% transient overshoot.

The preamp’s output noise over frequency is shown in Figure 59.

1

F

f

CR

VEN (CF+CS+CM+ 2CD)/C

FREQUENCY (Hz)

F

f

3

F

VOLTAGE NOISE (nV/ Hz)

f

=

1

2πRF(CF+CS+CM+2CD)

f

=

2

2πRFC

f

=

3

(CS+CM+2CD+CF)/C

RF NOISE

f

2

f

1

VEN

NOISE DUE TO AMPLIFIER

Figure 59. Photodiode Voltage Noise Contributions

02916-E-059

f

()

45

where f

is the amplifier crossover frequency, RF is the feedback

CR

resistor, and C

CR

is the total capacitance at the amplifier summing

S

CR

××π=2

F

S

junction (amplifier + photodiode + board parasitics). The value of C

C

F

that produces f

F

C

S

fR

××π=2

F

CR

can be shown to be

(45)

The pole in the loop transmission translates to a 0 in the amplifier’s noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission 0 introduced by C bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which adds to the output noise.

Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Tabl e 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with R

1.6 MHz) are also listed.

Rev. J | Page 24 of 28

limits the amplification. The noise gain

F

= 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about

F

AD8065/AD8066

()(

)

Table 5. RMS Noise Contributions of Photodiode Preamp

Contributor Expression RMS Noise with RF = 50 kΩ, CS = 15 pF, CF = 2 pF

RF (×2)

Amp to f1

Amp (f2 – f1)

Amp to (past f2)

2

F

fVEN ×

1

VEN −×

VEN

S

×

C

S

C

57142 .fRkT

××××

CCCC

+++

2

DFM

F

2

+++

CCCC

FDM

F

ff

12

57.1

××

f

3

270 μV (Total)

V

CC

64.5 μV

2.4 μV

31 μV

260 μV

4.7μF

1

/

AD8066

RF = 500Ω

1

/

AD8066

2

V

EE

RF = 500Ω

V

CC

2

V

EE

0.1μF

0.1μ F

R

S1

V

N

R

G

R

S2

V

P

Figure 60. High Speed Instrumentation Amplifier

HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER

Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065/AD8066. The dc transfer function is

⎛

()

OUT

⎜

VVV

1

PN

⎜ ⎝

For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 Ω for 50 Ω source impedance). The bandwidth for G = +1 is 50 MHz. For higher gains, the bandwidth is set by the preamp, equaling

−

3dB

⎞

1000

⎟

+−=

GCR

⎟

R

G

⎠

RRfInamp ××=

2/

F

2.2pF

R2

500Ω

V

CC

R1

500Ω

R3

500Ω

R4

500Ω

AD8065

V

2.2pF

0.1μF

0.1μ F

EE

4.7μF

4.7μ F

V

O

02916-E-060

Common-mode rejection of the in-amp is primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated

()

V

O

V

CM

δ−δ

=

()

21121δδ+

The summing junction impedance for the preamps is equal to R

|| 0.5(RG). This is the value to be used for matching purposes.

F

Rev. J | Page 25 of 28

AD8065/AD8066

VIDEO BUFFER

The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 61.

The G = +2 configuration compensates for the voltage division of the signal due to the signal termination. This buffer maintains

0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (see Figure 7). Differential gain and phase have been measured to be 0.02% and 0.028°, respectively, at ±5 V supplies.

+V

S

4.7μ F

75Ω

+

V

O

–

02916-E-061

AD8065

–V

S

0.1μ F

2.2pF

499Ω

249Ω

+ V

I

–

499Ω

Figure 61. Video Buffer

Rev. J | Page 26 of 28

AD8065/AD8066

0

OUTLINE DIMENSIONS

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

Figure 62. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.00

2.90

2.80

1.70

1.60

1.50

5

123

4

3.00

2.80

2.60

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

1.30

1.15

0.90

.15 MAX .05 MIN

0.95 BSC

1.90 BSC

SEATING PLANE

0.20 MAX

0.08 MIN

1.45 MAX

0.95 MIN

0.50 MAX

0.35 MIN

COMPLIANT TO JEDEC STANDARDS M O-178-AA

Figure 63. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

3.20

3.00

2.80

8

5

4

0.40

0.25

5.15

4.90

4.65

1.10 MAX

15° MAX

6° 0°

0.23

0.09

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 64. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

Rev. J | Page 27 of 28

10°

5° 0°

0.20

BSC

0.80

0.55

0.40

0.55

0.45

0.35

100709-B

121608-A

AD8065/AD8066

ORDERING GUIDE

1, 2

Model

AD8065AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8065AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8065AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ART-R2 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ART-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ARTZ-R2 AD8065ARTZ-REEL AD8065ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA # AD8065WARTZ-REEL7 −40°C to +105°C 5-Lead SOT-23 RJ-5 H2F# AD8065ART-EBZ Evaluation Board (8-Lead SOIC_N) AD8065AR-EBZ Evaluation Board (5-Lead SOT-23) AD8066AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8066AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ-RL −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ-R7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARM −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARMZ −40°C to +85°C 8-Lead MSOP RM-8 H7C AD8066ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H7C AD8066AR-EBZ Evaluation Board (8-Lead SOIC_N) AD8066ARM-EBZ Evaluation Board (5-Lead SOT-23)

1

Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

2

W = Qualified for Automotive Applications.

Temperature Range Package Description Package Option Branding

−40°C to +85°C 5-Lead SOT-23 RJ-5 HRA #

AUTOMOTIVE PRODUCTS

The AD8065W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. J | Page 28 of 28

ANALOG DEVICES AD8065, AD8066 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

APPLICATIONS

CONNECTION DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS ±5 V

SPECIFICATIONS ±12 V

SPECIFICATIONS +5 V

ABSOLUTE MAXIMUM RATINGS

MAXIMUM POWER DISSIPATION

OUTPUT SHORT CIRCUIT

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

SOIC-8 Pinout

THEORY OF OPERATION

CLOSED-LOOP FREQUENCY RESPONSE

NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE

INVERTING CLOSED-LOOP FREQUENCY RESPONSE

WIDEBAND OPERATION

INPUT PROTECTION

THERMAL CONSIDERATIONS INPUT AND OUTPUT OVERLOAD BEHAVIOR

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

POWER SUPPLY BYPASSING

GROUNDING

LEAKAGE CURRENTS

INPUT CAPACITANCE

OUTPUT CAPACITANCE

INPUT-TO-OUTPUT COUPLING

WIDEBAND PHOTODIODE PREAMP

HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER

VIDEO BUFFER

OUTLINE DIMENSIONS

ORDERING GUIDE

AUTOMOTIVE PRODUCTS