Datasheet AD8063 Datasheet (ANALOG DEVICES)

Low Cost, 300 MHz

V

V

www.BDTIC.com/ADI

FEATURES

Low cost
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Low offset voltage: 6 mV
High speed

300 MHz, −3 dB bandwidth (G = 1)
650 V/μs slew rate

8.5 nV/√Hz at 5 V
35 ns settling time to 0.1% with 1 V step

Operates on 2.7 V to 8 V supplies

Input voltage range = −0.2 V to +3.2 V with V

Excellent video specifications (R

Gain flatness: 0.1 dB to 30 MHz

0.01% differential gain error

0.04° differential phase error
35 ns overload recovery
Low power

6.8 mA/amplifier typical supply current

AD8063 400 μA when disabled

APPLICATIONS

Imaging
Photodiode preamps
Professional video and cameras
Handsets
DVDs/CDs
Base stations
Filters
ADC drivers
Clock buffers

= 150 Ω, G = 2)

L

= 5 V

S

Rail-to-Rail Amplifiers

AD8061/AD8062/AD8063

CONNECTION DIAGRAMS

AD8062

1

AD8061/

1

AD8063

NC

2

–IN

3

+IN

4

S

(Not to Scale)

NC = NO CONNECT

DISABLE

8

(AD8063 ONLY)

7

+V

S

6

V

OUT

5

NC–V

Figure 1. 8-Lead SOIC (R) Figure 2. 8-Lead SOIC (R)/MSOP (RM)

OUT

–

+IN

V

1

2

S

3

(Not to Scale)

AD8063

+V

6

5

DISABLE

–

IN

4

S

Figure 3. 6-Lead SOT-23 (RJ) Figure 4. 5-Lead SOT-23 (RJ)

3

0

VO = 0.2V p-p
R

= 1k

L

V

= 1V

BIAS

–3

R

–6

–12

IN

–9

1

50

V

BIAS

Figure 5. Small Signal Response, R

NORMALIZE D GAIN (dB)

OUT1

–

IN1

+IN1

–

V

S

01065-001

V

01065-002

F

OUT

R

L

FREQUENCY (M Hz)

OUT

–V

+IN

2

3

4

S

(Not to Scale)

AD8061

1

2

3

(Not to Scale)

RF = 0

10010

= 0 Ω, 50 Ω

F

RF = 50

+V

8

S

V

7

OUT2

–

IN2

6

+IN2

5

01065-003

+V

5

S

4

–IN

01065-004

01065-005

1k

GENERAL DESCRIPTION

The AD8061/AD8062/AD8063 are rail-to-rail output voltage
feedback amplifiers offering ease of use and low cost. They have
a bandwidth and slew rate typically found in current feedback
amplifiers. All have a wide input common-mode voltage range
and output voltage swing, making them easy to use on single
supplies as low as 2.7 V.

Despite being low cost, the AD8061/AD8062/AD8063 provide
exce

llent overall performance. For video applications, their

differential gain and phase errors are 0.01% and 0.04° into a

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi­tionally, they offer wide bandwidth to 300 MHz along with
650 V/μs slew rate.

The AD8061/AD8062/AD8063 offer a typical low power of

6.8 mA/

amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 μA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999–2007 Analog Devices, Inc. All rights reserved.

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Connection Diagrams...................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation..................................................... 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics ............................................. 7

Circuit Description......................................................................... 14

REVISION HISTORY

10/07—Rev. D to Rev. E

Changes to Applications .................................................................. 1

Updated Outline Dimensions....................................................... 19

12/05—Rev. C to Rev. D
U

pdated Format..................................................................Universal

Change to Features and General Description............................... 1

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 20

5/01—Rev. B to Rev. C
Repl

aced TPC 9 with new graph .................................................... 7

11/00—Rev. A to Rev. B

2/00—Rev. 0 to Rev. A

11/99—Revision 0: Initial Version

Headroom Considerations........................................................ 14

Overload Behavior and Recovery ............................................ 15

Capacitive Load Drive ............................................................... 16

Disable Operation ...................................................................... 16

Board Layout Considerations................................................... 16

Applications Information.............................................................. 17

Single-Supply Sync Stripper...................................................... 17

RGB Amplifier............................................................................ 17

Multiplexer.................................................................................. 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

Rev. E | Page 2 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 320 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz

−3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 280 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate G = 1, VO = 2 V step, RL = 2 kΩ 500 650 V/μs
G = 2, VO = 2 V step, RL = 2 kΩ 300 500 V/μs
Settling Time to 0.1% G = 2, VO = 2 V step 35 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −77 dBc
f
Crosstalk, Output to Output f = 5 MHz, G = 2, AD8062 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
Differential Gain Error (NTSC) G = 2, RL = 150 Ω 0.01 %
Differential Phase Error (NTSC) G = 2, RL = 150 Ω 0.04 Degrees
Third-Order Intercept f = 10 MHz 28 dBc
SFDR f = 5 MHz 62 dB

DC PERFORMANCE

Input Offset Voltage 1 6 mV
T
Input Offset Voltage Drift 3.5 μV/°C
Input Bias Current 3.5 9 μA
T
Input Offset Current ±0.3 ±4.5 μA

Open-Loop Gain VO = 0.5 V to 4.5 V, RL = 150 Ω 68 70 dB
V
INPUT CHARACTERISTICS

Input Resistance 13 MΩ

Input Capacitance 1 pF

Input Common-Mode Voltage Range −0.2 to

Common-Mode Rejection Ratio VCM = –0.2 V to +3.2 V 62 80 dB
OUTPUT CHARACTERISTICS

Output Voltage Swing (Load Resistance Is Terminated at Midsupply) RL = 150 Ω 0.3 0.1 to 4.5 4.75 V

R

Output Current VO = 0.5 V to 4.5 V 25 50 mA

Capacitive Load Drive, V
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE

Turn-On Time 40 ns

Turn-Off Time 300 ns

DISABLE

DISABLE
POWER SUPPLY

Operating Range 2.7 5 8 V

Quiescent Current per Amplifier 6.8 9.5 mA

Supply Current when Disabled (AD8063 Only) 0.4 mA

Power Supply Rejection Ratio ∆VS = 2.7 V to 5 V 72 80 dB

Voltage (Off)
Voltage (On)

= 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF

OUT

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ −50 dBc

C

to T

MIN

MIN

O

= 2 kΩ 0.25 0.1 to 4.9 4.85 V

L

2.8 V

3.2 V

2 6 mV

MAX

to T

4 9 μA

MAX

= 0.5 V to 4.5 V, RL = 2 kΩ 74 90 dB

+3.2

V

Rev. E | Page 3 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
–3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 250 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate G = 1, VO = 1 V step, RL = 2 kΩ 190 280 V/μs
G = 2, VO = 1.5 V step, RL = 2 kΩ 180 230 V/μs
Settling Time to 0.1% G = 2, VO = 1 V step 40 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −60 dBc
f
Crosstalk, Output to Output f = 5 MHz, G = 2 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz

DC PERFORMANCE

Input Offset Voltage 1 6 mV
T
Input Offset Voltage Drift 3.5 μV/°C
Input Bias Current 3.5 8.5 μA
T
Input Offset Current ±0.3 ±4.5 μA
Open-Loop Gain VO = 0.5 V to 2.5 V, RL = 150 Ω 66 70 dB
V

INPUT CHARACTERISTICS

Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range −0.2 to +12 V
Common-Mode Rejection Ratio VCM = –0.2 V to +1.2 V 80 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing (Load Resistance Is Terminated at Midsupply) RL = 150 Ω 0.3 0.1 to 2.87 2.85 V
R
Output Current VO = 0.5 V to 2.5 V 25 mA
Capacitive Load Drive, V
G = 2, RS = 4.7 Ω 300 pF

POWER-DOWN DISABLE

Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE

DISABLE

POWER SUPPLY

Operating Range 2.7 3 V
Quiescent Current per Amplifier 6.8 9 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio 72 80 dB

Voltage—Off
Voltage—On

= 0.8 V 30% overshoot, G = 1, RS = 0 Ω 25 pF

OUT

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ −44 dBc

C

to T

MIN

MIN

O

= 2 kΩ 0.3 0.1 to 2.9 2.90 V

L

0.8 V

1.2 V

2 6 mV

MAX

to T

4 8.5 μA

MAX

= 0.5 V to 2.5 V, RL = 2 kΩ 74 90 dB

Rev. E | Page 4 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz

G = –1, +2, VO = 0.2 V p-p 60 115 MHz

G = 1, VO = 1 V p-p 230 MHz

Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p, VO dc = 1 V 30 MHz

Slew Rate G = 1, VO = 0.7 V step, RL = 2 kΩ 110 150 V/μs

G = 2, VO = 1.5 V step, RL = 2 kΩ 95 130 V/μs

Settling Time to 0.1% G = 2, VO = 1 V step 40 ns
NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –60 dBc

f

Crosstalk, Output to Output f = 5 MHz, G = 2 –90 dBc

Input Voltage Noise f = 100 kHz 8.5 nV/√Hz

Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE

Input Offset Voltage 1 6 mV

T

Input Offset Voltage Drift 3.5 μV/°C

Input Bias Current 3.5 μA

T

Input Offset Current ±0.3 ±4.5 μA

Open-Loop Gain VO = 0.5 V to 2.2 V, RL = 150 Ω 63 70 dB
V
INPUT CHARACTERISTICS

Input Resistance 13 MΩ

Input Capacitance 1 pF

Input Common-Mode Voltage Range –0.2 to +0.9 V

Common-Mode Rejection Ratio VCM = –0.2 V to +0.9 V 0.8 dB
OUTPUT CHARACTERISTICS

Output Voltage Swing (Load Resistance Is Terminated at Midsupply) RL = 150 Ω 0.3 0.1 to 2.55 2.55 V

R

Output Current VO = 0.5 V to 2.2 V 25 mA

Capacitive Load Drive, V

G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE

Turn-On Time 40 ns

Turn-Off Time 300 ns

DISABLE

DISABLE
POWER SUPPLY

Operating Range 2.7 8 V

Quiescent Current per Amplifier 6.8 8.5 mA

Supply Current when Disabled (AD8063 Only) 0.4 mA

Power Supply Rejection Ratio 80 dB

Voltage (Off)
Voltage (On)

= 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF

OUT

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ –44 dBc

C

to T

MIN

MIN

O

= 2 kΩ 0.25 0.1 to 2.6 2.6 V

L

0.5 V

0.9 V

2 6 mV

MAX

to T

4 8.5 μA

MAX

= 0.5 V to 2.2 V, RL = 2 kΩ 74 90 dB

Rev. E | Page 5 of 20

AD8061/AD8062/AD8063

A

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 8 V
Internal Power Dissipation1

8-lead SOIC (R) 0.8 W
5-lead SOT-23 (RJ) 0.5 W
6-lead SOT-23 (RJ) 0.5 W

8-lead MSOP (RM) 0.6 W
Input Voltage (Common-Mode) (−VS − 0.2 V) to (+VS − 1.8 V)
Differential Input Voltage ±VS
Output Short-Circuit Duration Observe power derating curves
Storage Temperature Range

−65°C to +125°C

R-8, RM-8, SOT-23-5, SOT-23-6
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering,

300°C

10 sec)

1

Specification is for device in free air.

8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W.

5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W.

6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.

8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8061/AD8062/AD8063 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure. While the
AD8061/AD8062/AD8063 is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature (150°C) is not exceeded under all
conditions.

To ensure proper operation, it is necessary to observe the
max

imum power derating curves.

2.0

8-LEAD SOI C

PACKAGE

1.5

TION (W)

1.0

0.5

MSOP

MAXIMUM POWER DISSIP

0
–50 –40

–30

Figure 6. Maximum Power Dissipation vs. Temperature for

SOT-23-5, SOT-23-6

2010

AMBIENT TEMPERATURE (°C)

AD8

061/AD8062/AD8063

TJ = 150°C

605040300–10–20

70 80

01065-006

90

ESD CAUTION

Rev. E | Page 6 of 20

AD8061/AD8062/AD8063

V

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.2

3

1.0

(Unit)

S

0.8

+V

0.6

–V

0.4

0.2

VOLTAGE DIFFERENTIAL FROM

OUT

0

10

0

OUT

@ –40°C

20 30 40 50 60 70 80

LOAD CURRENT (mA)

+V

OUT

@ –40°C

–V

+V

OUT

@ +25°C

@ +25°C

OUT

@ +85°C

Figure 7. Output Saturation Voltage vs. Load Current

18

16

14

12

10

8

6

4

POWER SUPPLY CURRENT (mA)

2

0

2

463

SINGLE POWER SUPPLY (V)

5

–V

OUT

AD8062

AD8061

@ +85°C

7

0

–3

–6

NORMALIZED GAIN (dB)

01065-007

90

–9

–12

VO = 0.2V p-p

= 1k

R

L

V

BIAS

1

= 1V

G = +2

G = +5

FREQUENCY ( MHz)

G = +1

10010

01065-010

1k

Figure 10. Small Signal Frequency Response

3

VO = 1.0V p-p

= 1k

R

L

= 1V

V

BIAS

0

–3

–6

NORMALIZE D GAIN (dB)

–9

01065-008

8

–12

1

G = +5

FREQUENCY (MHz)

G = +1

G = +2

01065-011

10010

1k

Figure 8. I

3

0

VO = 0.2V p-p

= 1k

R

L

= 1V

V

BIAS

–3

–6

–12

IN

–9

1

V

50

BIAS

NORMALIZE D GAIN (dB)

Figure 9. Small Signal Response, R

R

F

vs. V

SUPPLY

FREQUE NCY (MHz)

SUPPLY

OUT

R

L

RF = 0

10010

= 0 Ω, 50 Ω

F

RF = 50

Figure 11. Large Signal Frequency Response

3

0

–3

–6

IN

NORMALIZE D GAIN (dB)

–9

01065-009

1k

–12

1

50

V

BIAS

Figure 12. Small Signal Frequency Response

Rev. E | Page 7 of 20

G = –5

R

F

R

L

FREQUENCY (MHz)

OUT

VS = 5V

= 0.2V p-p

V

O

= 1k

R

L

= 1V

V

BIAS

G = –1

G = –2

10010

01065-012

1k

AD8061/AD8062/AD8063

–

–

www.BDTIC.com/ADI

3

0

–3

G = –2

–6

NORMALIZE D GAIN (dB)

–9

–12

1

G = –5

FREQUENCY (MHz)

VS = 5V
V

= 1V p-p

O

R

= 1k

L

V

= 1V

BIAS

G = –1

10010

01065-013

1k

Figure 13. Large Signal Frequency Response

0.1

0

–0.1

–0.2

–0.3

NORMALIZED GAIN (dB)

–0.4

–0.5

1

VS = 5V

VS = 3V

FREQUENCY (MHz)

VS = 2.7V

10010

VO = 0.2V p-p
R

= 1k

L

V

= 1V

BIAS

G = +1

01065-014

1k

0

–10

–20

–30

–40

–50

–60

–70

HARMONIC DIS TORTION (dBc)

–80

–90

–100

0.5

1.0

2ND @ 1MHz

3RD @ 10MHz

2ND @ 10MHz

INPUT SIG NAL DC BIAS (V)

VS = 5V
R
G = +1

3RD @ 1MHz

2.52.01.5

= 1k

L

3.0

3.5

Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias

40

–50

–60

52.3

–70

–80

DISTORTIO N (dB)

–90

–100

–110

0.01

1.25V

FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)

1k

0.1µF

dc

0.1

5V

604

10µF

0.1µF

+

–

2ND H

+

50

1M INPUT

1k
(R

)

LOAD

3RD H

1

10

50

01065-016

01065-017

Figure 14. 0.1 dB Flatness

80

60

40

20

0

OPEN-LOOP GAIN (dB)

–20

–40

0.01 0.1 1 10 100 1k

Figure 15. AD8062 Open-Loop Gain

SERIES 2

FREQUENCY (MHz)

V

= 5 V, RL = 1 kΩ

S

and Phase vs. Frequency,

SERIES 1

200

150

100

50

0

–50

–100

PHASE (Degrees)

–150

–200

–250

01065-015

–300

Rev. E | Page 8 of 20

Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.

Input Sign

30

–40

–50

–60

–70

–80

DISTORTIO N (dB)

–90

–100

–110

–120

0

2ND

2ND

1

OUTPUT SI GNAL DC BIAS (V)

3RD

al DC Bias

10MHz

3RD

2ND

VS = 5V
R
G = +5

V

5MHz

= 1k

L

= 1V p-p

O

3RD

432

Figure 18. Harmonic Distortion vs. Output Signal DC Bias

1MHz

01065-018

5

AD8061/AD8062/AD8063

–

–

A

A

A

R

A

www.BDTIC.com/ADI

40

VS = 5V
R

= RL = 1k

F

–50

G = +2

–60

–70

–80

DISTORTION (dB)

–90

–100

–110

1.0

50

1k

5V

10µF

+

0.1µF

1k

50

1k

2.52.01.5

RTO OUTPUT (V p-p)

Figure 19. Harmonic Distortion vs. Output Signal Amplitude

30

VS = 5V

= RL = 1k

R

I

–40

= 2V p-p

V

O

G = 2

–50

–60

–70

–80

SINGLE +5V SUPPLY

DISTORTION (dB)

–90

–100

–110

0.01 0.1 1 1 0

S1 2ND HARMONIC/

DUAL ±2.5V SUPPLY

S1 2ND HARMONIC/

FREQUENCY ( MHz, START = 10kHz, STO P = 30MHz)

S1 3RD HARMONIC/

DUAL ±2.5V SUPPLY

Figure 20. Harmonic Distortion vs. Frequency

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

OUTPUT VOLTAGE (V)

0.2

0.1

0

0.10

0.2

TIME (µs)

Figure 21. 400 mV Pulse Response

2ND @ 10MHz

1M
INPUT
TO
3589A

3.0

2ND @ 2MHz

2ND @ 500kHz

3RD @ 2MHz

3RD @ 500kHz

4.0 4.5

3.5

S1 3RD HARMO NIC/
SINGLE +5V SUPPLY

VS = 5V
R

= 1k

L

G = +1

0.3 0.4 0.5

0.01

0

L GAIN

–0.01

(%)

–0.02

–0.04

–0.06

DIFFERENTI

01065-019

DIFFERENTIAL PHASE

1ST 2ND 3RD 4T H 5TH 6T H 7TH 8TH 9TH 10TH 11TH

0.02

0

–0.02

(Degrees)

–0.04

–0.06

1ST 2ND 3RD 4T H 5TH 6T H 7TH 8TH 9TH 10TH 11TH

01065-022

Figure 22. Differential Gain and Phase Error, G = 2,

NTSC Input S

0.010

L GAIN

0.005

(%)

0

–0.005

–0.010

DIFFERENTI

L PHASE

01065-020

DIFFERENTI

1ST 2ND 3RD 4 TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

0.04

0.03

0.02

0.01

(Degrees)

0

–0.01

–0.02

1ST 2ND 3RD 4 TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

ignal, R

= 1 kΩ, VS = 5 V

L

01065-023

Figure 23. Differential Gain and Phase Error, G = 2,

= 150 Ω, VS = 5 V

NTSC Input S

1000

900

VS = 5V

= 1k

R

800

700

600

TE (V/µs)

500

400

SLEW

300

200

100

01065-021

L

G = +1

0

1.0

ignal, R

L

FALL I NG E DG E

RISING EDG E

1.5

OUTPUT ST EP AMPLITUDE (V)

2.0 2.5

3.0

01065-024

Figure 24. Slew Rate vs. Output Step Amplitude

Rev. E | Page 9 of 20

AD8061/AD8062/AD8063

R

A

R

www.BDTIC.com/ADI

1400

1200

1000

800

TE (V/µs)

600

SLEW

400

200

0

04

FALLING EDGE

1.0 1.5

0.5 3.0 3.5

FALL I NG E DG E

V

= +5V

S

OUTPUT STEP (V)

V

=±4V

S

RISING EDGE

V

= +5V

S

2.0

2.5

RISING EDG E

Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, R

V

=±4V

S

= 1 kΩ, VS = 5 V

L

V

2.

5V

VOLTS

0V

500mV/DIV

01065-025

.0

0 20 4 0 60 80 100 120 140 160 180 200

IN

V

OUT

Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V

TIME (ns)

VS = ±2.5V
G = +1
R

= 1k



L

01065-028

1k

VS = 5V
R

100

10

VOLTAGE NOISE (nV/ Hz)

1

10 10M100 1k 100k 1M

10k

FREQUENCY (Hz)

Figure 26. Voltage Noise vs. Frequency

100

VS = 5V
R

10

1

CURRENT NOISE (pA/ Hz)

0

10 10M

100 1k 100k 1M

10k

FREQUENCY (Hz)

Figure 27. Current Noise vs. Frequency

= 1k

L

= 1k

L

VS = ±2.5V
G = +5

= 1k



R

L

V

2.5V

VOLTS

1.0V

0V

500mV/DIV

01065-026

0 20 4 0 60 80 100 120 140 160 180 200

Figure 29. Output Overload Recovery, Input Step

0

VCM = 0.2V p-p

–10

R

= 100

L

V

= ±2.5V

S

–20

–30

–40

(dB)

–50

CMR

–60

–70

–80

01065-027

–90

–100

0.01 500

0.1 10 100

OUT

V

IN

TIME (ns)

SIDE 2

V

IN

200mV p-p

1

FREQUENCY (MHz)

604

154

57.6

01065-029

= 0 V to 1 V

SIDE 1

604

50

154

01065-030

Figure 30. CMRR vs. Frequency

Rev. E | Page 10 of 20

AD8061/AD8062/AD8063

–

A

www.BDTIC.com/ADI

7

VS = 5V

6

5

4

(mA)

3

SUPPLY

I

2

1

0

1.0

Figure 34. AD8063

1.5 2.0 2.5

DISABLE VOLTAGE

DISABLE

3.5 4.0 4.5

3.0

Voltage vs. Supply Current

01065-034

5.0

PSRR (dB)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

VS = 0.2V p-p
R

= 1k

L

= 5V

V

S

0.01

1

FREQUENCY ( MHz)

Figure 31. ±PSRR vs. Frequency Delta

–PSRR

+PSRR

01065-031

5000.1 10 100

20

–30

–40

–50

–60

–70

–80

–90

–100

OUTPUT TO OUT PUT CROSSTALK (dB)

–110

–120

Figure 32. AD8062 Crosstalk, V

–10

–20

–30

TION (dB)

–40

–50

–60

DISABLED ISOL

–70

–80

–90

0.01

0

1k

1k

+2.5V

IN

50

–2.5V

INPUT = SIDE 2 INPUT = SIDE 1

0.1

1

1

FREQUENCY (MHz)

OUT

FREQUENCY ( MHz)

Figure 33. AD8063 Disabled Output

OUT

1k

VS = 5V
V

= 400mV rms

IN

R

= 1k

L

G = +2

10

100

500

= 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V

VS = 5V
V

= 0.2V p-p

O

R

= 1k

L

V

= 1V

BIAS

10010

1k

Isolation Frequency Response

6

5

4

3

2

OUTPUT VOLTAGE (V)

1

0

01065-032

–1

Figure 35. AD8063

1k

100

10

IMPEDANCE ()

0.1

01065-033

0.01

V

DISABLE

V

OUT

02

1

0.1 1k

VS = 5V
V

= 0.2V p-p

O

R

= 1k

L

V

BIAS

0.4

= 1V

Figure 36. Output Imped

V

OUT

0.8

DISABLE

1 10 100

FREQUENCY ( MHz)

1.2 1.6

TIME (µs)

Function, Voltage = 0 V to 5 V

ance vs. Frequency,

= 0.2 V p-p, RL = 1 kΩ, VS = 5 V

VS = 5V
G = +2
f

= 10MHz

IN

@ 1.3V
RL = 100

BIAS

01065-035

.0

01065-036

Rev. E | Page 11 of 20

AD8061/AD8062/AD8063

%

www.BDTIC.com/ADI

+0.1%

VS = 5V

= 1k

R

L

3.5V

VS = 5V
G = +2

= 1k

R

L

V

= 1V p-p

IN

–0.1%

SETTLING TIME TO 0.1

SETTLING TIME (ns)

t = 0

20ns/DIV

Figure 37. Output Settling Time to 0.1%

50

FALLING EDGE

45

40

35

30

25

20

15

10

5

0

0.5

1.0 1.5 2.0

OUTPUT VOLTAGE STEP

Figure 38. Settling Time vs. V

1k

1k

50

RISING EDGE

OUT

2.5V

VOLTS

1.5V

RL = 1k

500mV/DIV

01065-037

01020 80 90100

TIME (ns)

7060504030

01065-040

Figure 40. 1 V Step Response

VS = 5V
G = +2
R

= 1k

2.6V

2.5V

VOLTS

2.4V

VS = 5V

= 1k

R

L

G = +1

01065-038

2.5

20mV/DIV

0 10 20 80 90 100

TIME (ns)

Figure 41. 100 mV Step Response

L

V

= 100mV

IN

7060504030

01065-041

4.86V

2.43V

VOLTS

VS = 5V
G = –1

= 1k

R

F

= 1k

R

L

VOLTS

0V

0V

1V

2µs

01065-039

2µs/DIV

VS = 5V
G = +2
R

= RL = 1k

F

V

= 4V p-p

IN

1V/DIV

01065-042

Figure 39. Output Swing

Figure 42. Output Rail-to-Rail Swing

Rev. E | Page 12 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

VS = 5V
G = +2
R

= RF = 1k

L

V

= 2V p-p

IN

2.6V

VS = 5V
G = +1
R

= 1k

L

4.5V

2.5V

VOLTS

2.4V

50mV/DIV

0 5 10 40 45 50

TIME (ns)

3530252015

Figure 43. 200 mV Step Response

01065-043

2.5V

VOLTS

0.5V

1V/DIV

0 5 10 40 45 50

TIME (ns)

3530252015

Figure 44. 2 V Step Response

01065-044

Rev. E | Page 13 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

CIRCUIT DESCRIPTION

The AD8061/AD8062/AD8063 family is comprised of high
speed voltage feedback op amps. The high slew rate input stage
is a true, single-supply topology, capable of sensing signals at or
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads
and within 0.3 V when driving 150 Ω. High speed perform­ance is maintained at supply voltages as low as 2.7 V.

HEADROOM CONSIDERATIONS

These amplifiers are designed for use in low voltage systems.
To obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.

The AD8061/AD8062/AD8063 input common-mode voltage
r

ange extends from the negative supply voltage (actually 200 mV

below this), or ground for single-supply operation, to within

1.8 V of the positive supply voltage. Thus, at a gain of 2, the
AD8061/AD8062/AD8063 can provide full rail-to-rail output
swing for supply voltage as low as 3.6 V, assuming the input
signal swings from −V
the AD8061/AD8062/AD8063 can provide a rail-to-rail output
range down to 2.7 V total supply voltage.

Exceeding the headroom limit is not a concern for any inverting

in on any supply voltage, as long as the reference voltage at

ga
the amplifier’s positive input lies within the amplifier’s input
common-mode range.

The input stage is the headroom limit for signals when the
a

mplifier is used in a gain of 1 for signals approaching the

positive rail.

mmon-mode voltage for the AD8061/AD8062/AD8063

co

Figure 45 shows a typical offset voltage vs. input

amplifier on a 5 V supply. Accurate dc performance is main­tained from approximately 200 mV below the minus supply
to within 1.8 V of the positive supply. For high speed signals,
however, there are other considerations.

andwidth vs. dc input voltage for a unity-gain follower. As

b
the common-mode voltage approaches the positive supply,
the amplifier holds together well, but the bandwidth begins to
drop at 1.9 V within +V

This manifests itself in increased distortion or settling time.
Figure 16 plots the distortion of a 1 V p-p signal with the
AD8061/AD80

62/AD8063 amplifier used as a follower on
a 5 V supply vs. signal common-mode voltage. Distortion
performance is maintained until the input signal center voltage
gets beyond 2.5 V, as the peak of the input sine wave begins to
run into the upper common-mode voltage limit.

(or ground) to +VS/2. At a gain of 3,

S

Figure 46 shows −3 dB

.

S

–0.4

–0.8

–1.2

–1.6

–2.0

(mV)

OS

–2.4

V

–2.8

–3.2

–3.6

e, V

01065-045

01065-046

= 5 V

S

–4.0

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3. 5 4.0

Figure 45. V

2

0

–2

GAIN (dB)

–4

–6

–8

0.1

Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mod

vs. Common-Mode Voltage, VS = 5 V

OS

1 10 100 1k 10k

VCM (V)

FREQUENCY ( MHz)

VCM = 3.0

V

= 3.1

CM

V

= 3.2

CM

V

= 3.3

CM

V

= 3.4

CM

Higher frequency signals require more headroom than lower
frequencies to maintain distortion performance. Figure 47
ill

ustrates how the rising edge settling time for the amplifier
configured as a unity-gain follower stretches out as the top of
a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.

For signals approaching the minus supply and inverting gain

nd high positive gain configurations, the headroom limit is

a
the output stage. The AD8061/AD8062/AD8063 amplifiers use
a common emitter style output stage. This output stage
maximizes the available output range, limited by the saturation
voltage of the output transistors. The saturation voltage
increases with the drive current the output transistor is required
to supply, due to the output transistors’ collector resistance. The
saturation voltage is estimated using the equation

= 25 mV + IO × 8 Ω

V

SAT

where:

I

is the output current.

O

8 Ω is a typical value for the output transistors’ collector
resistance.

Rev. E | Page 14 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

3.6

3.4

3.2

3.0

2.8

2.6

2.4

OUTPUT VOLTAGE (V)

2.2

2.0

0

4 8 12 16 20 24 28 32

2V TO 3V ST EP

2.1V TO 3. 1V STEP

2.2V TO 3.2V STEP

2.3V TO 3. 3V STEP

TIME (ns)

2.4V TO 3.4V STEP

01065-047

Figure 47. Output Rising Edge for 1 V Step at

Input

Headroom Limits, G = 1, V

= 5 V, 0 V

S

As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals.

Figure 16, Figure 17, and Figure 18 illustrate this point,

pl

otting typical distortion vs. output amplitude and bias for

gains of 2 and 5.

OVERLOAD BEHAVIOR AND RECOVERY

Input

The specified input common-mode voltage of the AD8061/
AD8062/AD8063 is −200 mV below the negative supply to
within 1.8 V of the positive supply. Exceeding the top limit
results in lower bandwidth and increased settling time as seen
in

Figure 46 and Figure 47. Pushing the input voltage of a unity-

in follower beyond 1.6 V within the positive supply leads to

ga
the behavior shown in

utput error and much increased settling time. Recovery time

o
from input voltages 1.6 V or closer to the positive supply is
approximately 35 ns, which is limited by the settling artifacts
caused by transistors in the input stage coming out of saturation.

The AD8061/AD8062/AD8063 family does not exhibit phase

versal, even for input voltages beyond the voltage supply rails.

re
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.

Figure 48—an increasing amount of

3.7

3.5

3.3

3.1

VOLTAGE STEP
FROM 2.4V TO 3.4V

2.9

2.7

OUTPUT VOLTAGE (V)

2.5

2.3

2.1
0

VOLTAGE STEP
FROM 2.4V TO 3.6V

VOLTAGE STEP
FROM 2. 4V TO 3.8V,
4V AND 5V

200 300 400 500 600

100

TIME (ns)

01065-048

Figure 48. Pulse Response for G = 1 Follower,

Input Step Ov

erloading the Input Stage

Output

Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49

hows output recovery transients for the amplifier recovering

s
from a saturated output from the top and bottom supplies to a
point at midsupply.

5.0

4.6

4.2

3.8

3.4

3.0

2.6

2.2

1.8

1.4

1.0

INPUT AND OUTPUT VOLTAGE (V)

0.6

0.2

–0.2

INPUT VOLTAGE

EDGES

10 20 30 40 50 60 70

0

TIME (ns)

Figure 49. Overload R

ecovery, G = −1, V

OUTPUT VOLTAGE
5V TO 2.5V

OUTPUT VOLTAGE
0V TO 2.5V

R

V

IN

2.5V

–

= 5 V

S

R

5V

V

O

–

01065-049

Rev. E | Page 15 of 20

AD8061/AD8062/AD8063

V

V

A

www.BDTIC.com/ADI

CAPACITIVE LOAD DRIVE DISABLE OPERATION

The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:

• U

se a small resistor in series with the amplifier’s output and

the load capacitance.

• Reduce the bandwidth of the amplifier’s feedback loop by

increasing the overall noise gain.

Figure 50 shows a unity-gain follower using the series resistor

trategy. The resistor isolates the output from the capacitance

s
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.

R

AD8061

IN

Figure 50. Series Resistor Isolating Capacitive Load

SERIES

C

LOAD

V

O

01065-050

Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop.
p

roduces 30% overshoot vs. noise gain for a typical amplifier.

10k

1k

PACITIVE LOAD (p F)

100

C

10

12

Figure 51. Capacitive Load vs. Closed-Loop Gain

Figure 51 plots the capacitance that

RS = 4.7

RS = 0

34

CLOSED-LOOP GAIN

01065-051

5

The internal circuit for the AD8063 disable function is shown
in Figure 52. When the

DISABLE

node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 μA, and the AD8063 output
enters a high impedance state. If the

DISABLE

node is not
connected and allowed to float, the AD8063 stays biased at
full power.

CC

2V

TO AMPLIFIER

DISABLE

VEE

Figure 52. Disable Circuit of the AD8063

Figure 34 shows the AD8063 supply current vs.

DISABLE

BIAS

voltage. Figure 35 plots the output seen when the AD8063 input
is dr

iven with a 10 MHz sine wave, and

DISABLE

is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time.

Figure 33 shows the input/output isolation response with

e AD8063 shut off.

th

BOARD LAYOUT CONSIDERATIONS

Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.

The PCB should have a ground plane covering unused portions

the component side of the board to provide a low impedance

of
path. Remove the ground plane near the package to reduce
parasitic capacitance.

Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor
t

o bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 μF to
10 μF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.

Minimizing parasitic capacitance at the amplifier’s inverting

put pin is very important. Locate the feedback resistor close to

in
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.

01065-052

Rev. E | Page 16 of 20

AD8061/AD8062/AD8063

V

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

SINGLE-SUPPLY SYNC STRIPPER

When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of analog-to-digital conversion,
the sync pulses consume some of the dynamic range, so
removing them increases the converter’s available dynamic
range for the video information.

Figure 53 shows a basic circuit for creating a sync stripper using

e AD8061 powered by a single supply. When the negative

th
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.

3

0.1µF

7

VIDEO IN

75

3

AD8061

2

R

G

1k

R

4

F

1k

Figure 53. Single 3 V Sync Stripper Using AD8061

In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Because the sync level is
below the black level, it does not show up at the output. However,
all of the active video portion of the waveform is amplified by a
gain of 2 and then normalized to unity gain by the back­terminated transmission line.

the input and output waveforms.

of

1

2

500mV

Figure 54. Input and Output Wave

Video Sync Stripper Using an AD8061

Figure 54 is an oscilloscope plot

Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at a positive voltage.

10µF

6

75

PIN NUMBE RS ARE
FOR 8-LEAD PACKAGE

10µs

forms for a Single-Supply

VIDEO OUT

75

INPUT

OUTPUT

01065-054

01065-053

The circuit can be modified to provide the sync stripping

unction for such a waveform. Instead of connecting R

f

G

to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the noninverting input
to the output is 2, which means the black level is amplified by 2
to the output. However, the gain through R

is −1 to the output.

G

It takes a dc level of twice the input black level to shift the black
level to ground at the output. When this occurs, the sync is
stripped, and the active video is passed as in the ground­referenced case.

RED
DAC

GREEN

DAC

BLUE

DAC

75

75

75

1k

1k

1k

2

3

2

3

5

6

3V

7

AD8061

4

3V

8

AD8062

AD8062

1k

1k

0.1µF

1k

0.1µF

75

75

75

6

MONITOR

#1

10µF

10µF

1

7

4

75

75

75

RED

75

MONITOR

#2

GREEN

75

BLUE

75

Figure 55. RGB Cable Driver Using AD8061 and AD8062

RGB AMPLIFIER

Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.

However, high speed, rail-to-rail output amplifiers like the
AD8061 an
output ground-level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system.

d AD8062 accept ground-level input signals and

Figure 55 shows a circuit that performs this function.

01065-055

Rev. E | Page 17 of 20

AD8061/AD8062/AD8063

V

2

p

www.BDTIC.com/ADI

MULTIPLEXER

The AD8063 has a disable pin used to power down the ampli­f

ier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gain­step amplifier or a selectable frequency amplifier.

Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.

+4

10µF

0.1µF

–4V

+4V

1

0.1µF

1k

10µF

49.9

49.9

V

OUT

1V p-p
3MHz

TIME

BASE

OUT

49.9

1k

AD8063

The select signal and the output waveforms for this circuit are
shown in Figure 57. For synchronization clarity, two different
f

requency synthesizers, whose time bases are locked to each

other, generate the signals.

2µs

OUTPUT

SELECT

1V

Figure 57. AD8063 Mux Output

2V

01065-057

V p-

1MHz

10µF

0.1µF

–4V

1

0.1µF

1k

HCO4

10µF

TIME

BASE

IN

SELECT

49.9

1k

AD8063

Figure 56. Two-to-One Multiplexer Using Two AD8063s

01065-056

Rev. E | Page 18 of 20

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.90 BSC

1.60 BSC

1.30

1.15

0.90

0.15 MAX

5

123

PIN 1

COMPLIANT TO JEDEC STANDARDS MO-178-AA

1.90

BSC

0.50

0.30

4

2.80 BSC

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

2.90 BSC

1.90
BSC

0.50

0.30

45

2.80 BSC

2

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

1.60 BSC

PIN 1

INDICATOR

1.30

1.15

0.90

0.15 MAX

6

1 3

10°

5°
0°

10°

5.00 (0.1968)

4.80 (0.1890)

0.60

0.45

0.30

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSI ONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NO T APPROPRIATE FOR US E IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.60

4°

0.45

0°

0.30

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 60. 6-Lead Small Outline Transistor Package [SOT-23]

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 61. 8-Lead Mini Small Outline Package [MSOP]

(RJ-6)

Dimensions shown in millimeters

Dimensions shown in millimeters

Rev. E | Page 19 of 20

(RM-8)

AD8061/AD8062/AD8063

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8061AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8061AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8061AR-REEL7 −40°C to +85°C 8-Lead SOIC_N,
AD8061ARZ
AD8061ARZ-REEL
AD8061ARZ-REEL7

1

1

1

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8

−40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8061ART-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5
AD8061ART-REEL −40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5
AD8061ART-REEL7 −40°C to +85°C 5-Lead SOT
AD8061ARTZ-R2
AD8061ARTZ-REEL
AD8061ARTZ-REEL7

1

1

−40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 H0D

−40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5 H0D

1

−40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 H0D
AD8062AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8062AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8062AR-REEL7 −40°C to +85°C 8-Lead SOIC_N,
AD8062ARZ
AD8062ARZ-RL
AD8062ARZ-R7

1

1

1

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8

−40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8062ARM −40°C to +85°C 8-Lead MSOP RM-8
AD8062ARM-REEL −40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8
AD8062ARM-REEL7 –40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8
AD8062ARMZ
AD8062ARMZ-RL
AD8062ARMZ-R7

1

1

1

−40°C to +85°C 8-Lead MSOP RM-8 #HCA

−40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8 #HCA

–40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8 #HCA
AD8063AR –40°C to +85°C 8-Lead SOIC_N R-8
AD8063AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8063AR-REEL7 –40°C to +85°C 8-Lead SOIC_N,
AD8063ARZ
AD8063ARZ-REEL
AD8063ARZ-REEL7

1

1

1

40°C to +85°C 8-Lead SOIC_N R-8

40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8

40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8063ART-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6
AD8063ART-REEL –40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6
AD8063ART-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6
AD8063ARTZ-R2
AD8063ARTZ-REEL
AD8063ARTZ-REEL7

1

Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.

2

New branding after data code 0542, previously branded HGA.

3

New branding after data code 0542, previously branded HHA.

1

1

–40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 H0E

–40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6 H0E

1

–40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 H0E

7-Inch Tape and Reel R-8

HGA
HGA

-23, 7-Inch Tape and Reel RJ-5 HGA

2

2

2

7-Inch Tape and Reel R-8

HCA
HCA
HCA

7-Inch Tape and Reel R-8

HHA
HHA
HHA

3

3

3

©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01065-0-10/07(E)

Rev. E | Page 20 of 20