Datasheet AD8029 Datasheet (Analog Devices)

Low Power, High Speed

FEATURES

Low power

1.3 mA supply current/amplifier
High speed
125 MHz, –3 dB bandwidth (G = +1)
60 V/µs slew rate
80 ns settling time to 0.1%
Rail-to-rail input and output
No phase reversal, inputs 200 mV beyond rails
Wide supply range: 2.7 V to 12 V
Offset voltage: 6 mV max
Low input bias current

+0.7 µA to –1.5 µA
Small packaging
SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14

APPLICATIONS

Battery-powered instrumentation
Filters
A-to-D drivers
Buffering

GENERAL DESCRIPTION

The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output high speed amplifiers with a
quiescent current of only 1.3 mA per amplifier. Despite their
low power consumption, the amplifiers provide excellent
performance with 125 MHz small signal bandwidth and
60 V/µs slew rate. ADI’s proprietary XFCB process enables high
speed and high performance on low power.

This family of amplifiers exhibits true single-supply operation
with rail-to-rail input and output performance for supply
voltages ranging from 2.7 V to 12 V. The input voltage range
extends 200 mV beyond each rail without phase reversal. The
dynamic range of the output extends to within 40 mV of each
rail.

The AD8029/AD8030/AD8040 provide excellent signal quality
with minimal power dissipation. At G = +1, SFDR is –72 dBc at
1 MHz and settling time to 0.1% is only 80 ns. Low distortion
and fast settling performance make these amplifiers suitable
drivers for single-supply A/D converters.

The versatility of the AD8029/AD8030/AD8040 allows the user
to operate the amplifiers on a wide range of supplies while
consuming less than 6.5 mW of power. These features extend
the operation time in applications ranging from battery-

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Rail-to-Rail Input/Output Amplifier

AD8029/AD8030/AD8040

CONNECTION DIAGRAMS

1

NC

–IN

2

+IN

3

–V

4

S

NC = NO CONNECT

Figure 1. SOIC-8 (R)

1

V

1

OUT

–IN 1

2

+IN 1

3

4

–V

S

Figure 3. SOIC-8(R) and

SOT23-8 (RJ)

powered systems with large bandwidth requirements to high
speed systems where component density requires lower power
dissipation.

The AD8029/AD8030 are the only low power, rail-to-rail input
and output high speed amplifiers available in SOT23 and SC70
micro packages. The amplifiers are rated over the extended
industrial temperature range, –40°C to +125°C.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0

0.5

0

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

8

DISABLE
+V

7
6

V

5

NC

S

OUT

V

1

OUT

–V

2

S

3

+IN

03679-A-004

+–

6

5

4

Figure 2. SC70-6 (KS)

V

1

1

OUT

–IN 1

2

+IN 1

3

4

8

+V

S

7

+V

2

OUT

–IN 2

6

5

+IN 2

+V

S

+IN 2

5

–IN 2

6

V

2

7

OUT

03679-A-003

Figure 4. SOIC-14 (R) and

TSSOP-14 (RU)

INPUT

OUTPUT

G = +1
V

= +5V

S

R

= 1kΩ TIED TO MIDSUPPLY

L

TIME (µs)

03679-A-010

Figure 5. Rail-to-Rail Response

www.analog.com

+V

S

DISABLE

–IN

14

V

OUT

13

–IN 4
+IN 4

12

11

–V

10

+IN 3
–IN 3

9

V

8

OUT

1µs/DIV

03679-A-002

4

S

3

03679-A-001

AD8029/AD8030/AD8040

TABLE OF CONTENTS

Specifications..................................................................................... 3

Specifications with ±5 V Supply ................................................. 3

Specifications with +5 V Supply ................................................. 4

Specifications with +3 V Supply ................................................. 5

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation ..................................................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 15

Input Stage................................................................................... 15

Output Stage................................................................................ 15

Applications..................................................................................... 16

Wideband Operation................................................................. 16

Output Loading sensitivity........................................................ 16

Disable Pin .................................................................................. 17

Circuit Considerations .............................................................. 18

Design Tools and Technical Support....................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide............................................................................... 20

ESD Caution................................................................................ 20

REVISION HISTORY

Revision A
11/03—Data Sheet Changed from Rev. 0 to Rev. A

Change Page

Added AD8040 part .......................................................Universal

Change to Figure 5 ....................................................................... 1

Changes to Specifications............................................................ 3

Changes to Figures 10–12............................................................ 7

Change to Figure 14 ..................................................................... 8

Changes to Figures 20 and 21 ..................................................... 9

Inserted new Figure 36............................................................... 11

Change to Figure 40 ................................................................... 12

Inserted new Figure 41............................................................... 12

Added Output Loading Sensitivity section............................. 16

Changes to Table 5...................................................................... 17

Changes to Power Supply Bypassing section .......................... 18

Changes to Ordering Guide...................................................... 20

Rev. A | Page 2 of 20

AD8029/AD8030/AD8040

SPECIFICATIONS

SPECIFICATIONS WITH ±5 V SUPPLY

Table 1. VS = ±5 V @ TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted. All specifications are per amplifier.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.1 V p-p 80 125 MHz
G = +1, VO = 2 V p-p 14 19 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.1 V p-p 6 MHz

Slew Rate G = +1, VO = 2 V Step 62 V/µs

G = –1, VO = 2 V Step 63 V/µs

Settling Time to 0.1% G = +2, VO = 2 V Step 80 ns
NOISE/DISTORTION PERFORMANCE

Spurious Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p –74 dBc
f

Input Voltage Noise f = 100 kHz 16.5

Input Current Noise f = 100 kHz 1.1

Crosstalk (AD8030/AD8040) f = 5 MHz, VIN = 2 V p-p
DC PERFORMANCE

Input Offset Voltage PNP Active, VCM = 0 V 1.6 5 mV

NPN Active, VCM = 4.5 V 2 6 mV

Input Offset Voltage Drift T

Input Bias Current

1

T
PNP Active, VCM = 0 V –1.7 –2.8 µA
T

Input Offset Current ±0.1 ±0.9 µA

Open-Loop Gain Vo = ±4.0 V 65 74 dB
INPUT CHARACTERISTICS

Input Resistance 6 MΩ

Input Capacitance 2 pF

Input Common-Mode Voltage Range –5.2 to +5.2 V

Common-Mode Rejection Ratio VCM = –4.5 V to +3 V, RL = 10 kΩ 80 90 dB
DISABLE

PIN (AD8029)

DISABLE

Low Voltage

DISABLE

Low Current

DISABLE

High Voltage

DISABLE

High Current

Turn-Off Time

Turn-On Time

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge) VIN = +6 V to –6 V, G = –1 55/45 ns
Output Voltage Swing RL = 1 kΩ –VS + 0.22 +VS – 0.22 V
R
Short-Circuit Current Sinking and Sourcing 170/160 mA
Off Isolation (AD8029)

Capacitive Load Drive 30% Overshoot 20 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current/Amplifier 1.4 1.5 mA
Quiescent Current (Disabled) DISABLE
Power Supply Rejection Ratio Vs ± 1 V 73 80 dB

1

Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.

= 5 MHz, VO = 2 V p-p –56 dBc

C

Hz

nV/√

Hz

pA/√

dB

MIN

to T

MAX

–79

30 µV/°C

NPN Active, VCM = 4.5 V 0.7 1.3 µA

MIN

MIN

to T

to T

MAX

MAX

1 µA

2 µA

–V

+ 0.8 V

S

–6.5 µA
–V

+ 1.2 V

S

0.2 µA
DISABLE

50% of
VIN = –1 V, G = –1

DISABLE

50% of

to <10% of Final VO,

to <10% of Final VO,

150 ns

85 ns

VIN = –1 V, G = –1

= 10 kΩ –VS + 0.05 +VS – 0.05 V

L

V

= 0.1 V p-p, f = 1 MHz,

IN

= Low

DISABLE

= Low

–55 dB

150 200 µA

Rev. A | Page 3 of 20

AD8029/AD8030/AD8040

SPECIFICATIONS WITH +5 V SUPPLY

Table 2. VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.1 V p-p 80 120 MHz

G = +1, VO = 2 V p-p 13 18 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.1 V p-p 6 MHz
Slew Rate G = +1, VO = 2 V Step 55 V/µs

G = –1, VO = 2 V Step 60 V/µs

Settling Time to 0.1% G = +2, VO = 2 V Step 82 ns

NOISE/DISTORTION PERFORMANCE

Spurious Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p –73 dBc

f

Input Voltage Noise f = 100 kHz 16.5
Input Current Noise f = 100 kHz 1.1
Crosstalk (AD8030/AD8040) f = 5 MHz, VIN = 2 V p-p -79 dB

DC PERFORMANCE

Input Offset Voltage PNP Active, VCM = 2.5 V 1.4 5 mV

NPN Active, VCM = 4.5 V 1.8 6 mV

Input Offset Voltage Drift T
Input Bias Current

1

T

T

Input Offset Current ±0.1 ±0.9 µA
Open-Loop Gain Vo = 1 V to 4 V 65 74 dB

INPUT CHARACTERISTICS

Input Resistance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range –0.2 to +5.2 V
Common-Mode Rejection Ratio VCM = 0.25 V to 2 V, RL = 10 kΩ 80 90 dB

DISABLE

PIN (AD8029)
DISABLE
DISABLE
DISABLE
DISABLE

Low Voltage
Low Current
High Voltage
High Current

Turn-Off Time

Turn-On Time

OUTPUT CHARACTERISTICS

Overdrive Recovery Time

(Rising/Falling Edge) VIN = –1 V to +6 V, G = –1 45/50 ns

Output Voltage Swing RL = 1 kΩ –VS + 0.17 +VS – 0.17 V

R

Short-Circuit Current Sinking and Sourcing 95/60 mA
Off Isolation (AD8029)
Capacitive Load Drive 30% Overshoot 15 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current/Amplifier 1.3 1.5 mA

Quiescent Current (Disabled)

Power Supply Rejection Ratio VS ± 1 V 73 80 dB

1

Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.

= 5 MHz, VO = 2 V p-p –55 dBc

C

Hz

nV/√

Hz

pA/√

to T

MIN

25 µV/°C

MAX

NPN Active, VCM = 4.5 V 0.8 1.2 µA

to T

MIN

1 µA

MAX

PNP Active, VCM = 2.5 V –1.8 –2.8 µA

to T

MIN

2 µA

MAX

–V

+ 0.8 V

S

–6.5 µA
–V

+ 1.2 V

S

0.2 µA
DISABLE

50% of
VIN = –1 V, G = –1

DISABLE

50% of
VIN = –1 V, G = –1

= 10 kΩ –VS + 0.04 +VS – 0.04 V

L

= 0.1 V p-p, f = 1 MHz,

V

in

DISABLE

to <10% of Final VO,

to <10% of Final VO,

= Low

DISABLE

= Low

–55 dB

140 200 µA

155

ns

90

ns

Rev. A | Page 4 of 20

AD8029/AD8030/AD8040

SPECIFICATIONS WITH +3 V SUPPLY

Table 3. VS = +3 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.1 V p-p 80 112 MHz

G = +1, VO = 2 V p-p 13 18 MHz

Bandwidth for 0.1 dB Flatness G = +2, VO = 0.1 V p-p 6 MHz
Slew Rate G = +1, VO = 2 V Step 55 V/µs

G = –1, VO = 2 V Step 57 V/µs

Settling Time to 0.1% G = +2, VO = 2 V Step 110 ns

NOISE/DISTORTION PERFORMANCE

Spurious Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p –72 dBc

f

Input Voltage Noise f = 100 kHz 16.5
Input Current Noise f = 100 kHz 1.1
Crosstalk (AD8030/AD8040) f = 5 MHz, VIN = 2 V p-p -80 dB

DC PERFORMANCE

Input Offset Voltage PNP Active, VCM = 1.5 V 1.1 5 mV

NPN Active, VCM = 2.5 V 1.6 6 mV

Input Offset Voltage Drift T
Input Bias Current

1

T

Input Bias Current

1

T

Input Offset Current ±0.1 ±0.9 µA
Open-Loop Gain Vo = 0.5 V to 2.5 V 64 73 dB

INPUT CHARACTERISTICS

Input Resistance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range –0.2 to +3.2 V
Common-Mode Rejection Ratio VCM = 0.25 V to 1.25 V, RL = 10 kΩ 78 88 dB

DISABLE

PIN (AD8029)

DISABLE

Low Voltage

DISABLE

Low Current

DISABLE

High Voltage

DISABLE

High Current

Turn-Off Time

Turn-On Time

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge) VIN = –1 V to +4 V, G = –1 75/100 ns

Output Voltage Swing RL = 1 kΩ –VS + 0.09 +VS – 0.09 V

R

Short-Circuit Current Sinking and Sourcing 80/40 mA
Off Isolation (AD8029)
Capacitive Load Drive 30% Overshoot 10 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current/Amplifier 1.3 1.4 mA
Quiescent Current (Disabled)
Power Supply Rejection Ratio VS ± 1 V 70 76 dB

1

Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.

= 5 MHz, VO = 2 V p-p –60 dBc

C

Hz

nV/√

Hz

pA/√

to T

MIN

24 µV/°C

MAX

NPN Active, VCM = 2.5 V 0.7 1.2 µA

to T

MIN

1 µA

MAX

PNP Active, VCM = 1.5 V –1.5 –2.5 µA

to T

MIN

1.6 µA

MAX

–V

+ 0.8 V

S

–6.5 µA
–V

+ 1.2 V

S

0.2 µA
DISABLE

50% of
VIN = –1 V, G = –1

50% of
VIN = –1 V, G = –1

= 10 kΩ –VS + 0.04 +VS – 0.04 V

L

= 0.1 V p-p, f = 1 MHz,

V

IN

DISABLE

to <10% of Final VO,

DISABLE

to <10% of Final VO,

= Low

DISABLE

= Low

–55 dB

145 200 µA

165

ns

95

ns

Rev. A | Page 5 of 20

AD8029/AD8030/AD8040

ABSOLUTE MAXIMUM RATINGS

Table 4. AD8029/AD8030/AD8040 Stress Ratings

Parameter Rating

Supply Voltage 12.6 V
Power Dissipation See Figure 6
Common-Mode Input Voltage ±VS ± 0.5 V
Differential Input Voltage ±1.8 V
Storage Temperature –65°C to +125°C
Operating Temperature Range –40°C to +125°C
Lead Temperature Range

(Soldering 10 sec)

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8029/AD8030/
AD8040 package is limited by the associated rise in junction
temperature (T
locally reaches the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8029/AD8030/AD8040. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in silicon devices, potentially causing failure.

The still-air thermal properties of the package and PCB (θ
ambient temperature (T
package (P
junction temperature can be calculated as

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some in the load (V
The difference between the total drive power and the load
power is the drive power dissipated in the package.

) on the die. The plastic encapsulating the die

J

), and the total power dissipated in the

A

) determine the junction temperature of the die. The

D

= TA + (PD × θJA)

T

J

). Assuming the load (RL) is referenced to

S

300°C

),

JA

) is the sum of the

D

) times the

S

/2 × I

S

, some of which is

OUT

× I

OUT

OUT

).

= Quiescent Power + (Tot a l Dr i v e Pow e r – Load Power)

P

D

⎛

()

D

⎜

IVP

SS

⎜
⎝

V

×+×=

2

⎞

V

OUTS

⎟
⎟

R

L

⎠

RMS output voltages should be considered. If R

–, as in single-supply operation, then the total drive power is

V

S

× I

V

.

S

OUT

2

V

OUT

–

R

L

is referenced to

L

If the rms signal levels are indeterminate, consider the worst
case, when V

In single-supply operation with R

= VS/2.

is V

OUT

Airflow will increase heat dissipation, effectively reducing θ

= VS/4 for RL to midsupply:

OUT

()

D

()

+×=

IVP

SS

referenced to VS–, worst case

L

2

4/

V

S

R

L

.

JA

Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θ

. Care must be taken to minimize parasitic capaci-

JA

tances at the input leads of high speed op amps, as discussed in
the PCB Layout section.

Figure 6 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a
JEDEC standard 4-layer board. θ

2.5

2.0
SOIC-14

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0

–40 –20–10–30 0 10 20 30 40 50 60 70 80 90 100110120

TSSOP-14

SOIC-8

SOT-23-8

SC70-6

AMBIENT TEMPERATURE (°C)

Figure 6. Maximum Power Dissipation

values are approximations.

JA

03679-A-018

Output Short Circuit

Shorting the output to ground or drawing excessive current
from the AD8029/AD8030/AD8040 could cause catastrophic
failure.

Rev. A | Page 6 of 20

AD8029/AD8030/AD8040

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: VS = 5 V (TA = 25°C, RL = 1 kΩ tied to midsupply, unless otherwise noted.)

1

0
–1
–2
–3

R

–4
–5
–6
–7
–8
–9

–10
–11
–12

NORMALIZED CLOSED-LOOP GAIN (dB)

–13

V

–14

0.1 1 10 100 1000

G = +10

= 9kΩ, RG = 1kΩ

F

R

= RG = 1kΩ

F

= 0.1V p-p

O

G = +2

FREQUENCY (MHz)

G = –1
R

= RG = 1kΩ

F

G = +1
R

= 0Ω

F

03679-0-004

Figure 7. Small Signal Frequency Response for Various Gains

1

G = +1
V

= 0.1V p-p

O

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

1 10 100 1000

±5V

FREQUENCY (MHz)

+3V

+5V

03679-0-005

Figure 8. Small Signal Frequency Response for Various Supplies

1

G = +1
V

= 2V p-p

O

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

1 10 100

FREQUENCY (MHz)

±5V

+3V

+5V

03679-0-006

Figure 9. Large Signal Frequency Response for Various Supplies

0.2
DASHED LINES: V

SOLID LINES: V

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

NORMALIZED CLOSED-LOOP GAIN (dB)

–0.8

1 10 100

= 2V p-p

OUT

= 0.1V p-p

OUT

G = +2

FREQUENCY (MHz)

G = +1

RF = 1kΩ

03679-A-011

Figure 10. 0.1 dB Flatness Frequency Response

1

0

–1

–2

–3

–4

–5

–6

–7

NORMALIZED CLOSED-LOOP GAIN (dB)

–8

1 10 100

FREQUENCY (MHz)

±5V

+3V

G = +2
V

= 0.1V p-p

O

R

= 1kΩ

F

+5V

03679-A-012

Figure 11. Small Signal Frequency Response for Various Supplies

1

G = +2
V

= 2V p-p

O

0

–1

–2

–3

–4

–5

–6

–7

NORMALIZED CLOSED-LOOP GAIN (dB)

–8

1 10 100

FREQUENCY (MHz)

= +3

V

S

RF = 1kΩ

VS = ±5

VS = +5

03679-A-013

Figure 12. Large Signal Frequency Response for Various Supplies

Rev. A | Page 7 of 20

AD8029/AD8030/AD8040

6

G = +1

5

V

= 0.1V p-p

O

4
3
2
1

0
–1
–2
–3
–4

CLOSED-LOOP GAIN (dB)

–5
–6
–7
–8

1 10 100 1000

Figure 13. Small Signal Frequency Response for Various C

1

0

–1

–2

–3

–4

–5

–6

–7

NORMALIZED CLOSED-LOOP GAIN (dB)

–8

1 10 100

Figure 14. Frequency Response for Various Output Amplitudes

80

70

60

50

40

30

20

10

OPEN-LOOP GAIN (dB)

0

–10

–20

10 100 1k 10k 100k 1M 10M 100M 1G

Figure 15. Open-Loop Gain and Phase vs. Frequency

20pF

10pF

5pF

0pF

FREQUENCY (MHz)

2V p-p

1V p-p

0.1V p-p

FREQUENCY (MHz)

FREQUENCY (Hz)

03679-0-010

G = +2
R

= 1kΩ

F

03679-A-014

03679-0-054

LOAD

225

180

135

90

45

0

OPEN-LOOP PHASE (Degrees)

2

G = +1

= 0.1V p-p

V

O

1

0

–1

V

= VS– + 0.2V

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

1 10 100 1000

ICM

FREQUENCY (MHz)

= VS+– 0.2V

V

ICM

V

ICM

= 0V

03679-0-013

Figure 16. Small Signal Frequency Response for Various

Input Common-Mode Voltages

2

G = +1
V

= 0.1V p-p

O

1

0

–1

–2

–3

–4

CLOSED-LOOP GAIN (dB)

–5

–6

1 10 100

–40°C

FREQUENCY (MHz)

+125°C

+85°C
+25°C

03679-0-014

Figure 17. Small Signal Frequency Response vs. Temperature

1

G = +1
V

= 2V p-p

O

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

1 10 100

–40°C

FREQUENCY (MHz)

+125°C

+25°C

+85°C

03679-0-015

Figure 18. Large Signal Frequency Response vs. Temperature

Rev. A | Page 8 of 20

AD8029/AD8030/AD8040

–35

G = +1

= 2V p-p

V

OUT

= 1kΩ

R

–45

L

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

–55

–40

G = +1

= 2V p-p

V

OUT

SECOND HARMONIC: SOLID LINE

–50

THIRD HARMONIC: DASHED LINE

–60

HARMONIC DISTORTION (dBc)

–65

–75

–85

–95

–105

VS = +3V

VS = +5V

0.01 0.1 101
FREQUENCY (MHz)

VS = ±5V

03679-0-016

Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage

–40

G = +2
FREQ = 1MHz

= 1kΩ

R

–45

F

–50

VS = +3V

–55

–60

–65

–70

HARMONIC DISTORTION (dBc)

–75

–80

0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
OUTPUT AMPLITUDE (V p-p)

= +5V VS = +10V

V

S

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

03679-A-015

Figure 20. Harmonic Distortion vs. Output Amplitude

–30

VS = +5V
V

= 2.0V p-p

OUT

–40

R

= 1kΩ

L

R

= 1kΩ

F

–50

–60

–70

–80

–90

HARMONIC DISTORTION (dBc)

–100

–110

0.01 0.1 1 10

G = +2

G = –1

G = +1

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

FREQUENCY (MHz)

03679-A-016

Figure 21. Harmonic Distortion vs. Frequency and Gain

–70

–80

–90

HARMONIC DISTORTION (dBc)

–100

–110

0.01 0.1 1 10

RL = 1kΩ

FREQUENCY (MHz)

RL = 2kΩ

R

= 5kΩ

L

03679-0-075

Figure 22. Harmonic Distortion vs. Frequency and Load

–40

G = +1
V

= 2V p-p

OUT

FREQ = 1MHz

–50

= +3V

V

–60

–70

–80

HARMONIC DISTORTION (dBc)

–90

–100

1.0 1.5 2.0 2.5 3.0 3.5 4.0
INPUT COMMON-MODE VOLTAGE (V)

S

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

VS = +5V

03679-0-020

Figure 23. Harmonic Distortion vs. Input Common Mode Voltage

1000

100

VOLTAGE NOISE

10

VOLTAGE NOISE (nV/ Hz)

1

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

CURRENT NOISE

03679-0-069

100

10

1

CURRENT NOISE (pA/ Hz)

0.1

Figure 24. Voltage and Current Noise vs. Frequency

Rev. A | Page 9 of 20

AD8029/AD8030/AD8040

100

G = +1
V

= ±2.5V

S

75

50

100

G = +1

= ±2.5V

V

S

75

50

CL = 20pF
CL = 10pF

C

= 5pF

L

25

0

–25

OUTPUT VOLTAGE (mV)

–50

–75

–100

Figure 25. Small Signal Transient Response

2.5
G = +1

= ±2.5V

V

2.0

S

1.5

1.0

0.5

0

–0.5

–1.0

OUTPUT VOLTAGE (V)

–1.5

–2.0

0.5V/DIV 25ns/DIV

–2.5

Figure 26. Large Signal Transient Response

4

3

2

1

0

–1

OUTPUT VOLTAGE (V)

–2

–3

–4

TIME (ns)

4V p-p

2V p-p

TIME (ns)

INPUT

OUTPUT

TIME (ns)

G = –1 (RF = 1kΩ)
R

L

V

S

Figure 27. Output Overdrive Recovery

= 1kΩ
= ±2.5V

200ns/DIV1V/DIV

20ns/DIV25mV/DIV

03679-0-022

03679-0-024

25

0

–25

OUTPUT VOLTAGE (mV)

–50

–75

–100

TIME (ns)

20ns/DIV25mV/DIV

03679-0-025

Figure 28. Small Signal Transient Response with Capacitive Load

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0
G = +1

= +5V

V

0.5

S

R

= 1kΩ TIED TO MIDSUPPLY

L

0

03679-A-023

Figure 29. Rail-to-Rail Response, G = +1

INPUT

TIME (Seconds)

OUTPUT

1µs/DIV

03679-0-059

4

3

2

1

0

–1

OUTPUT VOLTAGE (V)

–2

–3

–4

OUTPUT

INPUT

TIME (ns)

G = +1
RL = 1kΩ

= ±2.5V

V

S

200ns/DIV1V/DIV

03679-0-027

Figure 30. Input Overdrive Recovery

Rev. A | Page 10 of 20

AD8029/AD8030/AD8040

+

–

V

G = +2

= ±2.5V

V

1V

S

(250mV/DIV)

IN

V

(500mV/DIV)

OUT

G = +2

V

– 2VIN (0.1%/DIV)

OUT

V

(500mV/DIV)

1V

OUT

500ns/DIV

Figure 31. Long-Term Settling Time

–20

–30

–40

–50

–60

CMRR (dB)

–70

–80

–90

–100

1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 32. Common-Mode Rejection Ratio vs. Frequency

–20

G = +1

= 1kΩ

R

L

DISABLE = LOW

–30

= 0.1V p-p

V

IN

–40

–50

OUTPUT (dB)

–60

–70

–80

0.1 1 10 100 1000
FREQUENCY (MHz)

Figure 33. AD8029 Off-Isolation vs. Frequency

03679-0-062

03679-0-078

03679-0-055

+0.1%

–0.1%

03679-0-063

+0.1%

–0.1%

V

– 2VIN (0.1%/DIV)

OUT

20ns/DIV

Figure 34.0.1% Short-Term Settling Time

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–PSRR

–80

–90

–100

1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

+PSRR

03679-0-033

Figure 35. PSRR v s. Frequency

–30

V

IN

–40

50Ω

–50

–60

–70

–80

CROSSTALK = 20log

–90

CROSSTALK (dB)

–100

–110

–120
–130

0.01

DRIVE AMP

1kΩ

LISTEN AMP

V

OUT

1kΩ

V

OUT

(

V

IN

FREQUENCY (MHz)

)

AD8040
(AMP 4 DRIVE
AMP 1 LISTEN)

AD8030
(AMP 2 DRIVE
AMP 1 LISTEN)

10000.1 1.0 10 100

03679-A-005

Figure 36. AD8030/AD8040 Crosstalk vs. Frequency

Rev. A | Page 11 of 20

AD8029/AD8030/AD8040

2.5

2.0

1.5

A)

1.0

µ

0.5

0

–0.5

–1.0

INPUT BIAS CURRENT (

–1.5

–2.0

–2.5

–10123456789101

VS = +3V

INPUT COMMON-MODE VOLTAGE (V)

Figure 37. Input Bias Current vs. Input Common-Mode Voltage

–1.0

–1.2

–1.4

–1.6

–1.8

INPUT BIAS CURRENT (PNP ACTIVE) (µA)

–2.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

VS = +3VS = +5VS = ±5

TEMPERATURE (°C)

Figure 38. Input Bias Current vs. Temperature

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

SUPPLY CURRENT (mA)

1.0

0.9

0.8
–40 –20 0 20 40 60 80 100 120

VS = ±5V

TEMPERATURE (°C)

Figure 39 Quiescent Supply Current vs. Temperature

V

NPN ACTIVE

PNP ACTIVE

= +5V

V

S

S

V

S

= +5V

= +3V

V

= +10V

S

03679-0-073

03679-0-074

03679-0-067

1.0

0.8

0.6

0.4

0.2

0

1

4

RL = 1kΩ TO
MIDSUPPLY

3

G = +1

2

1

0

–1

–2

INPUT OFFSET VOLTAGE (mV)

–3

–4

–10123456789101

VS = +3V VS = +5V VS = +10V

INPUT COMMON-MODE VOLTAGE (V)

03679-A-017

1

Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage

4

3

2

1

0

–1

–2

INPUT OFFSET VOLTAGE (mV)

INPUT BIAS CURRENT (NPN ACTIVE) (µA)

–3

–4

VS = ±5V

VS = +3V

TEMPERATURE (°C)

VS = +5V

125–40 –25 –10 5 20 35 50 65 80 95 110

03679-A-006

Figure 41. Input Offset Voltage vs. Temperature

120

COUNT = 1088
MEAN = 0.44mV
STDEV = 1.05mV

100

80

60

FREQUENCY

40

20

0

–5 –4 –3 –2 –1 0 1 2 3 4 5

INPUT OFFSET VOLTAGE (mV)

03679-0-064

Figure 42. Input Offset Voltage Distribution

Rev. A | Page 12 of 20

AD8029/AD8030/AD8040

1M

DISABLE = LOW

100k

10k

1000

)

Ω

G = +1

100

1k

100

OUTPUT IMPEDANCE (Ω)

10

1
100k 1M 10M 100M 1G

FREQUENCY (Hz)

03679-0-061

Figure 43. AD8029 Output Impedance vs. Frequency, Disabled

0.5

0.4

0.3

0.2

0.1
VS = +3V VS = +5V VS = ±5V

0

–0.1

–0.2

–0.3

OUTPUT SATURATION VOLTAGE (V)

–0.4

–0.5

100 1000 10000

LOAD RESISTANCE (Ω)

LOAD RESISTANCE TIED
TO MIDSUPPLY

VOL– V

S

VOH– V

S

03679-0-041

Figure 44. Output Saturation Voltage vs. Load Resistance

170

150

130

110

VS = ±5V

V

90

= +5V

S

10

OUTPUT IMPEDANCE (

1

0.1
1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

03679-0-060

Figure 45. Output Impedance vs. Frequency, Enabled

2.0

1.5

1.0

0.5

0

RL = 1k

–0.5

–1.0

INPUT ERROR VOLTAGE (mV)

–1.5

–2.0

–2.5 –2.0 –1.5 –1.0 –0.5 –0 0.5 1.0 1.5 2.0 2.5

OUTPUT VOLTAGE (V)

Ω

RL = 10k

VS =±2.5V

Ω

03679-0-072

Figure 46. Input Error Voltage vs. Output Voltage

70

50

V

= +3V

OUTPUT SATURATION VOLTAGE (mV)

30

S

–40 –25 –10 5 20 35 50 65 80 95 110 125

RL = 1kΩ TIED TO MIDSUPPLY
SOLID LINE: V
DASHED LINE: VOL – V

TEMPERATURE (°C)

S+

– VOH

Figure 42. Output Saturation Voltage vs. Temperature

S–

03679-0-066

Rev. A | Page 13 of 20

AD8029/AD8030/AD8040

OUTPUT AMPLITUDE (V)

–0.5

–1.0

–1.5

1.5

1.0

0.5

1.5

1.0

0.5

0

R
R
RL = 10kΩ

= 100Ω

L

= 1kΩ

L

0 50 100 150 200 250 300 350

Figure 47. AD8029

DISABLE (–0.5V TO –2V)

TIME (ns)

DISABLE

Turn-Off Timing

DISABLE (–2V TO –0.5V)

OUTPUT DISABLED

VS = ±2.5V
G = –1 (R

= 1kΩ)

F

03679-A-020

OUTPUT ENABLED

1

VS = +3V, +5V, +10V

0

–1

–2

–3

–4

–5

DISABLE PIN CURRENT (µA)

–6

–7

010.8 1.2 2 3

Figure 49. AD8029

DISABLE PIN VOLTAGE (V)

DISABLE

Pin Current vs.

DISABLE

03679-A-022

Pin Voltage

0

RL = 100Ω
R

= 1kΩ

L

R

= 10kΩ

L

TIME (ns)

DISABLE

VS = ±2.5V
G = –1 (R

Turn-On Timing

= 1kΩ)

F

03679-A-021

OUTPUT AMPLITUDE (V)

–0.5

–1.0

–1.5

0 50 100 150 200 250 300 350

Figure 48. AD8029

Rev. A | Page 14 of 20

AD8029/AD8030/AD8040

THEORY OF OPERATION

+V

Q

10

Q

11

03679-0-051

BOT

S

V

OUT

–V

S

and M

× IL.

C

TOP

, thus

R

TH

5

R

5R6R7R8

+VS–1.2V

I

TH

–V

S

Q

6

Q

Q

8

7

OUT IN

COM

DISABLE

AD8029 ONLY

IN–

IN+

TO DISABLE

CIRCUITRY

Q

Figure 50. Simplified Schematic

The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output amplifiers fabricated using Analog
Devices’ XFCB process. The XFCB process enables the AD8029/
AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a
120 MHz bandwidth and a 60 V/µs slew rate. A simplified sche­matic of the AD8029/AD8030/AD8040 is shown in Figure 50.

INPUT STAGE

For input common-mode voltages less than a set threshold
(1.2 V below V
(comprising Q
the input voltage to go 200 mV below –V
common-mode voltages exceeding the same threshold cause

to be routed away from the PNP differential pair and into

I

TAI L

the NPN differential pair through transistor Q
condition, the input common-mode voltage is allowed to rise
200 mV above +V
behavior. The transition between these two modes of operation
leads to a sudden, temporary shift in input stage transconduc­tance, g
V

, and dc parameters (such as the input offset voltage

m

), which in turn adversely affect the distortion performance.

OS

The SPD block shortens the duration of this transition, thus
improving the distortion performance. As shown in Figure 50,
the input differential pair is protected by a pair of two series
diodes, connected in anti-parallel, which clamp the differential
input voltage to approximately ±1.5 V.

), the resistor degenerated PNP differential pair

CC

toQ4) carries the entire I

1

while still maintaining linear amplifier

S

current, allowing

TAI L

. Conversely, input

S

. Under this

9

SPD

Q

9

R1R2R3R

Q

1

I

TAIL

OUTPUT

4

M

TOP

Q

2

Q

3

Q

4

M

BOT

BUFFER

C

MT

C

MB

OUTPUT STAGE

The currents derived from the PNP and NPN input differential
pairs are injected into the current mirrors M
establishing a common-mode signal voltage at the input of the
output buffer.

The output buffer performs three functions:

1. It buffers and applies the desired signal voltage to the

output devices, Q

2. It senses the common-mode current level in the output

devices.

3. It regulates the output common-mode current by

establishing a common-mode feedback loop.

The output devices Q
configuration, and are Miller-compensated by internal
capacitors, C

and CMB.

MT

The output voltage compliance is set by the output devices’
collector resistance R
current I

. For instance, a light equivalent load (5 kΩ) allows the

L

output voltage to swing to within 40 mV of either rail, while
heavier loads cause this figure to deteriorate as R

and Q11.

10

and Q11 work in a common-emitter

10

(about 25 Ω), and by the required load

C

Rev. A | Page 15 of 20

AD8029/AD8030/AD8040

APPLICATIONS

WIDEBAND OPERATION

R

F

C2

+V

S

10µF

C1

R

G

R1

V

IN

R1 = RF||R

G

Figure 51. Wideband Non-inverting Gain Configuration

R

G

V

IN

R1 = RF||R

G

R1

Figure 52. Wideband Inverting Gain Configuration

OUTPUT LOADING SENSITIVITY

To achieve maximum performance and low power dissipation,
the designer needs to consider the loading at the output of
AD8029/AD8030/AD8040. Table 5 shows the effects of output
loading and performance.

When operating at unity gain, the effective load at the amplifier
output is the resistance (R
gains other than 1, in noninverting configurations, the feedback
network represents an additional current load at the amplifier
output. The feedback network (R
which lowers the effective resistance at the output of the
amplifier. The lower effective resistance causes the amplifier to
supply more current at the output. Lower values of feedback
resistance increase the current draw, thus increasing the
amplifier’s power dissipation.

0.1µF

–

DISABLE

DISABLE

V

OUT

03679-0-052

V

03679-0-053

OUT

AD8029

+

C4

0.1µF

C3

10µF

–V

S

R

F

C2

+V

S

10µF

C1

0.1µF

–

AD8029

+

C4

0.1µF

C3

10µF

–V

S

) being driven by the amplifier. For

L

+ RG) is in parallel with RL,

F

For example, if using the values shown in Table 5 for a gain of 2,
with resistor values of 2.5 kΩ, the effective load at the output is

1.67 kΩ. For inverting configurations, only the feedback resistor
is in parallel with the output load. If the load is greater than

R

F

that specified in the data sheet, the amplifier can introduce
nonlinearities in its open-loop response, which increases
distortion. Figure 53 and Figure 54 illustrate effective output
loading and distortion performance. Increasing the resistance of
the feedback network can reduce the current consumption, but
has other implications.

–40

VS = 5V

VS = 5V
V

V

= 0.1V p-p

= 2.0V p-p

OUT

OUT

–50

SECOND HARMONIC – SOLID LINES
THIRD HARMONIC – DOTTED LINES

–60

HARMONIC DISTORTION (dBc)

–70

–80

–90

–100

–110

–120

0.01

RL = 1kΩ

RL = 5kΩ

RL = 2.5kΩ

0.1 1.0 10
FREQUENCY (MHz)

03679-A-008

Figure 53. Gain of 1 Distortion

–40

VS = 5V

VS = 5V
V

V

= 0.1V p-p

= 2.0V p-p

OUT

OUT

–50

SECOND HARMONIC – SOLID LINES
THIRD HARMONIC – DOTTED LINES

HARMONIC DISTORTION (dBc)

–60

–70

–80

–90

–100

–110

–120

0.01

RF = RL = 1kΩ

RF = RL = 5kΩ

RF = RL = 2.5kΩ

0.1 1.0 10
FREQUENCY (MHz)

03679-A-009

Figure 54. Gain of 2 Distortion

Rev. A | Page 16 of 20

AD8029/AD8030/AD8040

Table 5. Effect of Load on Performance

Noninverting
Gain

1 0 N/A 1 120 0.02 –80 –72 16.5
1 0 N/A 2 130 0.6 –84 –83 16.5
1 0 N/A 5 139 1 –87.5 –92.5 16.5
2 1 1 1 36 0 –72 –60 33.5
2 2.5 2.5 2.5 44.5 0.2 –79 –72.5 34.4
2 5 5 5 43 2 –84 –86 36
–1 1 1 1 40 0.01 –68 –57 33.6
–1 2.5 2.5 2.5 40 0.05 –74 –68 34
–1 5 5 5 34 1 –78 –80 36

RF
(kΩ)

RG
(kΩ)

R

LOAD

(kΩ)

–3 dB SS BW
(MHz)

Peaking
(dB)

HD2 at 1 MHz,
2 V p-p (dB)

HD3 at 1 MHz,
2 V p-p (dB)

Output Noise
(nV/√Hz)

The feedback resistance (R

|| RG) combines with the input

F

capacitance to form a pole in the amplifier’s loop response. This
can cause peaking and ringing in the amplifier’s response if the
RC time constant is too low. Figure 55 illustrates this effect.
Peaking can be reduced by adding a small capacitor (1 pF–4 pF)
across the feedback resistor. The best way to find the optimal
value of capacitor is to empirically try it in your circuit. Another
factor of higher resistance values is the impact it has on noise
performance. Higher resistor values generate more noise. Each
application is unique and therefore a balance must be reached
between distortion, peaking, and noise performance. Table 5
outlines the trade-offs that different loads have on distortion,
peaking, and noise performance. In gains of 1, 2, and 10,
equivalent loads of 1 kΩ, 2 kΩ, and 5 kΩ are shown.

With increasing load resistance, the distortion and –3 dB
bandwidth improve, while the noise and peaking degrade
slightly.

2

VS = 5V

= 0.1V p-p

V

OUT

1

0

–1

–2

–3

–4

–5

–6

–7

NORMALIZED CLOSED-LOOP GAIN (dB)

–8

Figure 55. Frequency Response for Various Feedback/Load Resistances

1

RF = RL = 2.5kΩ

RF = RL = 1kΩ

G = +2

10 100 1000

FREQUENCY (MHz)

RF = RL = 5kΩ

RL = 1kΩ

RL = 2.5kΩ

RL = 5kΩ

G = +1

03679-A-007

DISABLE PIN

The AD8029 disable pin allows the amplifier to be shut down
for power conservation or multiplexing applications. When in
the disable mode, the amplifier draws only 150 µA of quiescent
current. The disable pin control voltage is referenced to the
negative supply. The amplifier enters power-down mode any
time the disable pin is tied to the most negative supply or within

0.8 V of the negative supply. If left open, the amplifier will
operate normally. For switching levels, refer to Table 6.

Table 6. Disable Pin Control Voltage

Disable Pin
Voltage

+3 V +5 V

Low
(Disabled) 0 V to <0.8 V 0 V to <0.8 V –5 V to <–4 .2 V

High
(Enabled) 1.2 V to 3 V 1.2 V to 5 V –3.8 V to +5 V

Supply Voltage

±5 V

Rev. A | Page 17 of 20

AD8029/AD8030/AD8040

CIRCUIT CONSIDERATIONS

PCB Layout

High speed op amps require careful attention to PCB layout to
achieve optimum performance. Particular care must be
exercised to minimize lead lengths of the bypass capacitors.
Excess lead inductance can influence the frequency response
and even cause high frequency oscillations. Using a multilayer
board with an internal ground plane can help reduce ground
noise and enable a more compact layout.

To achieve the shortest possible trace length at the inverting
input, the feedback resistor, R
distance from the output pin to the input pin. The return node
of the resistor R
return node of the negative supply bypass capacitor.

On multilayer boards, all layers beneath the op amp should be
cleared of metal to avoid creating parasitic capacitive elements.
This is especially true at the summing junction, i.e., the inver­ting input, –IN. Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.

should be situated as close as possible to the

G

Grounding

To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and thus the high frequency impedance of
the path. Fast current changes in an inductive ground return
will create unwanted noise and ringing.

The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
from ground, the load should be placed at the same physical
location as the bypass capacitor ground. For large values of
capacitors, which are intended to be effective at lower
frequencies, the current return path length is less critical.

, should be located the shortest

F

Power Supply Bypassing

Power supply pins are actually inputs to the op amp. Care must
be taken to provide the op amp with a clean, low noise dc
voltage source.

Power supply bypassing is employed to provide a low imped­ance path to ground for noise and undesired signals at all
frequencies. This cannot be achieved with a single capacitor
type; but with a variety of capacitors in parallel the bandwidth
of power supply bypassing can be greatly extended. The bypass
capacitors have two functions:

1. Provide a low impedance path for noise and undesired

signals from the supply pins to ground.

2. Provide local stored charge for fast switching conditions

and minimize the voltage drop at the supply pins during
transients. This is typically achieved with large electrolytic
capacitors.

Good quality ceramic chip capacitors should be used and
always kept as close as possible to the amplifier package. A
parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic
covers a wide range of rejection for unwanted noise. The 10 µF
capacitor is less critical for high frequency bypassing and, in
most cases, one per supply line is sufficient. The values of
capacitors are circuit-dependant and should be determined by
the system’s requirements.

DESIGN TOOLS AND TECHNICAL SUPPORT

Analog Devices is committed to the design process by providing
technical support and online design tools. ADI offers technical
support via free evaluation boards, sample ICs, Spice models,
interactive evaluation tools, application notes, phone and email
support—all available at

www.analog.com.

Rev. A | Page 18 of 20

AD8029/AD8030/AD8040

Y

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8)

Dimensions shown in millimeters and (inches)

2.00 BSC

5 4

1.25 BSC

1.00

0.90

0.70

0.10MAX

6

1

2

PIN 1

1.30 BSC

0.30

0.15

0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB

Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6)

2.90 BSC

84 7

1.60 BSC

13

2

PIN 1

1.95

1.30

1.15

0.90

0.15 MAX

BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

Figure 58. 8-Lead Small Outline Transistor Package [SOT23] (RJ-8)

6.20 (0.2440)

5.80 (0.2284)

41

BSC

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

2.10 BSC

3

0.65 BSC

1.10 MAX

0.22

0.08

SEATING
PLANE

Dimensions shown in millimeters

5 6

2.80 BSC

0.65 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

Dimensions shown in millimeters

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

8°
4°
0°

8°
4°
0°

× 45°

0.46

0.36

0.26

0.60

0.45

0.30

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8.75 (0.3445)

8.55 (0.3366)

14

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

8

6.20 (0.2441)

7

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

8°
0°

0.50 (0.0197)

0.25 (0.0098)




1.27 (0.0500)

0.40 (0.0157)

× 45°



Figure 59. 14-Lead Standard Small Outline Package [SOIC] (R-14)

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

14

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

0.75

0.60

0.45

Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)

Dimensions shown in millimeters

Rev. A | Page 19 of 20

AD8029/AD8030/AD8040

ORDERING GUIDE

Model Minimum Ordering Quantity Temperature Range Package Description Package Option Branding

AD8029AR 1 –40°C to +125°C 8-Lead SOIC R-8
AD8029AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8029AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8029AKS-R2 250 –40°C to +125°C 6-Lead SC70 KS-6 H6B
AD8029AKS-REEL 10,000 –40°C to +125°C 6-Lead SC70 KS-6 H6B
AD8029AKS-REEL7 3,000 –40°C to +125°C 6-Lead SC70 KS-6 H6B
AD8030AR 1 –40°C to +125°C 8-Lead SOIC R-8
AD8030AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8030AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8030ARJ-R2 250 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B
AD8030ARJ-REEL 10,000 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B
AD8030ARJ-REEL7 3,000 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B
AD8040AR 1 –40°C to +125°C 14-Lead SOIC R-14
AD8040AR-REEL 2500 –40°C to +125°C 14-Lead SOIC R-14
AD8040AR-REEL7 1000 –40°C to +125°C 14-Lead SOIC R-14
AD8040ARU 1 –40°C to +125°C 14-Lead TSSOP RU-14
AD8040ARU-REEL 2500 –40°C to +125°C 14-Lead TSSOP RU-14
AD8040ARU-REEL7 1000 –40°C to +125°C 14-Lead TSSOP RU-14

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03679–0–11/03(A)

Rev. A | Page 20 of 20