ANALOG DEVICES AD 8027 ARZ Datasheet

Rail-to-Rail Input/Output Amplifiers

AD8027/AD8028

Rev. D Document Feedback

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Technical Support www.analog.com

DNC = DO NOT CO NNE C

T. DO NOT

CONNECT T

O THIS PIN.

DNC

1

–IN

2

+IN

3

–V

S

4

+V

S

V

OUT

DNC

8
7
6
5

DISABLE/SELECT

AD8027

03327-101

OUTPUT VOLTAGE (V p-p)

0 1 2 3 4 5 6 7 8 9 10

–140

–120

–100

–80

–60

–40

–20

SFDR (dB)

G = +1
FREQUENCY = 100kHz
RL = 1kΩ

VS = ±5V

VS = +3V

VS = +5V

03327-063

Data Sheet

FEATURES

High speed
190 MHz, −3 dB bandwidth (G = +1)
100 V/µs slew rate
Low distortion

120 dBc at 1 MHz SFDR

80 dBc at 5 MHz SFDR
Selectable input crossover threshold
Low noise

4.3 nV/√Hz

1.6 pA/√Hz
Low offset voltage: 900 µV maximum
Low power: 6.5 mA per amplifier supply current
Power-down mode
No phase reversal: V
Wide supply range: 2.7 V to 12 V
Small packaging: 8-lead SOIC, 6-lead SOT-23, 10-lead MSOP
Qualified for automotive applications (AD8028WARMZ-R7 only)

APPLICATIONS

Filters
ADC drivers
Level shifting
Buffering
Professional video
Low voltage instrumentation

GENERAL DESCRIPTION

The AD8027/AD80281 are high speed amplifiers with rail-to-rail
input and output that operate on low supply voltages and are
optimized for high performance and a wide dynamic signal range.
The AD8027/AD8028 have low noise (4.3 nV/√Hz, 1.6 pA/√Hz)
and low distortion (120 dBc at 1 MHz). In applications that use a
fraction of or use the entire input dynamic range and require
low distortion, the AD8027/AD8028 are ideal choices.

Many rail-to-rail input amplifiers have an input stage that switches
from one differential pair to another as the input signal crosses
a threshold voltage, which causes distortion. The AD8027/AD8028
have a unique feature that allows the user to select the input
crossover threshold voltage through the

DISABLE

(

DISABLE

to as

/SELECT x in the 10-lead MSOP, hereafter referred

/SELECT throughout this data sheet). This feature
controls the voltage at which the complementary transistor
input pairs switch. The AD8027/AD8028 also have intrinsically
low crossover distortion.

1

Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

> |VS| + 200 mV

IN

DISABLE

/SELECT pin

Low Distortion, High Speed

PIN CONNECTION DIAGRAM

Figure 1. 8-Lead SOIC, AD8027

See the Pin Configurations and Function Descriptions section
for additional pin configurations and information about the pin
functions.

With their wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifiers are
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high per­formance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA (typical) per amplifier. The AD8027/

AD8028 have a shutdown mode that is controlled via

DISABLE

the

/SELECT pin.

The AD8027/AD8028 are available in 8-lead SOIC, 6-lead SOT-23,
and 10-lead MSOP packages. The AD8028WARMZ-R7 is an
automotive grade version, qualified for automotive applications.
See the Automotive Products section for more details. The

AD8027/AD8028 family is designed to work over the extended

temperature range of −40°C to +125°C.

Figure 2. SFDR vs. Output Voltage

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2003–2015 Analog Devices, Inc. All rights reserved.

AD8027/AD8028 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Pin Connection Diagram ................................................................ 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 7

Maximum Power Dissipation ..................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Test Circ uit ...................................................................................... 19

Theory of Operation ...................................................................... 20

Input Stage ................................................................................... 20

Crossover Selection .................................................................... 20

Output Stage ................................................................................ 21

DC Errors .................................................................................... 21

Wideband Operation ..................................................................... 22

Circuit Considerations .............................................................. 22

Applications Information .............................................................. 24

Using the

Driving a 16-Bit ADC ................................................................ 24

Band-Pass Filter .......................................................................... 25

Design Tools and Technical Support ....................................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 27

Automotive Products ................................................................. 27

DISABLE

/SELECT Pin ............................................ 24

REVISION HISTORY

7/15—Rev. C to Rev. D

Changed SELECT to
+V

, and VS− to −VS ....................................................... Throughout

S

Changes to Features Section, Figure 1, and General Description

Section ................................................................................................ 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Changes to Table 3 ............................................................................ 5

Added Pin Configurations and Function Descriptions Section 8
Added Figure 4, Figure 5, Table 5, and Table 6; Renumbered

Sequentially ....................................................................................... 8

Added Figure 6, Figure 7, Table 7, and Table 8 ............................. 9

Changes to Figure 10 Caption and Figure 13 Caption .............. 10

Changes to Figure 16 Caption and Figure 19 Caption .............. 11

Changes to Figure 20 Caption and Figure 21 ............................. 12

Changes to Figure 26 Caption....................................................... 13

Changes to Figure 36 and Figure 37............................................. 14

Changes to Figure 42 ...................................................................... 15

Changes to Figure 50 Caption....................................................... 17

Added Test Circuit Section and Figure 59 .................................. 19

Changes to Theory of Operation Section .................................... 20

Changes to Crossover Selection Section and Figure 61 ............ 21

Changes to Wideband Operation Section, Figure 62, Figure 63,

and Figure 64 ................................................................................... 22

Changes to PCB Layout Section ................................................... 23

DISABLE

/SELECT, NC to DNC, VS+ to

Changes to Using the

Table 6 .............................................................................................. 24

Changes to Figure 67 and Design Tools and Technical Support

Section .............................................................................................. 25

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 27

Added Automotive Products Section .......................................... 27

3/05—Rev. B to Rev. C

Updated Format .................................................................. Universal

Change to Figure 1 ............................................................................ 1

10/03—Rev. A to Rev. B

Changes to Figure 1 ........................................................................... 1

8/03—Rev. 0 to Rev. A

Addition of AD8028 ........................................................... Universal

Changes to General Description ..................................................... 1

Changes to Figure 1, Figure 3, Figure 4, Figure 8, Figure 13,

Figure 15, Figure 17 .......................................................... 1, 6, 7, 8, 9

Changes to Figure 58, Figure 60 ............................................. 18, 20

Changes to Specifications ................................................................. 3

Updated Outline Dimensions ....................................................... 22

Updated Ordering Guide .............................................................. 23

3/03—Revision 0: Initial Version

DISABLE

/SELECT Pin Section and

Rev. D | Page 2 of 27

Data Sheet AD8027/AD8028

OUT

MIN

MAX

OUT

MIN

MAX

OUT

Slew Rate

G = +1, V

OUT

= 2 V step

90 V/µs

OUT

OUT

OUT

OUT

MIN

MAX

AD8028W only: T

MIN

to T

MAX

900

µV

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

OUT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

OUT

SPECIFICATIONS

VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, V

AD8028W only: T
G = +1, V
AD8028W only: T

Bandwidth for 0.1 dB Flatness G = +2, V

= 0.2 V p-p 138 190 MHz

to T

138 MHz

= 2 V p-p 20 32 MHz

to T

20 MHz

= 0.2 V p-p 16 MHz

G = −1, V

Settling Time to 0.1% G = +2, V

= 2 V step 100 V/µs

= 2 V step 35 ns

NOISE/DISTORTION PERFORMANCE

Spurious-Free Dynamic Range

fC = 1 MHz, V

= 2 V p-p, RF = 24.9 Ω 120 dBc

OUT

(SFDR)

fC = 5 MHz, V

= 2 V p-p, RF = 24.9 Ω 80 dBc
Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.1 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.2 Degrees
Crosstalk, Output to Output G = +1, RL = 100 Ω, V

= 2 V p-p, VS = ±5 V at 1 MHz −93 dB

DC PERFORMANCE

Input Offset Voltage

DISABLE

AD8028W only: T

DISABLE

Input Offset Voltage Drift T

/SELECT = tristate or open, PNP active 200 800 µV

to T

850 µV

/SELECT = high, NPN active 240 900 µV

to T

1.50 µV/°C
Input Bias Current1 VCM = 0 V, NPN active 4 6 µA
T
AD8028W only: T

to T

4 µA

to T

6 µA
VCM = 0 V, PNP active −8 −11 µA
T
AD8028W only: T
Input Offset Current AD8028W only: T
Open-Loop Gain V

to T

−8 µA
to T

−11 µA

to T

±0.1 ±0.9 µA

= ±2.5 V, AD8028W only: T

to T

100 110 dB

INPUT CHARACTERISTICS

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage

−5.2 to +5.2

V

Range
Common-Mode Rejection Ratio VCM = ±2.5 V 90 110 dB
AD8028W only: T

DISABLE

/SELECT PIN

to T

88 dB

Selection Input Voltage

Crossover Low T

Crossover High2 Tristate < ±20 µA, T
Disable Input Voltage T
Disable Switching Speed 50% of input to <10% of final V

to T

−3.0 V
to T

−3.9 to −3.7 V

to T

−4.6 V

980 ns

Enable Switching Speed 45 ns

Rev. D | Page 3 of 27

AD8027/AD8028 Data Sheet

MIN

MAX

POWER SUPPLY

MIN

MAX

MIN

MAX

Power Supply Rejection Ratio

VS ± 1 V, AD8028W only: T

MIN

to T

MAX

90

110 dB

OUT

MIN

MAX

OUT

MIN

MAX

OUT

Slew Rate

G = +1, V

OUT

= 2 V step

85 V/µs

OUT

OUT

OUT

OUT

S

MIN

MAX

AD8028W only: T

MIN

to T

MAX

900

µV

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

OUT

MIN

MAX

Parameter Test Conditions/Comments Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge)
Output Voltage Swing AD8028W only: T
Short-Circuit Output Sinking and sourcing 120 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz,

Capacitive Load Drive 30% overshoot 20 pF

Operating Range 2.7 12 V
Quiescent Current per Amplifier 6.5 8.5 mA
AD8028W only: T
Quiescent Current (Disabled)

AD8028W only: T

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

2

It is recommended to float the

DISABLE

V

= 5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.

S

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, V
AD8028W only: T

G = +1, V
AD8028W only: T

Bandwidth for 0.1 dB Flatness G = +2, V

VIN = +6 V to −6 V, G = −1 40/45 ns

to T

−4.9 to +4.9 −4.94 to +4.94 V

/SELECT = low −49 dB

9.5 mA

500 µA

to T

DISABLE

/SELECT = low 370 500 µA

to T

/SELECT pin for crossover high mode.

DISABLE

= 0.2 V p-p 131 185 MHz

to T

131 MHz

= 2 V p-p 18 28 MHz

to T

18 MHz

= 0.2 V p-p 12 MHz

G = −1, V
Settling Time to 0.1% G = +2, V

= 2 V step 100 V/µs

= 2 V step 40 ns

NOISE/DISTORTION PERFORMANCE

Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, V

fC = 5 MHz, V

= 2 V p-p, RF = 24.9 Ω 90 dBc

= 2 V p-p, RF = 24.9 Ω 64 dBc
Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.1 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.2 Degrees
Crosstalk, Output to Output G = +1, RL = 100 Ω, V

V

= ±5 V at 1 MHz

= 2 V p-p,

OUT

−92 dB

DC PERFORMANCE

Input Offset Voltage

DISABLE

AD8028W only: T

DISABLE

Input Offset Voltage Drift T

/SELECT = tristate or open, PNP active 200 800 µV

to T

850 µV

/SELECT = high NPN active 240 900 µV

to T

2 µV/°C
Input Bias Current1 VCM = 2.5 V, NPN active 4 6 µA
T
AD8028W only: T

to T

4 µA

to T

6 µA
VCM = 2.5 V, PNP active −8 −11 µA
T
AD8028W only: T
Input Offset Current AD8028W only: T
Open-Loop Gain V

to T

−8 µA
to T

−11 µA

to T

±0.1 ±0.9 µA

= 1 V to 4 V, AD8028W only: T

Rev. D | Page 4 of 27

to T

96 105 dB

Data Sheet AD8027/AD8028

Common-Mode Rejection Ratio

VCM = 0 V to 2.5 V

90

105 dB

MIN

MAX

Selection Input Voltage

MIN

MAX

MIN

MAX

MIN

MAX

OUT

MIN

MAX

MIN

MAX

Quiescent Current (Disabled)

/SELECT = low

320

450

µA

MIN

MAX

MIN

MAX

OUT

MIN

MAX

OUT

MIN

MAX

OUT

OUT

OUT

OUT

OUT

OUT

Input Current Noise

f = 100 kHz

1.6 pA/√Hz

Parameter Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range −0.2 to +5.2 V

AD8028W only: T

DISABLE

/SELECT PIN

Crossover Low T

to T

2.0 V

Crossover High2 Tristate < ±20 µA, T

Disable Input Voltage T

to T

0.4 V

Disable Switching Speed 50% of input to <10% of final V

to T

84 dB

to T

1.1 to 1.3 V

1100 ns

Enable Switching Speed 50 ns

OUTPUT CHARACTERISTICS

Overdrive Recovery Time

VIN = −6 V to +1 V, G = −1 50/50 ns

(Rising/Falling Edge)
Output Voltage Swing AD8028W only: T
Off Isolation VIN = 0.2 V p-p, f = 1 MHz,

to T

0.08 to 4.92 0.04 to 4.96 V

DISABLE

/SELECT = low −49 dB
Short-Circuit Current Sinking and sourcing 105 mA
Capacitive Load Drive 30% overshoot 20 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current per Amplifier 6 8.5 mA
AD8028W only: T

to T

9 mA

DISABLE
AD8028W only: T
Power Supply Rejection Ratio VS ± 1 V, AD8028W only: T

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

2

It is recommended to float the

DISABLE

/SELECT pin for crossover high mode.

to T

450 µA

to T

90 105 dB

V

= 3 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.

S

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, V
AD8028W only: T

G = +1, V
AD8028W only: T

Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate G = +1, V
G = −1, V
Settling Time to 0.1% G = +2, V

= 0.2 V p-p 125 180 MHz

to T

125 MHz

= 2 V p-p 19 29 MHz

to T

19 MHz
= 0.2 V p-p 10 MHz
= 2 V step 73 V/µs
= 2 V step 100 V/µs
= 2 V step 48 ns

NOISE/DISTORTION PERFORMANCE

Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, V

fC = 5 MHz, V

= 2 V p-p, RF = 24.9 Ω 85 dBc
= 2 V p-p, RF = 24.9 Ω 64 dBc

Input Voltage Noise f = 100 kHz 4.3 nV/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.15 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.20 Degrees
Crosstalk, Output to Output G = +1, RL = 100 Ω, V

= 2 V p-p, VS = 3 V at

OUT

−89 dB

1 MHz

Rev. D | Page 5 of 27

AD8027/AD8028 Data Sheet

MIN

MAX

AD8028W only: T

MIN

to T

MAX

900

µV

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

OUT

MIN

MAX

Common-Mode Rejection Ratio

VCM = 0 V to 1.5 V

88

100 dB

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

OUT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Parameter Test Conditions/Comments Min Typ Max Unit

DC PERFORMANCE

Input Offset Voltage

DISABLE

AD8028W only: T

DISABLE

/SELECT = tristate or open, PNP active 200 800 µV

to T

850 µV

/SELECT = high NPN active 240 900 µV

Input Offset Voltage Drift T

to T

2 µV/°C
Input Bias Current1 VCM = 1.5 V, NPN active 4 6 µA
T
AD8028W only: T

to T

4 µA

to T

6 µA
VCM = 1.5 V, PNP active −8 −11 µA
T
AD8028W only: T

Input Offset Current AD8028W only: T
Open-Loop Gain V

to T

−8 µA
to T

−11 µA

to T

±0.1 ±0.9 µA

= 1 V to 2 V, AD8028W only: T

to T

90 100 dB

INPUT CHARACTERISTICS

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range RL = 1 kΩ −0.2 to +3.2 V

AD8028W only: T

DISABLE

/SELECT PIN

to T

78 dB

Selection Input Voltage

Crossover Low T

Crossover High2 Tristate < ±20 µA, T
Disable Input Voltage T
Disable Switching Speed 50% of input to <10% of final V

to T

2.0 V
to T

1.1 to 1.3 V

to T

0.4 V

1150 ns

Enable Switching Speed 50 ns

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

VIN = −4 V to +1 V, G = −1 55/55 ns

(Rising/Falling Edge)

Output Voltage Swing AD8028W only: T

to T

0.07 to 4.93 0.03 to 4.97 V
Short-Circuit Current Sinking and sourcing 72 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz,

DISABLE

/SELECT = low −49 dB

Capacitive Load Drive 30% overshoot 20 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current per Amplifier 6.0 8.0 mA
AD8028W only: T
Quiescent Current (Disabled)

DISABLE

/SELECT = low 300 420 µA

AD8028W only: T
Power Supply Rejection Ratio VS ± 1 V, AD8028W only: T

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

2

It is recommended to float the

DISABLE

/SELECT pin for crossover high mode.

to T

9 mA

to T

420 µA

to T

88 100 dB

Rev. D | Page 6 of 27

Data Sheet AD8027/AD8028

Power Dissipation

See Figure 3

( )

L

OUT

L

OUTS

SS

D

R

V

R

V

V

IVP

2

–

2















×+×=

( )

( )

L

S

SS

D

R

V

IVP

2

4/

+×=

AMBIENT T E M P E RATURE (°C)

MAXIMUM POWER DISSIPATION (W)

–55 –35 –15 5 25 45 65 85 105 125

0

0.5

1.0

1.5

2.0

6-LEAD SOT-23

8-LEAD SOIC

10-LEAD MSOP

03327-002

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 12.6 V

Common-Mode Input Voltage ±VS ± 0.5 V
Differential Input Voltage ±1.8 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature Range (Soldering 10 sec) 300°C
Junction Temperature 150°C

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature
(T

) on the die. The plastic encapsulating the die locally reaches

J

the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8027/AD8028.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.

The still air thermal properties of the package and PCB (θ
ambient temperature (T
package (P

) determine the junction temperature of the die.

D

The junction temperature can be calculated as

T

= TA + (PD × θJA)

J

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V
dissipated in the package and some in the load (V
The difference between the total drive power and the load
power is the drive power dissipated in the package.

P

= Quiescent Power + (Total Drive Power − Load Power)

D

), and the total power dissipated in the

A

). Assuming the load (RL) is referenced to

S

) is the sum of the

D

) times the

S

/2 × I

S

, some of which is

OUT

OUT

× I

),

JA

).

OUT

Rev. D | Page 7 of 27

It is recommended that rms output voltages be considered. If R
is referenced to –V
drive power is V

, as in single-supply operation, the total

S

× I

.

S

OUT

If the rms signal levels are indeterminate, consider the worst
case, when V

= VS/4 for RL to midsupply.

OUT

In single-supply operation with R
is V

= VS/2.

OUT

Airflow increases heat dissipation, effectively reducing θ

referenced to –VS, worst case

L

. Also,

JA

more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θ

. Care must be taken to minimize parasitic capacitances

JA

at the input leads of high speed op amps, as described in the
PCB Layout section.

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 6-lead SOT-23 (170°C/W), and 10-lead MSOP
(130°C/W) packages on a JEDEC standard 4-layer board.

Output Short Circuit

Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 can cause catastrophic failure.

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

ESD CAUTION

L

AD8027/AD8028 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD8027

1

DNC

–IN

2

+IN

3

4

–V

S

DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.

Figure 4. 8-Lead SOIC, AD8027 Pin Configuration

Table 5. 8-Lead SOIC, AD8027 Pin Function Descriptions

Pin No. Mnemonic Description

1, 5 DNC Do Not Connect. Do not connect to these pins.
2 −IN Negative Input.

3 +IN Positive Input.
4 −VS Negative Supply.
6 V

Output Voltage.

OUT

7 +VS Positive Supply
8

DISABLE

/SELECT Power-Down/Select. The power-down function places the device into low power

consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.

8

DISABLE/SELECT

+V

7

S

V

6

OUT

DNC

5

03327-001

1

V

OUT

2

–V

S

+IN

3

AD8027

+–

6

+V

S

5

DISABLE/SELECT

4

–IN

Figure 5. 6-Lead SOT-23, AD8027 Pin Configuration

Table 6. 6-Lead SOT-23, AD8027 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Output Voltage.

OUT

2 −VS Negative Supply.
3 +IN Positive Input.
4 −IN Negative Input.
5

DISABLE

/SELECT Power-Down/Select. The power-down function places the device into low power

consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.

6 +VS Positive Supply.

03327-102

Rev. D | Page 8 of 27

Data Sheet AD8027/AD8028

1

V

OUTA

–IN A

+IN A

–

2

+

3

–V

4

S

AD8028

Figure 6. 8-Lead SOIC, AD8028 Pin Configuration

Table 7. 8-Lead SOIC, AD8028 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Output Voltage, Channel A.

OUTA

2 −IN A Negative Input, Channel A.
3 +IN A Positive Input, Channel A.
4 −VS Negative Supply.
5 +IN B Positive Input, Channel B.
6 −IN B Negative Input, Channel B.
7 V

Output Voltage, Channel B.

OUTB

8 +VS Positive Supply.

1

V

OUTA

–IN A

2

–

+IN A

DISABLE/SELECT A

Figure 7. 10-Lead MSOP, AD8028 Pin Configuration

+

3

4

–V

S

AD8028

5

8

+V

S

V

7

OUTB

–IN B

6

–

+

+IN B

5

10

+V

S

9

V

OUTB

–IN B

8

–

+

+IN B

7

6

DISABLE/SELECT B

03327-103

03327-104

Table 8. 10-Lead MSOP, AD8028 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Output Voltage, Channel A.

OUTA

2 −IN A Negative Input, Channel A.
3 +IN A Positive Input, Channel A.
4 −VS Negative Supply.
5

DISABLE

/SELECT A Power-Down/Select, Channel A. The power-down function places the device into low power

consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.

6

DISABLE

/SELECT B Power-Down/Select, Channel B. The power-down function places the device into low power

consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive

supply rail or the negative supply rail.
7 +IN B Positive Input, Channel B.
8 −IN B Negative Input, Channel B.
9 V

Output Voltage, Channel B.

OUTB

10 +VS Positive Supply.

Rev. D | Page 9 of 27

AD8027/AD8028 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Default conditions: VS = 5 V at TA = 25°C, RL = 1 kΩ, unless otherwise noted.

2

V

= 200mV p-p

OUT

1

0

–1

–2

–3

–4

–5

–6

–7

–8

NORMALI ZED CLO SED-L OOP GAIN (d B)

–9

–10

0.1 1 10 100 1000

G = +10

G = –1

FREQUENCY (MHz)

AD8027
G = +1

G = +2

AD8028

G = +1

Figure 8. Small Signal Frequency Response for Various Gains

2

G = +1

1

= 200mV p-p

V

OUT

0

–1

–2

–3

–4

–5

–6

–7

CLOSED- LOOP GAIN (dB)

–8

–9

–10

0.1 1 10 100 1000

FREQUENCY (MHz)

VS = +5V

VS = +3V

VS = 5V

Figure 9. AD8027 Small Signal Frequency Response for Various Supplies

2

G = +1

1

= 2V p-p

V

OUT

0

–1

–2

–3

–4

–5

–6

–7

CLOSED-LOOP GAIN (dB)

–8

–9

–10

0.1 1 10 1000

VS = +3V

FREQUENCY (MHz)

VS = 5V

VS = +5V

100

Figure 10. Large Signal Frequency Response for Various Supplies, G = +1

03327-003

03327-004

03327-005

8

G = +2

7

= 200mV p-p

V

OUT

6

5

4

3

2

1

0

–1

CLOSED-LOOP GAIN (dB)

–2

–3

–4

0.1 1 10 100 1000

VS = +3V

VS = +5V

VS = 5V

FREQUENCY (MHz)

Figure 11. Small Signal Frequency Response for Various Supplies

2

G = +1

1

= 200mV p-p

V

OUT

0

–1

–2

–3

–4

–5

–6

–7

CLOSED-LOOP GAIN (dB)

–8

–9

–10

0.1 1 10 100 1000

FREQUENCY (MHz)

V

S

= +5V

VS =±5V

V

= +3V

S

Figure 12. AD8028 Small Signal Frequency Response for Various Supplies

8

G = +2

7

= 2V p-p

V

OUT

6

5

4

3

2

1

0

–1

CLOSED-LOOP GAIN (dB)

–2

–3

–4

0.1 1 10 100 1000

VS = +5V

VS = +3V

FREQUENCY (MHz)

VS = 5V

Figure 13. Large Signal Frequency Response for Various Supplies, G = +2

03327-006

03327-007

03327-008

Rev. D | Page 10 of 27

Data Sheet AD8027/AD8028

4

G = +1

3

= 200mV p-p

V

OUT

2

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

0.1 1 10 100 1000

FREQUENCY (MHz)

C

L

CL = 20pF

CL = 5pF

= 0pF

Figure 14. AD8027 Small Signal Frequency Response for Various C

8

G = +2

7

6

5

4

3

2

1

0

–1

CLOSED-LOOP GAIN (dB)

–2

–3

–4

0.1 1 10 100 1000

V

= 2V p-p

OUT

V

OUT

FREQUENCY (MHz)

= 4V p-p

V

= 200mV p-p

OUT

Figure 15. Frequency Response for Various Output Amplitudes

2

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

G = +1

–7

= 200mV p-p

V

OUT

–8

0.1 1 10 100 1000

FREQUENCY (MHz)

–40°C

+125°C

+25°C

Figure 16. AD8027 Small Signal Frequency Response vs. Frequency for

Various Temperatures

LOAD

03327-009

Values

03327-010

03327-011

3

G = +1

2

V

= 200mV p-p

OUT

1

0

–1

–2

–3

–4

–5

–6

CLOSED-LOOP GAIN (dB)

–7

–8

–9

–10

0.1 1 10 100 1000

FREQUENCY (MHz)

CL = 20pF

CL = 0pF

C

= 5pF

L

Figu re 17. AD8028 Small Signal Frequency Response for Various C

8

G = +2

7

6

5

4

3

2

1

0

–1

CLOSED-LOOP GAIN (dB)

–2

–3

–4

0.1 1 10 100 1000

Figure 18. Small Signal Frequency Response for Various R

V

= 0.2V p-p

OUT

= 150



R

L

V

= 2.0V p- p

OUT

R

= 150



L

V

= 2.0V p-p

OUT

R

= 1k



L

FREQUENCY (MHz)

V

OUT

R

L

= 0.2V p-p

= 1k



LOAD

2

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

G = +1
V

= 200mV p-p

OUT

–8

0.1 1 10 100 1000

FREQUENCY (MHz)

–40°C

+125°C

+25°C

Figure 19. AD8028 Small Signal Frequency Response vs. Frequency for

Various Temperatures

Values

LOAD

Values

03327-012

03327-013

03327-014

Rev. D | Page 11 of 27

AD8027/AD8028 Data Sheet

–

T

–

4

3

2

DISABLE/SELECT = HIGH

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

–8

0.1 1 10 100 1000

DISABLE/ SELECT = HIGH O R TRI

G = +1

= 200mV p-p

V

OUT

V

= +VS– 0.3V

ICM

DISABLE/SELECT = HIGH

V

= +VS– 0.2V

ICM

V

= –VS+ 0.2V

ICM

DISABLE/SELECT = TRI

V

V

= –VS+ 0.3V

ICM

DISABLE/ SELECT = TRI

FREQUENC Y (MHz)

ICM

= 0V

03327-015

Figure 20. Small Signal Frequency Response vs. Frequency for Various Input

Common-Mode Voltages

10

–20

–30

–40

–50

–60

–70

–80

–90

CROSSTALK (d B)

–100

–110

–120

–130

–140

0.001 0.01 0.1 1 10 100 1000

BTOA

FREQUENC Y (MHz)

ATO B

03327-016

Figure 21. AD8028 Crosstalk, Output to Output (see Figure 59)

110

100

GAIN

90

80

70

60

50

40

30

OPEN-LOOP GAIN (dB)

20

10

0

–10

10 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

PHASE

135

115

95

75

55

35

PHASE (Degrees)

15

–5

–25

Figure 22. Open-Loop Gain and Phase vs. Frequency

100

10

AGE NOISE (nV/ Hz)

VOL

1

10 100 1k 10k 100k

VOLTAGE

CURRENT

1M 10M 100M 1G

FREQUENCY (Hz)

Figure 23. Voltage and Current Noise vs. Frequency

6.9
G = +2
R

= 150

6.8

6.7

6.6

6.5

6.4

6.3

6.2

CLOSED-LOOP GAIN (dB)

6.1

6.0

5.9

0.1 1 10 1000



L

V

= 200mV p-p

OUT

V

OUT

FREQUENCY (MHz)

100

Figure 24. 0.1 dB Flatness Frequency Response

20

G = +1
V

= 2V p-p

OUT

R

= 1k

L

–40

SECOND HARMO NIC: SOLID LI NE
THIRD HARMO NIC: DASHED LINE

–60

VS = +3V

–80

V

= +5V

–100

DISTORT ION (d B)

–120

–140

03327-017

S

V

= 5V

S

0.1 1 2010

FREQUENCY (MHz)

Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage

100

10

CURRENT NOI SE (pA/ Hz)

1

03327-018

= 2V p-p

03327-019

03327-020

Rev. D | Page 12 of 27

Data Sheet AD8027/AD8028

–

–

–

–

–

20

–45

–40

–60

V

= +3V

S

–80

–100

DISTORTION (dB)

–120

–140

012345678910

SECOND HARMONIC: SO LID L INE
THIRD HARMO NIC: DASHED L INE

OUTPUT VOLTAGE (V p-p)

V

= +5V

S

VS = 5V

Figure 26. Harmonic Distortion vs. Output Voltage

50

–60

–70

–80

–90

–100

–110

DISTORT ION (d B)

–120

–130

SECOND HARMO NIC: SO LID LI NE
THIRD HARMO NIC: DASHED LINE

–140

0.51.01.52.02.53.03.54.04.5

INPUT COMMON-MODE VOLTAGE (V)

VS = +3V

V

= +5V

S

Figure 27. Harmonic Distortion vs. Input Common-Mode Voltage,

DISABLE

/SELECT = High

20

G = +1 (RF = 24.9)

= 2.0V p-p

V

OUT

SECOND HARMO NIC: SO LID L INE

–40

THIRD HARMO NIC: DASHED L INE

RL = 1k



–55

–65

–75

–85

–95

DISTORTION (dB)

–105

–115

–125

03327-021

0.51.01.52.02.53.03.54.04.5

DISABLE/SELECT = HIGH

INPUT CO MMON-MO DE VOLTAGE (V)

Figure 29. Harmonic Distortion vs. Input Common-Mode Voltage, V

DISABLE/SELECT = TRI

SECOND HARMO NIC: SO LID LI NE
THIRD HARMO NIC: DASHED L INE

= 5 V

S

03327-024

50

G = +1 (RF = 24.9)

= 1.0V p-p AT 100kHz

V

OUT

–60

–70

–80

–90

–100

–110

DISTORTION (dB)

–120

–130

–140

03327-022

0.5 1. 0 1. 5 2.0 2.5 3.0 3.5 4.0 4.5

INPUT COMMON-MODE VOLTAGE (V)

VS = +3V

V

= +5V

S

SECOND HARMO NIC: SOLID LINE
THIRD HARMO NIC: DASHE D LINE

03327-025

Figure 30. Harmonic Distortion vs. Input Common-Mode Voltage,

DISABLE

/SELECT = Trisate or Open

20

VS = +5
V

= 2.0V p-p

OUT

SECOND HARMONIC: SO LID L INE

–40

THIRD HARMO NIC: DASHED L INE

G = +2

–60

–80

RL = 150



–100

DISTORT ION (d B)

–120

–140

0.1 1 10 20

FREQUENCY (MHz)

Figure 28. Harmonic Distortion vs. Frequency and Load

03327-023

–60

–80

–100

DISTORTION (dB)

–120

–140

0.1 1 10 20

G = +10

FREQUENCY (MHz)

Figure 31. Harmonic Distortion vs. Frequency and Gain

G = +1

03327-026

Rev. D | Page 13 of 27

AD8027/AD8028 Data Sheet

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

0.20

0.15

0.10

G = +1

= ± 2.5V

V

S

0.20

0.15

0.10

G = +1

= ±2.5V

V

S

C

L

= 20pF

C

= 5pF

L

0.05

0

–0.05

–0.10

–0.15

–0.20

Figure 32. Small Signal Transient Response

1.0

2.0

2.0

1.0

0

G = +1

= ±2.5V

V

S

V

V

OUT

OUT

= 4V p-p

= 2V p-p

Figure 33. Large Signal Transient Response, G = +1

2.5

2.0

1.5

1.0

0.5

0.5

1.0

1.5

2.0

2.5

0

G = +2

= ±2.5V

V

S

V

V

OUT

OUT

= 4V p-p

= 2V p-p

Figure 34. Large Signal Transient Response, G = +2

0.05

0

–0.05

–0.10

20ns/DIV50mV/DIV

03327-027

–0.15

–0.20

20ns/DIV50mV/DIV

03327-030

Figure 35. Small Signal Transient Response with Capacitive Load

4.0
G = –1

3.5
R

= 1k

L

3.0

V

= ±2.5V

S

2.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

100ns/DIV500mV/DIV

03327-028

3.5

4.0

INVERTED

INPUT

50ns/DIV500mV/DIV

03327-031

Figure 36. Overdrive Recovery, G = −1

4.0
G = +1

3.5

= 1k

R

L

3.0

= ±2.5V

V

S

2.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

20ns/DIV50mV/DIV

03327-029

3.5

4.0

INPUT

Figure 37. Overdrive Recovery, G = +1

50ns/DIV500mV/DIV

03327-032

Rev. D | Page 14 of 27

Data Sheet AD8027/AD8028

–

–

(

10

–8

G = +2

V

VIN (200mV/DIV)

– 2VIN (2mV/DIV)

OUT

Figure 38. Long-Term Settling Time

VIN (200mV/DIV)

5s/DIV

+0.1%

–0.1%

–6

–4

–2

0

2

4

INPUT BI AS CURRENT (A)

10

03327-033

VS= +3V

6

DISABLE/ SELECT = HIG H

8

012345678910

INPUT COMMON-MODE VOLTAGE (V)

Figure 41. Input Bias Current vs. Input Common-Mode Voltage

250

200

DISABLE/SELECT = TRI

V

= +5V

S

= 5V

V

S

DISABLE/ SELECT = TRI

03327-036

(400mV/DIV)

V

OUT

V

– 2VIN (0.1%/DIV)

OUT

20ns/DIV

Figure 39. 0.1% Short-Term Settling Time

4.5

4.0

3.5

3.0

2.5

INPUT BIAS CURRENT [DISABLE/SELECT = HIGH] (µA)

DISABLE/SELECT = HIGH

V

=±5V

V

S

–40 –25 –10 5 20 35 50 65 80 11095 125

= +3V

S

DISABLE/ SELECT = TRI

TEMPERATURE (°C)

V

= +5V

S

Figure 40. Input Bias Current vs. Temperature

+0.1%

–0.1%

–7.0

–7.5

–8.0

–8.5

6.5

150

100

FREQUENCY

50

0

–800 –600 –400 –200 0 200 400 600 800

03327-034

INPUT OFFSET VOLTAGE (µV)

DISABLE/ SELECT = HIGH

03327-037

Figure 42. Input Offset Voltage Distribution

360

340

320

300

V)

280



DISABLE/SELECT = TRI

260

V

=5V

240

220

200

180

160

140

120

INPUT OFFSET VOLTAGE

100

INPUT BI AS CURRENT [DISABLE/SELECT = T RI] (µ A)

03327-035

S

DISABLE/SELECT = HIGH

= +5V

V

S

80

60

–40 –25 –10 5 20 35 50 65 80 11095 125

TEMPERATURE (°C)

V

= +3V

S

03327-038

Figure 43. Input Offset Voltage vs. Temperature

Rev. D | Page 15 of 27

AD8027/AD8028 Data Sheet

–

290

270

V)



250

230

210

190

INPUT OFFSET VOLT AGE (

170

DISABLE/SELECT = HIGH

DISABLE/SELECT = TRI

VS=5V

120

100

80

60

CMRR (dB)

40

20

150

–5–4–3–2–1012345

INPUT COMMON-MODE VOLTAGE (V)

03327-039

Figure 44. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5 V

290

VS= +5V

270

V)



250

230

210

190

INPUT OFFSET VOLTAGE (

170

150

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 45. Input Offset Voltage vs. Input Common-Mode Voltage, V

270

VS= +3V

250

230

DISABLE/ SELECT = HIG H

DISABLE/SELECT = TRI

INPUT COMMON-MODE VOLTAGE (V)

DISABLE/ SELECT = HIGH

= 5 V

S

03327-040

0

1k 10k 100k 1 M 10M 100M

FREQUENCY (Hz)

Figure 47. Common-Mode Rejection Ratio (CMRR) vs. Frequency

0

–10

–20

–30

–40

–50

–60

PSSR (dB)

–70

–80

–90

–100

–110

100 1k 10k 100k 1M 10M 100M 1G

–PSRR

+PSRR

FREQUENCY (Hz)

Figure 48. Power Supply Rejection Ratio (PSRR) vs. Frequency

20

VIN = 0.2V p-p
G = +1

–30

DISABLE/SELECT = LOW

–40

–50

03327-042

03327-043

210

190

INPUT OFFSET VOLTAGE (V)

170

150

0 0.50 1.00 1.50 2.00 2.50 3.00

INPUT COMMON-MODE VOLTAGE (V)

DISABLE/SELECT = TRI

Figure 46. Input Offset Voltage vs. Input Common-Mode Voltage, V

= 3 V

S

03327-041

–60

–70

OFF ISOLATION (dB)

–80

–90

–100

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 49. Off Isolation vs. Frequency

03327-044

Rev. D | Page 16 of 27

Data Sheet AD8027/AD8028

200

150

100

50

VS = +3V VS = +5V VS =5V

0

–50

–100

–150

OUTPUT SATURATION VOLTAGE (mV)

–200

100 1000 10000

LOAD RESISTANCE ()

LOAD RESISTANCE TIED
TO MI DSUPPLY

VOL – V

S–

VOH– V

S+

Figure 50. Output Saturation Voltage vs. Load Resistance

100

03327-045

130

120

110

100

90

80

OPEN-LOOP GAIN (dB)

70

60

0 102030405060

+3V

I

LOAD



5V

+5V

(mA)

Figure 53. Open-Loop Gain vs. Load Current

1M

DISABLE/SELECT = LOW

03327-048

10

1

0.1

OUTPUT IMPEDANCE ()

0.01

0.001

G = +2

1k 10k 100k 1M 10M 100M 1G

G = +5

G = +1

FREQUENCY (Hz)

Figure 51. Output Enabled—Impedance vs. Frequency

45

VS = +5V
R

= 1k TI ED TO MIDSUPPLY

L

40

V

– –V

OL

35

30

OUTPUT SATURATION VOLTAGE (mV)

25

–40 –25 –10 5 20 35 50 65 80 11095 125

S

+VS – V

TEMPERATURE (°C)

Figure 52. Output Saturation Voltage vs. Temperature

100k

)



10k

1k

OUTPUT IMPEDANCE (

100

10

03327-046

100k 1M 10M 100M 1G

FREQUENCY (Hz)

03327-049

Figure 54. Output Disabled—Impedance vs. Frequency

80

VS = +5V

60

A)



40

20

0

OH

03327-047

–20

–40

DISABLE/SELECT CURRENT (

–60

–80

0 0.5 1.0 1.5 2. 0 2.5 3.0

Figure 55.

DISABLE

+125°C

= +10V

V

S

AT +25°C

+25°C

–40°C

DISABLE/SELECT VOLTAGE (V)

DISABLE

/SELECT Current vs.

/SELECT Voltage and Temperature

03327-050

Rev. D | Page 17 of 27

AD8027/AD8028 Data Sheet

1.5

1.0

0.5

0

–0.5

OU T PU T VO LTAG E (V )

–1.0

–1.5

0 50 100 150 200 250

TIME (ns)

DISABLE/ SELECT PIN

(–2.0V TO –0.5V)

OUTPUT

G = –1
V
V

= 2.5V

S

= –1.0V

IN

Figure 56. Enable Turn On Timing

1.5

DISABLE/SELECT PIN (–2.0V TO –0.5V)

1.0
OUTPUT

0.5

03327-051

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

SUPPLY CURRENT (mA)

5.0

4.5

4.0
–40 –25 –10 5 20 35 50 65 80 11095 125

=5V

V

S

VS = +3V

TEMPERATURE ( °C)

V

= +5V

S

Figure 58. Quiescent Supply Current vs. Temperature and Supply Voltage

03327-053

0

–0.5

OUTPUT VOLTAGE (V)

–1.0

G = –1
V

=2.5V

S

V

= –1.0V

IN

–1.5

0.512345678910

3327-052

Figure 57. Disable Turn-Off Timing

Rev. D | Page 18 of 27

Data Sheet AD8027/AD8028

CROSSTAL K = 20log (V

OUT/VIN

)

1/2

AD8028

+

U1

R3
1kΩ

R2
50Ω

R1

50Ω

V1

VI

–

1/2

AD8028

+

U2

V

OUT

–

03327-116

TEST CIRCUIT

Figure 59. Crosstalk Test Circuit (see Figure 21)

Rev. D | Page 19 of 27

AD8027/AD8028 Data Sheet

V

THEORY OF OPERATION

The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices, Inc., extra fast complementary
bipolar (XFCB) process. The XFCB process enables the

AD8027/AD8028 to run on 2.7 V to 12 V supplies with 190 MHz

of bandwidth and a 100 V/μs slew rate. The AD8027/AD8028
have 4.3 nV/√Hz of wideband noise with 17 nV/√Hz noise at
10 Hz. This noise performance, with an offset of less than
900 μV maximum and drift performance of 1.50 μV/°C typical,
makes the AD8027/AD8028 ideal for high speed, precision
applications. Additionally, the input stage operates 200 mV
beyond the supply rails and shows no phase reversal. The
amplifiers feature overvoltage protection on the input stage.
When the inputs exceed the supply rails by 0.7 V, ESD protection
diodes turn on, drawing excessive current through the differen­tial input pins. Include a series input resistor to limit the input
current to less than 10 mA.

INPUT STAGE

The rail-to-rail input performance is achieved by operating
complementary input pairs. The common-mode level of the
differential input signal determines which pair is on. As shown
in Figure 60, a tail current (I
PNP differential input structure consisting of Q1 and Q2. A
reference voltage is generated internally that is connected to the
base of Q5. This voltage is continually compared against the
common-mode input voltage. When the common-mode level
exceeds the internal reference voltage, Q5 diverts the tail
current (I

) from the PNP input pair to a current mirror that

TAI L

sources the NPN input pair consisting of Q3 and Q4.

) is generated that sources the

TAI L

VCC

+

1.2V

–

The NPN input pair can then operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 60). In the event of differential input signals that exceed

1.4 V, the diodes conduct and excessive current flows through
them. Include a series input resistor to limit the input current to
10 mA.

CROSSOVER SELECTION

The AD8027/AD8028 have a crossover selection feature that
allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, avoid operating in this region because it can introduce
offset and distortion to the output signal. To help avoid operat­ing in the crossover region, the AD8027/AD8028 allow the user
to select from two preset crossover locations (voltage levels)
using the
200 mV and is defined by the voltage level at the base of Q5 in
Figure 60. Internally, two separate voltage sources are created
approximately 1.2 V from either rail. One rail or the other is
connected to Q5, based on the voltage applied to the
SELECT pin. This allows either dominant PNP pair operation,
when the
pair operation, when the

The
down function when it is pulled low. This pin allows the designer
to achieve the best precision and ac performance for high-side
and low-side signal applications. See Figure 54 through Figure 57
for

I

TAIL

DISABLE

DISABLE

DISABLE

DISABLE

/SELECT pin. The crossover region is about

/SELECT pin is left open, or dominant NPN

DISABLE

/SELECT pin is pulled high.

/SELECT pin also provides the traditional power-

/SELECT pin characteristics.

DISABLE

/

I

Q5 Q3 Q1

SEL

LOGIC

VEE

+

–

VP

1.2V

Figure 60. Simplified Input Stage

Q2 Q4

VN

CMFB

I

CMFB

VEE

VCC

VOUTP

VOUTN

03327-054

Rev. D | Page 20 of 27

Data Sheet AD8027/AD8028















+

=

G

F

G

PNPOS

OUTPNPOS

R

RR

VV

,

,,















+

=

G

F

G

NPNOS

OUTNPNOS

R

R

R

VV

,

,,

( )















+

×−=

G

F

G

NPNOS,PNPOS,DIS

R

RR

VVV

( )















−















+

×−=−

F

G

F

G

S

NPNB,PNPB,

NPNOS,PNPOS,

R

R

RR

RIIVV

FB

G

F

G

S

B

OS

RI

R

RR

RIV

−+

−















+

=F

V

OUT

IB+

R

F

R

G

IB–

V

OS

R

S

+ –

+ –

V

IN

+–

–V

S

+V

S

–

+

AD8027/

AD8028

03327-055

DISABLE/SELECT

In the event that the crossover region cannot be avoided, spe­cific attention is given to the input stage to ensure constant
transconductance and minimal offset in all regions of operation.
The regions are PNP input pair running, NPN input pair
running, and both running at the same time (in the 200 mV
crossover region). Maintaining constant transconductance in
all regions ensures the best wideband distortion performance
when going between these regions. With this technique, the

AD8027/AD8028 can typically achieve 85 dBc SFDR for a

2 V p-p, 1 MHz, and G = +1 signal on ±1.5 V supplies. Another
requirement needed to achieve this level of distortion is that the
offset of each pair must be laser trimmed, even for low frequency
signals.

OUTPUT STAGE

The AD8027/AD8028 use a common emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 53 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = +1, as shown in Figure 14. Include a
small (25 Ω to 50 Ω) series resistor, R

, if the capacitive load

SNUB

is to exceed 20 pF for a gain of 1. Increasing the closed-loop
gain increases the amount of capacitive load that can be driven
before a series resistor must be included.

DC ERRORS

The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as described in the Input
Stage section. To use the dc performance over the entire common­mode range, the input bias current and input offset voltage of
each pair must be considered.

Referring to Figure 61, the output offset voltage of each pair is
calculated by

The size of the discontinuity is defined as

Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (V

OS, PNP

− V

) is trimmed to

OS, NPN

minimize this effect.
Because the input pairs are complementary, the input bias cur-

rent reverses polarity when going through the crossover region
shown in Figure 41. The offset between pairs is described by

where:

I

is the input bias current of either input when the PNP

B, PNP

input pair is active.

I

is the input bias current of either input pair when the

B, NPN

NPN pair is active.
If R

is sized so that it equals RF when multiplied by the gain

S

factor, this effect is eliminated. It is strongly recommended to
balance the impedances in this manner when traveling through
the crossover region to minimize the dc error and distortion. As
an example, assuming that the PNP input pair has an input bias
current of 6 µA and the NPN input pair has an input bias
current of −2 µA, a 200 µV shift in offset occurs when traveling
through the crossover region with R

equal to 0 Ω and RS equal

F

to 25 Ω.
In addition to the input bias current shift between pairs, each

input pair has an input bias current offset that contributes to the
total offset in the following manner:

where the difference of the two input stages is the discontinuity
experienced when going through the crossover region.

Figure 61. Op Amp DC Error Sources

Rev. D | Page 21 of 27

AD8027/AD8028 Data Sheet

–

WIDEBAND OPERATION

Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the feedback network
of the application requires consideration of the following issues:

 Poles formed by the amplifier input capacitances with the

resistances seen at the amplifier input terminals

 Effects of mismatched source impedances
 Resistor value impact on the voltage noise of the

application

 Amplifier loading effects

The AD8027/AD8028 have an input capacitance of 2 pF. This
input capacitance forms a pole with the amplifier feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low also takes advantage of the

AD8027/AD8028 low input voltage noise of 4.3 nV/√Hz.

With a wide bandwidth of 190 MHz, the AD8027/AD8028 have
numerous applications and configurations. The AD8027/AD8028
device shown in Figure 62 is configured as a noninverting ampli­fier. Table 9 provides an easy selection table of gain, resistor
values, bandwidth, and noise performance, and Figure 63 shows
the inverting configuration.

R

F

C1

+V

S

0.1F

R

G

–

AD8027/

AD8028

R1

V

IN

+

C2

10F

C3

10F

V

OUT

DISABLE/SELECT

C

F

R

F

C1

+V

S

0.1F

C2

V

IN

R1 = RF||R

C5

R

G

G

–

AD8027/

AD8028

+

R1

10F

V

OUT

DISABLE/SELECT

C3

10F

C4

0.1F

–V

S

03327-057

Figure 63. Wideband Inverting Gain Configuration

CIRCUIT CONSIDERATIONS

Balanced Input Impedances

Balanced input impedances can help to improve distortion
performance. When the amplifier transitions from PNP pair
to NPN pair operation, a change in both the magnitude and
direction of the input bias current occurs. When multiplied by
imbalanced input impedances, a change in offset can result. The
key to minimizing this distortion is to keep the input impedances
balanced on both inputs. Figure 64 shows the effect of the
imbalance and degradation in SFDR performance for a 50 Ω
source impedance, with and without a 50 Ω balanced feedback
path.

20

G = +1
V

= 2V p-p

OUT

–30

R

= 1k

L

V

= +3V

S

–40

C4

R1 = RF||R

G

0.1F

–V

S

03327-056

Figure 62. Wideband Noninverting Gain Configuration

–50

–60

= 0

R

F

SFDR (dB )

–70

–80

–90

–100

0.1 1 10 20

RF = 24.9

R

= 49.9

F

FREQUENCY (MHz)

Figure 64. SFDR vs. Frequency and Various R

03327-058

F

Table 9. Component Values, Bandwidth, and Noise Performance (VS = ±2.5 V)

Noise Gain
(Noninverting) R

(Ω) RF (Ω) RG (Ω) −3 dB Small Signal BW (MHz) Output Noise with Resistors (nV/√Hz)

SOURCE

1 50 0 Not applicable 190 4.4
2 50 499 499 95 10
10 50 499 54.9 13 45

Rev. D | Page 22 of 27

Data Sheet AD8027/AD8028

PCB Layout

As with all high speed op amps, achieving optimum perform­ance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high fre­quency oscillations. The use of a multilayer board with an
internal ground plane can reduce ground noise and enable a
tighter layout.

To achieve the shortest possible lead length at the inverting
input, position the feedback resistor, R

, beneath the board so

F

that it spans the distance from the output, to the inverting
input. Situate the return node of the resistor, R

, as closely as

G

possible to the return node of the negative supply bypass
capacitor.

On multilayer boards, clear all layers underneath the op amp of
metal to avoid creating parasitic capacitive elements. This is
especially true at the summing junction (the negative input).
Extra capacitance at the summing junction can cause increased
peaking in the frequency response and lower phase margin.

Grounding

To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and, therefore, the high frequency imped­ance of the path. Fast current changes in an inductive ground
return can create unwanted noise and ringing.

The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass capacitor.
Because load currents flow from supplies as well as ground,
place the load at the same physical location as the bypass capacitor
ground. For large values of capacitors, which are intended to be
effective at lower frequencies, the current return path length is
less critical.

Power Supply Bypassing

Power supply pins are actually inputs, and care must be taken to
provide a clean, low noise, dc voltage source to these inputs.
The bypass capacitors have two functions.

• Provide a low impedance path for unwanted frequencies

from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.

• Provide sufficient localized charge storage, for fast

switching conditions and minimizing the voltage drop at
the supply pins and the output of the amplifier. This is
usually accomplished with larger electrolytic capacitors.

Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.

Use high quality ceramic chip capacitors and always keep them
as close as possible to the amplifier package. A parallel combina­tion of a 0.01 µF ceramic and a 10 µF electrolytic covers a wide
range of rejection for unwanted noise. The 10 µF capacitor is
less critical for high frequency bypassing, and, in most cases,
one per supply line is sufficient.

Rev. D | Page 23 of 27

AD8027/AD8028 Data Sheet

OFF

+5V

+5V

+

–

AD8028

ANALOG I NP UT +

INPUT RANGE

(0.15V TO 2.65V)

+

–

ANALOG I NP UT –

AD7677

+5V

16 BITS

15Ω

15Ω

2.7nF
4MHz LPF

4MHz LPF

2.7nF

0.1µF

0.1µF

AD8028

03327-059

DISABLE/SELECT

(OPEN)

DISABLE/SELECT

(OPEN)

APPLICATIONS INFORMATION

USING THE

DISABLE

The AD8027/AD8028 unique

/SELECT PIN

DISABLE

/SELECT pin has two

functions:

• The power-down function places the AD8027/AD8028

into low power consumption mode. In power-down mode,
the amplifiers draw 500 µA maximum of supply current.

• The second function, as described in the Crossover

Selection section, shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to
the other) closer to either the positive supply rail or the
negative supply rail. This selectable crossover point allows
the user to minimize distortion based on the input signal
and environment. The default state is −1.2 V from the
positive power supply, with the

DISABLE

/SELECT pin left
floating or in tristate mode. In tristate mode, it is important
that current to the pin is limited to ±20 μA maximum.

Table 10 lists the voltage levels and modes of operation for

DISABLE

the

Table 10.

Mode

/SELECT pin over the full temperature range.

DISABLE

/SELECT Pin Mode Control

DISABLE

/SELECT Pin Voltage (V)

Disable −VS to –VS + 0.4
Crossover Referenced −1.2 V

−VS + 1.1 to –VS +1.3

to Positive Supply

Crossover Referenced +1.2 V

−VS + 2.0 to +VS

to Negative Supply

When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.

The disable time of the AD8027/AD8028 amplifiers is load
dependent. Table 11 lists typical enable/disable times. See
Figure 56 and Figure 57 for the actual switching measurements.

Table 11.

DISABLE

/SELECT Switching Speeds

Supply Voltages (RL = 1 kΩ)

Time

±5 V +5 V +3 V

tON 45 ns 50 ns 50 ns
t

980 ns 1100 ns 1150 ns

DRIVING A 16-BIT ADC

With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs such as the AD7677, a
16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 65 shows
the typical schematic for driving the ADC. The AD8028 driving
the AD7677 offers performance close to nonrail-to-rail amplifiers
and avoids the need for an additional supply other than the
single 5 V supply already used by the ADC.

In this application, the
avoid the crossover region of the AD8028 for low distortion
operation.

Table 12 lists summary test data for the schematic shown in
Figure 65.

Table 12. ADC Driver Performance, f
V

= 4.7 V p-p

OUT

Parameter Measurement

Second Harmonic Distortion −105 dB
Third Harmonic Distortion −102 dB
Total Harmonic Distortion −102 dB
SFDR 105 dBc

DISABLE

/SELECT pins are biased to

= 100 kHz,

C

Figure 65. Unity-Gain Differential Drive

Rev. D | Page 24 of 27

Data Sheet AD8027/AD8028

G

As shown in Figure 66, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL).

1.0

The test data shown in Figure 68 indicates that this design
yields a filter response with a center frequency of f

= 1 MHz,

O

and a bandwidth of 450 kHz.

CH1 S21 LO

5dB/REF 6.342dB 1:6.3348dB 1.00 000MHz

0.5

0

INL (LSB)

–0.5

–1.0

0 16384 32768 49152 65536

CODE

03327-060

Figure 66. Integral Nonlinearity

BAND-PASS FILTER

In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 are excellent choices
for active filter applications. In realizing this filter, it is impor­tant that the amplifier have a large signal bandwidth of at least
10× the center frequency, f
in the amplifier, causing instability and oscillations.

In Figure 67, the AD8027/AD8028 device is configured as a
1 MHz band-pass filter. The target specifications are f
and a −3 dB pass band of 500 kHz. To start the design, select f
Q, C1, and R4. Then use the following equations to calculate the
remaining variables:

(MHz)

f

O



Q

PassBand

. Otherwise, a phase shift can occur

O

(MHz)

= 1 MHz

O

O

1

0.1

1

FREQUENCY – MHz

10

03327-062

Figure 68. Band-Pass Filter Response

DESIGN TOOLS AND TECHNICAL SUPPORT

Analog Devices is committed to simplifying the design process
by providing technical support and online design tools. Analog
Devices offers technical support via evaluation boards, sample
ICs, interactive evaluation tools, data sheets, SPICE models,
application notes, and phone and email support available at

www.analog.com.

,

k = 2πfOC1
C2 = 0.5C1
R1 = 2/k, R2 = 2/(3k), R3 = 4/k
H = 1/3(6.5 − 1/Q)
R5 = R4/(H − 1)

R2

105Ω

R1

316Ω

V

IN

C1

1000pF

C2

500pF

Figure 67. Band-Pass Filter Schematic

R3

634Ω

523Ω

R5

+5V

+

AD8027/

AD8028

–

–5V

R4

523Ω

C3

0.1µF

DISABLE/

SELECT

C4

0.1µF

V

OUT

03327-061

Rev. D | Page 25 of 27

AD8027/AD8028 Data Sheet

C

ON

T

RO

LL

I

NG

DI

M

EN

SI

O

NS

A

RE

IN

M

IL

LI

M

ET

ER

S

; I

N

CH

D

I

M

E

N

S

I

O

N

S

(

IN

PA

R

EN

T

H

E

S

E

S

)

A

R

E

R

O

U

N

DE

D

-O

FF

M

IL

LI

M

ET

E

R E

QU

I

VA

LE

N

TS

FO

R

R

E

FE

R

EN

CE

O

NL

Y A

N

D A

RE

N

OT

AP

P

RO

P

RI

AT

E

FO

R U

S

E I

N D

E

SI

G

N.

C

O

M

PL

IA

N

T T

O

JE

DE

C

ST

AN

D

AR

DS

M

S-

0

12

-A

A

012

40

7

-A

0

.2

5

(0

.0

0

98

)

0.

1

7 (

0

.0

06

7

)

1

.

2

7

(

0

.

0

5

0

0

)

0

.

4

0

(

0

.

0

1

5

7

)

0.

50

(

0.

01

9

6)

0

.2

5 (

0

.0

0

99

)

45

°

8

°

0

°

1

.7

5

(0

.0

6

88

)

1

.3

5

(0

.0

5

32

)

S

EA

T

IN

G

P

LA

NE

0.

2

5 (

0

.0

09

8

)

0

.

10

(0

.

00

40

)

4

1

8

5

5

.

0

0

(

0

.

1

9

6

8

)

4

.

8

0

(

0

.

1

8

9

0

)

4.

0

0 (

0.

1

57

4)

3.

8

0 (

0.

1

49

7

)

1

.

2

7

(

0.

05

0

0)

B

SC

6

.2

0 (

0

.2

44

1

)

5.

80

(

0.

2

28

4)

0

.

5

1

(

0

.

0

2

0

1

)

0

.

3

1

(

0

.

0

1

2

2

)

CO

P

LA

N

AR

IT

Y

0.

1

0

COMPLIANT TO JEDEC STANDARDS MO-178-AB

10°

4°
0°

SEATING
PLANE

1.90
BSC

0.95 BSC

0.60

BSC

6 5

1 2 3

4

3.00

2.90

2.80

3.00

2.80

2.60

1.70

1.60

1.50

1.30

1.15

0.90

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.20 MAX

0.08 MIN

0.50 MAX

0.30 MIN

0.55

0.45

0.35

PIN 1

INDICATOR

12-16-2008-A

OUTLINE DIMENSIONS

Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Figure 70. 6-Lead Small Outline Transistor Package [SOT-23]

Dimensions shown in millimeters

(RJ-6)

Rev. D | Page 26 of 27

Data Sheet AD8027/AD8028

AD8027ARTZ-REEL7

−40°C to +125°C

6-Lead SOT-23

RJ-6

3000

H4B#

COMPLIANT TO JEDEC STANDARDS MO-187-BA

091709-A

6°
0°

0.70

0.55

0.40

5

10

1

6

0.50 BSC

0.30

0.15

1.10 MAX

3.10

3.00

2.90

COPLANARITY

0.10

0.23

0.13

3.10

3.00

2.90

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and

ORDERING GUIDE

1, 2

Model

Temperature Range Package Description Package Option Ordering Quantity Branding3

AD8027ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1
AD8027ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 2500
AD8027ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1000
AD8027ARTZ-R2 −40°C to +125°C 6-Lead SOT-23 RJ-6 250 H4B#

AD8028ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1
AD8028ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 2500
AD8028ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1000
AD8028ARMZ −40°C to +125°C 10-Lead MSOP RM-10 1 H5B#
AD8028ARMZ-REEL7 −40°C to +125°C 10-Lead MSOP RM-10 1000 H5B#
AD8028WARMZ-R7 −40°C to +125°C 10-Lead MSOP RM-10 1000 Y5R#
AD8027ART-EBZ Evaluation Board
AD8028AR-EBZ Evaluation Board

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

3

# denotes lead-free, may be top or bottom marked.

AUTOMOTIVE PRODUCTS

The AD8028W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.

registered trademarks are the property of their respective owners.
D03327-0-7/15(D)

Figure 71. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Rev. D | Page 27 of 27