ANALOG DEVICES AD 8022 ARZ Datasheet

Dual High Speed,

O

Data Sheet

FEATURES

Low power amplifiers provide low noise and low distortion,

ideal for xDSL modem receiver
Wide supply range: +5 V, ±2.5 V to ±12 V voltage supply
Low power consumption: 4.0 mA/Amp
Voltage feedback

Ease of Use

Lower total noise (insignificant input current noise

contribution compared to current feedback amps)

Low noise and distortion

2.5 nV/√Hz voltage noise @ 100 kHz

1.2 pA/√Hz current noise

MTPR < −66 dBc (G = +7)

SFDR 110 dB @ 200 kHz
High speed

130 MHz bandwidth (−3 dB), G = +1

Settling time to 0.1%, 68 ns

50 V/μs slew rate
High output swing: ±10.1 V on ±12 V supply
Low offset voltage, 1.5 mV typical

APPLICATIONS

Receiver for ADSL, VDSL, HDSL, and proprietary

xDSL systems
Low noise instrumentation front end
Ultrasound preamps
Active filters
16-bit ADC buffers

GENERAL DESCRIPTIONS

Low Noise Op Amp

FUNCTIONAL BLOCK DIAGRAM

UT1

–IN1

+IN1

–V

100

AD8022

1

2

–
+

3

4

S

–
+

Figure 1.

8

7

6

5

AD8022

+V

S

OUT2

–IN2

+IN2

01053-001

The AD8022 consists of two low noise, high speed, voltage
feedback amplifiers. Each amplifier consumes only 4.0 mA of
quiescent current, yet has only 2.5 nV/√Hz of voltage noise.
These dual amplifiers provide wideband, low distortion
performance, with high output current optimized for stability
when driving capacitive loads. Manufactured on ADI’s high

10

voltage generation of XFCB bipolar process, the AD8022
operates on a wide range of supply voltages. The AD8022 is
available in both an 8-lead MSOP and an 8-lead SOIC. Fast over

(pA/ Hz, nV/ Hz)

eN (nV/ Hz)

voltage recovery and wide bandwidth make the AD8022 ideal as
the receive channel front end to an ADSL, VDSL, or proprietary
xDSL transceiver design.

In an xDSL line interface circuit, the AD8022’s op amps can be
configured as the differential receiver from the line transformer

1

10 10M1M100k10k1k100

Figure 2. Current and Voltage Noise vs. Frequency

FREQUENCY (Hz)

iN (pA/ Hz)

01053-002

or as independent active filters.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD8022* Product Page Quick Links

Comparable Parts

View a parametric search of comparable parts

Evaluation Kits

• AD8022 Evaluation Board

• ADSP-SC584 Evaluation Hardware for the ADSP-SC58x/
ADSP-2158x SHARC Family (349-ball CSPBGA)

• ADSP-SC589 Evaluation Hardware for the ADSP-SC58x/
ADSP-2158x SHARC Family (529-ball CSPBGA)

• Universal Evaluation Board for Dual High Speed
Operational Amplifiers

Documentation

Application Notes

• AN-356: User's Guide to Applying and Measuring
Operational Amplifier Specifications

• AN-402: Replacing Output Clamping Op Amps with Input
Clamping Amps

• AN-417: Fast Rail-to-Rail Operational Amplifiers Ease
Design Constraints in Low Voltage High Speed Systems

• AN-581: Biasing and Decoupling Op Amps in Single
Supply Applications

• AN-649: Using the Analog Devices Active Filter Design
Tool

• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design

Data Sheet

• AD8022: Dual High Speed Low Noise Op Amp Data Sheet

User Guides

• UG-128: Universal Evaluation Board for Dual High Speed
Op Amps in SOIC Packages

• UG-129: Universal Evaluation Board for Dual High Speed
Op Amps in MSOP Packages

• UG-886: Universal Evaluation Board for Dual High Speed
Op Amps Offered in 8-Lead MSOP

Tools and Simulations

• Analog Filter Wizard

• Analog Photodiode Wizard

• Op Amp Stability with Capacitive Load

• Power Dissipation vs Die Temp

• VRMS/dBm/dBu/dBV calculators

• AD8022 SPICE Macro-Model

Last Content Update: 08/30/2016

Reference Designs

• CN0039

• CN0048

Reference Materials

Product Selection Guide

• High Speed Amplifiers Selection Table

• SAR ADC & Driver Quick-Match Guide

Technical Articles

• Maximize Performance When Driving Differential ADCs

Tutorials

• MT-032: Ideal Voltage Feedback (VFB) Op Amp

• MT-033: Voltage Feedback Op Amp Gain and Bandwidth

• MT-048: Op Amp Noise Relationships: 1/f Noise, RMS
Noise, and Equivalent Noise Bandwidth

• MT-049: Op Amp Total Output Noise Calculations for
Single-Pole System

• MT-050: Op Amp Total Output Noise Calculations for
Second-Order System

• MT-052: Op Amp Noise Figure: Don't Be Misled

• MT-053: Op Amp Distortion: HD, THD, THD + N, IMD,
SFDR, MTPR

• MT-056: High Speed Voltage Feedback Op Amps

• MT-058: Effects of Feedback Capacitance on VFB and
CFB Op Amps

• MT-059: Compensating for the Effects of Input Capacitance
on VFB and CFB Op Amps Used in Current-to-Voltage
Converters

• MT-060: Choosing Between Voltage Feedback and Current
Feedback Op Amps

Design Resources

• AD8022 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Discussions

View all AD8022 EngineerZone Discussions

Sample and Buy

Visit the product page to see pricing options

Technical Support

Submit a technical question or find your regional support
number

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

AD8022 Data Sheet

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Maximum Power Dissipation .....................................................5

ESD Caution.................................................................................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 12

Applications..................................................................................... 13

REVISION HISTORY

8/11—Rev. B to Rev. C

Changes to Figure 40 ......................................................................14

Updated Outline Dimensions........................................................16

Changes to Ordering Guide...........................................................16

5/05—Rev. A to Rev. B

Changes to Format.............................................................Universal

Deleted Evaluation Boards Section.............................................. 14

Deleted Generating DMT Section................................................ 14

Changes to Ordering Guide.......................................................... 16

Updated Outline Dimensions....................................................... 16

9/02—Rev. 0 to Rev. A

Changes to Features ..........................................................................1

Changes to Applications...................................................................1

Changes to Product Description.....................................................1

Changes to Functional Block Diagram ..........................................1

Changes to Figure 1...........................................................................1

Changes to Specifications Table......................................................2

Edits to TPCs 1, 2, 3, 6 ......................................................................5

New TPCs 7, 8....................................................................................6

Edits to TPCs 16, 17, 18....................................................................7

Edits to TPC 19..................................................................................8

Edits to TPC 28..................................................................................9

Edits to Figure 3...............................................................................11

Edits to Figure 6...............................................................................14

Updated Outline Dimensions........................................................16

DMT Modulation and Multitone Power Ratio (MTPR)....... 13

Channel Capacity and SNR....................................................... 13

Power Supply and Decoupling.................................................. 13

Layout Considerations............................................................... 15

Outline Dimensions .......................................................................16

Ordering Guide .......................................................................... 16

Rev. C | Page 2 of 16

Data Sheet AD8022

SPECIFICATIONS

At 25°C, VS = ±12 V, RL = 500 Ω, G = +1, T

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth1 V
Slew Rate V
Rise and Fall Time V
Settling Time 0.1% V
Overdrive Recovery Time

NOISE/DISTORTION PERFORMANCE

Distortion V

Second Harmonic fC = 1 MHz −95 dBc

Third Harmonic fC = 1 MHz −100 dBc
Multitone Input Power Ratio2 G = +7 differential
26 kHz to 132 kHz −67.2 dBc
144 kHz to 1.1 MHz −66 dBc
Voltage Noise (RTI) f = 100 kHz 2.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz

DC PERFORMANCE

Input Offset Voltage −1.5 ±6 mV
T
Input Offset Current ±120 nA
Input Bias Current 2.5 5.0 μA
T
Open-Loop Gain 72 dB

INPUT CHARACTERISTICS

Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range −11.25 to +11.75 V
Common-Mode Rejection Ratio VCM = ±3 V 98 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 500 Ω ±10.1 V
R
Linear Output Current G = +1, RL = 150 Ω, dc error = 1% ±55 mA
Short-Circuit Output Current 100 mA
Capacitive Load Drive RS = 0 Ω, <3 dB of peaking 75 pF

POWER SUPPLY

Operating Range +4.5 ±13.0 V
Quiescent Current 4.0 5.5 mA/Amp
T
Power Supply Rejection Ratio VS = ±5V to ±12 V 80 dB

OPERATING TEMPERATURE RANGE −40 +85 °C

1

FPBW = Slew Rate/(2π V

2

Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.

PEAK

).

= –40°C, T

MIN

OUT

OUT

OUT

OUT

OUT

OUT

V

OUT

= 50 mV p-p 110 130 MHz
= 50 mV p-p 25 MHz
= 4 V p-p 4 MHz
= 2 V p-p, G = +2 40 50 V/μs
= 2 V p-p, G = +2 30 ns
= 2 V p-p 62 ns
= 150% of max output

= +85°C, unless otherwise noted.

MAX

200 ns

voltage, G = +2

= 2 V p-p

OUT

to T

MIN

MIN

= 2 kΩ ±10.6 V

L

MIN

±7.25 mV

MAX

to T

±7.5 μA

MAX

to T

6.1 mA/Amp

MAX

Rev. C | Page 3 of 16

AD8022 Data Sheet

At 25°C, VS = ±2.5 V, RL = 500 Ω, G = +1, T

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth1 V
Slew Rate V
Rise and Fall Time V
Settling Time 0.1% V
Overdrive Recovery Time

NOISE/DISTORTION PERFORMANCE

Distortion V

Second Harmonic fC = 1 MHz −77.5 dBc

Third Harmonic fC = 1 MHz −94 dBc
Multitone Input Power Ratio2 G = +7 differential, VS = ±6 V
26 kHz to 132 kHz −69 dBc
144 kHz to 1.1 MHz −66.7 dBc
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 1 pA/√Hz

DC PERFORMANCE

Input Offset Voltage −0.8 ±5.0 mV
T
Input Offset Current ±65 nA
Input Bias Current 2.0 5.0 μA
T
Open-Loop Gain 64 dB

INPUT CHARACTERISTICS

Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range −1.83 to +2.0 V
Common-Mode Rejection Ratio VCM = ±2.5 V, VS = ±5.0 V 98 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 500 Ω −1.38 to +1.48 V
Linear Output Current G = +1, RL = 100 Ω, dc error = 1% ±32 mA
Short-Circuit Output Current 80 mA
Capacitive Load Drive RS = 0 Ω, <3 dB of peaking 75 pF

POWER SUPPLY

Operating Range +4.5 ±13.0 V
Quiescent Current 3.5 4.25 mA/Amp
T
Power Supply Rejection Ratio ∆VS = ±1 V 86 dB

OPERATING TEMPERATURE RANGE −40 +85 °C

1

FPBW = Slew Rate/(2 π V

2

Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.

PEAK

).

= –40°C, T

MIN

= 50 mV p-p 100 120 MHz

OUT

= 50 mV p-p 22 MHz

OUT

= 3 V p-p 4 MHz

OUT

= 2 V p-p, G = +2 30 42 V/μs

OUT

= 2 V p-p, G = +2 40 ns

OUT

= 2 V p-p 75 ns

OUT

= 150% of max output

V

OUT

= +85°C, unless otherwise noted.

MAX

225 ns

voltage, G = +2

= 2 V p-p

OUT

to T

MIN

MIN

MIN

±6.25 mV

MAX

to T

7.5 μA

MAX

to T

4.4 mA/Amp

MAX

Rev. C | Page 4 of 16

Data Sheet AD8022

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage (+VS to −VS) 26.4 V

Internal Power Dissipation1

8-Lead SOIC (R) 1.6 W

8-Lead MSOP (RM) 1.2 W
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±0.8 V
Output Short-Circuit Duration Observe Power Derating Curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range

−40°C to +85°C

(A Grade)
Lead Temperature Range

300°C

(Soldering 10 sec)

1

Specification is for the device in free air:

8-Lead SOIC: θJA = 160°C/W.
8-Lead MSOP: θJA = 200°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8022 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.

While the AD8022 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves.

2.0

1.5

8-LEAD SOIC PACKAGE

1.0

8-LEAD MSOP

0.5

MAXIMUM POWER DISSIPATION (W)

0

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

Figure 3. Maximum Power Dissipation vs. Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

TJ = 150°C

01053-003

Rev. C | Page 5 of 16

AD8022 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

5

4

3

V

2

1

0

(dB)

–1

–2

–3

–4

–5

0.1 1 10 100 500

Figure 4. Frequency Response vs. R

0.4
G = +2
R

0.3

0.2

0.1

0

–0.1

(dB)

–0.2

–0.3

–0.4

–0.5

–0.6

100k 1M 10M 100M

IN

50Ω

= 500Ω

L

R

F

V

OUT

50Ω

FREQUENCY (MHz)

FREQUENCY (Hz)

RF = 715Ω

50Ω

RF = 402Ω

RF = 0Ω

, G = +1, VS = ±12 V, VIN = 63 mV p-p

F



±12V

±5.0V



±2.5V

Figure 5. Fine-Scale Gain Flatness vs. Frequency, G = +2

0.4
G = +2
R

= 500Ω

0.3

L

0.2

0.1

0

–0.1

(dB)

–0.2

–0.3

–0.4

–0.5

–0.6

100k 1M 10M 100M

FREQUENCY (Hz)

±12V

±5.0V

±2.5V

Figure 6. Fine-Scale Gain Flatness vs. Frequency, G = +1

01053-004

01053-005

01053-006

5

4

3

2

1

0

(dB)

–1

–2

–3

–4

–5

0.1 1 10 100 500

Figure 7. Frequency Response vs. Signal Level, V

5

4

3

2

1

0

–1

–2

FREQUENCY RESPONCE (dB)

–3

–4

–5

0.1 1 10 100 500

Figure 8. Frequency Response vs. Capacitive Load; C

140

120

100

80

60

FREQUENCY (MHz)

40

20

0

0 2 4 6 8 10 12 14

Figure 9. Bandwidth vs. Supply, R

V

V

IN

50Ω

IN

50Ω

715Ω

402Ω

VIN = 2.0V p-p

VIN = 0.8V p-p

VIN = 0.4V p-p

715Ω

V

OUT

453Ω

56.2Ω

FREQUENCY (MHz)

R

S

C

L

FREQUENCY (kHz)

G = +1, RF = 402Ω

G = +2, RF = 715Ω

SUPPLY VOLTAGE (±V)

VIN = 0.2V p-p

V

OUT

453Ω

56.2Ω

30pF

0pF

= 500 Ω, VIN = 200 mV p-p

L

= ±12 V, G = +1

S

= 0 pF and 50 pF; RS = 0 Ω

L

VIN = 0.05V p-p

50pF

01053-007

01053-008

01053-009

Rev. C | Page 6 of 16

Data Sheet AD8022

80

70

60

50

40

30

GAIN (dB)

20

10

0

–10

5k 10k 100k 10M1M 100M 500M

FREQUENCY (Hz)

Figure 10. Open-Loop Gain vs. Frequency

01053-010

100mV

100

90

10

0%

100mV

Figure 13. Noninverting Small Signal Pulse Response,

= 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω

R

L

100ns

INPUT

OUTPUT

01053-013

180

0

FREQUENCY (Degrees)

–180

5k 10k 100k 10M1M 100M 500M

FREQUENCY (Hz)

Figure 11. Open-Loop Phase vs. Frequency

100mV

100

90

100ns

INPUT

01053-011

2.00V

100

90

10

0%

100ns

INPUT

OUTPUT

2.00V

01053-014

Figure 14. Noninverting Large Signal Pulse Response,

R

= 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω

L

1.00V

100

90

100ns

INPUT

10

0%

OUTPUT

100mV

01053-012

Figure 12. Noninverting Small Signal Pulse Response,

= 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω

R

L

10

0%

OUTPUT

1.00V

01053-015

Figure 15. Noninverting Large Signal Pulse Response,

= 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω

R

L

Rev. C | Page 7 of 16

AD8022 Data Sheet

0.4

–50

0.3

0.2

= ±12 V,

S

= 500 Ω

L

+0.1%

–0.1%

0.1

0

–0.1

SETTLING ERROR (%)

–0.2

–0.3

–0.4

0 20 40 60 80 100 120

TIME (ns)

Figure 16. Settling Time to 0.1%, V

Step Size = 2 V p-p, G = +2, R

0.4

0.3

0.2

0.1

0

+0.1%

01053-016

–60

–70

–80

–90

–100

–110

HARMONIC DISTORTION (dB)

–120

–130

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 19. Distortion vs. Frequency, V

= 0 Ω, V

R

F

OUT

–50

–60

–70

–80

–90

3RD

2ND

= ±12 V, RL = 500 Ω,

S

= 2 V p-p, G = +1

2ND

3RD

01053-019

–0.1

SETTLING ERROR (%)

–0.2

–0.3

–0.4

0 20 40 60 80 100 120

Figure 17. Settling Time to 0.1%, V

70

60

50

40

30

SLEW RATE (V/μs)

20

10

0

2.5 4.5 6.5 8.5 10.5 12.5

TIME (ns)

= ±2.5 V, Step Size = 2 V p-p,

G = +2, R

SUPPLY VOLTAGE (V)

S

= 500 Ω

L

NEGATIVE EDGE

POSITIVE EDGE

Figure 18. Slew Rate vs. Supply Voltage, G = +2

–0.1%

01053-017

01053-018

–100

–110

HARMONIC DISTORTION (dB)

–120

–130

1k 10k 100k 1M 10M

Figure 20. Distortion vs. Frequency, V

R

= 500 Ω, RF = 0 Ω, V

L

–20

–30

–40

–50

–60

–70

–80

–90

HARMONIC DISTORTION (dBc)

–100

–120

0 5 10 15 20

Figure 21. Distortion vs. Output Voltage, V

G = +2, f = 1 MHz, R

FREQUENCY (Hz)

= ±2.5 V,

= 2 V p-p, G = +1

OUT

OUTPUT VOLTAGE (V p-p)

= 500 Ω, RF = 715 Ω

L

S

3RD

2ND

= ±12 V,

S

01053-020

01053-021

Rev. C | Page 8 of 16

Data Sheet AD8022

2

0

–20

–40

–67.2dBc

–60

–80

HARMONIC DISTORTION (dBc)

–100

–120

0 1.50.5 1.0 2.0 2.5 3.0

Figure 22. Distortion vs. Output Voltage, V

G = +1, f = 1 MHz, R

2ND

3RD

OUTPUT VOLTAGE (V p-p)

= 500 Ω, RF = 0 Ω

L

= ±2.5 V,

S

+V

AD8022

1/2

715Ω

50Ω

500Ω

715Ω

AD8022

1/2

–V

Figure 23. Multitone Power Ratio Test Circuit

10dB/DIV (dBc)

01053-022

102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 112.4111.4110.4

Figure 25. Multitone Power Ratio: V

FREQUENCY (kHz)

= ±12 V, RL = 500 Ω,

S

01053-025

Full Rate ADSL (DMT), Upstream

–66.7dBc

10dB/DIV (dBc)

549.3 559.3558.3557.3556.3555.3554.3553.3552.3551.3550.3

01053-023

Figure 26. Multitone Power Ratio: V

FREQUENCY (kHz)

= ±6 V, RL = 500 Ω,

S

01053-026

Full Rate ADSL (DMT), Downstream

10dB/DIV (dBc)

549.3 559.3558.3557.3556.3555.3554.3553.3552.3551.3550.3

Figure 24. Multitone Power Ratio: V

Full Rate ADSL (DMT), Downstream

–66.0dBc

FREQUENCY (kHz)

= ±12 V, RL = 500 Ω,

S

01053-024

10dB/DIV (dBc)

102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 112.4111.4110.4

Figure 27. Multitone Power Ratio: V

Full Rate ADSL (DMT), Upstream

–69.0dBc

FREQUENCY (kHz)

= ±6 V, RL = 500 Ω,

S

01053-027

Rev. C | Page 9 of 16

AD8022 Data Sheet

–0.5

–1.0

–1.5

0

SIDE A

SIDE B

SIDE A

SIDE B

VS = ±2.5V

–50

–60

–70

–80

CMRR (dB)

56.7

1k

Ω

1k

Ω

50

1k

Ω

1k

Ω

Ω

Ω

VOLTAGE OFFSET (mV)

–2.0

–2.5

–60 –40 –20 140120100806040200

TEMPERATURE (°C)

Figure 28. Voltage Offset vs. Temperature

4.5

4.0

3.5

A)

3.0

μ

2.5

2.0

1.5

BIAS CURRENT (

1.0

0.5

0

–60 –40 –20 140120100806040200

VS = ±2.5V

VS = ±12V

TEMPERATURE (°C)

Figure 29. Bias Current vs. Temperature

4

3

V

IN

2

1

0

(mV)

OS

V

–1

–2

–3

–4

–12.5 –10.0 –7.5 –5.0 –2.5 12.510.07.55.02.50

1k

Ω

1k

Ω

1k

Ω

1k

Ω

500

Ω

V

OUT

VS = ±2.5V

VS = ±12V

VCM(V)

Figure 30. Voltage Offset vs. Input Common-Mode Voltage

VS = +12V

01053-028

01053-029

01053-030

–90

–100

1k 10k 1M100k

FREQUENCY Hz)

Figure 31. CMRR vs. Frequen cy

8.5

8.0

VS = ±12V

7.5

7.0

6.5

VS = ±2.5V

6.0

TOTAL SUPPLY CURRENT (mA)

5.5

5.0
–50 150100500

TEMPERATURE (°C)

Figure 32. Total Supply Current vs. Temperature

0

–10

–20

–30

–40

–50

–60

–70

–80

POWER SUPPLY REJECTION (dB)

–90

–100

10k 100M10M1M100k

–PSRR

FREQUENCY (Hz)

Figure 33. Power Supply Rejection vs. Frequency V

+PSRR

= ±12 V

S

01053-031

01053-032

01053-033

Rev. C | Page 10 of 16

Data Sheet AD8022

0

–10

–20

–30

–40

–50

–60

–70

–80

POWER SUPPLY REJECTION (dB)

–90

–100

10k 100M10M1M100k

–PSRR

+PSRR

FREQUENCY (Hz)

Figure 34. Power Supply Rejection vs. Frequency V

0

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

–100

10k 100M10M1M100k

SIDE A OUT

SIDE B OUT

FREQUENCY (Hz)

Figure 35. Output-to-Output Crosstalk vs. Frequency, V

= ±2.5 V

S

= ±12 V

S

01053-034

01053-035

0

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

–100

100k 100M10M1M

SIDE A OUT

SIDE B OUT

FREQUENCY (Hz)

Figure 36. Output-to-Output Crosstalk vs. Frequency, V

100

31

)

Ω

10

3.16

1

0.316

0.1

OUTPUT IMPEDANCE (

0.0316

30k 500M100M10M1M100k

FREQUENCY (Hz)

Figure 37. Output Impedance vs. Frequency, V

= ±2.5 V

S

= ±12 V

S

01053-036

01053-037

Rev. C | Page 11 of 16

AD8022 Data Sheet

V

THEORY OF OPERATION

The AD8022 is a voltage-feedback op amp designed especially
for ADSL or other applications requiring very low voltage and
current noise along with low supply current, low distortion, and
ease of use.

The AD8022 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with
similar fTs in the 4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features enable the construction of
high frequency, low distortion amplifiers with low supply
currents.

+

S

15Ω

+IN

7.5pF

–IN

600μA

OUTPUT

15Ω

As shown in Figure 38, the AD8022 input stage consists of an
NPN differential pair in which each transistor operates a
300 μA collector current. This gives the input devices a high
transconductance and therefore gives the AD8022 a low input
noise of 2.5 nV/√Hz @ 100 kHz. The input stage drives a folded
cascode that consists of a pair of PNP transistors. These PNPs
then drive a current mirror that provides a differential input to
single-ended output conversion. The output stage provides a
high current gain of 10,000 so that the AD8022 can maintain a
high dc open-loop gain, even into low load impedances.

–V

01053-038

S

Figure 38. Simplified Schematic

Rev. C | Page 12 of 16

Data Sheet AD8022

APPLICATIONS

The low noise AD8022 dual xDSL receiver amplifier is
specifically designed for the dual differential receiver amplifier
function within xDSL transceiver hybrids, as well as other low
noise amplifier applications. The AD8022 can be used in
receiving modulated signals including discrete multitone
(DMT) on either end of the subscriber loop. Communication
systems designers can be challenged when designing an xDSL
modem transceiver hybrid capable of receiving the smallest
signals embedded in noise that inherently exists on twisted-pair
phone lines. Noise sources include near-end crosstalk (NEXT),
far-end crosstalk (FEXT), background, and impulse noise, all of
which are fed, to some degree, into the receiver front end. Based
on a Bellcore noise survey, the background noise level for
typical twisted-pair telephone loops is −140 dBm/√Hz or
31 nV/√Hz. It is therefore important to minimize the noise
added by the receiver amplifiers to preserve as much signal-to­noise ratio (SNR) as possible. With careful transceiver hybrid
design, using the AD8022 dual, low noise, receiver amplifier to
maintain power density levels lower than −140 dBm/√Hz in
ADSL modems is easily achieved.

DMT MODULATION AND MULTITONE POWER RATIO (MTPR)

ADSL systems rely on discrete multitone DMT modulation to
carry digital data over phone lines. DMT modulation appears in
the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figure 24
to Figure 27 for MTPR results while the AD8022 receives DMT
driving 800 mV rms across a 500 Ω differential load.) A
uniquely encoded quadrature amplitude modulation (QAM)
signal occurs at the center frequency of each subband or tone.
Difficulties exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s)
from other subbands, regardless of whether the corruption
comes from an adjacent subband or harmonics of other
subbands. Conventional methods of expressing the output
signal integrity of line receivers, such as spurious-free dynamic
range (SFDR), single tone harmonic distortion (THD), two­tone intermodulation distortion (IMD), and third-order
intercept (IP3), become significantly less meaningful when
amplifiers are required to process DMT and other heavily
modulated waveforms. A typical xDSL downstream DMT signal
can contain as many as 256 carriers (subbands or tones) of
QAM signals. MTPR is the relative difference between the
measured power in a typical subband (at one tone or carrier) vs.
the power at another subband specifically selected to contain no
QAM data.

In other words, a selected subband (or tone) remains open or
void of intentional power (without a QAM signal) yielding an

empty frequency bin. MTPR, sometimes referred to as the
empty bin test, is typically expressed in dBc, similar to
expressing the relative difference between single tone
fundamentals and second or third harmonic distortion
components. Measurements of MTPR are typically made at the
output of the receiver directly across the differential load. Other
components aside, the receiver function of an ADSL transceiver
hybrid is affected by the turns ratio of the selected transformers
within the hybrid design. Since a transformer reflects the
secondary voltage back to the primary side by the inverse of the
turns ratio, 1/N, increasing the turns ratio on the secondary side
reduces the voltage across the primary side inputs of the
differential receiver. Increasing the turns ratio of the
transformers can inadvertently cause a reduction of the SNR by
reducing the received signal strength.

CHANNEL CAPACITY AND SNR

The efficiency of an ADSL system in delivering the digital data
embedded in the DMT signals can be compromised when the
noise power of the transmission system increases. Figure 39
shows the relationship between SNR and the relative maximum
number of bits per tone or subband while maintaining a bit
error rate at 10

60

50

40

30

SNR (dB)

20

10

0

–7

errors per second.

01105

Figure 39. ADSL DMT SNR vs. Bits/Tone

BITS/TONE

5

POWER SUPPLY AND DECOUPLING

The AD8022 should be powered with a good quality (that is,
low noise) dual supply of ±12 V for the best overall
performance. The AD8022 circuit also functions at voltages
lower than ±12 V. Careful attention must be paid to decoupling
the power supply pins. A pair of 10 μF capacitors located in
near proximity to the AD8022 is required to provide good
decoupling for lower frequency signals. In addition, 0.1 μF
decoupling capacitors should be located as close to each of the
power supply pins as is physically possible.

01053-039

Rev. C | Page 13 of 16

AD8022 Data Sheet

A

A

A

01053-040

TP13

TP8

C9

0.1µF

A

OUT2

OUT1

TP9

C10

0.1µF

AVD D

TP10

R16

TP14

R

20kΩ

2kΩ

JP4

AVD D

C11

C8

0.1µF

C7

1µF

TP11

AVD D

B

JP1

CLK

123

A

R15

49.9Ω

TP1

J1

27282526232421221819201617

DVDD

CLOCK

U1

AD9754

DB12

DB13

2143658

NC

AVDD

IOUTA

DCOM

IOUTB

COMP2

DB10

DB11

DB8

DB9

DB6

DB7

7

ACOM

REFIO

FS ADJ

COMP1

DB3

DB4

DB5

DB2

11

109131214

REFLO

DB1

15

SLEEP

DB0

0.1µF

123

AVD D

A

A

CT1

A A A

JP2

J2

PDIN

R17

49.9Ω

TP12

1

DVDD

EXTCLK

VCC

VEE

AGND

VDD

2345678910

R7

DVDD

DVDD

1

2345678910

R3

1

151613

141112910

RES PK

2143658

16 PIN DIP

C19

2345678910

R5

1

7

C1

C25C2C27

C26

C29

C27

16 PIN DIP

RES PK

151613

141112910

2143658

C31

C30

C33

C32

AA

C6

+

TP7

B6

TP6

B5

TP19

B4

TP4

B3

TP2

B2

10µF

A

+

C5

10µF

TP5

TP18

C4

+

10µF

98765432

R6

10

11

DIFFERENTI AL

DMT OUTPUTS

A

98765432

R2

10

7

C35

C34

C36

249Ω

A

750Ω

0.1µF

AVC C

750Ω

AD8022

A

249Ω

A

0.1µF

AD8022

AVE E

DVDD

226Ω

10kΩ49.9Ω

98765432

R6

10

1

1µF

A

AA

10kΩ49.9Ω

A

1µF

AA

DGND

C3

+

TP3

B1

DVDD

10µF

2345678910

R1

1

317511915

13

2119172523292733353739

31

P1

428

6

2021

AWG

TO TEK

121016142220182624302834363840

32

98765432

10

R2

Figure 40. DMT Signal Generator Schematic

C12

22pF

OUT1

J3

C13

22pF

OUT2

J4

Rev. C | Page 14 of 16

Data Sheet AD8022

191Ω

+V

IN

COMMON-

MODE

VOLTAGE

–V

IN

191Ω

7.5

2.5

–2.5

–7.5

–12.5

–17.5

(dB)

–22.5

–27.5

–32.5

–37.5

–42.5

10k 10M1M100k

Figure 42. Frequency Response of Sallen-Key Filter

6800pF

5% NPO

1%

50V

5%

6800pF

5% NPO

3

2

6

5

12V

8

AD8022

249Ω

1%

249Ω

1%

AD8022

4

1

7

1%

SIGNAL C

0.1μF
16V

10%
X7R

1%

243Ω

1%

8200pF

LEVEL

M

8200pF

243Ω

1%

10%

10%

422Ω

0.1μF

NPO

Figure 41. Differential Input Sallen-Key Filter

Using AD8022 on Single Supply, +12 V

FREQUENCY (Hz)

LAYOUT CONSIDERATIONS

As is the case with all high speed amplifiers, careful attention to
printed circuit board layout details prevent associated board

+V

OUT

–V

OUT

01053-041

01053-042

parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the
board to provide a low impedance return path. Removing the
ground plane from the area near the input signal lines reduces
stray capacitance. Chip capacitors should be used for supply
bypassing. One end of the capacitor should be connected to the
ground plane, and the other should be connected no more than
1/8 inch away from each supply pin. An additional large
(0.47 μF to 10 μF) tantalum capacitor should be connected in
parallel, although not necessarily as close, in order to supply
current for fast, large signal changes at the AD8022 output.
Signal lines connecting the feedback and gain resistors should
be as short as possible, minimizing the inductance and stray
capacitance associated with these traces. Locate termination
resistors and loads as close as possible to the input(s) and
output, respectively. Adhere to stripline design techniques for
long signal traces (greater than about 1 inch). Following these
generic guidelines improves the performance of the AD8022 in
all applications.

Rev. C | Page 15 of 16

AD8022 Data Sheet

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)—Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

4

0.40

0.25

5.15

4.90

4.65

1.10 MAX

15° MAX

6°
0°

0.23

0.09

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 44. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)—Dimensions shown in millimeters

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

0.80

0.55

0.40

45°

10-07-2009-B

012407-A

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD8022AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARMZ −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARM-EBZ Evaluation Board
AD8022AR-EBZ

1

Z = RoHS Compliant Part.

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D01053-0-8/11(C)

Rev. C | Page 16 of 16

Evaluation Board