ANALOG DEVICES AD 8021 ARMZ Datasheet

Low Noise, High Speed Amplifier

FEATURES

Low noise

2.1 nV/√Hz input voltage noise

2.1 pA/√Hz input current noise

Custom compensation

Constant bandwidth from G = −1 to G = −10

High speed

200 MHz (G = −1)
190 MHz (G = −10)

Low power

34 mW or 6.7 mA typical for 5 V supply
Output disable feature, 1.3 mA
Low distortion

−93 dBc second harmonic, f

−108 dBc third harmonic, f

DC precision

1 mV maximum input offset voltage

0.5 μV/°C input offset voltage drift
Wide supply range, 5 V to 24 V
Low price
Small packaging

Available in SOIC-8 and MSOP-8

APPLICATIONS

ADC preamps and drivers
Instrumentation preamps

Active filters
Portable instrumentation
Line receivers
Precision instruments

Ultrasound signal processing

High gain circuits

GENERAL DESCRIPTION

The AD8021 is an exceptionally high performance, high speed
voltage feedback amplifier that can be used in 16-bit resolution
systems. It is designed to have both low voltage and low current
noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating
at the lowest quiescent supply current (7 mA @ ±5 V) among
today’s high speed, low noise op amps. The AD8021 operates
over a wide range of supply voltages from ±2.25 V to ±12 V, as
well as from single 5 V supplies, making it ideal for high speed,
low power instruments. An output disable pin allows further
reduction of the quiescent supply current to 1.3 mA.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

= 1 MHz

C

= 1 MHz

C

for 16-Bit Systems

AD8021

CONNECTION DIAGRAM

LOGIC

REFERENCE

–IN

+IN

–V

Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8)

The AD8021 allows the user to choose the gain bandwidth
product that best suits the application. With a single capacitor,
the user can compensate the AD8021 for the desired gain with
little trade-off in bandwidth. The AD8021 is a well-behaved
amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
overload recovery of 50 ns.

The AD8021 is stable over temperature with low input offset
voltage drift and input bias current drift, 0.5 μV/°C and 10 nA/°C,
respectively. The AD8021 is also capable of driving a 75 Ω line
with ±3 V video signals.

The AD8021 is both technically superior and priced considerably
less than comparable amps drawing much higher quiescent
current. The AD8021 is a high speed, general-purpose amplifier,
ideal for a wide variety of gain configurations and can be used
throughout a signal processing chain and in control loops. The
AD8021 is available in both standard 8-lead SOIC and MSOP
packages in the industrial temperature range of −40°C to +85°C.

24

= 50mV p-p

V

OUT

21

G = –10, R

18

15

12

9

6

3

CLOSED-LOOP GAIN (dB)

0

–3

–6

0.1M 1G1M 10M 100M

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

F

R

= 100Ω, CC = 0pF

IN

G = –5, R

= 1kΩ, RG = 200Ω,

F

R

= 66.5Ω, CC = 1.5pF

IN

= 499Ω, RG = 249Ω,

G = –2, R

F

R

= 63.4Ω, CC = 4pF

IN

G = –1, R

= 499Ω, RG = 499Ω,

F

R

= 56.2Ω, CC = 7pF

IN

Figure 2. Small Signal Frequency Response

AD8021

1

2

3

4

S

= 1kΩ, RG = 100Ω,

FREQUENCY (Hz)

8

7

6

5

DISABLE

+V

S

V

OUT

C

COMP

01888-001

01888-002

AD8021

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications..................................................................................... 19

Applications....................................................................................... 1

General Description......................................................................... 1

Connection Diagram .......................................................................1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 7

Maximum Power Dissipation ..................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics............................................. 9

Test Circ uit s................................................................................. 17

REVISION HISTORY

5/06—Rev. E to Rev. F

Updated Format..................................................................Universal

Changes to General Description .................................................... 1

Changes to Figure 3.......................................................................... 7

Changes to Figure 60...................................................................... 19

Changes to Table 9.......................................................................... 23

3/05—Rev. D to Rev. E

Updated Format..................................................................Universal

Change to Figure 19 ....................................................................... 11

Change to Figure 25 ....................................................................... 12

Change to Table 7 and Table 8 ...................................................... 22

Change to Driving 16-Bit ADCs Section .................................... 22

Using the Disable Feature.......................................................... 20

Theory of Operation ...................................................................... 21

PCB Layout Considerations...................................................... 21

Driving 16-Bit ADCs................................................................. 22

Differential Driver...................................................................... 22

Using the AD8021 in Active Filters .........................................23

Driving Capacitive Loads.......................................................... 23

Outline Dimensions .......................................................................25

Ordering Guide .......................................................................... 25

7/03—Rev. B to Rev. C

Deleted All References to Evaluation Board................... Universal

Replaced Figure 2 ..............................................................................5

Updated Outline Dimensions....................................................... 20

2/03—Rev. A to Rev. B

Edits to Evaluation Board Applications....................................... 20

Edits to Figure 17 ........................................................................... 20

6/02—Rev. 0 to Rev. A

Edits to Specifications.......................................................................2

10/03—Rev. C to Rev. D

Updated Format..................................................................Universal

Rev. F | Page 2 of 28

AD8021

SPECIFICATIONS

VS = ±5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.

Table 1.

Parameter Conditions

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth

Slew Rate, 1 V Step

Settling Time to 0.01%
Overload Recovery (50%)

DISTORTION/NOISE PERFORMANCE

G = +1, C
G = +2, C
G = +5, C
G = +10, C
G = +1, C
G = +2, C
G = +5, C
G = +10, C
V

O

= 10 pF, VO = 0.05 V p-p 355 490

C

= 7 pF, VO = 0.05 V p-p 160 205

C

= 2 pF, VO = 0.05 V p-p 150 185

C

= 0 pF, VO = 0.05 V p-p 110 150

C

= 10 pF 95 120

C

= 7 pF 120 150

C

= 2 pF 250 300

C

= 0 pF 380 420

C

= 1 V step, RL = 500 Ω

±2.5 V input step, G = +2

AD8021AR/AD8021ARM

Min Typ Max Unit

23
50

f = 1 MHz

HD2
HD3

= 2 V p-p

V

O

= 2 V p-p

V

O

−93

−108

f = 5 MHz

HD2

HD3
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error

DC PERFORMANCE

= 2 V p-p

V

O

= 2 V p-p

V

O

f = 50 kHz
f = 50 kHz
NTSC, R
NTSC, R

= 150 Ω

L

= 150 Ω

L

Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current

to T

MAX

T

MIN

+Input or −input
Input Bias Current Drift
Input Offset Current
Open-Loop Gain

INPUT CHARACTERISTICS

Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio

OUTPUT CHARACTERISTICS

= ±4 V −86 −98

V

CM

Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot

DISABLE CHARACTERISTICS

Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current

= 50 mV p-p/1 V p-p

V

O

f = 10 MHz

= 0 V to 2 V, 50% logic to 50% output

V

O

= 0 V to 2 V, 50% logic to 50% output

V

O

V

DISABLE

− V

LOGIC REFERENCE

LOGIC REFERENCE = 0.4 V

DISABLE = 4.0 V

−70

−80

2.1 2.6 nV/√Hz

2.1

0.03

0.04

0.4 1.0 mV

0.5

7.5 10.5 μA
10

0.1 0.5 ±μA

82 86

10
1

−4.1 to +4.6

−3.5 to +3.2 −3.8 to +3.4
60
75
15/120

−40
45
50

1.75/1.90
70
2

MHz
MHz
MHz
MHz
V/μs
V/μs
V/μs
V/μs
ns
ns

dBc
dBc

dBc
dBc

pA/√Hz
%
Degrees

μV/°C

nA/°C

dB

MΩ
pF
V
dB

V
mA
mA
pF

dB
ns
ns
V
μA
μA

Rev. F | Page 3 of 28

AD8021

Parameter Conditions

Disabled Leakage Current

POWER SUPPLY

LOGIC REFERENCE = 0.4 V
DISABLE = 0.4 V

Operating Range
Quiescent Current

+Power Supply Rejection Ratio

−Power Supply Rejection Ratio

Output enabled
Output disabled

= 4 V to 6 V, VEE = −5 V −86 −95

V

CC

= 5 V, VEE = −6 V to −4 V −86 −95

V

CC

AD8021AR/AD8021ARM

Min Typ Max Unit

30
33

±2.25 ±5 ±12.0 V

7.0 7.7 mA

1.3 1.6 mA

= ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.

V

S

Table 2.

AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 520 560 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 175 220 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 170 200 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 125 165 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 105 130 V/μs
G = +2, CC = 7 pF 140 170 V/μs
G = +5, CC = 2 pF 265 340 V/μs
G = +10, CC = 0 pF 400 460 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 21 ns
Overload Recovery (50%) ±6 V input step, G = +2 90 ns

DISTORTION/NOISE PERFORMANCE

f = 1 MHz

HD2 VO = 2 V p-p −95 dBc
HD3 VO = 2 V p-p −116 dBc

f = 5 MHz

HD2 VO = 2 V p-p −71 dBc

HD3 VO = 2 V p-p −83 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
Differential Gain Error NTSC, RL = 150 Ω 0.03 %
Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees

DC PERFORMANCE

Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift T

MIN

to T

0.2 μV/°C

MAX

Input Bias Current +Input or −input 8 11.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 84 88 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range −11.1 to +11.6 V
Common-Mode Rejection Ratio VCM = ±10 V −86 −96 dB

μA
μA

dB
dB

Rev. F | Page 4 of 28

AD8021

AD8021AR/AD8021ARM

Parameter Conditions Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Swing −10.2 to +9.8 −10.6 to +10.2 V
Linear Output Current 70 mA
Short-Circuit Current 115 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 15/120 pF

DISABLE CHARACTERISTICS

Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 2 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 2 V, 50% logic to 50% output 50 ns

V

DISABLE Voltage—Off/On

DISABLE

− V

LOGIC REFERENCE

Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA

DISABLE = 4.0 V

Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA

DISABLE = 0.4 V

POWER SUPPLY

Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 7.8 8.6 mA
Output disabled 1.7 2.0 mA
+Power Supply Rejection Ratio VCC = 11 V to 13 V, VEE = −12 V −86 −96 dB

−Power Supply Rejection Ratio VCC = 12 V, VEE = −13 V to −11 V −86 −100 dB

1.80/1.95 V

2 μA

33 μA

= 5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.

V

S

Table 3.

AD8021AR/AD8021ARM

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 270 305 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 155 190 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 135 165 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 95 130 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 80 110 V/μs
G = +2, CC = 7 pF 110 140 V/μs
G = +5, CC = 2 pF 210 280 V/μs
G = +10, CC = 0 pF 290 390 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 28 ns
Overload Recovery (50%) 0 V to 2.5 V input step, G = +2 40 ns

DISTORTION/NOISE PERFORMANCE

f = 1 MHz

HD2 VO = 2 V p-p −84 dBc
HD3 VO = 2 V p-p −91 dBc

f = 5 MHz

HD2 VO = 2 V p-p −68 dBc

HD3 VO = 2 V p-p −81 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz

Rev. F | Page 5 of 28

AD8021

AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit

DC PERFORMANCE

Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift T
Input Bias Current +Input or −input 7.5 10.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 72 76 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range 0.9 to 4.6 V
Common-Mode Rejection Ratio 1.5 V to 3.5 V −84 −98 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing 1.25 to 3.38 1.10 to 3.60 V
Linear Output Current 30 mA
Short-Circuit Current 50 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 10/120 pF

DISABLE CHARACTERISTICS

Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 1 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 1 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA

Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA

POWER SUPPLY

Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 6.7 7.5 mA
Output disabled 1.2 1.5 mA
+Power Supply Rejection Ratio VCC = 4.5 V to 5.5 V, VEE = 0 V −74 −82 dB

−Power Supply Rejection Ratio VCC = 5 V, VEE = −0.5 V to +0.5 V −76 −84 dB

to T

MIN

V

DISABLE

0.8 μV/°C

MAX

− V

LOGIC REFERENCE

DISABLE = 4.0 V

DISABLE = 0.4 V

1.55/1.70 V

2 μA

33 μA

Rev. F | Page 6 of 28

AD8021

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 26.4 V
Power Dissipation

Observed power

derating curves
Input Voltage (Common Mode) ±VS ± 1 V
Differential Input Voltage

1

±0.8 V
Differential Input Current ±10 mA
Output Short-Circuit Duration

Observed power

derating curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C

1

The AD8021 inputs are protected by diodes. Current-limiting resistors are

not used to preserve the low noise. If a differential input exceeds ±0.8 V, the
input current should be limited to ±10 mA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8021 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit can cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.

While the AD8021 is internally short-circuit protected, this can
not be sufficient to guarantee that the maximum junction tem­perature (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum
power derating curves.

2.0

1.5

8-LEAD SOIC

1.0

8-LEAD MSOP

0.5

MAXIMUM POW ER DISSIP ATION (W)

0.01
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65

1

Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead

Figure 3. Maximum Power Dissipation vs. Temperature

MSOP: θ

= 145°C/W.

JA

AMBIENT TEM PERATURE (°C)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

01888-004

5

8

75

1

Rev. F | Page 7 of 28

AD8021

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LOGIC

REFERENCE

–IN

+IN

–V

AD8021

1

2

3

4

S

8

7

6

5

DISABLE

+V

S

V

OUT

C

COMP

01888-003

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 LOGIC REFERENCE Reference for Pin 81 Voltage Level. Connect to logic low supply.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −V
5 C
6 V

S

Compensation Capacitor. Tie to −VS. (See the Applications section for value.)

COMP

Output.

OUT

Negative Supply Voltage.

7 +VS Positive Supply Voltage.
8

1

When Pin 8 (

Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to
+VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.

DISABLE

) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of

DISABLE

Disable, Active Low.

Rev. F | Page 8 of 28

AD8021

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, RL = 1 kΩ, G = +2, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 976 Ω, RD = 53.6 Ω, CC = 7 pF, CL = 0, CF = 0, V
frequency = 1 MHz, unless otherwise noted.

24

G = +10, R

21

18

G = +5, R

15

12

9

G = +2, R

6

3

CLOSED-LOOP GAIN (dB)

G = +1, R

0

–3

–6

0.1M 1G1M 10M 100M

= 1kΩ, RG = 110Ω, CC = 0pF

F

= 1kΩ, RG = 249Ω, CC = 2pF

F

= RG = 499Ω, CC = 7pF

F

= 75Ω, CC = 10pF

F

FREQUENCY (Hz)

01888-005

9

G = +2

8

7

6

5

4

GAIN (dB)

3

2

1

0

–1

10M 100M

FREQUENCY (Hz)

VS = ±2.5V

VS = ±2.5V

OUT

VS = ±5V

VS = ±12V

= 2 V p-p,

01888-008

1G1M

Figure 5. Small S ignal Freq uency Respons e vs. Frequency and Gain,

= 50 mV p-p, Noninverting (See Figure 48)

V

OUT

24

21

G = –10, RF = 1kΩ, RG = 100Ω,

18

= 100Ω, CC = 0pF

R

IN

15

= 1kΩ, RG = 200Ω,

G = –5, R

12

9

GAIN (dB)

6

3

0

–3

–6

0.1M 1G1M 10M 100M

F

= 66.5Ω, CC = 1.5pF

R

IN

= 499Ω, RG = 249Ω,

G = –2, R

F

= 63.4Ω, CC = 4pF

R

IN

= 499Ω, RG = 499Ω,

G = –1, R

F

= 56.2Ω, CC = 7pF

R

IN

FREQUENCY (Hz)

Figure 6. Small S ignal Freq uency Respons e vs. Frequency and

Gain, V

9

G = +2

8

7

6

5

4

GAIN (dB)

3

2

1

0

–1

0.1M 1G1M

= 50 mV p-p Inverting (See Figure 48)

OUT

= 9pF

C

C

C

= 7pF

C

CC = 9pF

10M 100M

FREQUENCY (Hz)

C

C

C

C

= 5pF

= 7pF

Figure 7. Small S ignal Freq uency Respons e vs. Frequency and

Compensation Capacitor, V

= 50 mV p-p (See Figu re 48)

OUT

01888-006

01888-007

Figure 8. Small S ignal Freq uency Respons e vs. Frequency and Supply,

V

= 50 mV p-p, Noninverting (See Figure 48)

OUT

3

G = –1

2

1

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

–7

10M 100M

FREQUENCY (Hz)

VS = ±2.5V

VS = ±12V

VS = ±2.5V

VS = ±5V

01888-009

1G1M

Figure 9. Small S ignal Freq uency Respons e vs. Frequency and Supply,

= 50 mV p-p, Inverting (See Figure 50)

V

OUT

9

G = +2

8

7

6

5

4

GAIN (dB)

3

2

1

0

–1

V

= 4V p-p

OUT

V

= 1V p-p

OUT

10M 100M

Figure 10. Frequency Response v s. Frequency and V

V

= 0.1V AND 50mV p -p

OUT

FREQUENCY (Hz)

Figure 48)

(See

, Noninverting

OUT

01888-010

1G1M

Rev. F | Page 9 of 28

AD8021

10

G = +2

9

8

7

6

5

GAIN (dB)

4

3

2

1

0

0.1M 1G1M

RL = 100Ω

10M 100M

FREQUENCY (Hz)

RL = 1kΩ

Figure 11. Large Signal Frequency R esponse v s. Frequency and

Load, Noninverting (See

Figure 49)

01888-011

10

G = +2
R

= R

9

F

G

8

7

6

5

GAIN (dB)

4

3

2

1

0

RF = 1kΩ AND CF = 2.2pF

1M

R

= 499Ω

F

R

= 75Ω

F

FREQUENCY (Hz)

= 1kΩ

R

F

= 250Ω

R

F

RF = 150Ω

1G0.1M 10M 100M

Figure 14. Small Signal Fre quency Response vs. Freq uency an d R

Noninverting, V

= 50 mV p-p (See Figure 48)

OUT

01888-014

,

F

9

G = +2

8

7

6

5

4

GAIN (dB)

3

2

1

0

–1

+85°C

V

=

OUT

2V p-p

+25°C

–40°C

10M 100M

FREQUENCY (Hz)

–40°C

+85°C

+25°C

V

=

OUT

50mV p-p

1G1M

Figure 12. Frequency Response v s. Frequency, Tempe rature, and

, Noninverting (See Figure 48)

V

OUT

GAIN (dB)

–12

18

G = +2

15

12

9

6

3

0

–3

–6

–9

10M

FREQUENCY (Hz)

50pF

100M

30pF

20pF

10pF

0pF

1G1M

Figure 13. Small Signal Frequency Response vs.

Frequency and Capacitive Load, Noninverting, V

Figure 49 and Figure 71)

(See

= 50 mV p-p

OUT

15

G = +2

12

9

6

3

0

GAIN (dB)

–3

–6

–9

–12

01888-012

–15

0.1M 1G1M

10M 100M

FREQUENCY (Hz)

Figure 15. Small Signal Fre quency Response vs. Freq uency an d R

Noninverting, V

100

90

80

70

60

50

40

30

OPEN-LOOP GAIN (dB)

20

10

01888-013

0

10k

100k 1G1M

= 50 mV p-p (See Figure 48)

OUT

FREQUENCY (Hz)

Figure 16. Open-Loop Gain and Phase vs. Frequency, R

= 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50)

R

F

= 49.9Ω

R

S

R

= 100Ω

S

= 249Ω

R

S

10M 100M

= 100 Ω,

G

180

135

90

45

0

–45

–90

–135

,

S

01888-015

PHASE (Degrees)

01888-016

Rev. F | Page 10 of 28

AD8021

6.4
G = +2

6.2

6.0

GAIN (dB)

5.8

5.6

5.4

1M

FREQUENCY (Hz)

VS = ±5V

10M 100M

VS = ±2.5V

Figure 17. 0.1 dB Flatness vs. Frequency and Supply, V

= 150 Ω, Noninverting (See Figure 49)

R

L

VS = ±12V

= 1 V p-p,

OUT

01888-017

–20

–30

–40

–50

–60

–70

(dBm)

OUT

–80

P

–90

–100

–110

–120

9.5

Δf

= 0.2MHz

9.7 10.3

f

1

10.0

FREQUENCY (MHz)

f

2

Figure 20. Intermodulation Distortion vs. Frequency

P

OUT

976Ω

53.6Ω 50Ω

10.5

01888-020

–20

–30

–40

DISTORTION (dBc)

–50

–60

–70

–80

–90

–100

–110

–120

–130

RL = 100Ω

0.1M

R

= 1kΩ

L

THIRD

FREQUENCY (Hz)

1M

SECOND

10M 20M

Figure 18. Second and Third Harmonic Distortion vs. Frequency and R

–30

–40

–50

–60

DISTORTION (dBc)

–70

–80

–90

–100

–110

–120

–130

100k

VS = ±2.5V

SECOND

THIRD

THIRD

VS = ±5V

SECOND

SECOND

1M 20M

FREQUENCY (Hz)

VS = ±12V

10M

Figure 19. Second and Third Harmonic Distortion vs. Frequency and V

01888-018

L

01888-019

S

50

45

40

VS = ±5V

35

V

= ±2.5V

30

THIRD-ORDER INTERCEPT (dBm)

25

20

0

S

515

10 20

FREQUENCY (MHz)

Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage

–50

–60

–70

–80

–90

SECOND

DISTORTION (dBc)

–100

RL = 1kΩ

–110

–120

1

Figure 22. Second and Third Harmonic Distortion vs. V

SECOND

RL = 100Ω

THIRD

THIRD

2345

(V p-p)

V

OUT

OUT

6

and R

01888-021

01888-022

L

Rev. F | Page 11 of 28

AD8021

–50

3.5

–3.1

DISTORTION (dBc)

–100

–110

–120

–60

–70

–80

–90

1

SECOND

f

= 5MHz

C

THIRD

SECOND

f

= 1MHz

C

THIRD

2345

(V p-p)

V

OUT

Figure 23. Second and Third Harmonic Distortion vs. V

), G = +2

C

DISTORTION (dBc)

–100

–40

–50

–60

–70

–80

–90

Fundamental Frequency (f

f

= 5MHz

C

SECOND

THIRD

SECOND

f

= 1MHz

C

THIRD

OUT

6

and

01888-023

3.4

3.3

3.2

3.1

3.0

POSITIVE OUTPUT VOLTAGE (V)

2.9

2.8
0 800 1600

400 1200 2000

LOAD (Ω)

POSITIVE OUTPUT

NEGATIVE OUTPUT

Figure 26. DC Output Voltages vs. Load (See

120

100

80

60

40

SHORT-CIRCUIT CURRENT (mA)

20

VS = ±12V

VS = ±5.0V

VS = ±2.5V

Figure 48)

–3.2

–3.3

–3.4

–3.5

–3.6

NEGATIVE OUTPUT VOLTAGE (V)

–3.7

01888-026

–3.8

–110

1

2345

V

(V p-p)

OUT

Figure 24. Second and Third Harmonic Distortion vs. V

Fundamental Frequency (f

–70

f

= 1MHz

C

R

= 1kΩ

L

R

= R

F

–80

–90

–100

DISTORTION (dBc)

–110

–120

G

G = +2

0 400 800

200 600 1000

FEEDBACK RESISTANCE (Ω)

), G = +10

C

SECOND

THIRD

OUT

6

and

Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (R

01888-024

01888-025

)

F

0

–50 –10 30–30 10 50

TEMPERATURE ( °C)

70 90 110

Figure 27. Short-Circuit Current to Ground vs. Temperature

50

G = 2

(mV)

V

OUT

–10

–20

–30

–40

–50

40

30

20

10

80400

RL = 1kΩ, 150Ω

120 160 200

TIME (ns)

Figure 28. Small Signal Transient Response vs.

, VO = 50 mV p-p, Noninverting (See Figure 49)

R

L

01888-027

01888-028

Rev. F | Page 12 of 28

AD8021

V

= 4V p-p

2.0

O

G = 2

2.0

V

= 2V p-p

O

G = 2

= 4V p-p

V

O

G = –1

RL = 1kΩ

500

RL = 150Ω

80400

(See

V

100 150 200 250

120 160 200

TIME (ns)

Figure 49)

V

IN

OUT

TIME (ns)

, Noninverting

L

1.0

(V)

OUT

V

–1.0

–2.0

Figure 29. Large Signal Transient Response vs. R

5

4

3

2

1

–1

VOLTS

–2

–3

–4

–5

Figure 30. Large Signal Transient Response, Inverting (See

Figure 50)

01888-029

01888-030

1.0

(V)

OUT

V

–1.0

–2.0

80400

TIME (ns)

= ±5V

V

S

120 160 200

Figure 32. Large Signal Transient Response vs. V

VIN = ±3V
G = +2
V

= 1V/DIV

IN

V

= 2V/DIV

OUT

R

= 150Ω

L

V

IN

0 100 200 300 400 500

TIME (ns)

Figure 33. Overdrive Recovery vs. R

V

OUT

, RL = 1kΩ

L

(See Figure 49)

V

(See Figure 48)

S

= ±2.5V

S

01888-032

01888-033

CL = 50pF
G = 2

2.0

C

= 10pF, 0pF

L

80400

120 160 200

TIME (ns)

(V)

OUT

V

1.0

–1.0

–2.0

Figure 31. Large Signal Transient Response vs. C

V

= 4V p-p

O

(See Figure 48)

L

01888-031

Rev. F | Page 13 of 28

G = 2

+0.01%

–0.01%

OUTPUT SETTLING

VERT = 0.2mV/DIV

Figure 34. 0.01% Settling Time, 2 V Step

25ns

HOR = 5ns/DIV

01888-034

AD8021

100

80

60

40

20

0

–20

SETTLING (µV)

–40

–60

–80

–100

04 8 16 32

PULSE WI DTH = 120ns

PULSE WI DTH = 300µs

5V

0V

t

1

Figure 35. Long-Term Settling, 0 V to 5 V, V

50

G = +1

40

30

20

10

(mV)

OUT

V

–10

–20

–30

–40

–50

Figure 36. Small Signal Transient Response, V

12

80400

(See

TIME (µs)

TIME (ns)

20 28

= ±12 V, G = +13

S

120 160 200

= 50 mV p-p, G = +1

O

Figure 48)

100

10

INPUT CURRENT NOISE (pA/√Hz)

24

01888-035

1

100 10M1k 10k 100k

10

FREQUENCY (Hz)

1M

01888-038

Figure 38. Input Current Noise vs. Frequency

0.48

0.44

0.40

0.36

0.32

VOLTAGE OFFSET (mV)

0.28

01888-036

0.24
–50 0

–25 10025

TEMPERATURE (°C)

Figure 39. V

vs. Temperature

OS

50 75

01888-039

100

Hz)

√

10

VOLTAGE NOISE (nV/

1

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

2.1nV/√Hz

Figure 37. Input Voltage No ise vs. Freq uency

01888-037

10M

Rev. F | Page 14 of 28

8.4

8.0

A)

μ

7.6

7.2

6.8

INPUT BIAS CURRENT (

6.4

6.0
–50 0

–25 10025

Figure 40. Input Bias Current vs. Temperature

TEMPERATURE (°C)

50 75

01888-040

AD8021

–20

–30

–40

–50

–60

–70

CMRR (dB)

–80

–90

–100

–110

–120

10k 1M

100k 10M 100M

Figure 41. CMRR vs. Fre quency ( See Figure 51)

FREQUENCY (Hz)

01888-041

0

–10

–20

–30

–40

–50

–60

–70

DISABLED ISOLATION (dB)

–80

–90

–100

0.1M 10M

1M 1G100M

FREQUENCY (Hz)

Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 5 4)

01888-044

300

100

30

10

3

1

0.3

0.1

OUTPUT IMPEDANCE (Ω)

0.03

0.01

0.003
10k 1M

100k 1G10M 100M

FREQUENCY (Hz)

Figure 42. Output Impedance vs. Freq uency, Chip Ena bled

Figure 52)

(See

= 45ns

DISABLE

V

OUTPUT

)/Disable (t

EN

t

= 50ns

DIS

TIME (ns)

) Time vs. V

DIS

(See Figure 53)

OUT

4V

2V

2V

t

EN

1V

0 100 200 300 400 500

Figure 43. Enable (t

01888-042

01888-043

300k

100k

30k

10k

3k

1k

300

100

OUTPUT IMPEDANCE (Ω)

30

10

3

10k 1M

100k 1G10M 100M

FREQUENCY (Hz)

Figure 45. Output Impedance vs. Frequency, Chip Disabled

Figure 55)

(See

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

VS = ±2.5V

FREQUENCY (Hz)

–PSRR

+PSRR

VS = ±12V

VS = ±5V

1M 500M100M10k 10M100k

Figure 46. PSRR vs. Frequency and Supply Voltage

(See

Figure 56 and Figure 57)

01888-045

01888-046

Rev. F | Page 15 of 28

AD8021

8.5

8.0

7.5

7.0

6.5

SUPPLY CURRENT (mA)

6.0

5.5
–50 25

0 10050

TEMPERATURE (°C)

Figure 47. Quiescent Supply Current vs. Temperature

75–25

01888-047

Rev. F | Page 16 of 28

AD8021

TEST CIRCUITS

+V

50Ω

50Ω

50Ω

50Ω CABLE

50Ω CABLE

R

49.9Ω

R

IN

R

G

S

S

C

–V

S

R

O

5

C

R

F

C

F

Figure 48. Noninverting Gain

FET

PROBE

+V

50Ω CABLE

R

49.9Ω

R

S

IN

R

G

S

5

C

C

–V

S

R

F

C

F

Figure 49. Noninverting Gain and FET Probe

+V

S

R

49.9Ω

49.9Ω

C

–V

C

S

R

G

R

IN

O

5

R

F

Figure 50. Inverting Gain

HP8753D

NETWORK

ANALYZER

50Ω

AD8021

499Ω

499Ω

55.6Ω

50Ω

+V

S

5

C

C

7pF

–V

S

499Ω499Ω

Figure 51. CMRR

R

R

D

D

49.9Ω

50Ω CABLE

C

L

50Ω CABLE

01888-051

100Ω

01888-048

R

L

01888-049

01888-050

499Ω

1.0V

4V

49.9Ω

Figure 54. Input-to-Output Isolation, Chip Disabled

100Ω

AD8021

+V

S

5

C

C

7pF

–V

S

R

G

R

499Ω

F

50Ω

HP8753D

NETWORK
ANALYZER

Figure 52. Output Impedance, Chip Enabled

AD8021

+V

49.9Ω

49.9Ω

49.9Ω

1

8

499Ω

S

LOGIC REF
DISABLE

C

C

7pF

–V

S

499Ω

5

Figure 53. Enable/Disable

HP8753D

NETWORK
ANALYZER

50Ω

49.9Ω

1

LOGIC REF
DISABLE

8

–V

499Ω499Ω

+V

S

50Ω

S

C

7pF

AD8021

5

C

FET
PROBE

AD8021

1

+V

S

8

5

C

C

7pF

–V

S

50Ω

NETWORK

ANALYZER

Figure 55. Output Impedance, Chip Disabled

976Ω

50Ω CABLE

1kΩ

HP8753D

01888-052

53.6Ω

01888-054

01888-055

01888-053

Rev. F | Page 17 of 28

AD8021

BIAS

BNC

+V

S

249Ω

499Ω

50Ω

+V

–V

S

49.9Ω, 5W

S

C

C

7pF

499Ω

HP8753D

NETWORK

ANALYZER

5

50Ω

976Ω

53.6Ω

50Ω CABLE

01888-056

BIAS

BNC

50Ω

S

249Ω

499Ω



–V

49.9Ω

5W

–V

S

NETWORK

ANALYZER

+V

S

C

C

7pF

499Ω

HP8753D

5

50Ω

976Ω

53.6Ω

50Ω CABLE

01888-057

Figure 56. Positive PSRR

Figure 57. Negative PSRR

Rev. F | Page 18 of 28

AD8021

APPLICATIONS

The typical voltage feedback op amp is frequency stabilized
with a fixed internal capacitor, C

, using dominant pole

INTERNAL

compensation. To a first-order approximation, voltage feedback
op amps have a fixed gain bandwidth product. For example, if
its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain
of G = +10, its bandwidth is only about 20 MHz. The AD8021 is
a voltage feedback op amp with a minimal C

1.5 pF. By adding an external compensation capacitor, C

INTERNAL

of about

, the

C

user can circumvent the fixed gain bandwidth limitation of
other voltage feedback op amps.

Unlike the typical op amp with fixed compensation, the
AD8021 allows the user to:

• Maximize the amplifier bandwidth for closed-loop gains

between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.

• Optimize the trade-off between bandwidth and phase

margin for a particular application.

• Match bandwidth in gain blocks with different noise gains,

such as when designing differential amplifiers (as shown in
Figure 65).

110

100

90
86
80

70

C

= 10pF

C

60

50

40

30

OPEN-LOOP GAIN (dB)

20

10

0

–10

10k 10M

1k 1G 10G

100k

FREQUENCY (Hz)

C

1M

= 0pF

C

(B)

(B)

(A)

(A)
(C)

100M

(C)

Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response

180

135

90

45

0

PHASE (Degrees)

01888-058

Figure 58 is the AD8021 gain and phase plot that has been
simplified for instructional purposes. Arrow A in

Figure 58
shows a bandwidth of about 200 MHz and a phase margin at
about 60° when the desired closed-loop gain is G = +1 and
the value chosen for the external compensation capacitor is
C

= 10 pF. If the gain is changed to G = +10 and CC is fixed at

C

10 pF, then (as expected for a typical op amp) the bandwidth is

degraded to about 20 MHz and the phase margin increases to
90° (Arrow B). However, by reducing C

to 0 pF, the bandwidth

C

and phase margin return to about 200 MHz and 60° (Arrow C),
respectively. In addition, the slew rate is dramatically increased,
as it roughly varies with the inverse of C

10

9

8

7

6

5

4

3

2

COMPENSATION CAPACITANCE (pF)

1

0

12 3 4 5 6 7 8 91011

Figure 59. Suggested Compensation Capacitance vs. Gain for

NOISE GAIN (V/V)

Maintaining 1 dB Peaking

.

C

01888-059

Table 6 and Figure 59 provide recommended values of com­pensation capacitance at various gains and the corresponding
slew rate, bandwidth, and noise. Note that the value of the
compensation capacitor depends on the circuit noise gain, not
the voltage gain. As shown in

Figure 60, the noise gain, GN, of
an op amp gain block is equal to its noninverting voltage gain,
regardless of whether it is actually used for inverting or nonin­verting gain. Thus,

Noninverting G

Inverting G

R

S

3

1

2

NONINVERTI NG

= RF/RG + 1

N

= RF/RG + 1

N

R

G

R

F

1kΩ

R

G

249Ω

249Ω

2

3

+

AD8021

–

–V

S

C

COMP

G = GN = +5

6

5

Figure 60. The Noise Gain of Both is 5

1kΩ

–

AD8021

+

–V

S

C

COMP

INVERTING

R

F

6

5

G = –4

= +5

G

N

01888-060

Rev. F | Page 19 of 28

AD8021

CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49).

Table 6. Recommended Component Values

Noise Gain
(Noninverting
Gain)

1 75 75 NA 10 120 490 2.1 2.8
2 49.9 499 499 7 150 205 4.3 8.2
5 49.9 1 k 249 2 300 185 10.7 15.5
10 49.9 1 k 110 0 420 150 21.2 27.9
20 49.9 1 k 52.3 0 200 42 42.2 52.7
100 49.9 1 k 10 0 34 6 211.1 264.1

R

(Ω) RF (Ω) RG (Ω) C

S

(pF) Slew Rate (V/μs)

COMP

−3 dB
SS BW
(MHz)

Output Noise
(AD8021 Only)
(nV/√Hz)

Output Noise
(AD8021 with Resistors)
(nV/√Hz)

With the AD8021, a variety of trade-offs can be made to fine­tune its dynamic performance. Sometimes more bandwidth
or slew rate is needed at a particular gain. Reducing the
compensation capacitance, as illustrated in

Figure 7, increases
the bandwidth and peaking due to a decrease in phase margin.
On the other hand, if more stability is needed, increasing the
compensation capacitor decreases the bandwidth while
increasing the phase margin.

As with all high speed amplifiers, parasitic capacitance and
inductance around the amplifier can affect its dynamic
response. Often, the input capacitance (due to the op amp itself,
as well as the PC board) has a significant effect. The feedback
resistance, together with the input capacitance, can contribute
to a loss of phase margin, thereby affecting the high frequency
response, as shown in

Figure 14. A capacitor (CF) in parallel

with the feedback resistor can compensate for this phase loss.

Additionally, any resistance in series with the source creates a
pole with the input capacitance (as well as dampen high
frequency resonance due to package and board inductance
and capacitance), the effect of which is shown in

Figure 15.

It must also be noted that increasing resistor values increases
the overall noise of the amplifier and that reducing the feedback
resistor value increases the load on the output stage, thus
increasing distortion (see

Figure 22).

USING THE DISABLE FEATURE

When Pin 8 (
REFERENCE) by approximately 2 V or more, the part is
enabled. When Pin 8 is brought down to within about 1.5 V
of Pin 1, the part is disabled. See
enable voltage levels. If the disable feature is not used, Pin 8 can
be tied to V
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part is in an enabled state.

DISABLE

) is higher than Pin 1 (LOGIC

Table 1 for exact disable and

or a logic high source, and Pin 1 can be tied to

S

Rev. F | Page 20 of 28

AD8021

C

R

THEORY OF OPERATION

The AD8021 is fabricated on the second generation of Analog
Devices proprietary High Voltage eXtra-Fast Complementary
Bipolar (XFCB) process, which enables the construction of PNP
and NPN transistors with similar f

s in the 3 GHz region. The

T

transistors are dielectrically isolated from the substrate (and
each other), eliminating the parasitic and latch-up problems
caused by junction isolation. It also reduces nonlinear capaci­tance (a source of distortion) and allows a higher transistor, f

,

T

for a given quiescent current. The supply current is trimmed,
which results in less part-to-part variation of bandwidth, slew
rate, distortion, and settling time.

As shown in

Figure 61, the AD8021 input stage consists of an

NPN differential pair in which each transistor operates at a

0.8 mA collector current. This allows the input devices a high
transconductance; thus, the AD8021 has a low input noise of

2.1 nV/√Hz @ 50 kHz. The input stage drives a folded cascode
that consists of a pair of PNP transistors. The folded cascode
and current mirror provide a differential-to-single-ended
conversion of signal current. This current then drives the high
impedance node (Pin 5), where the C

external capacitor is

C

connected. The output stage preserves this high impedance with
a current gain of 5000, so that the AD8021 can maintain a high
open-loop gain even when driving heavy loads.

Two internal diode clamps across the inputs (Pin 2 and Pin 3)
protect the input transistors from large voltages that could
otherwise cause emitter-base breakdown, which would result in
degradation of offset voltage and input bias current.

+V

S

+IN

–IN

C

INTERNAL

1.5pF

C

COMP

Figure 61. Simplified Schematic

OUTPUT

–V

S

C

C

01888-061

PCB LAYOUT CONSIDERATIONS

As with all high speed op amps, achieving optimum performance
from the AD8021 requires careful attention to PC board layout.
Particular care must be exercised to minimize lead lengths
between the ground leads of the bypass capacitors and between
the compensation capacitor and the negative supply. Otherwise,
lead inductance can influence the frequency response and even
cause high frequency oscillations. Use of a multilayer printed
circuit board, with an internal ground plane, reduces ground
noise and enables a compact component arrangement.

Due to the relatively high impedance of Pin 5 and low values of
the compensation capacitor, a guard ring is recommended. The
guard ring is simply a PC trace that encircles Pin 5 and is
connected to the output, Pin 6, which is at the same potential as
Pin 5. This serves two functions. It shields Pin 5 from any local
circuit noise generated by surrounding circuitry. It also
minimizes stray capacitance, which would tend to otherwise
reduce the bandwidth. An example of a guard ring layout is
shown in

Also shown in
immediately adjacent to the edge of the AD8021 package, spanning
Pin 4 and Pin 5. This capacitor must be a high quality surface­mount COG or NPO ceramic. The use of leaded capacitors is
not recommended. The high frequency bypass capacitor(s)
should be located immediately adjacent to the supplies,
Pin 4 and Pin 7.

To achieve the shortest possible lead length at the inverting
input, the feedback resistor R
spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of Resistor R
as possible to the return node of the negative supply bypass
capacitor connected to Pin 4.

Figure 62.

Figure 62, the compensation capacitor is located

LOGIC REFERENCE

–IN

+IN

–V

METAL

BYPASS

APACITO

is located beneath the board and

F

should be situated as close

G

(TOP VIEW)

1

2

3

4

S

GROUND

PLANE

COMPENSATION

CAPACITOR

DISABLE

8

+V

7

S

C

V

COMP

6

5

Figure 62. Recommended Location of

Critical Components and Guard Ring

OUT

GROUND

BYPASS
CAPACITOR

PLANE

01888-062

Rev. F | Page 21 of 28

AD8021

DRIVING 16-BIT ADCs

Low noise and adjustable compensation make the AD8021
especially suitable as a buffer/driver for high resolution ADCs.

As seen in
at frequencies between 100 kHz and 1 MHz. This is an
advantage for complex waveforms that contain high frequency
information, because the phase and gain integrity of the sampled
waveform can be preserved throughout the conversion process.
The increase in loop gain results in improved output regulation
and lower noise when the converter input changes state during
a sample. This advantage is particularly apparent when using
16-bit high resolution ADCs with high sampling rates.

Figure 63 shows a typical ADC driver configuration. The
AD8021 is in an inverting gain of −7.5, f
output voltage is 10 V p-p. The results are listed in

Table 7. Summary of ADC Driver Performance (fC = 65 kHz,
V

OUT

Parameter Measurement Unit

Second Harmonic Distortion −101.3 dBc
Third Harmonic Distortion −109.5 dBc
THD −100.0 dBc
SFDR +100.3 dBc

Figure 64 shows another ADC driver connection. The circuit
was tested with a noninverting gain of 10.1 and an output
voltage of approximately 20 V p-p for optimum resolution and
noise performance. No filtering was used. An FFT was
performed using Analog Devices evaluation software for the

AD7665 16-bit converter. The results are listed in Table 8.

Figure 19, the harmonic distortion is better than 90 dBc

is 65 kHz, and its

C

+12V

3

50Ω

590Ω

R

200Ω

+

AD8021

2

–

G

–12V

C

10pF

56pF

C

5

R

1.5kΩ

6

F

Figure 63. Inverting ADC Driver, Gain = −7.5, f

IN
HI

IN
HI

+5V

AD7665

570kSPS

C

= 10 V p-p)

+12V

50Ω

3

50Ω

Figure 64. Noninverting ADC Driver, Gain = 10, f

50Ω

82.5Ω

+

AD8021

2

–

–12V

R

G

6

5

C

C

R

F

750Ω

OPTIONAL C

IN

HI

F

IN

LO

Table 7.

= 65 kHz

+5V

AD7665

570kSPS

ADC

= 100 kHz

C

16 BITS

01888-063

16 BITS

01888-064

Table 8. Summary of ADC Driver Performance
(f

= 100 kHz, V

C

= 20 V p-p)

OUT

Parameter Measurement Unit

Second Harmonic Distortion −92.6 dBc
Third Harmonic Distortion −86.4 dBc
THD −84.4 dBc
SFDR +5.4 dBc

DIFFERENTIAL DRIVER

The AD8021 is uniquely suited as a low noise differential driver
for many ADCs, balanced lines, and other applications requiring
differential drive. If pairs of internally compensated op amps are
configured as inverter and follower, the noise gain of the inverter
is higher than that of the follower section, resulting in an
imbalance in the frequency response (see

A better solution takes advantage of the external compensation
feature of the AD8021. By reducing the C
inverter, its bandwidth can be increased to match that of the
follower, avoiding compromises in gain bandwidth and phase
delay. The inverting and noninverting bandwidths can be
closely matched using the compensation feature, thus
minimizing distortion.

Figure 65 illustrates an inverter-follower driver circuit operating
at a gain of 2, using individually compensated AD8021s. The
values of feedback and load resistors were selected to provide a
total load of less than 1 kΩ, and the equivalent resistances seen
at each op amp’s inputs were matched to minimize offset voltage
and drift.

Figure 67 is a plot of the resulting ac responses of

driver halves.

249Ω

3

232Ω

+

AD8021

2

–

–V

3

+

AD8021

2

–

–V

S

S

V

IN

49.9Ω

499Ω

332Ω

Figure 65. Differential Amplifier

G = +2

7pF

499Ω

G = –2

5pF

664Ω

Figure 66).

COMP

6

5

1kΩ

6

5

1kΩ

value of the

V

OUT1

V

OUT2

01888-065

Rev. F | Page 22 of 28

AD8021

12

9

6

3

0

–3

GAIN (dB)

–6

–9

–12

–15

–18

100k 1M 10M 100M 1G

FREQUENCY (Hz)

G = –2
G = +2

01888-066

Figure 66. AC Response of Two Identically Compensated High Speed Op

Amps Configured for a Gain of +2 and a Gain of −2

12

9

6

3

0

–3

GAIN (dB)

–6

–9

–12

–15

–18

100k 1M 10M 100M 1G

FREQUENCY (Hz)

G = ±2

01888-067

Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps

(

Figure 66) Configured for a Gain of +2 and a Gain of −2,

(Note the Close Gain Match)

USING THE AD8021 IN ACTIVE FILTERS

The low noise and high gain bandwidth of the AD8021 make it
an excellent choice in active filter circuits. Most active filter
literature provides resistor and capacitor values for various
filters but neglects the effect of the op amp’s finite bandwidth on
filter performance; ideal filter response with infinite loop gain is
implied. Unfortunately, real filters do not behave in this manner.
Instead, they exhibit finite limits of attenuation, depending on
the gain bandwidth of the active device. Good low-pass filter
performance requires an op amp with high gain bandwidth for
attenuation at high frequencies, and low noise and high dc gain
for low frequency, pass-band performance.

Figure 68 shows the schematic of a 2-pole, low-pass active filter
and lists typical component values for filters having a Bessel­type response with a gain of 2 and a gain of 5.
network analyzer plot of this filter’s performance.

Figure 69 is a

C1

+V

S

V

IN

R2R1

C2

R

G

Figure 68. Schematic of a Second-Order, Low-Pass Active Filter

AD8021

3

2

6

V

OUT

5

C

C

–V

S

R

F

01888-068

Table 9. Typical Component Values for Second-Order, Low­Pass Active Filter of

Gain R1

(Ω)

R2
(Ω)

Figure 68

RF
(Ω)

RG
(Ω)

C1
(nF)

C2
(nF)

CC
(pF)

2 71.5 215 499 499 10 10 7
5 44.2 365 365 90.9 10 10 2

50

40

30

20

10

0

GAIN (dB)

–10

–20

–30

–40

–50

1k 10k 100k 1M 10M

G = 2

FREQUENCY (Hz)

Figure 69. Frequency Response of the Filter Circuit of

G = 5

01888-069

Figure 68

for Two Different Gains

DRIVING CAPACITIVE LOADS

When the AD8021 drives a capacitive load, the high frequency
response can show excessive peaking before it rolls off. Two
techniques can be used to improve stability at high frequency
and reduce peaking. The first technique is to increase the
compensation capacitor, C
maintaining gain flatness at low frequencies. The second
technique is to add a resistor, R
pin of the AD8021 and the capacitive load, C
the response of the AD8021 when both C
reduce peaking. For a given C
determine the value of R
the frequency response. Note, however, that using R
the low frequency output by a factor of R

, which reduces the peaking while

C

, in series between the output

B

SNUB

. shows

Figure 70

L

and R

C

, Figure 71 can be used to

L

that maintains 2 dB of peaking in

B

SNUB

/(R

LOAD

SNUB

B are used to

SNUB

attenuates

SNUB

B + R

LOAD

).

Rev. F | Page 23 of 28

AD8021

18

16

14

49.9

12

10

8

GAIN (dB)

6

4

2

0

0.1 100010 100

499

+V

49.9

Ω

Ω

–V

Ω

Figure 70. Peaking vs. R

S

PR

5

S

C

C

Ω

499

1.0
FREQUENCY (MHz)

FET

OBE

R

SNUB

6

33pF

CC = 8pF;
R

and CC for CL = 33 pF

SNUB

1k

SNUB

R

L

Ω

= 17.4

Ω

CC = 7pF;
R

= 0

SNUB

CC = 8pF;
R

= 0

SNUB

Ω

Ω

01888-070

20

18

16

14

12

(Ω)

10

SNUB

R

8

6

4

2

0

0 5 10 20 25 30 35 40 45 5015

Figure 71. Relationship of R

CAPACITIVE LOAD (pF)

vs. CBL for 2 dB Peaking at a Gain of +2

SNUB

01888-071

Rev. F | Page 24 of 28

AD8021

OUTLINE DIMENSIONS

5.00 (0.1 968)

4.80 (0.1 890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 72. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

1

0.65 BSC

0.38

0.22

0.10

5.15

4.90

4.65

4

SEATING
PLANE

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

× 45°

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 73. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8021AR −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ
AD8021ARZ-REEL
AD8021ARZ-REEL7
AD8021ARM −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARMZ
AD8021ARMZ-REEL
AD8021ARMZ-REEL7

1

Z = Pb-free part, # denotes lead-free product may be top or bottom marked.

1

1

1

1

1

1

−40°C to +85°C 8-Lead SOIC R-8

−40°C to +85°C 8-Lead SOIC R-8

−40°C to +85°C 8-Lead SOIC R-8

−40°C to +85°C 8-Lead MSOP RM-8 HNA#

−40°C to +85°C 8-Lead MSOP RM-8 HNA#

−40°C to +85°C 8-Lead MSOP RM-8 HNA#

Rev. F | Page 25 of 28

AD8021

NOTES

Rev. F | Page 26 of 28

AD8021

NOTES

Rev. F | Page 27 of 28

AD8021

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01888-0-5/06(F)

Rev. F | Page 28 of 28