ANALOG DEVICES AD7994 Service Manual

4-Channel, 10- and 12-Bit ADCs with I2C-

V

V

V

www.BDTIC.com/ADI

Compatible Interface in 16-Lead TSSOP

FEATURES

10- and 12-bit ADC with fast conversion time: 2 µs typ
4 single-ended analog input channels
Specified for V
Low power consumption
Fast throughput rate: 188 kSPS
Temperature range:−40°C to +125°C

Sequencer operation
Automatic cycle interval mode

2

C®-compatible serial interface

I

2

C interface supports standard, fast, and high speed modes

I
Out-of-range indicator/alert function
Pin-selectable addressing via AS
Shutdown mode: 1 µA max
16-lead TSSOP package
See AD7998 and AD7992 for 8-channel and 2-channel

equivalent devices, respectively.

GENERAL DESCRIPTION

The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power,
successive approximation ADCs with an I
face. The parts operate from a single 2.7 V to 5.5 V power
supply and feature a 2 µs conversion time. The parts contain a
4-channel multiplexer and track-and-hold amplifier that can
handle input frequencies up to 11 MHz.

The AD7993/AD7994 provide a 2-wire serial interface that is
compatible with I
AD7993-0/AD7994-0 and AD7993-1/AD7994-1, and each
version allows for at least two different I
interface on the AD7993-0/AD7994-0 supports standard and

2

C interface modes. The I2C interface on the AD7993-1/

fast I
AD7994-1 supports standard, fast, and high speed I
modes.

The AD7993/AD7994 normally remain in a shutdown state
while not converting, and power up only for conversions. The
conversion process can be controlled using the

by a command mode where conversions occur across I
operations, or an automatic conversion interval mode selected
through software control.

The AD7993/AD7994 require an external reference that should
be applied to the REF
V

. This allows the widest dynamic input range to the ADC.

DD

of 2.7 V to 5.5 V

DD

2

C-compatible inter-

2

C interfaces. Each part comes in two versions,

2

C addresses. The I2C

2

C interface

CONVST

2

C write

pin and can be in the range of 1.2 V to

IN

pin,

AD7993/AD7994

FUNCTIONAL BLOCK DIAGRAM

T/H

LIMIT

LIMIT

AGND

REF

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

I2C INTERFACE

Figure 1.

IN

CONFIGURATION

CONVST

CONTROL

LOGIC

OSCILLATOR

CONVERSION

RESULT

REGISTER

REGISTER

ALERT STATUS

REGISTER

CYCLE TIMER

REGISTER

ALERT/
BUSY

SCL
SDA

03472-0-001

V

DD

AD7993/AD7994

VIN1

2

IN

I/P

MUX

3

IN

4

IN

DATA

LOW

REGISTER CH1–CH4

DATA

HIGH

REGISTER CH1–CH4

HYSTERESIS

REGISTER CH1–CH4

AS

AGND

On-chip limit registers can be programmed with high and low
limits for the conversion result, and an open-drain, out-of­range indicator output (ALERT) becomes active when the
programmed high or low limits are violated by the conversion
result. This output can be used as an interrupt.

PRODUCT HIGHLIGHTS

1. 2 µs conversion time with low power consumption.

2

2. I

C-compatible serial interface with pin-selectable
addresses. Two AD7993/AD7994 versions allow five
AD7993/AD7994 devices to be connected to the same
serial bus.

3. The parts feature automatic shutdown while not converting

to maximize power efficiency. Current consumption is
1 µA max when in shutdown mode.

4. Reference can be driven up to the power supply.

5. Out-of-range indicator that can be software disabled or

enabled.

6. One-shot and automatic conversion rates.

7. Registers can store minimum and maximum conversion

results.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7993/AD7994

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TABLE OF CONTENTS

AD7993 Specifications..................................................................... 3

AD7994 Specifications..................................................................... 5

I2C Timing Specifications................................................................ 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Pin Function Descriptions.................... 10

Serial Interface ................................................................................ 23

Serial Bus Address...................................................................... 23

Writing to the AD7993/AD7994 .................................................. 24

Writing to the Address Pointer Register for a Subsequent

Read.............................................................................................. 24

Writing a Single Byte of Data to the Alert Status Register or

Cycle Register.............................................................................. 24

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical C o n necti on D i a g ram ................................................... 16

Analog Input ............................................................................... 16

Internal Register Structure ............................................................ 18

Address Pointer Register ...........................................................18

Configuration Register .............................................................. 19

Conversion Result Register....................................................... 20

Limit Registers ............................................................................ 20

Alert Status Register................................................................... 21

Cycle Timer Register.................................................................. 22

Sample Delay and Bit Trial Delay............................................. 22

Writing Two Bytes of Data to a Limit or Hysteresis

Register ........................................................................................ 24

Reading Data from the AD7993/AD7994................................... 26

Alert/Busy Pin................................................................................. 27

SMBus Alert ................................................................................ 27

Busy .............................................................................................. 27

Placing the AD7993-1/AD7994-1 into High Speed Mode ... 27

The Address Select (AS) Pin..................................................... 27

Modes of Operation ....................................................................... 28

Mode 1—Using the

Mode 2—Command Mode....................................................... 29

Mode 3—Automatic Cycle Interval Mode.............................. 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

Related Parts in I2C-Compatible ADC Product Family........ 31

CONVST

Pin ........................................... 28

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7993/AD7994

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AD7993 SPECIFICATIONS

Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7993-0,
all specifications apply for f
T

= T

MIN

to T

MAX.

A

up to 400 kHz. For the AD7993-1, all specs apply for f

SCL

Table 1.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal-to-Noise + Distortion (SINAD)2 61 dB min
Total Harmonic Distortion (THD) 2 –75 dB max
Peak Harmonic or Spurious Noise (SFDR) 2 –76 dB max
Intermodulation Distortion (IMD)

2

Second-Order Terms –86 dB typ

Third-Order Terms –86 dB typ
Aperture Delay2 10 ns max
Aperture Jitter2 50 ps typ
Channel-to-Channel Isolation2 -90 dB typ FIN = 108 Hz, see the Terminology section
Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity
Differential Nonlinearity

1, 2

±0.5 LSB max

1, 2

±0.5 LSB max Guaranteed no missed codes to 10 bits

Offset Error2 ±1.5 LSB max
±2.5 LSB max Mode 2 (Command Mode)

Offset Error Match2 ±0.5 LSB max
Gain Error

2

±1.5 LSB max

Gain Error Match2 ±0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

IN

V
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to VDD V min/V max
DC Leakage Current ±1 µA max
Input Impedance 69 kΩ typ During a conversion

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V
Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD
Input Capacitance, C
Input Hysteresis, V

3

IN

0.1(VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted.

SCL

= 10 kHz sine wave for f

F

IN

SCL

to 3.4 MHz
FIN = 1 kHz sine wave for f

SCL

fa = 10.1 kHz, fb = 9.9 kHz for f

1.7 MHz to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f

400 kHz

Mode 1 (CONVST

Mode)

from 1.7 MHz

up to 400 kHz

from

SCL

up to

SCL

Rev. 0 | Page 3 of 32

AD7993/AD7994

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Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V
Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V
Input Leakage Current, IIN ±1 µA max VIN = 0 V or V
Input Capacitance, C

3

10 pF max

IN

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I
Floating-State Leakage Current ± 1 µA max
Floating-State Output Capacitance

3

Output Coding Straight (Natural) Binary

CONVERSION RATE See Modes of Operation section

Conversion Time 2 µs typ
Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f
21 kSPS typ f
121 kSPS typ f

Mode 2 5.5 kSPS typ f
22 kSPS typ f
147 kSPS typ f
POWER REQUIREMENTS

V

DD

I

DD

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V

Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f

Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

POWER DISSIPATION

Fully Operational
Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f
Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

1

Min/max ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.

Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

2

See the Terminology section.

3

Guaranteed by initial characterization.

DD

= 3 mA

SINK

= 6 mA

SINK

10 pF max

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz, 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max
Digital inputs = 0 V or V

DD

SCL

SCL

SCL

SCL

SCL

Mode 1

SCL

Mode 2

SCL

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 4 of 32

AD7993/AD7994

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AD7994 SPECIFICATIONS

Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V. For the AD7994-0,

all specifications apply for f

T

= T

MIN

to T

MAX.

A

up to 400 kHz. For the AD7994-1, all specs apply for f

SCL

Table 2.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal-to-Noise + Distortion (SINAD)2 70.5 dB min
Signal-to-Noise Ratio (SNR)

2

71 dB min
Total Harmonic Distortion (THD)2 –78 dB max
Peak Harmonic or Spurious Noise (SFDR)2 –79 dB max
Intermodulation Distortion (IMD)2

Second-Order Terms –90 dB typ

Third-Order Terms –90 dB typ
Aperture Delay2 10 ns max
Aperture Jitter2 50 ps typ
Channel-to-Channel Isolation2 -90 dB typ FIN = 108 Hz, see the Terminology section
Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity

1, 2

±1 LSB max

±0.2 LSB typ

Differential Nonlinearity

1, 2

+1/–0.9 LSB max Guaranteed no missed codes to 12 bits

±0.2 LSB typ

Offset Error2 ±4 LSB max
±6 LSB max Mode 2 (Command Mode)
Offset Error Match2 ±1 LSB max
Gain Error2 ±2 LSB max
Gain Error Match2 ±1 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

IN

V
DC Leakage Current ± 1 µA max
Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to V

DD

V min/V max
DC Leakage Current ± 1 µA max
Input Impedance 69 kΩ typ During a converison

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V
Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ± 1 µA max VIN = 0 V or V
Input Capacitance, C
Input Hysteresis, V

3

IN

0.1 (VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted.

SCL

= 10 kHz sine wave for f

F

IN

from 1.7 MHz to

SCL

3.4 MHz

FIN = 1 kHz sine wave for f

fa = 10.1 kHz, fb = 9.9 kHz for f

up to 400 kHz

SCL

SCL

to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f

Mode 1 (CONVST

Mode)

DD

SCL

from 1.7 MHz

up to 400 kHz

Rev. 0 | Page 5 of 32

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Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V
Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V
Input Leakage Current, IIN ±1 µA max VIN = 0 V or V
Input Capacitance, C

3

10 pF max

IN

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance3 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE See the Serial Interface section

Conversion Time 2 µs typ
Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f
21 kSPS typ f
121 kSPS typ f

Mode 2 5.5 kSPS typ f
22 kSPS typ f
147 kSPS typ f
POWER REQUIREMENTS

V

DD

I

DD

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V

Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f
Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f
Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f
Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

POWER DISSIPATION

Fully Operational
Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

1

Min/max AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.

Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

2

See the section. Terminology

3

Guaranteed by initial characterization.

DD

= 3 mA

SINK

= 6 mA

SINK

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz , 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max
Digital inputs = 0 V or V

DD

SCL

SCL

SCL

SCL

SCL

Mode 1

SCL

Mode 2

SCL

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 6 of 32

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I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line.
tr and tf measured between 0.3 V

High speed mode timing specifications apply to the AD7993-1/AD7994-1 only. Standard and fast mode timing specifications apply to

th the AD7993-0/AD7994-0 and the AD7993-1/AD7994-1. See Figure 2.

bo

and 0.7 VDD.

DD

Unless otherwise noted, V

= 2.7 V to 5.5 V; REFIN = 2.5 V; TA =T

DD

MIN

to T

MAX

.

Table 3.

AD7993/AD7994
Limit at T

MIN

, T

MAX

Parameter Conditions Min Max Unit Description

f

SCL

Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode
C
C
t1 Standard mode 4 µs t

= 100 pF max 3.4 MHz

B

= 400 pF max 1.7 MHz

B

, SCL high time

HIGH

Fast mode 0.6 µs
High speed mode
C
C
t2 Standard mode 4.7 µs t

= 100 pF max 60 ns

B

= 400 pF max 120 ns

B

, SCL low time

LOW

Fast mode 1.3 µs
High speed mode
C
C
t3 Standard mode 250 ns t

= 100 pF max 160 ns

B

= 400 pF max 320 ns

B

, data setup time

SU;DAT

Fast mode 100 ns
High speed mode 10 ns

1

t

Standard mode 0 3.45 µs t

4

, data hold time

HD;DAT

Fast mode 0 0.9 µs
High speed mode
C
C
t5 Standard mode 4.7 µs t

= 100 pF max 0 702 ns

B

= 400 pF max 0 150 ns

B

, setup time for a repeated start condition

SU;STA

Fast mode 0.6 µs
High speed mode 160 ns
t6 Standard mode 4 µs t

, hold time (repeated) start condition

HD;STA

Fast mode 0.6 µs
High speed mode 160 ns
t7 Standard mode 4.7 µs

, bus free time between a stop and a start

t

BUF

condition
Fast mode 1.3 µs
t8 Standard mode 4 µs t

, setup time for stop condition

SU;STO

Fast mode 0.6 µs
High speed mode 160 ns
t9 Standard mode 1000 ns t

, rise time of SDA signal

RDA

Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
C

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

Rev. 0 | Page 7 of 32

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AD7993/AD7994

Parameter Conditions Min Max Unit Description

t10 Standard mode 300 ns t
Fast mode 20 + 0.1 CB300 ns
High speed mode
C
C

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

t11 Standard mode 1000 ns t
Fast mode 20 + 0.1 CB300 ns
High speed mode
C
C
t

Standard mode 1000 ns

11A

= 100 pF max 10 40 ns

B

= 400 pF max 20 80 ns

B

Fast mode 20 + 0.1 CB300 ns
High speed mode
C
C

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

t12 Standard mode 300 ns t
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
C

2

t

SP

= 100 pF max 10 40 ns

B

= 400 pF max 20 80 ns

B

Fast mode 0 50 ns Pulse width of suppressed spike
High speed mode 0 10 ns
t

POWER-UP

1 typ µs Power-up time

1

A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

2

For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.

t

11

t

2

Limit at T

t

12

MIN

, T

MAX

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

, rise time of SCL signal after a repeated start

t

RCL1

condition and after an acknowledge bit

, fall time of SCL signal

FCL

t

6

SCL

SDA

t

7

P

S = START CONDITION
P = STOP CONDITION

t

6

S

t

4

Figure 2. Two-Wire Serial Interface Timing Diagram

t

3

t

1

t

5

t

10

S

Rev. 0 | Page 8 of 32

t

8

t

9

P

03472-0-002

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to 7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range

Commercial (B Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°
Junction Temperature 150°C
20-Lead TSSOP

θJA Thermal Impedance 150.4°C/W

θJC Thermal Impedance 27.6°C/W
Pb/SN Temperature, Soldering

Reflow (10 s to 30 s) 240(+0/-5)°C
Pb-Free Temperature, Soldering

Reflow 260(+0)°C
ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 9 of 32

AD7993/AD7994

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A

A

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PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

1

GND
GND

2

DD

IN

AD7993/

3

AD7994

4

TOP VIEW

(Not to Scale)

5
6
7
8

GND
GND

V

REF

VIN1
VIN3

Figure 3. 16-Lead TSSOP Pin Configuration

16

AGND
SCL

15

SDA

14

ALERT/BUSY

13

CONVST

12

AS

11

VIN2

10

V

4

9

IN

03472-0-003

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1, 2, 3, 4, 16 AGND

Analog Ground. Ground reference point for all circuitry on the AD7993/AD7994. All analog input signals

should be referred to this AGND voltage.
5 VDD Power Supply Input. The VDD range for the AD7993/AD7994 is from 2.7 V to 5.5 V.
6 REFIN

Voltage Reference Input. The external reference for the AD7993/AD7994 should be applied to this input pin.

The voltage range for the external reference is 1.2 V to V

between REF

and AGND. See Figure 22.

IN

. A 0.1 µF and 1 µF capacitor should be placed

DD

7 VIN1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN.
8 VIN3 Analog Input 3. Single-ended analog input channel. The input range is 0 V to REFIN.
9 VIN4 Analog Input 4. Single-ended analog input channel. The input range is 0 V to REFIN.
10 VIN2 Analog Input 2. Single-ended analog input channel. The input range is 0 V to REFIN.
11 AS

Logic Input. Address select input that selects one of three I

2

C addresses for the AD7993/AD7994, as shown in

Table 6. The device address depends on the voltage applied to this pin.
12

CONVST

Logic Input Signal/Convert Start Signal. This is an edge-triggered logic input. The rising edge of this signal

powers up the part. The power-up time for the part is 1 µs. The falling edge of CONVST

places the track/hold
into hold mode and initiates a conversion. A power-up time of at least 1 µs must be allowed for the CONVST
high pulse; otherwise, the conversion result is invalid (see the Modes of Operation section).

13 ALERT/BUSY

Digital Output, Selectable as an ALERT or BUSY Output Function. When configured as an ALERT, this pin acts
as an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATA
or DATA

register values. See the Limit Registers section. When configured as a BUSY output, this pin

LOW

becomes active when a conversion is in progress. Open-drain output.

14 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required.
15 SCL Digital Input. Serial bus clock. External pull-up resistor required.

Table 6. I2C Address Selection

Part Number AS Pin I2C Address

AD7993-0 GND 010 0001
AD7993-0 VDD 010 0010
AD7993-1 GND 010 0011
AD7993-1 VDD 010 0100
AD7993-x

1

Float 010 0000
AD7994-0 GND 010 0001
AD7994-0 VDD 010 0010
AD7994-1 GND 010 0011
AD7994-1 VDD 010 0100
AD7994-x1 Float 010 0000

1

If the AS pin is left floating on any of the AD7993/AD7994 parts, the device address is 010 0000.

HIGH

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