Datasheet AD7994 Datasheet (ANALOG DEVICES)

4-Channel, 10- and 12-Bit ADCs with I2C-

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Compatible Interface in 16-Lead TSSOP

FEATURES

10- and 12-bit ADC with fast conversion time: 2 µs typ 4 single-ended analog input channels Specified for V Low power consumption Fast throughput rate: 188 kSPS Temperature range:−40°C to +125°C

Sequencer operation Automatic cycle interval mode

C®-compatible serial interface

C interface supports standard, fast, and high speed modes

I Out-of-range indicator/alert function Pin-selectable addressing via AS Shutdown mode: 1 µA max 16-lead TSSOP package See AD7998 and AD7992 for 8-channel and 2-channel

equivalent devices, respectively.

GENERAL DESCRIPTION

The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power, successive approximation ADCs with an I face. The parts operate from a single 2.7 V to 5.5 V power supply and feature a 2 µs conversion time. The parts contain a 4-channel multiplexer and track-and-hold amplifier that can handle input frequencies up to 11 MHz.

The AD7993/AD7994 provide a 2-wire serial interface that is compatible with I AD7993-0/AD7994-0 and AD7993-1/AD7994-1, and each version allows for at least two different I interface on the AD7993-0/AD7994-0 supports standard and

C interface modes. The I2C interface on the AD7993-1/

fast I AD7994-1 supports standard, fast, and high speed I modes.

The AD7993/AD7994 normally remain in a shutdown state while not converting, and power up only for conversions. The conversion process can be controlled using the

by a command mode where conversions occur across I operations, or an automatic conversion interval mode selected through software control.

The AD7993/AD7994 require an external reference that should be applied to the REF V

. This allows the widest dynamic input range to the ADC.

of 2.7 V to 5.5 V

C-compatible inter-

C interfaces. Each part comes in two versions,

C addresses. The I2C

C interface

CONVST

C write

pin and can be in the range of 1.2 V to

pin,

AD7993/AD7994

FUNCTIONAL BLOCK DIAGRAM

T/H

LIMIT

AGND

REF

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

I2C INTERFACE

Figure 1.

CONFIGURATION

CONVST

CONTROL

LOGIC

OSCILLATOR

CONVERSION

RESULT

ALERT STATUS

CYCLE TIMER

ALERT/ BUSY

SCL SDA

03472-0-001

AD7993/AD7994

VIN1

I/P

MUX

DATA

LOW

DATA

HIGH

HYSTERESIS

AGND

On-chip limit registers can be programmed with high and low limits for the conversion result, and an open-drain, out-ofrange indicator output (ALERT) becomes active when the programmed high or low limits are violated by the conversion result. This output can be used as an interrupt.

PRODUCT HIGHLIGHTS

1. 2 µs conversion time with low power consumption.

2. I

C-compatible serial interface with pin-selectable addresses. Two AD7993/AD7994 versions allow five AD7993/AD7994 devices to be connected to the same serial bus.

3. The parts feature automatic shutdown while not converting

to maximize power efficiency. Current consumption is 1 µA max when in shutdown mode.

4. Reference can be driven up to the power supply.

5. Out-of-range indicator that can be software disabled or

enabled.

6. One-shot and automatic conversion rates.

7. Registers can store minimum and maximum conversion

results.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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TABLE OF CONTENTS

AD7993 Specifications..................................................................... 3

AD7994 Specifications..................................................................... 5

I2C Timing Specifications................................................................ 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Pin Function Descriptions.................... 10

Serial Interface ................................................................................ 23

Serial Bus Address...................................................................... 23

Writing to the AD7993/AD7994 .................................................. 24

Writing to the Address Pointer Register for a Subsequent

Read.............................................................................................. 24

Writing a Single Byte of Data to the Alert Status Register or

Cycle Register.............................................................................. 24

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical C o n necti on D i a g ram ................................................... 16

Analog Input ............................................................................... 16

Internal Register Structure ............................................................ 18

Address Pointer Register ...........................................................18

Configuration Register .............................................................. 19

Conversion Result Register....................................................... 20

Limit Registers ............................................................................ 20

Alert Status Register................................................................... 21

Cycle Timer Register.................................................................. 22

Sample Delay and Bit Trial Delay............................................. 22

Writing Two Bytes of Data to a Limit or Hysteresis

Reading Data from the AD7993/AD7994................................... 26

Alert/Busy Pin................................................................................. 27

SMBus Alert ................................................................................ 27

Busy .............................................................................................. 27

Placing the AD7993-1/AD7994-1 into High Speed Mode ... 27

The Address Select (AS) Pin..................................................... 27

Modes of Operation ....................................................................... 28

Mode 1—Using the

Mode 2—Command Mode....................................................... 29

Mode 3—Automatic Cycle Interval Mode.............................. 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

Related Parts in I2C-Compatible ADC Product Family........ 31

CONVST

Pin ........................................... 28

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

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AD7993 SPECIFICATIONS

Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7993-0, all specifications apply for f T

= T

MIN

to T

MAX.

up to 400 kHz. For the AD7993-1, all specs apply for f

SCL

Table 1.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal-to-Noise + Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD) 2 –75 dB max Peak Harmonic or Spurious Noise (SFDR) 2 –76 dB max Intermodulation Distortion (IMD)

Second-Order Terms –86 dB typ

Third-Order Terms –86 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 -90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB DC ACCURACY

Resolution 10 Bits Integral Nonlinearity Differential Nonlinearity

1, 2

±0.5 LSB max

1, 2

±0.5 LSB max Guaranteed no missed codes to 10 bits

Offset Error2 ±1.5 LSB max ±2.5 LSB max Mode 2 (Command Mode)

Offset Error Match2 ±0.5 LSB max Gain Error

±1.5 LSB max

Gain Error Match2 ±0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

V DC Leakage Current ±1 µA max Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ±1 µA max Input Impedance 69 kΩ typ During a conversion

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

0.1(VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted.

SCL

= 10 kHz sine wave for f

SCL

to 3.4 MHz FIN = 1 kHz sine wave for f

SCL

fa = 10.1 kHz, fb = 9.9 kHz for f

1.7 MHz to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f

400 kHz

Mode 1 (CONVST

Mode)

from 1.7 MHz

up to 400 kHz

from

SCL

up to

SCL

Rev. 0 | Page 3 of 32

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Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I Floating-State Leakage Current ± 1 µA max Floating-State Output Capacitance

Output Coding Straight (Natural) Binary

CONVERSION RATE See Modes of Operation section

Conversion Time 2 µs typ Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f 21 kSPS typ f 121 kSPS typ f

Mode 2 5.5 kSPS typ f 22 kSPS typ f 147 kSPS typ f POWER REQUIREMENTS

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V

Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f

Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

POWER DISSIPATION

Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

Min/max ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.

Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

See the Terminology section.

Guaranteed by initial characterization.

= 3 mA

SINK

= 6 mA

SINK

10 pF max

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz, 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max Digital inputs = 0 V or V

SCL

Mode 1

SCL

Mode 2

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 4 of 32

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AD7994 SPECIFICATIONS

Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V. For the AD7994-0,

all specifications apply for f

= T

MIN

to T

MAX.

up to 400 kHz. For the AD7994-1, all specs apply for f

SCL

Table 2.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal-to-Noise + Distortion (SINAD)2 70.5 dB min Signal-to-Noise Ratio (SNR)

71 dB min Total Harmonic Distortion (THD)2 –78 dB max Peak Harmonic or Spurious Noise (SFDR)2 –79 dB max Intermodulation Distortion (IMD)2

Second-Order Terms –90 dB typ

Third-Order Terms –90 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 -90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB DC ACCURACY

Resolution 12 Bits Integral Nonlinearity

1, 2

±1 LSB max

±0.2 LSB typ

Differential Nonlinearity

1, 2

+1/–0.9 LSB max Guaranteed no missed codes to 12 bits

±0.2 LSB typ

Offset Error2 ±4 LSB max ±6 LSB max Mode 2 (Command Mode) Offset Error Match2 ±1 LSB max Gain Error2 ±2 LSB max Gain Error Match2 ±1 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

V DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to V

V min/V max DC Leakage Current ± 1 µA max Input Impedance 69 kΩ typ During a converison

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ± 1 µA max VIN = 0 V or V Input Capacitance, C Input Hysteresis, V

0.1 (VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted.

SCL

= 10 kHz sine wave for f

from 1.7 MHz to

SCL

3.4 MHz

FIN = 1 kHz sine wave for f

fa = 10.1 kHz, fb = 9.9 kHz for f

up to 400 kHz

SCL

to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f

Mode 1 (CONVST

Mode)

SCL

from 1.7 MHz

up to 400 kHz

Rev. 0 | Page 5 of 32

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Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE See the Serial Interface section

Conversion Time 2 µs typ Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f 21 kSPS typ f 121 kSPS typ f

Mode 2 5.5 kSPS typ f 22 kSPS typ f 147 kSPS typ f POWER REQUIREMENTS

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V

Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

POWER DISSIPATION

Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

Min/max AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.

Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

See the section. Terminology

Guaranteed by initial characterization.

= 3 mA

SINK

= 6 mA

SINK

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz , 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max Digital inputs = 0 V or V

SCL

Mode 1

SCL

Mode 2

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 6 of 32

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I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and tf measured between 0.3 V

High speed mode timing specifications apply to the AD7993-1/AD7994-1 only. Standard and fast mode timing specifications apply to

th the AD7993-0/AD7994-0 and the AD7993-1/AD7994-1. See Figure 2.

and 0.7 VDD.

Unless otherwise noted, V

= 2.7 V to 5.5 V; REFIN = 2.5 V; TA =T

MIN

to T

MAX

Table 3.

AD7993/AD7994 Limit at T

MIN

, T

MAX

Parameter Conditions Min Max Unit Description

SCL

Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode C C t1 Standard mode 4 µs t

= 100 pF max 3.4 MHz

= 400 pF max 1.7 MHz

, SCL high time

HIGH

Fast mode 0.6 µs High speed mode C C t2 Standard mode 4.7 µs t

= 100 pF max 60 ns

= 400 pF max 120 ns

, SCL low time

LOW

Fast mode 1.3 µs High speed mode C C t3 Standard mode 250 ns t

= 100 pF max 160 ns

= 400 pF max 320 ns

, data setup time

SU;DAT

Fast mode 100 ns High speed mode 10 ns

Standard mode 0 3.45 µs t

, data hold time

HD;DAT

Fast mode 0 0.9 µs High speed mode C C t5 Standard mode 4.7 µs t

= 100 pF max 0 702 ns

= 400 pF max 0 150 ns

, setup time for a repeated start condition

SU;STA

Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs t

, hold time (repeated) start condition

HD;STA

Fast mode 0.6 µs High speed mode 160 ns t7 Standard mode 4.7 µs

, bus free time between a stop and a start

BUF

condition Fast mode 1.3 µs t8 Standard mode 4 µs t

, setup time for stop condition

SU;STO

Fast mode 0.6 µs High speed mode 160 ns t9 Standard mode 1000 ns t

, rise time of SDA signal

RDA

Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

Rev. 0 | Page 7 of 32

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AD7993/AD7994

Parameter Conditions Min Max Unit Description

t10 Standard mode 300 ns t Fast mode 20 + 0.1 CB300 ns High speed mode C C

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

t11 Standard mode 1000 ns t Fast mode 20 + 0.1 CB300 ns High speed mode C C t

Standard mode 1000 ns

11A

= 100 pF max 10 40 ns

= 400 pF max 20 80 ns

Fast mode 20 + 0.1 CB300 ns High speed mode C C

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

t12 Standard mode 300 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF max 10 40 ns

= 400 pF max 20 80 ns

Fast mode 0 50 ns Pulse width of suppressed spike High speed mode 0 10 ns t

POWER-UP

1 typ µs Power-up time

A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.

Limit at T

MIN

, T

MAX

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

, rise time of SCL signal after a repeated start

RCL1

condition and after an acknowledge bit

, fall time of SCL signal

FCL

SCL

SDA

S = START CONDITION P = STOP CONDITION

Figure 2. Two-Wire Serial Interface Timing Diagram

Rev. 0 | Page 8 of 32

03472-0-002

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to 7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1±10 mA Operating Temperature Range

Commercial (B Version) −40°C to +125°C

Storage Temperature Range −65°C to +150° Junction Temperature 150°C 20-Lead TSSOP

θJA Thermal Impedance 150.4°C/W

θJC Thermal Impedance 27.6°C/W Pb/SN Temperature, Soldering

Reflow (10 s to 30 s) 240(+0/-5)°C Pb-Free Temperature, Soldering

Reflow 260(+0)°C ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 32

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PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

GND GND

AD7993/

AD7994

TOP VIEW

(Not to Scale)

5 6 7 8

GND GND

REF

VIN1 VIN3

Figure 3. 16-Lead TSSOP Pin Configuration

AGND SCL

SDA

ALERT/BUSY

CONVST

VIN2

03472-0-003

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1, 2, 3, 4, 16 AGND

Analog Ground. Ground reference point for all circuitry on the AD7993/AD7994. All analog input signals

should be referred to this AGND voltage. 5 VDD Power Supply Input. The VDD range for the AD7993/AD7994 is from 2.7 V to 5.5 V. 6 REFIN

Voltage Reference Input. The external reference for the AD7993/AD7994 should be applied to this input pin.

The voltage range for the external reference is 1.2 V to V

between REF

and AGND. See Figure 22.

. A 0.1 µF and 1 µF capacitor should be placed

7 VIN1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN. 8 VIN3 Analog Input 3. Single-ended analog input channel. The input range is 0 V to REFIN. 9 VIN4 Analog Input 4. Single-ended analog input channel. The input range is 0 V to REFIN. 10 VIN2 Analog Input 2. Single-ended analog input channel. The input range is 0 V to REFIN. 11 AS

Logic Input. Address select input that selects one of three I

C addresses for the AD7993/AD7994, as shown in

Table 6. The device address depends on the voltage applied to this pin. 12

CONVST

Logic Input Signal/Convert Start Signal. This is an edge-triggered logic input. The rising edge of this signal

powers up the part. The power-up time for the part is 1 µs. The falling edge of CONVST

places the track/hold into hold mode and initiates a conversion. A power-up time of at least 1 µs must be allowed for the CONVST high pulse; otherwise, the conversion result is invalid (see the Modes of Operation section).

13 ALERT/BUSY

Digital Output, Selectable as an ALERT or BUSY Output Function. When configured as an ALERT, this pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATA or DATA

LOW

becomes active when a conversion is in progress. Open-drain output.

14 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 15 SCL Digital Input. Serial bus clock. External pull-up resistor required.

Table 6. I2C Address Selection

Part Number AS Pin I2C Address

AD7993-0 GND 010 0001 AD7993-0 VDD 010 0010 AD7993-1 GND 010 0011 AD7993-1 VDD 010 0100 AD7993-x

Float 010 0000 AD7994-0 GND 010 0001 AD7994-0 VDD 010 0010 AD7994-1 GND 010 0011 AD7994-1 VDD 010 0100 AD7994-x1 Float 010 0000

If the AS pin is left floating on any of the AD7993/AD7994 parts, the device address is 010 0000.

HIGH

Rev. 0 | Page 10 of 32

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TERMINOLOGY

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise and distortion ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For the AD7993/AD7994, it is defined as

22222

65432

VVVVV

THD

log20)dB(

++++

Channel-to-Channel Isolation

A measure of the level of crosstalk between channels, taken by applying a full-scale sine wave signal to the unselected input channels, and determining how much the 108 Hz signal is attenuated in the selected channel. The sine wave signal applied to the unselected channels is then varied from 1 kHz up to 2 MHz, each time determining how much the 108 Hz signal in the selected channel is attenuated. This figure represents the worst-case level across all channels.

Aperture Delay

The measured interval between the sampling clock’s leading edge and the point at which the ADC takes the sample.

Aperture Jitter

The sample-to-sample variation in the effective point in time at which the sample is taken.

Full-Power Bandwidth

The input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

where V

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through

sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n equal zero. For example, second-order terms include (fa + fb) and (fa − fb), while third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb).

The AD7993/AD7994 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second and third-order terms are specified separately. The calculation of intermodulation distortion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB.

Power Supply Rejection Ratio (PSRR)

The ratio of the power in the ADC output at the full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V

PSRR (dB) = 10 log (Pf/Pf

where Pf is the power at frequency f in the ADC output; Pf the power at frequency f

supply of frequency fS:

)

coupled onto the ADC VDD supply.

Integral Nonlinearity

The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to (00…001) from the ideal—that is, AGND + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to (111…111) from the ideal (that is, REF

− 1 LSB) after the

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Rev. 0 | Page 11 of 32

AD7993/AD7994

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

–20

–40

–60

SINAD (dB)

–80

FS = 121kSPS FSCL = 3.4MHz FIN = 10kHz SNR = 71.84dB SINAD = 71.68dB THD = 86.18dB SFDR = –88.70dB

SINAD (dB)

VDD = 4.5V

VDD = 3V

VDD = 3.3V

VDD = 5.5V

VDD = 5V

VDD = 2.7V

–100

–120

20 40060

FREQUENCY (kHz)

Figure 4. AD7994 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

FS = 121kSPS

–10

–30

–50

SINAD (dB)

–70

–90

–110

10 40060

20 30 50

FREQUENCY (kHz)

FSCL = 3.4MHz FIN = 10kHz SINAD = 61.63dB THD = 91.82dB SFDR = –94.95dB

Figure 5. AD7993 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

100

VDD = 3V

PSRR (dB)

10 1000

VDD = 5V

VDD = 3V/5V 200mV p-p SINE WAVE ON V

2nF CAPACITOR ON V

100

SUPPLY RIPPLE FREQUENCY(kHz)

Figure 6. PSRR vs. Supply Ripple Frequency

03473-0-004

1 1000

FREQUENCY(kHz)

10010

03473-0-007

Figure 7. AD7994 SINAD vs. Analog Input Frequency for

Various Supply Voltages, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

03473-0-005

Figure 8. AD7994 Typical INL, V

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4



03473-0-006

–0.6

–0.8

–1.0

20001500500 10000 2500 3000 3500 4000 CODE

= 5.5 V, Mode 1, 3.4 MHz f

20001500500 10000 2500 3000 3500 4000 CODE

Figure 9. AD7994 Typical DNL, VDD = 5.5 V, Mode 1, 3.4 MHz f

, 136 kSPS

SCL

, 121 kSPS

SCL

, 121 kSPS

SCL

03473-0-008

03473-0-009

Rev. 0 | Page 12 of 32

AD7993/AD7994

www.BDTIC.com/ADI

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

Figure 10. Typical INL, VDD = 2.7 V, Mode 1, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

20001500500 10000 2500 3000 3500 4000 CODE

SCL

Figure 11. AD7994 Typical DNL, VDD = 2.7 V, Mode 1, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

-0.6

–0.8

–1.0

1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V)

POSITIVE INL

NEGATIVE INL

Figure 12. AD7994 Change in INL vs. Reference Voltage VDD = 5 V,

Mode 1, 121 kSPS

, 121 kSPS

SCL

03473-0-010

03473-0-011

03473-0-012

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

-0.6

–0.8

–1.0

1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V)

POSITIVE DNL

NEGATIVE DNL

Figure 13. AD7994 Change in DNL vs. Reference Voltage V

Mode 1, 121 kSPS

0.0007

0.0006

0.0005

0.0004

0.0003

0.0002

SUPPLY CURRENT (mA)

0.0001

2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)

Figure 14. AD7994 Shutdown Current vs. Supply Voltage,

–40°C, +25°C, and +85°C

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

100 600 1100 1600 2100 2600 3100

SCL FREQUENCY (kHz)

Figure 15. AD7994 Average Supply Current vs. I2C Bus Rate for

= 3 V and 5 V

–40°C

+25°C

+85°C

MODE 2 V

= 5V

MODE 2 V

= 3V

MODE 1 V

= 5V

MODE 1 V

= 3V

= 5 V,

03473-0-013

03472-0-014

03473-0-015

Rev. 0 | Page 13 of 32

AD7993/AD7994

www.BDTIC.com/ADI

2.0 TEMPERATURE = +85°C

1.8

TEMPERATURE = +25°C TEMPERATURE = –40°C

1.6

TEMPERATURE = +85°C TEMPERATURE = +25°C

1.4

TEMPERATURE = –40°C

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)

Figure 16. AD7994 Average Supply Current vs. Supply Voltage

for Various Temperatures

MODE 2 - 147kSPS

MODE 1 - 121kSPS

03473-0-016

12.0

11.8

11.6

11.4

11.2

ENOB (BITS)

11.0

10.8

10.6

10.4

1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000

ENOB VDD = 3V

SINAD VDD = 3V

REFERENCE VOLTAGE (V)

Figure 17. AD7994 SINAD/ENOB vs. Reference Voltage,

Mode 1, 121 kSPS

ENOB VDD = 5V

SINAD VDD = 5V

SINAD (dB)

03473-0-017

Rev. 0 | Page 14 of 32

AD7993/AD7994

www.BDTIC.com/ADI

CIRCUIT INFORMATION

The AD7993/AD7994 are low power, 10- and 12-bit, singlesupply, 4-channel A/D converters, respectively. The parts can be operated from a 2.7 V to 5.5 V supply.

The AD7993/AD7994 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an A/D converter, an

on-chip oscillator, internal data registers, and an I

C-compatible serial interface, all housed in a 16-lead TSSOP package that offers the user considerable space-saving advantages over alternative solutions. The AD7993/AD7994 require an external reference in the range of 1.2 V to V

The AD7993/AD7994 normally remain in a power-down state while not converting. When supplies are first applied, the parts come up in a power-down state. Power-up is initiated prior to a conversion, and the device returns to shutdown upon completion of the conversion. Conversions can be initiated on the AD7993/AD7994 by pulsing the

CONVST

signal, using an

automatic cycle interval mode, or using a command mode where wake-up and a conversion occurs during a write address function (see the Modes of Operation section). When the conversion is complete, the AD7993/AD7994 again enter shutdown mode. This automatic shut-down feature allows power saving between conversions. Any read or write operations across the

C interface can occur while the devices are in shutdown.

CONVERTER OPERATION

The AD7993/AD7994 are successive approximation analog-todigital converters based around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of an ADC during the acquisition and conversion phase, respectively. Figure 18 shows an ADC during the acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on V

AGND

SW1

SW2

Figure 18. ADC Acquisition Phase

COMPARATOR

CAPACITIVE

DAC

CONTROL

LOGIC

03472-0-018

When the ADC starts a conversion, as shown in Figure 19, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The input is disconnected once the conversion begins. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 20 shows the ADC transfer function.

CAPACITIVE

DAC

GND

SW1

SW2

Figure 19. ADC Conversion Phase

COMPARATOR

CONTROL

LOGIC

ADC Transfer Function

The output coding of the AD7993/AD7994 is straight binary. The designed code transitions occur at successive integer LSB values—that is, 1 LSB, 2 LSB, and so on. The LSB size is

/1024 for the AD7993 and REFIN/4096 for the AD7994.

REF

Figure 20 shows the ideal transfer characteristic for the AD7993/AD7994.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000 AGND + 1LSB

Figure 20. AD7993/AD7994 Transfer Characteristic

AD7993 1LSB = REF AD7994 1LSB = REF

ANALOG INPUT

0V TO REF

+REFIN– 1LSB

IN IN

/1024 /4096

03472-0-020

03472-0-019

Rev. 0 | Page 15 of 32

AD7993/AD7994

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TYPICAL CONNECTION DIAGRAM

Figure 22 shows the typical connection diagram for the AD7993/ AD7994. In Figure 22 the address select pin (AS) is tied to V however, AS can also be tied to AGND or left floating, allowing the user to select up to five AD7993/AD7994 devices on the same serial bus. An external reference must be applied to the AD7993/AD7994. This reference can be in the range of 1.2 V to

. A precision reference like the REF 19x family, AD780,

ADR03, or ADR381 can be used to supply the reference voltage to the ADC.

SDA and SCL form the 2-wire I

C/SMBus-compatible interface. External pull-up resisters are required for both SDA and SCL lines.

The AD7993-0/AD7994-0 support standard and fast I interface modes. The AD7993-1/AD7994-1 support standard,

fast, and high speed I

C interface modes. Therefore, if operating the AD7993/AD7994 in either standard or fast mode, up to five AD7993/AD7994 devices can be connected to the bus as noted:

3 × AD7993-0/AD7994-0 and 2 × AD7993-1/ AD7994-1 or 3 × AD7993-1/AD7994-1 and 2 × AD7994-0/AD7993-0

In high speed mode, up to three AD7993-1/AD7994-1 devices can be connected to the bus.

Wake-up from shutdown prior to a conversion is approximately 1 µs, and conversion time is approximately 2 µs. The AD7993/ AD7994 enter shutdown mode again after each conversion, which is useful in applications where power consumption is a concern.

ANALOG INPUT

Figure 21 shows an equivalent circuit of the AD7993/AD7994’s

;

analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part.

4pF

Figure 21. Equivalent Analog Input Circuit

CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED

30pF

03472-0-022

Capacitor C1 in Figure 21 is typically about 4 pF and primarily can be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance (R (track-and-hold switch), and also includes the R

) of a switch

of the input

multiplexer. The total resistor is typically about 400 Ω. C2, the ADC sampling capacitor, has a typical capacitance of 30 pF.

5V SUPPLY

2-WIRE SERIAL INTERFACE

µC/µP

03472-0-021

REF 19x

0V to REF

0.1µF

INPUT

0.1µF10µF

VIN1

REF

1µF

Figure 22. AD7993/AD7994 Typical Connection Diagram

AD7993/

AD7994

GND

Rev. 0 | Page 16 of 32

SDA

SCL

ALERT

CONVST

RPRPR

AD7993/AD7994

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For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. THD increases as the source impedance increases, and performance degrades. Figure 23 shows the THD vs. the analog input signal frequency when using supply voltages of 3 V ± 10% and 5 V ± 10%. Figure 24 shows the THD vs. the analog input signal frequency for different source impedances.

–40

–50

–60

–70

THD (dB)

–100

VDD = 2.7V

–80

–90

10 1000

INPUT FREQUENCY(kHz)

Figure 23. THD vs. Analog Input Frequency for Various

Supply Voltages, FS = 136 kSPS, Mode 1

–40

–50

–60

VDD = 3V

VDD = 4.5V

VDD = 5V

100

RIN = 1000

VDD = 3.3V

VDD = 5.5V

Ω

VDD = 5V

03472-0-023

–70

THD (dB)

–80

–90

–100

10 1000

INPUT FREQUENCY(kHz)

Figure 24. THD vs. Analog Input Frequency for Various

Source Impedances for V

RIN = 100

Ω

RIN = 50

RIN = 10

Ω

100

= 5 V, 136 kSPS, Mode 1

Ω

03472-0-024

Rev. 0 | Page 17 of 32

AD7993/AD7994

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INTERNAL REGISTER STRUCTURE

The AD7993/AD7994 contain 17 internal registers (see Figure 25) that are used to store conversion results, high and low conversion limits, and information to configure and control the device. Sixteen are data registers and one is an address pointer register.

Each data register has an address that the address pointer register points to when communicating with it. The conversion result register is the only data register that is read only.

CONVERSION

RESULT REGISTER

ALERT STATUS

CONFIGURATION

CYCLE TIMER

DATA

LOW

DATA

HIGH

ADDRESS

POINTER

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

D A

ADDRESS POINTER REGISTER

Because it is the register to which the first data byte of every write operation is written automatically, the address pointer register does not have and does not require an address. The address pointer register is an 8-bit register in which the 4 LSBs are used as pointer bits to store an address that points to one of the AD7993/AD7994’s data registers. The 4 MSBs are used as command bits when operating in Mode 2 (see the Modes of Operation section). The first byte following each write address is the address of one of the data registers, which is stored in the address pointer register and selects the data register to which subsequent data bytes are written. Only the 4 LSBs of this register are used to select a data register. On power-up, the address pointer register contains all 0s, pointing to the conversion result register.

Table 7. Address Pointer Register

C4 C3 C2 C1 P3 P2 P1 P0

0 0 0 0 Register Select

Table 8. AD7993/AD7994 Register Addresses

P3 P2 P1 P0 Registers

0 0 0 0 Conversion Result Register (Read) 0 0 0 1 Alert Status Register (Read/Write) 0 0 1 0 Configuration Register (Read/Write) 0 0 1 1 Cycle Timer Register (Read/Write) 0 1 0 0 DATA 0 1 0 1 DATA 0 1 1 0 Hysteresis Reg CH1 (Read/Write) 0 1 1 1 DATA 1 0 0 0 DATA 1 0 0 1 Hysteresis Reg CH2 (Read/Write) 1 0 1 0 DATA 1 0 1 1 DATA 1 1 0 0 Hysteresis Reg CH3 (Read/Write) 1 1 0 1 DATA 1 1 1 0 DATA 1 1 1 1 Hysteresis Reg CH4 (Read/Write)

Reg CH1 (Read/Write)

LOW

Reg CH1 (Read/Write)

HIGH

Reg CH2 (Read/Write)

LOW

Reg CH2 (Read/Write)

HIGH

Reg CH3 (Read/Write)

LOW

Reg CH3 (Read/Write)

HIGH

Reg CH4 (Read/Write)

LOW

Reg CH4 (Read/Write)

HIGH

SERIAL BUS INTERFACE

Figure 25. AD7993/AD7994 Register Structure

SDA

SCL

03472-0-025

Rev. 0 | Page 18 of 32

AD7993/AD7994

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CONFIGURATION REGISTER

The configuration register is an 8-bit read/write register that is used to set the operating modes of the AD7993/AD7994. The bit functions are outlined in Table 9. A single-byte write is necessary when writing to the configuration register.

Table 9. Configuration Register Bit Function Descriptions and Default Settings at Power-Up

D7 D6 D5 D4 D3 D2 D1 D0

CH4 CH3 CH2 CH1 FLTR ALERT EN BUSY/ALERT ALERT/BUSY POLARITY 0 0 0 0 1 0 0 0

Table 10. Bit Function Descriptions

Bit Mnemonic Comment

D7 to D4 CH4 to CH1

D3 FLTR

D2 ALERT EN

D1 BUSY/ALERT

BUSY/ALERT POLARITY

These 4-channel address bits select the analog input channel(s) selects a channel for conversion. If more than one channel bit is set to 1, the AD7993/AD7994 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11 shows how these 4-channel address bits are decoded. Prior to initiating a conversion, the channel(s) must be selected in the configuration register.

The value written to this bit of the control register determines whether the filtering on SDA and SCL is

ed or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed.

enabl The hardware ALERT function is enabled if this bit is set to 1 and disabled if this bit is set to 0. This bit is used

in conjunction (see Table 12).

This bit is used in conjunction with the ALER ALERT or BUSY output (see Table 12), and if Pin 13 is configured as an ALERT output pin, if it is to be reset.

This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an ALERT or BUSY output. It

with the BUSY/ALERT bit to determine if the ALERT/BUSY pin act as an ALERT or a BUSY output

T EN bit to determine if the ALERT/BUSY output, Pin 13, acts as an

is active low if this bit is set to 0, and active high if it is set to 1.

Table 11. Channel Selection

D7 D6 D5 D4 Analog Input Channel Comments

0 0 0 0 No channel selected; see address pointer byte, Mode 2. 0 0 0 1 Convert on VIN1. 0 0 1 0 Convert on VIN2. 0 0 1 1 Sequence between VIN1 and VIN2. 0 1 0 0 Convert on VIN3. 0 1 0 1 Sequence between VIN1 and VIN3. 0 1 1 0 Sequence between VIN2 and VIN3. 0 1 1 1 Sequence between VIN1, VIN2, and VIN3. 1 0 0 0 Convert on VIN4. 1 0 0 1 Sequence between VIN1 and VIN4. 1 0 1 0 Sequence between VIN2 and VIN4. 1 0 1 1 Sequence between VIN1, VIN2, and VIN4. 1 1 0 0 Sequence between VIN3 and VIN4. 1 1 0 1 Sequence between VIN1, VIN3, and VIN4. 1 1 1 0 Sequence between VIN2, VIN3, and VIN4. 1 1 1 1 Sequence between VIN1, VIN2, VIN3, and VIN4.

The AD7993/AD7994 convert on the selected channel in the seq lowest channel in the sequence.

Table 12. Alert/Busy Function

D2 D1 ALERT/BUSY Pin Configuration

0 0 Pin does not provide any interrupt signal. 0 1 Pin configured as a busy output. 1 0 Pin configured as an alert output. 1 1

Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register (if any is active). If 1/ and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back.

1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit,

to be converted. A 1 in any of Bits D7 to D4

uence in ascending order, starting with the

Rev. 0 | Page 19 of 32

AD7993/AD7994

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CONVERSION RESULT REGISTER

The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2-byte read is necessary to read data from this register. Table 13 shows the contents of the first byte to be read from the AD7993/AD7994 and Table 14 shows the contents of the second byte to be read.

Table 13. Conversion Value Register (First Read)

D15 D14 D13 D12 D11 D10 D9 D8

Alert_Flag Zero CH

Table 14. Conversion Value Register (Second Read)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1/0 B0/0

The conversion result of the AD7993/AD7994 consists of an Alert_Flag bit, a zero bit, two channel identifier bits, and the 10- and 12-bit data result. For the AD7993, the 2 LSB (D1 and D0) of the second read contain two trailing 0s.

The Alert_Flag bit indicates whether the conversion result b

eing read or any other channel result has violated the limit registers associated with it. If an alert occurs, the master may wish to read the alert status register to obtain more information on where the alert occurred if the Alert_Flag bit is set.

The Alert_Flag bit is followed by a zero bit and two channel iden

tifier bits that indicate which channel the conversion result corresponds to. These, in turn, are followed by the 10- bit and 12-bit conversion result, MSB first.

Table 15. Channel Identifier Bits

Alert_Flag Zero CH

0/1 0 0 0 Channel 1 (VIN1) 0/1 0 0 1 Channel 2 (VIN2) 0/1 0 1 0 Channel 3 (VIN3) 0/1 0 1 1 Channel 4 (VIN4)

LIMIT REGISTERS

The AD7993/AD7994 have four pairs of limit registers. Each pair stores high and low conversion limits for each analog input channel. Each pair of limit registers has one associated hysteresis register. All 12 registers are 16 bits wide; only the 12 LSBs of the registers are used for the AD7993/AD7994. For the AD7993, the 2 LSBs, D1 and D0, should contain 0s. On power-up, the contents of the DATA channel is full scale, while the contents of the DATA registers is zero scale by default. The AD7993/AD7994 signal an alert (in either hardware, software, or both, depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers.

ID1

MSB B10 B9 B8

ID0

Channel No. Result

ID0

HIGH

LOW

DATA

The DATA

HIGH

registers for each channel are 16-bit read/write

HIGH

registers; only the 12 LSBs of each register are used. This register stores the upper limit that activates the alert output and/or the Alert_Flag bit in the conversion result register. If the value in the conversion result register for a channel is greater than the value in the DATA

HIGH

alert occurs. When the conversion result returns to a value at least N LSB below the DATA

HIGH

output pin and Alert_Flag bit are reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bits D2 and D1 in the configuration register. For the AD7993, D1 and D0 of the DATA

Table 16. DATA

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 17. DATA

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

HIGH

DATA

The DATA

LOW

register; only the 12 LSBs of each register are used. The register stores the lower limit that activates the ALERT output and/or the Alert_Flag bit in the conversion result register. If the value in the conversion result register for a channel is less than the value in the DATA

LOW

occurs. When the conversion result returns to a value at least N LSB above the DATA

LOW

and Alert_Flag bit are reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT output pin can also be reset by writing to Bits D2 and D1 in the configuration register. For the AD7993, D1 to D0 of the DATA

Table 18. DATA

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 19. DATA

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

LOW

Rev. 0 | Page 20 of 32

AD7993/AD7994

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Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register, of which only the 12 LSBs of the register are used. The hysteresis register stores the hysteresis value, N, when using the limit registers. Each pair of limit registers has a dedicated hysteresis register. The hysteresis value determines the reset point for the ALERT pin/Alert_Flag if a violation of the limits has occurred. For example, if a hysteresis value of 8 LSB is required on the upper and lower limits of Channel 1, the 12-bit word, 0000 0000 0000 1000, should be written to the hysteresis register of CH1, the address of which is shown in Table 8. On power-up, the hysteresis registers contain a value of 8 LSB for the AD7994 and 2 LSB for the AD7993. If a different hysteresis value is required, that value must be written to the hysteresis register for the channel in question. For the AD7993, D1 and D0 of the hysteresis register should contain 0s.

Table 20. Hysteresis Register (First Read/Write)

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 21. Hysteresis Register (Second Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Using the Limit Registers to Store Min/Max Conversion Results for CH1 to CH4

If full scale, that is, all 1s, is written to the hysteresis register for a particular channel, the DATA

and DATA

HIGH

registers for

LOW

that channel no longer act as limit registers as previously described, but instead act as storage registers for the maximum and minimum conversion results returned from conversions on a channel over any given period of time. This function is useful in applications where the widest span of actual conversion results is required rather than using the alert to signal that an intervention is necessary. This function could be useful for monitoring temperature extremes during refrigerated goods transportation.

It must be noted that on power-up, the contents of the DA contents of the DATA

HIGH

registers are zero scale by default.

LOW

Therefore, minimum and maximum conversion values being stored in this way are lost if power is removed or cycled.

ALERT STATUS REGISTER

The alert status register is an 8-bit read/write register that provides information on an alert event. If a conversion results in activating the ALERT pin or the Alert_Flag bit in the conversion result register, as described in the Limit Registers section, the alert status register may be read to gain further information. It contains two status bits per channel, one corresponding to the DATA DATA

limit. The bit with a status of 1 shows where the

LOW

violation occurred—that is, on which channel—and whether the violation occurred on the upper or lower limit. If a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corresponding bit for that alert event is also set.

The entire contents of the alert status register may be cleared by wr

iting 1, 1 to Bits D2 and D1 in the configuration register, as shown in Table 12. This may also be achieved by writing all 1s to the alert status register itself. Therefore, if the alert status register is addressed for a write operation, which is all 1s, the contents of the alert status register are cleared or reset to all 0s.

Table 22. Alert Status Register

D7 D6 D5 D4 D3 D2 D1 D0

CH4HI CH4LO CH3HI CH3LO CH2HI CH2LO CH1HI CH1LO

Table 23. Alert Status Register Bi

Bit Mnemonic Comment

D0 CH1

D1 CH1

D2 CH2

D3 CH2

D4 CH3

D5 CH3

D6 CH4

D7 CH4

Violation of DATA this bit set to 1, no violation if bit is set to 0.

Violation of DATA this bit set to 1, no violation if if bit is set to 0.

limit and the other to the

HIGH

t Function Descriptions

limit on Channel 1 if

LOW

limit on Channel 1 if

HIGH

limit on Channel 2 if

LOW

limit on Channel 2 if

HIGH

limit on Channel 3 if

LOW

limit on Channel 3 if

HIGH

limit on Channel 4 if

LOW

limit on Channel 4 if

HIGH

Rev. 0 | Page 21 of 32

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CYCLE TIMER REGISTER

The cycle timer register is an 8-bit read/write register that stores the conversion interval value for the automatic cycle interval mode of the AD7993/AD7994 (see the Modes of Operation section). D5 to D3 of the cycle timer register are unused and should contain 0s at all times. On power-up, the cycle timer register contains all 0s, thus disabling automatic cycle operation of the AD7993/AD7994. To enable automatic cycle mode, the user must write to the cycle timer register, selecting the required conversion interval. Table 24 shows the structure of the cycle timer register while Table 25 shows how the bits in this register are decoded to provide various automatic sampling intervals.

Table 24. Cycle Timer Register and Default Power-Up Settings

D7 D6 D5 D4 D3 D2 D1 D0

Sample Delay

0 0 0 0 0 0 0 0

Table 25. Cycle Timer Intervals

D2 D1 D0

0 0 0 Mode not selected 0 0 1 T 0 1 0 T 0 1 1 T 1 0 0 T 1 0 1 T 1 1 0 T 1 1 1 T

Bit Trial Delay

0 0 0

Typical Conversion Interval (T

= conversion time of the ADC)

CONVERT

× 32

CONVERT

× 64

CONVERT

× 128

CONVERT

× 256

CONVERT

× 512

CONVERT

× 1024

CONVERT

× 2048

CONVERT

Cyc Bit2

Cyc Bit1

Cyc Bit0

SAMPLE DELAY AND BIT TRIAL DELAY

It is recommended that no I2C bus activity occur when a conversion is taking place. However, if this is not possible, for example when operating in Mode 2 or Mode 3, then in order to maintain the performance of the ADC, Bits D7 and D6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I bus. This results in a quiet period for each bit decision. In certain cases where there is excessive activity on the interface lines, this may have the effect of increasing the overall conversion time. However, if bit trial delays extend longer than 1 µs, the conversion terminates.

When Bits D7 and D6 are both 0, the bit trial and sample in

terval delaying mechanism is implemented. The default setting of D7 and D6 is 0. To turn off both delay mechanisms, set D7 and D6 to 1.

Table 26. Cycle Timer Register and Defaults at Power-Up

D7 D6 D5 D4 D3 D2 D1 D0

Sample Delay

0 0 0 0 0 0 0 0

Bit Trial Delay

0 0 0

Cyc Bit 2

Cyc Bit 1

Cyc Bit 0

Rev. 0 | Page 22 of 32

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SERIAL INTERFACE

Control of the AD7993/AD7994 is carried out via the I2Ccompatible serial bus. The AD7993/AD7994 is connected to this bus as a slave device under the control of a master device, for example, the processor.

SERIAL BUS ADDRESS

Like all I2C-compatible devices, the AD7993/AD7994 have a 7-bit serial address. The 3 MSB of this address for the AD7993/ AD7994 are set to 010. The AD7993/AD7994 come in two versions, the AD7993-0/AD7994-0 and AD7993-1AD7994-1. The two versions have three different I which are selected by either tying the address select pin, AS, to AGND or V different addresses for the two versions, up to five AD7993/ AD7994 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the bus. See Table 6.

The serial bus protocol operates as follows:

The master initiates data transfer by establishing a start co

ndition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/

direction of the data transfer, that is, whether data is written to or read from the slave device.

, or by letting the pin float (see Table 6). By giving

C addresses available,

bit that determines the

Data is sent over the serial bus in sequences of nine clock p

ulses, eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal.

When all data bytes have been read or written, stop conditions a

re established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device pulls the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.

Any number of bytes of data may be transferred over the serial b

us in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

The peripheral whose address corresponds to the transmitted addr

ess responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/

bit is a 0, the master writes to the slave device. If the

bit is a 1, the master reads from the slave device.

Rev. 0 | Page 23 of 32

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WRITING TO THE AD7993/AD7994

Depending on the register being written to, there are three different writes for the AD7993/AD7994.

WRITING TO THE ADDRESS POINTER REGISTER FOR A SUBSEQUENT READ

In order to read from a particular register, the address pointer register must first contain the address of that register. If it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in Figure 26. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation may be subsequently performed to read the register of interest.

WRITING A SINGLE BYTE OF DATA TO THE ALERT STATUS REGISTER OR CYCLE REGISTER

The alert status register, configuration register and the cycle register are 8-bit registers, so only one byte of data can be written to each. Writing a single byte of data to one of these registers consists of the serial bus write address, the chosen data register address written to the address pointer register, followed by the data byte written to the selected data register. See Figure 27.

WRITING TWO BYTES OF DATA TO A LIMIT OR HYSTERESIS REGISTER

Each of the four limit registers are 16-bit registers, so two bytes of data are required to write a value to any one of them. Writing two bytes of data to one of these registers consists of the serial bus write address, the chosen limit register address written to the address pointer register, followed by two data bytes written to the selected data register. See Figure 28.

If the master is write addressing the AD7993/AD7994, it can write to more than one register. After the first write operation has completed for the first data register in the next byte, the master writes to the address pointer byte to select the next data register for a write operation. This eliminates the need to readdress the device in order to write to another data register.

SCL

SDA

START BY

MASTER

SCL

SDA

START BY

MASTER

191 9

SERIAL BUS ADDRESS BYTE

119 9

FRAME 1

Figure 26. Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

R/W

AD7993/AD7994

A0A1A2A300

R/W

AD7993/AD7994

Figure 27. Single-Byte Write Sequence

C4 C3 C2 P2 P1 P0A0A1A2A300

ACK. BY

ADDRESS POINTER REGISTER BYTE

C4 C3 C2 P2 P1 P0

ACK. BY

ADDRESS POINTER REGISTER BYTE

91 9

D7 D6 D5 D2 D1 D0

FRAME 2

FRAME 3

DATA BYTE

ACK. BY

AD7993/AD7994

ACK. BY

AD7993/AD7994

ACK.BY

AD7993/AD7994

STOP BY MASTER

STOP BY

MASTER

03472-0-026

03472-0-027

Rev. 0 | Page 24 of 32

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119 9

SCL

FRAME 2

AD7993/AD7994

ACK. BY

AD7993/AD7994

ACK. BY

STOP BY MASTER

03472-0-028

SCL (CONTINUED)

SDA (CONTINUED)

SDA

START BY

MASTER

SERIAL BUS ADDRESS BYTE

FRAME 1

D11

A0A1A2A300

R/W

D10 D9 D8

AD7993/AD7994

C4 C3 C2 P2 P1 P0

ACK. BY

AD7993/AD7994

D7 D6 D5 D2 D1/0 D0/0

ACK. BY

ADDRESS POINTER REGISTER

199

LEAST SIGNIFICANT DATA BYTEMOST SIGNIFICANT DATA BYTE

Figure 28. Two-Byte Write Sequence

Rev. 0 | Page 25 of 32

AD7993/AD7994

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READING DATA FROM THE AD7993/AD7994

Reading data from the AD7993/AD7994 is a 1-byte or 2-byte operation. Reading back the contents of the alert status register or the cycle timer register is a single-byte read operation, as shown in Figure 29. This assumes the particular register address has previously been set up by a single-byte write operation to the address pointer register, as shown in Figure 26. Once the register address has been set up, any number of reads can be performed from that particular register without having to write to the address pointer register again. If a read from a different register is required, the relevant register address has to be written to the address pointer register, and again, any number of reads from this register may then be performed.

1199

SCL

Reading data from the configuration register, conversion result register, DATA

registers, DATA

HIGH

registers, or hysteresis

LOW

registers is a 2-byte operation, as shown in Figure 30. The same rules apply for a 2-byte read as a 1-byte read.

When reading data back from a register on the AD7993 or the AD7994, for example the conversion result register, if more than two read bytes are supplied, the same or new data is read from the AD7993/AD7994 without the need to readdress the device. This allows the master to continuously read from a data register without having to readdress the AD7993/AD7994.

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

Figure 29. Reading a Single Byte of Data from a Selected Register

119 9

1 D11

FRAME 1

SERIAL BUS ADDRESS BYTE

Figure 30. Reading Two Bytes of Data from the Conversion Result Register

SDA

START BY

SCL

START BY

MASTER

A0A1A2A301

R/W

ACK. BY

AD7993/AD7994

SCL (CONTINUED)

SDA (CONTINUED)

AD7993/AD7994

D7 D6 D5 D2 D1 D0

ACK. BY

SINGLE DATA BYTE FROM AD7993/AD7994

ALERT

FLAG

D7 D6 D5 D2

ZERO

ID1CHID0

MOST SIGNIFICANT DATA BYTE FROM

FRAME 2

AD7993/AD7994

FRAME 2

AD7993/AD7994

D10 D9 D8A0A1A2A300

D1/0 D0/0

NO ACK. BY

MASTER

ACK. BY MASTER

MASTER

STOP BY MASTER

STOP B MASTER

03472-0-029

03472-0-030

Rev. 0 | Page 26 of 32

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ALERT/BUSY PIN

The ALERT/BUSY pin may be configured as an alert output or busy output, as shown in Table 12.

SMBus ALERT

The AD7993/AD7994 alert output is an SMBus interrupt line for devices that want to trade their ability to master for an extra pin. The AD7993/AD7994 is a slave-only device and uses the SMBus alert to signal the host device that it wants to talk. The SMBus alert on the AD7993/AD7994 is used as an out-ofconversion range indicator (a limit violation indicator).

The ALERT pin has an open-drain configuration that allows the alert outputs of several AD7993/AD7994s to be wiredAND’ed together when the ALERT pin is active low. D0 of the configuration register is used to set the active polarity of the ALERT output. The power-up default is active low. The ALERT function can be enabled or disabled by setting D2 of the configuration register to 1 or 0, respectively.

The host device can process the ALERT interrupt and simultaneously access all SMBus ALERT devices through the alert response address. Only the device that pulled the ALERT low acknowledges the ARA (alert response address). If more than one device pulls the ALERT pin low, the highest priority (lowest address) device wins communication rights via standard I2C arbitration during the slave address transfer.

The ALERT output becomes active when the value in the conversion result register exceeds the value in the DATA register or falls below the value in the DATA

LOW

reset when a write operation to the configuration register sets D1 and D0 to a 1, or when the conversion result returns N LSB below or above the value stored in the DATA DATA

LOW

HIGH

The ALERT output requires an external pull-up resistor that can be connected to a voltage different from V

provided the

maximum voltage rating of the ALERT output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be as large as possible to avoid excessive sink currents at the ALERT output.

HIGH

BUSY

When the ALERT/BUSY pin is configured as a BUSY output, the pin is used to indicate when a conversion is taking place. The polarity of the BUSY pin is programmed through bit D0 in the configuration register.

PLACING THE AD7993-1/AD7994-1 INTO HIGH SPEED MODE

High speed mode communication commences after the master addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to begin. No device connected to the bus is allowed to acknowledge the high speed master code; therefore, the code is followed by a not acknowledge (see Figure 31). The master must then issue a repeated start followed by the device address with a R/

bit. The selected device then acknowledges its address.

All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices all return to fast mode.

THE ADDRESS SELECT (AS) PIN

The address select pin on the AD7993/AD7994 is used to set

C address for the AD7993/AD7994 device. The AS pin

the I can be tied to V should be made as close as possible to the AS pin; avoid having long tracks introducing extra capacitance on the pin. This is important for the float selection, because the AS pin has to charge to a midpoint after the start bit during the first address byte. Extra capacitance on the AS pin increases the time taken to charge to the midpoint and may cause an incorrect decision on the device address. When the AS pin is left floating, the AD7993/AD7994 can work with a capacitive load up to 40 pF.

, to AGND, or left floating. The selection

HIGH SPEED MODE

SCL

SDA

START BY

MASTER

191

FAST MODE

NACK

HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE

Figure 31. Placing the Part into High Speed Mode

Rev. 0 | Page 27 of 32

0 1 A2 A1 A0XX1000

ACK. BY

AD7993/AD7994

03472-0-031

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MODES OF OPERATION

When supplies are first applied to the AD7993/AD7994, the ADC powers up in shutdown mode and normally remains in this shutdown state while not converting. There are three different methods of initiating a conversion on the devices.

MODE 1—USING THE

CONVST

A conversion can be initiated on the AD7993/AD7994 by pulsing the

CONVST

signal. The conversion clock for the part

is internally generated so no external clock is required, except when reading from or writing to the I edge of

CONVST

, the AD7993/AD7994 begin to power up

(see Point A in Figure 32). The power-up time from shutdown mode for the AD7993/AD7994 is approximately 1 µs; the CONVST up fully.

falling edge of the

signal must remain high for 1 µs for the part to power

CONVST

can be brought low after this time. The

CONVST

signal places the track-and-hold

into hold mode; a conversion is also initiated at this point (Point B in Figure 32). When the conversion is complete, approximately 2 µs later, the parts return to shutdown (Point C in Figure 32) and remain there until the next rising edge of CONVST

. The master can then read the ADC to obtain the

conversion result. The address pointer register must be pointing to the conversion result register in order to read back the conversion result.

C interface. On the rising

If the

CONVST

the falling edge of

pulse does not remain high for more than 1 µs,

CONVST

still initiates a conversion but the

result is invalid because the AD7993/AD7994 are not fully powered up when the conversion takes place. To maintain the performance of the AD7993/AD7994 in this mode it is recommended that the I

C bus is quiet when a conversion is

taking place.

The cycle timer register and Bits C4 to C1 in the address pointer register should contain all 0s when operating the AD7994/ AD7993 in this mode. The

CONVST

pin should be tied low for

all other modes of operation. To select an analog input channel for conversion in this mode, the user must write to the configuration register and select the corresponding channel for conversion. To set up a sequence of channels to be converted with each

CONVST

pulse, set the corresponding channel bits in

the configuration register (see Table 11).

Once the conversion is complete, the master can address the AD7993/AD7994 to read the conversion result. If further conversions are required, the SCL line can be taken high while the

CONVST

signal is pulsed again; then an additional 18 SCL

pulses are required to read the conversion result.

When operating the AD7993-1/AD7994-1 in Mode 1 and reading after the conversion with a 3.4 MHz SCL, the ADCs can achieve a throughput rate of up to 121 kSPS.

BA C

POWER-UP

CONVST

SCA

SDA

CONVERT

119

S 7-BIT ADDRESS

Figure 32. Mode 1 Operation

FIRST DATA BYTE (MSBs)

SECOND DATA BYTE (LSBs)

03472-0-032

Rev. 0 | Page 28 of 32

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MODE 2—COMMAND MODE

This mode allows a conversion to be automatically initiated any time a write operation occurs. In order to use this mode, Command Bits C4 to C1 in the address pointer byte, shown in Table 7, must be programmed.

To select a single analog input for conversion in this mode, t

he user must set bits C4 to C1of the address pointer byte to indicate which channel to convert (see Table 27). When all four command bits are 0, this mode is not in use.

A sequence can also be set up for this mode. If more than one co

mmand bit is set in the address pointer byte, the ADC starts converting on the lowest channel in the sequence and then the next lowest until all the channels in the sequence have been converted. The ADC stops converting the sequence when it receives a STOP bit.

Figure 29 illustrates a 2-byte read operation from the convers

ion result register. This operation is normally preceded by a write to the address pointer register so that the following read accesses the desired register, in this case the conversion result register (Figure 26). If Command Bits C4 to C1 are set when the contents of the address pointer register are being loaded, the AD7993/AD7994 begin to power up and convert the selected channel(s). Power-up begins on the fifth SCL falling edge of the address point byte (see Point A in Figure 33).

Table 27 shows the channel selection in this mode via C

ommand Bits C4 to C1 in the address pointer register. The wake-up and conversion times combined should take approximately 3 µs. Following this, the AD7993/AD7994 must be addressed again to indicate that a read operation is required. The read then takes place from the conversion result register. This read accesses the conversion result from the channel selected via the command bits. If the Command Bits C2 and C1 were set to 1, 1, then a four byte read would be necessary. The first read accesses the data from the conversion on V this read takes place, a conversion occurs on V read accesses this data from V mode operates.

When operating the AD7994-1/AD7993-1 in Mode 2 with a

h speed mode, 3.4 MHz SCL, the conversion may not be

hig complete before the master tries to read the conversion result. If this is the case, the AD7994-1/AD7993-1 hold the SCL line low during the ACK clock after the read address until the conversion is complete. When the conversion is complete, the AD7994-1/AD7993-1 release the SCL line and the master can then read the conversion result.

After the conversion is initiated by setting the command bits in th

e address pointer byte, if the AD7993/AD7994 receive a stop

or NACK from the master, the devices stop converting.

2. Figure 34 illustrates how this

1. While

2. The second

Table 27. Address Pointer Byte

C4 C3 C2 C1 P3 P2 P1 P0 Mode 2, Convert On Comments

0 0 0 0 0 0 0 0 Not selected 0 0 0 1 0 0 0 0 VIN1 0 0 1 0 0 0 0 0 VIN2 0 0 1 1 0 0 0 0 Sequence between VIN1 and VIN2 0 1 0 0 0 0 0 0 VIN3 0 1 0 1 0 0 0 0 Sequence between VIN1 and VIN3 0 1 1 0 0 0 0 0 Sequence between VIN2 and VIN3 0 1 1 1 0 0 0 0 Sequence between VIN1, VIN2, and VIN3 1 0 0 0 0 0 0 0 VIN4 1 0 0 1 0 0 0 0 Sequence between VIN1 and VIN4 1 0 1 0 0 0 0 0 Sequence between VIN2 and VIN4 1 0 1 1 0 0 0 0 Sequence between VIN1, VIN2, and VIN4 1 1 0 0 0 0 0 0 Sequence between VIN3 and VIN4 1 1 0 1 0 0 0 0 Sequence between VIN1, VIN3, and VIN4 1 1 1 0 0 0 0 0 Sequence between VIN2, VIN3, and VIN4 1 1 1 1 0 0 0 0 Sequence between VIN1, VIN2, VIN3, and VIN4

With the pointer bits set to all 0s, the next read accesses the results of the conversion result register.

Rev. 0 | Page 29 of 32

AD7993/AD7994

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SCL

SDA

SCL

SDA

7-BIT ADDRESS

119

Sr RA A

7-BIT ADDRESS

WA A

ACK BY

AD7993/AD7994

ACK BY

AD7993/AD7994

COMMAND/ADDRESS

POINT BYTE

9 9

FIRST DATA BYTE

(MSBs)

911A9

ACK BY

AD7993/AD7994

ACK BY

MASTER

SECOND DATA BYTE

(LSBs)

Sr/P

NACK BY

MASTER

03472-0-033

Figure 33. Mode 2 Operation

SCL

SDA

7-BIT ADDRESS

Sr 7-BIT ADDRESS

COMMAND/ADDRESS

ACK BY

AD7993/AD7994

FIRST DATA BYTE

ACK BY

AD7993/AD7994

POINT BYTE

(MSBs)

911

ACK BY

AD7993/AD7994

SECOND DATA BYTE

ACK BY

MASTER

RESULT FROM CH1

(LSBs)

ACK BY

MASTER

FIRST DATA BYTE

(MSBs)

SECOND DATA BYTE

ACK BY

MASTER

RESULT FROM CH2

(LSBs)

A/A

03472-0-034

Figure 34. Mode 2 Sequence Operation

MODE 3—AUTOMATIC CYCLE INTERVAL MODE

An automatic conversion cycle can be selected and enabled by writing a value to the cycle timer register. A conversion cycle interval can be set up on the AD7993/AD7994 by programming the relevant bits in the 8-bit cycle timer register, as decoded in Table 25. Only the 3 LSB are used; the 5 MSB should contain 0s. When the 3 LSB of the register are programmed with any configuration other than all 0s, a conversion takes place every X ms; the cycle interval, X, depends on the configuration of these three bits in the cycle timer register. There are seven different cycle time intervals to choose from, as shown in Table 25. Once the conversion takes place, the part powers down again until the next conversion. To exit this mode of

Rev. 0 | Page 30 of 32

operation, the user must program the 3 LSB of the cycle timer register to contain all 0s. To select a channel(s) for operation in the cycle mode, set the corresponding channel bit(s), D7 to D4, of the configuration register. If more than one channel bit is set in the configuration register, the ADC automatically cycles through the channel sequence starting with the lowest channel and working its way up through the sequence. Once the sequence is complete, the ADC starts converting on the lowest channel again, continuing to loop through the sequence until the cycle timer register’s contents are set to all 0s. This mode is useful for monitoring signals such as battery voltage, and temperature, alerting only when the limits are violated.

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OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]

6.40

BSC

1.20 MAX

0.30

0.19

0.10

Dimensions shown in millimeters

SEATING PLANE

(RU-16)

0.20

0.09 8°

0°

0.75

0.60

0.45

ORDERING GUIDE

Model

AD7993BRU-0 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-0REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRUZ-0

AD7993BRUZ-0REEL3 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-1 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRU-1REEL –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRUZ-13 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7993BRUZ-1REEL3 –40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-0 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-0REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRUZ-03 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRUZ-0REEL3 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-1 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRU-1REEL –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRUZ-13 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package AD7994BRUZ-1REEL3 –40°C to +125°C ±1 LSB RU-16 Thin Shrink Small Outline Package EVAL-AD7993CB Standalone Evaluation Board EVAL-AD7994CB Standalone Evaluation Board

Temperature Range Linearity Error2(Max) Package Option Package Description

–40°C to +125°C ±0.5 LSB RU-16 Thin Shrink Small Outline Package

The AD7993-0/AD7994-0 supports standard and fast I2C interface modes. The AD7993-1/AD7994-1 support standard, fast, and high speed I2C interface modes.

Linearity error here refers to integral nonlinearity.

Z = Pb-free part.

RELATED PARTS IN I

C-COMPATIBLE ADC PRODUCT FAMILY

Part Number Resolution Number of Input Channels Package

AD7998 12 8 20-lead TSSOP AD7997 10 8 20-lead TSSOP AD7992 12 2 10-lead MSOP

Rev. 0 | Page 31 of 32

AD7993/AD7994

www.BDTIC.com/ADI

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

D03472–0–10/04(0)

Rev. 0 | Page 32 of 32

Datasheet AD7994 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

AD7993 SPECIFICATIONS

AD7994 SPECIFICATIONS

I2C TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT INFORMATION

CONVERTER OPERATION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

INTERNAL REGISTER STRUCTURE

ADDRESS POINTER REGISTER

CONFIGURATION REGISTER

CONVERSION RESULT REGISTER

LIMIT REGISTERS

ALERT STATUS REGISTER

CYCLE TIMER REGISTER

SAMPLE DELAY AND BIT TRIAL DELAY

SERIAL INTERFACE

SERIAL BUS ADDRESS

WRITING TO THE AD7993/AD7994

WRITING TWO BYTES OF DATA TO A LIMIT OR HYSTERESIS REGISTER

READING DATA FROM THE AD7993/AD7994

ALERT/BUSY PIN

SMBus ALERT

BUSY

PLACING THE AD7993-1/AD7994-1 INTO HIGH SPEED MODE

THE ADDRESS SELECT (AS) PIN

MODES OF OPERATION

MODE 2—COMMAND MODE

MODE 3—AUTOMATIC CYCLE INTERVAL MODE

OUTLINE DIMENSIONS

ORDERING GUIDE