ANALOG DEVICES AD7991, AD7995, AD7999 Service Manual

4-Channel, 12-/10-/8-Bit ADC with

V

I2C-Compatible Interface in 8-Lead SOT-23

FEATURES

12-/10-/8-bit ADCs with fast conversion time: 1 μs typical 4 analog input channels/3 analog input channels with

reference input Specified for V Sequencer operation Temperature range: −40°C to +125°C

2

I

C-compatible serial interface supports standard, fast,

and high speed modes 2 versions allow 2 I Low power consumption

Shutdown mode: 1 μA maximum 8-lead SOT-23 package

APPLICATIONS

System monitoring Battery-powered systems Data acquisition Medical instruments

GENERAL DESCRIPTION

The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power, successive approximation ADCs with an I Each part operates from a single 2.7 V to 5.5 V power supply and features a 1 µs conversion time. The track-and-hold amplifier allows each part to handle input frequencies of up to 14 MHz, and a multiplexer allows taking samples from four channels.

Each AD7991/AD7995/AD7999 provides a 2-wire serial interface compatible with I AD7995 come in two versions and each version has an individual I connected to the same I fast, and high speed I one version.

The AD7991/AD7995/AD7999 normally remain in a shutdown state, powering up only for conversions. The conversion process is controlled by a command mode, during which each I operation initiates a conversion and returns the result over the

2

I

C bus.

When four channels are used as analog inputs, the reference for the part is taken from V range to the ADC. Therefore, the analog input range to the ADC is 0 V to V V

input, can also be used with this part.

IN3/VREF

of 2.7 V to 5.5 V

DD

2

C addresses

2

C®-compatible interface.

2

C interfaces. The AD7991 and

2

C address. This allows two of the same devices to be

2

C bus. Both versions support standard,

2

C interface modes. The AD7999 comes in

2

; this allows the widest dynamic input

DD

. An external reference, applied through the

DD

C read

AD7991/AD7995/AD7999

FUNCTIONAL BLOCK DIAGRAM

DD

V

IN0

V

IN3/VREF

V

IN1

V

IN2

I/P

T/H

MUX

AD7991/AD7995/AD7999

PRODUCT HIGHLIGHTS

1. Four single-ended analog input channels, or three single-

ended analog input channels and one reference input channel.

2

2. I

C-compatible serial interface. Standard, fast, and high

speed modes.

3. Automatic shutdown.

4. Reference derived from the power supply or external

reference.

5. 8-lead SOT-23 package.

Table 1. Related Devices

Device Resolution Input Channels

AD7998 12 8 AD7997 10 8 AD7994 12 4 AD7993 10 4 AD7992 12 2

12-/10-/8-BIT

CONTROL

LOGIC AND INTERFACE

Figure 1.

SAR

ADC

2

I

GND

C

SCL SDA

06461-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7991/AD7995/AD7999

REVISION HISTORY

10/09—Rev. 0 to Rev. A

Changes to Table 3 ............................................................................ 5

Changes to Table 4 ............................................................................ 7

Updated Ordering Guide ............................................................... 27

12/07—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD7991/AD7995/AD7999

SPECIFICATIONS

AD79911

The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 2.

Y Version Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

2, 3

See the Sample Delay and Bit Trial Delay section, f from 1.7 MHz to 3.4 MHz

f

= 1 kHz sine wave for f

IN

Signal-to-Noise and Distortion (SINAD)4 69.5 70 dB

Signal-to-Noise Ratio (SNR)4 70 71 dB

Total Harmonic Distortion (THD)4 −75.5 dB

Peak Harmonic or Spurious Noise (SFDR)4 −77.5 dB

Intermodulation Distortion (IMD)4

fa = 11 kHz, fb = 9 kHz for f

1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for f

to 400 kHz Second-Order Terms −92 dB Third-Order Terms −88 dB

Channel-to-Channel Isolation4 −90 dB fIN = 10 kHz Full-Power Bandwidth4 14 MHz @ 3 dB

1.5 MHz @ 0.1 dB DC ACCURACY

2, 5

Resolution 12 Bits Integral Nonlinearity4 ±1 LSB

±0.5 LSB

Differential Nonlinearity4 ±0.9 LSB Guaranteed no missed codes to 12 bits

±0.5 LSB

Offset Error4 ±1 ±5 LSB Offset Error Matching ±0.5 LSB Offset Temperature Drift 4.43 ppm/°C Gain Error4 ±2 LSB Gain Error Matching ±0.7 LSB Gain Temperature Drift 0.69 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V

V V

REF

= V DC Leakage Current ±1 μA Input Capacitance 34 pF

Channel 0 to Channel 2—during acquisition phase

4 pF

Channel 0 to Channel 2—outside

acquisition phase 35 pF Channel 3—during acquisition phase 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD V

REF

DC Leakage Current ±1 μA V

Input Capacitance 5 pF Outside conversion phase

REF

35 pF During conversion phase Input Impedance 69 kΩ

= 2.5 V, f

REF

= 10 kHz sine wave for f

IN

or VDD

IN3/VREF

= 3.4 MHz,

SCL

up to 400 kHz

SCL

from

up

SCL

Rev. A | Page 3 of 28

AD7991/AD7995/AD7999

Y Version Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 V I

0.6 V I Floating-State Leakage Current ±1 μA Floating-State Output Capacitance6 10 pF Output Coding Straight (natural) binary

THROUGHPUT RATE 18 × (1/f

POWER REQUIREMENTS2

VDD 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating, Interface Active

(Fully Operational)

0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Active7 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive7 1/1.6 μA VDD = 3.3 V/5.5 V

Power Dissipation

ADC Operating, Interface Active

(Fully Operational)

0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Active7 0.24/0.88 mW VDD = 3.3 V/5.5 V, 400 kHz f

0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive7 3.3/8.8 μW VDD = 3.3 V/5.5 V

1

Functional from VDD = 2.35 V.

2

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

3

For f

up to 400 kHz, clock stretching is not implemented. Above f

SCL

4

See the Terminology section.

5

For f

≤ 1.7 MHz, clock stretching is not implemented; for f

SCL

6

Guaranteed by initial characterization.

7

See the Reading from the AD7991/AD7995/AD7999 section.

0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

6

10 pF

IN

0.1 (VDD) V

HYST

= 3 mA

SINK

= 6 mA

SINK

)

SCL

≤ 1.7 MHz; see the Serial Interface

f

SCL

section

17.5 × (1/f + 2 μs

)

SCL

f

> 1.7 MHz; see the Serial Interface

SCL

section

= VDD; for f

V

REF

clock stretching is implemented

0.09/0.25 mA V

0.3/1.38 mW V

.

SCL

= 400 kHz, clock stretching is implemented.

SCL

> 1.7 MHz, clock stretching is implemented.

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.4 MHz,

SCL

Rev. A | Page 4 of 28

AD7991/AD7995/AD7999

AD79951

The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 3.

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

f

Signal-to-Noise and

Distortion (SINAD)

Total Harmonic Distortion

5

(THD)

Peak Harmonic or Spurious

Noise (SFDR)

Intermodulation

Distortion (IMD)

fa = 5.4 kHz, fb = 4.6 kHz for f

Second-Order Terms −90 −90 dB Third-Order Terms −86 −86 dB

Channel-to-Channel

Isolation

5

Full-Power Bandwidth5 14 14 MHz @ 3 dB

1.5 1.5 MHz @ 0.1 dB DC ACCURACY

3, 6

Resolution 10 10 Bits Integral Nonlinearity5 ±0.4 ±0.4 LSB Differential Nonlinearity5 ±0.4 ±0.4 LSB Guaranteed no missed codes to 10 bits Offset Error5 ±1 ±1.5 LSB Offset Error Matching ±0.04 ±0.2 LSB Offset Temperature Drift 4.13 4.13 ppm/°C Gain Error5 ±0.15 ±0.5 LSB Gain Error Matching ±0.06 ±0.25 LSB Gain Temperature Drift 0.50 0.50 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition

4 4 pF Channel 0 to Channel 2—outside acquisition

35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD 1.2 VDD V

REF

DC Leakage Current ±1 ±1 μA V

Input Capacitance 5 5 pF Outside conversion phase

REF

35 35 pF During conversion phase Input Impedance 69 69 kΩ

3, 4

See the Sample Delay and Bit Trial Delay

section, f

1.7 MHz to 3.4 MHz = 1 kHz sine wave for f

IN

5

61.5 61 dB

−85 −75 dB

5

−85 −76 dB

fa = 11 kHz, fb = 9 kHz for f

3.4 MHz

−90 −90 dB f

= 10 kHz

IN

0 V

REF

V V

REF

= V

REF

phase

= 2.5 V, f

REF

= 10 kHz sine wave for f

IN

or VDD

IN3/VREF

SCL

= 3.4 MHz,

from

SCL

up to 400 kHz

from 1.7 MHz to

up to 400 kHz

SCL

Rev. A | Page 5 of 28

AD7991/AD7995/AD7999

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 0.4 V I

0.6 0.6 V I Floating-State Leakage

Current

Floating-State Output

Capacitance

Output Coding Straight (natural) binary Straight (natural) binary

THROUGHPUT RATE 18 × (1/f

17.5 × (1/f

POWER REQUIREMENTS3 V

VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating,

Interface Active (Fully Operational)

Power-Down, Interface

Active

Inactive

8

Power Dissipation

ADC Operating,

Interface Active (Fully Operational)

Power-Down, Interface

1

Functional from VDD = 2.35 V.

2

A Version tested at VDD = 3.3 V and f

3

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

4

For f

SCL

5

See the Terminology section.

6

For f

SCL

7

Guaranteed by initial characterization.

8

See the Reading from the AD7991/AD7995/AD7999 section.

8

Active

8

Inactive

up to 400 kHz, clock stretching is not implemented. Above f

≤ 1.7 MHz, clock stretching is not implemented; for f

0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

7

10 10 pF

IN

0.1 (VDD) 0.1 (VDD) V

HYST

SINK

±1 ±1 μA

7

10 10 pF

2 μs

) 18 × (1/f

SCL

) +

17.5 × (1/f

SCL

2 μs

) f

SCL

) +

f

SCL

clock stretching is implemented

0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.25 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

0.07/0.16 mA V

0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f 1 1/1.6 μA V

0.3/1.38 mW V

0.83 0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

0.24/0.88 mW V

0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

3.3 3.3/8.8 μW V

= 3.4 MHz. Functionality tested at f

SCL

.

SCL

> 1.7 MHz, clock stretching is implemented.

SCL

= 400 kHz.

SCL

= 400 kHz, clock stretching is implemented.

SCL

= 3 mA = 6 mA

≤ 1.7 MHz; see the Serial Interface section

SCL

> 1.7 MHz; see the Serial Interface section

SCL

= VDD; for f

REF

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.4 MHz,

SCL

Rev. A | Page 6 of 28

AD7991/AD7995/AD7999

AD79991

The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 4.

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

f

Signal-to-Noise and

Distortion (SINAD)

Total Harmonic

Distortion (THD)

Peak Harmonic or

Spurious Noise (SFDR)

Intermodulation

Distortion (IMD) fa = 5.4 kHz, fb = 4.6 kHz for f Second-Order Terms −83 −83 dB Third-Order Terms −75 −75 dB Channel-to-Channel

Isolation

5

Full-Power Bandwidth5 14 14 MHz @ 3 dB

1.5 1.5 MHz @ 0.1 dB DC ACCURACY

3, 6

Resolution 8 8 Bits Integral Nonlinearity5 ±0.04 ±0.1 LSB Differential Nonlinearity5 ±0.05 ±0.1 LSB Guaranteed no missed codes to eight bits Offset Error5 ±0.3 ±0.35 LSB Offset Error Matching ±0.02 ±0.05 LSB Offset Temperature Drift 4.26 4.26 ppm/°C Gain Error5 ±0.06 ±0.175 LSB Gain Error Matching ±0.03 ±0.06 LSB Gain Temperature Drift 0.59 0.59 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD 1.2 VDD V

REF

DC Leakage Current ±1 ±1 μA V

Input Capacitance 5 5 pF Outside conversion phase

REF

35 35 pF During conversion phase Input Impedance 69 69 kΩ

3, 4

See the Sample Delay and Bit Trial Delay section,

49.5 49.5 dB

5

−65 −65 dB

5

fa = 11 kHz, fb = 9 kHz for f

−90 −90 dB f

= 10 kHz sine wave for f

f

IN

= 1 kHz sine wave for f

IN

3.4 MHz

= 10 kHz

IN

0 V

REF

V V

REF

= V

REF

IN3/VREF

REF

or VDD

= 2.5 V, f

SCL

= 3.4 MHz,

SCL

from 1.7 MHz to 3.4 MHz

up to 400 kHz

from 1.7 MHz to

SCL

up to 400 kHz

SCL

Rev. A | Page 7 of 28

AD7991/AD7995/AD7999

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 0.4 V I

0.6 0.6 V I Floating-State Leakage

Current

Floating-State Output

Capacitance

Output Coding Straight (natural) binary Straight (natural) binary

THROUGHPUT RATE 18×(1/f

17.5×(1/f

POWER REQUIREMENTS3 V

VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating,

Interface Active (Fully Operational)

Power-Down,

Interface Active

Power-Down ,

Interface Inactive

Power Dissipation

ADC Operating, Interface Active (Fully Operational)

Power-Down,

Interface Active

Power-Down ,

Interface Inactive

1

Functional from VDD = 2.35 V.

2

A Version tested at VDD=3.3 V and f

3

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

4

For f

up to 400 kHz, clock stretching is not implemented. Above f

SCL

5

See the Terminology section.

6

For f

≤ 1.7 MHz, clock stretching is not implemented; for f

SCL

7

Guaranteed by initial characterization.

8

See the Reading from the AD7991/AD7995/AD7999 section.

0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

7

10 10 pF

IN

0.1 (VDD) 0.1 (VDD) V

HYST

SINK

±1 ±1 μA

7

10 10 pF

+ 2 μs

) 18×(1/f

SCL

)

17.5×(1/f

SCL

+ 2 μs

) f

SCL

)

f

SCL

clock stretching is implemented

0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.25 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

0.07/0.16 mA V

8

0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f 1 1/1.6 μA V

8

0.24/0.88 mW V

8

0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

3.3 3.3/8.8 μW V

8

= 3.4 MHz. Functionality tested at f

SCL

0.83

SCL

.

0.3/1.38

0.83/4.4

= 400 kHz.

SCL

= 400 kHz, clock stretching is implemented.

SCL

> 1.7 MHz, clock stretching is implemented.

SCL

mW mW

V VDD = 3.3 V/5.5 V, 3.4 MHz f

= 3 mA = 6 mA

≤ 1.7 MHz; see the Serial Interface section > 1.7 MHz; see the Serial Interface section

= VDD; for f

REF

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.4 MHz,

SCL

Rev. A | Page 8 of 28

AD7991/AD7995/AD7999

I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with t

and tf measured between 0.3 VDD and 0.7 VDD (see Figure 2). Unless otherwise noted, VDD = 2.7 V to 5.5 V and TA = T

r

Table 5.

Limit at t

, t

MIN

MAX

Parameter Conditions Min Typ Max Unit Description

1

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz High speed mode C C

1

t

Standard mode 4 μs t

1

= 100 pF maximum 3.4 MHz

B

= 400 pF maximum 1.7 MHz

B

, SCL high time

HIGH

Fast mode 0.6 μs High speed mode C C

1

t

Standard mode 4.7 μs t

2

= 100 pF maximum 60 ns

B

= 400 pF maximum 120 ns

B

, SCL low time

LOW

Fast mode 1.3 μs High speed mode C C

1

t

Standard mode 250 ns t

3

= 100 pF maximum 160 ns

B

= 400 pF maximum 320 ns

B

, data setup time

SU;DAT

Fast mode 100 ns High speed mode 10 ns

1, 2

t

Standard mode 0 3.45 μs t

4

, data hold time

HD;DAT

Fast mode 0 0.9 μs High Speed mode C C

1

t

Standard mode 4.7 μs t

5

= 100 pF maximum 0 703 ns

B

= 400 pF maximum 0 150 ns

B

, setup time for a repeated start condition

SU;STA

Fast mode 0.6 μs High Speed mode 160 ns

1

t

Standard mode 4 μs t

6

, hold time for a repeated start condition

HD;STA

Fast mode 0.6 μs High speed mode 160 ns

1

t

Standard mode 4.7 μs t

7

, bus-free time between a stop and a start condition

BUF

Fast mode 1.3 μs

1

t

Standard mode 4 μs t

8

, setup time for a stop condition

SU;STO

Fast mode 0.6 μs High speed mode 160 ns t9 Standard mode 1000 ns t

, rise time of the SDA signal

RDA

Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF maximum 10 80 ns

B

= 400 pF maximum 20 160 ns

B

MIN

to T

MAX

.

Rev. A | Page 9 of 28

ANALOG DEVICES AD7991, AD7995, AD7999 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

I2C TIMING SPECIFICATIONS