ANALOG DEVICES AD7983 Service Manual

16-Bit, 1.33 MSPS PulSAR ADC in

V

0

FEATURES

16-bit resolution with no missing codes Throughput: 1.33 MSPS Low power dissipation: 10.5 mW typical @ 1.33 MSPS INL: ±0.6 LSB typical, ±1.0 LSB maximum SINAD: 91.6 dB @ 10 kHz THD: −115 dB @ 10 kHz Pseudo differential analog input range

0 V to V

Any input range and easy to drive with the ADA4841 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic

interface Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs and busy indicator 10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN

(LFCSP), SOT-23 size Wide operating temperature range: −40°C to +85°C

APPLICATIONS

Battery-powered equipment Communications AT E Data acquisitions Medical instruments

with V

REF

between 2.9 V to 5.5 V

REF

MSOP/QFN

AD7983

APPLICATION DIAGRAM

2.9VTO 5V 2.5

TO VREF

IN+

IN–

REF

AD7983

GND

VDD

VIO

SDI

SCK

SDO

CNV

Figure 1.

GENERAL DESCRIPTION

The AD7983 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.

The AD7983 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C.

1.8V TO 5V

3- OR 4-WI RE INTERFACE (SPI, DAISY CHAIN, CS)

06974-001

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Dri ver

14-Bit AD7940 AD7942 16-Bit AD7680 AD7683 AD7687

1

AD7684 AD7694 AD7693 18-Bit AD7691

1

AD7984

1

Pin-for-pin compatible.

AD7946 AD7686 AD7688

AD7690

1

AD7982

AD7980

AD7983

1

AD7685

1

ADA4841

ADA4941 ADA4841

ADA4941

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7983

REVISION HISTORY

3/10—Rev. 0 to Rev. A

Deleted Endnote 1 from Features Section, General Description

Section, and Table 1 .......................................................................... 1

Changes to Table 5 ............................................................................ 6

Deleted Endnote 1 from Figure 5 Caption .................................... 7

Changes to Figure 21 ...................................................................... 12

Deleted Endnote 1 from Circuit Information Section............... 12

Changes to Figure 41 Caption ....................................................... 24

Changes to Ordering Guide .......................................................... 24

11/07—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7983

SPECIFICATIONS

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits ANALOG INPUT

Voltage Range IN+ − IN− 0 V Absolute Input Voltage IN+ −0.1 V IN− −0.1 +0.1 V Analog Input CMRR fIN = 100 kHz 60 dB Leakage Current @ 25°C Acquisition phase 1 nA Input Impedance See the Analog Inputs section

ACCURACY

No Missing Codes 16 Bits Differential Linearity Error −0.9 ±0.4 +0.9 LSB Integral Linearity Error −1.0 ±0.6 +1.0 LSB Transition Noise 0.52 LSB Gain Error, T

MIN

to T

MAX

3

±2 LSB Gain Error Temperature Drift ±0.41 ppm/°C Zero Error, T

MIN

3

to T

−0.9 ±0.44 +0.9 mV

MAX

Zero Temperature Drift 0.54 ppm/°C Power Supply Sensitivity

VDD = 2.5 V ± 5%

±0.1 LSB

THROUGHPUT

Conversion Rate 0 1.33 MSPS Transient Response Full-scale step 290 ns

AC ACCURACY

Dynamic Range 93 dB Signal-to-Noise Ratio, SNR fIN = 1 kHz 90.5 92 dB Spurious-Free Dynamic Range, SFDR fIN = 10 kHz 114 dB Total Harmonic Distortion, THD fIN = 10 kHz −115 dB Signal-to-(Noise + Distortion), SINAD fIN = 10 kHz 91.6 dB

1

All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

2

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV.

3

See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.

V

REF

+ 0.1 V

REF

1

2

1

Rev. A | Page 3 of 24

AD7983

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 2.9 5.1 V Load Current 1.33 MSPS 500 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 10 MHz Aperture Delay 2.0 ns

DIGITAL INPUTS

Logic Levels

VIL VIO > 3V –0.3 0.3 × VIO V VIH VIO > 3V 0.7 × VIO VIO + 0.3 V VIL VIO ≤ 3V –0.3 0.1 × VIO V VIH VIO ≤ 3V 0.9 × VIO VIO + 0.3 V IIL −1 +1 μA IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format Serial 16 bits straight binary Pipeline Delay

Conversion results available immediately

after completed conversion VOL I VOH I

= 500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD 2.375 2.5 2.625 V VIO Specified performance 2.3 5.5 V VIO Range 1.8 5.5 V Standby Current

1, 2

VDD and VIO = 2.5 V 0.35 nA

Power Dissipation 1.33 MSPS throughput 10.5 12 mW Energy per Conversion 7.9 nJ/sample

TEMPERATURE RANGE

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During the acquisition phase.

3

Contact sales for extended temperature range.

3

to T

MIN

−40 +85 °C

MAX

Rev. A | Page 4 of 24

AD7983

TIMING SPECIFICATIONS

TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions.

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width (CS Mode)

SCK Period (CS Mode)

VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns

SCK Period (Chain Mode) t

VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns

VIO Above 2.3 V 16 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 9.5 ns

VIO Above 3 V 11 ns

VIO Above 2.7 V 12 ns

VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 3 V 10 ns

VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge t SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with Busy Indicator) t

300 500 ns

CONV

250 ns

ACQ

750 ns

CYC

t

10 ns

CNVH

t

SCK

4.5 ns

SCKL

4.5 ns

SCKH

3 ns

HSDO

DSDO

t

EN

t

20 ns

DIS

5 ns

SSDICNV

t

2 ns

HSDICNV

0 ns

HSDICNV

5 ns

SSCKCNV

5 ns

HSCKCNV

2 ns

SSDISCK

3 ns

HSDISCK

15 ns

DSDOSDI

1

Y% VIO

t

DELAY

V V

2

IH

2

IL

06974-003

TO SDO

20pF

C

L

500µA I

OL

1.4V

OH

06974-002

Figure 2. Load Circuit for Digital Interface Timing

1

X% VIO

t

DELAY

2

V

IH

2

V

IL

1

FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.

2

MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICAT IONS I N TABLE 3.

Figure 3. Voltage Levels for Timing

Rev. A | Page 5 of 24

AD7983

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+,1 IN−1 to GND −0.3 V to V

Supply Voltage

REF, VIO to GND −0.3 V to +6 V VDD to GND −0.3 V to +3 V

VDD to VIO +3 V to −6 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance

10-Lead MSOP 200°C/W

10-Lead QFN (LFCSP) 48.7°C/W θJC Thermal Impedance

10-Lead MSOP 44°C/W

10-Lead QFN (LFCSP) 2.96°C/W Lead Temperature

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1

See the Analog Inputs section.

+ 0.3 V or ±130 mA

REF

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 24

AD7983

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

REF

2

VDD

GND

IN+

IN–

AD7983

3

TOP VIEW

(Not to Scale)

4

5

Figure 4. 10-Lead MSOP Pin Configuration

10

VIO

9

SDI

8

SCK

7

SDO

6

CNV

06974-004

REF 1 10 VI O

VDD 2 9 SDI

IN+ 3 8 SCK

IN– 4 7 SDO

GND 5

AD7983

TOP VIEW

(Not to Scale)

6 CNV

06974-005

Figure 5. 10-Lead QFN (LFCSP) Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1 REF AI

Reference Input Voltage. The REF range is from 2.9 V to 5.1 V. It is referred to the GND pin. This pin should

be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI

Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is

0 V to V

REF

. 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI

Convert Input. This input has multiple functions. On its risng edge, it initiates the conversions and selects the interface mode of the part: chain or CS mode. In CS mode, it enables the SDO pin when low.

In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as

follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital

data level on SDI is output on SDO with a delay of 16 SCK cycles.

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can

CS

enable the serial output signals when low; if SDI or CNV is low when the conversion is complete,

the busy indicator feature is enabled. 10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,

3 V, or 5 V).

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 7 of 24

AD7983

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V, REF = 5 V, VIO = 3.3 V, unless otherwise noted.

1.25

1.00

0.75

0.50

0.25

0

INL (LSB)

–0.25

–0.50

–0.75

–1.00

–1.25

0 65536

16384 32768 49152

POSITIVE INL: 0.30LSB NEGATIVE INL: –0. 37LSB

CODE

Figure 6. Integral Nonlinearity vs. Code

120k

06974-026

1.00

0.75

0.50

0.25

0

DNL (LSB)

–0.25

–0.50

–0.75

–1.00

0 65536

16384 32768 49152

POSITIVE DNL: 0. 14LSB NEGATIVE DNL: –0.14L SB

CODE

Figure 9. Differential Nonlinearity vs. Code

80k

06974-029

16604

580000

CODE IN HEX

96765

17590

100k

COUNTS

80k

60k

40k

20k

0

7FB6

7FB7 7FB8 7FB9 7FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC0 7FC1 7FC2

Figure 7. Histogram of a DC Input at the Code Center

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0

100 200 300 400 500 600

FREQUENCY (kHz)

Figure 8. FFT Plot

f

= 1.33MSPS

S

f

= 10kHz

IN

SNR = 91.6dB THD = –114.9dB SFDR = 113.8d B SINAD = 91.6dB

61565

829

CODE IN HEX

67532

1146

000000000

06974-042

70k

60k

50k

40k

COUNTS

30k

20k

10k

000055

06974-041

0

7FF7

7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003

Figure 10. Histogram of a DC Input at the Code Transition

95

94

93

92

91

90

SNR (dB)

89

88

87

86

06974-028

85

–10 0

–9 –8 –7 –6 –5 –4 –3 –2 –1

INPUT LEVEL (dB of Full Scale)

06974-032

Figure 11. SNR vs. Input Level

Rev. A | Page 8 of 24

ANALOG DEVICES AD7983 Service Manual

FEATURES

APPLICATIONS

APPLICATION DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS