Datasheet AD797 Datasheet (ANALOG DEVICES)

Ultralow Distortion,

Ultralow Noise Op Amp

FEATURES CONNECTION DIAGRAM

Low noise

0.9 nV/√Hz typ (1.2 nV/√Hz max) input voltage noise at 1 kHz

50 nV p-p input voltage noise, 0.1 Hz to 10 Hz Low distortion

−120 dB total harmonic distortion at 20 kHz

Excellent AC characteristics

800 ns settling time to 16 bits (10 V step) 110 MHz gain bandwidth (G = 1000) 8 MHz bandwidth (G = 10) 280 kHz full power bandwidth at 20 V p-p 20 V/μs slew rate

Excellent DC precision

80 μV max input offset voltage

1.0 μV/°C V

OS

drift Specified for ±5 V and ±15 V power supplies High output drive current of 50 mA

APPLICATIONS

Professional audio preamplifiers IR, CCD, and sonar imaging systems Spectrum analyzers Ultrasound preamplifiers Seismic detectors ΣΔ ADC/DAC buffers

–IN +IN 3

–V

S

1 2

4

AD797

TOP VIEW

OFFSET NULL

Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] and

8-Lead Standard Small Outline Package [SOIC_N]

GENERAL DESCRIPTION

The AD797 is a very low noise, low distortion operational amplifier ideal for use as a preamplifier. The low noise of

0.9 nV/√Hz and low total harmonic distortion of −120 dB at audio bandwidths give the AD797 the wide dynamic range necessary for preamps in microphones and mixing consoles.

Furthermore, the AD797’s excellent slew rate of 20 V/μs and 110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications.

The AD797 is also useful in IR and sonar imaging applications where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for buffering the inputs to ΣΔ ADCs or the outputs of high resolution DACs especially when used in critical applications such as seismic detection and spectrum analyzers. Key features such as a 50 mA output current drive and the specified power supply voltage range of ±5 V to ±15 V make the AD797 an excellent general-purpose amplifier.

8 7 6 5

DECOMPENSATION AND DISTORTION NEUTRALIZATION

+V

S

OUTPUT OFFSET NULL

AD797

00846-001

5

4

Hz)

3

2

1

INPUT VOLTAGE NOISE (nV/

0

100

10

FREQUENCY (Hz)

10M

1M100k10k1k

00846-002

Figure 2. AD797 Voltage Noise Spectral Density

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

–90

–100

–110

THD (dB)

–120

MEASUREMENT LIMIT

–130

300100

FREQUENCY (Hz)

Figure 3. THD vs. Frequency

100k30k10k3k1k

300k

0.001

0.0003

THD (%)

0.0001

00846-003

AD797

SPECIFICATIONS

@ TA = +25°C and VS = ±15 V dc, unless otherwise noted.

Table 1.

AD797A AD797B Parameter Conditions V Min Typ Max Min Typ Max Unit

INPUT OFFSET VOLTAGE ±5 V, ±15 V 25 80 10 40 μV T

Offset Voltage Drift ±5 V, ±15 V 0.2 1.0 0.2 0.6 μV/°C INPUT BIAS CURRENT ±5 V, ±15 V 0.25 1.5 0.25 0.9 μA T INPUT OFFSET CURRENT ±5 V, ±15 V 100 400 80 200 nA T OPEN-LOOP GAIN V R T R T @ 20 kHz1 DYNAMIC PERFORMANCE

Gain Bandwidth Product G = 1000 ±15 V 110 110 MHz

G = 1000

–3 dB Bandwidth G = 10 ±15 V 8 8 MHz

Full Power Bandwidth

1

R

Slew Rate R

Settling Time to 0.0015% 10 V step ±15 V 800 1200 800 1200 ns COMMON-MODE REJECTION VCM = CMVR ±5 V, ±15 V 114 130 120 130 dB T POWER SUPPLY REJECTION VS = ±5 V to ±18 V 114 130 120 114 dB T INPUT VOLTAGE NOISE f = 0.1 Hz to 10 Hz ±15 V 50 50 nV p-p f = 10 Hz ±15 V 1.7 1.7 2.5 nV/√Hz f = 1 kHz ±15 V 0.9 1.2 0.9 1.2 nV/√Hz f = 10 Hz to 1 MHz ±15 V 1.0 1.3 1.0 1.2 μV rms INPUT CURRENT NOISE f = 1 kHz ±15 V 2.0 2.0 pA/√Hz INPUT COMMON-MODE VOLTAGE RANGE ±15 V ±11 ±12 ±11 ±12 V ±5 V ±2.5 ±3 ±2.5 ±3 V OUTPUT VOLTAGE SWING R R R

Short-Circuit Current ±5 V, ±15 V 80 80 mA

Output Current3 ±5 V, ±15 V 30 50 30 50 mA TOTAL HARMONIC DISTORTION R f = 250 kHz, 3 V rms R f = 20 kHz, 3 V rms INPUT CHARACTERISTICS

Input Resistance (Differential) 7.5 7.5 kΩ

Input Resistance (Common Mode) 100 100 MΩ

Input Capacitance (Differential)4 20 20 pF

Input Capacitance (Common Mode) 5 5 pF

to T

MIN

MAX

to T

MIN

MAX

to T

MIN

MAX

= ±10 V ±15 V 1 20 2 20 V/μV

OUT

= 2 kΩ 1 6 2 10 V/μV

LOAD

to T

MIN

MAX

= 600 Ω 1 5 2 7 V/μV

LOAD

to T

MIN

MAX

2

50 125/180 30 60 μV

0.5 3.0 0.25 2.0 μA

120 600/700 120 300 nA

1 15 2 15 V/μV

14000 20000 14000 20000 V/V

15 V 450 450 MHz

VO = 20 V p-p,

= 1 kΩ ±15 V 280 280 kHz

LOAD

= 1 kΩ ±15 V 12.5 20 12.5 20 V/μs

LOAD

to T

MIN

MAX

to T

MIN

MAX

= 2 kΩ ±15 V ±12 ±13 ±12 ±13 V

LOAD

= 600 Ω ±15 V ±11 ±13 ±11 ±13 V

LOAD

= 600 Ω ±5 V ±2.5 ±3 ±2.5 ±3 V

LOAD

= 1 kΩ, CN = 50 pF ±15 V −98 –90 –98 –90 dB

LOAD

= 1 kΩ ±15 V –120 –110 –120 –110 dB

LOAD

110 120 114 120 dB

110 120 130 120 dB

Rev. E | Page 3 of 20

AD797

AD797A AD797B Parameter Conditions V Min Typ Max Min Typ Max Unit

OUTPUT RESISTANCE AV = +1, f = 1 kHz 3 3 mΩ POWER SUPPLY

Operating Range ±5 ±18 ±5 ±18 V Quiescent Current ±5 V, ±15 V 8.2 10.5 8.2 10.5 mA

1

Full Power Bandwidth = Slew Rate/2 π V

2

Specified using external decompensation capacitor; see Applications section.

3

Output current for |V – V | > 4 V, A > 200 kΩ.

4

Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.

S OUT OL

PEAK

.

Rev. E | Page 4 of 20

AD797

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Ratings

Supply Voltage ±18 V Internal Power Dissipation @ 25°C

1

Input Voltage ±V Differential Input Voltage

2

Output Short-Circuit Duration

S

±0.7 V Indefinite Within

Max Internal

Power Dissipation Storage Temperature Range (Cerdip) −65°C to +150°C Storage Temperature Range (N, R Suffix) −65°C to +125°C Operating Temperature Range

AD797A/B −40°C to +85°C Lead Temperature Range (Soldering 60 sec) 300°C

1

Internal Power Dissipation:

8-Lead SOIC = 0.9 W (T –25°C)/θ

8-Lead Plastic DIP and Cerdip = 1.3 W − (T –25°C)/θ

Thermal Characteristics

8-Lead Plastic DIP Package: θJA = 95°C/W

8-Lead Small Outline Package: θJA = 155°C/W

2

The AD797’s inputs are protected by back-to-back diodes. To achieve low noise, internal current limiting resistors are not incorporated into the design of this amplifier. If the differential input voltage exceeds ±0.7 V, the input current should be limited to less than 25 mA by series protection resistors. Note, however, that this degrades the low noise performance of the device.

A JA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these products feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. E | Page 5 of 20

AD797

TYPICAL PERFORMANCE CHARACTERISTICS

20

15

10

5

INPUT COMMON-MODE RANGE (±V)

VERTICAL SCALE (0.01μV/DIV)

0

5

10 15

SUPPLY VOLTAGE (±V)

Figure 4. Common-Mode Voltage Range vs. Supply

20

15

OUTPUT VOLTAGE SWING (±V)

10

–V

OUT

5

0

5

SUPPLY VOLTAGE (±V)

+V

OUT

10

Figure 5. Output Voltage Swing vs. Supply

30

VS= ±15V

20

00846-004

HORIZONTAL SCALE (5sec/DIV)

00846-007

Figure 7. 0.1 Hz to 10 Hz Noise

0

–0.5

–1.0

INPUT AS CURRENT (μA)

–1.5

00846-005

15

20

–2.0

–60 140–40 100 120806040200–20

TEMPERATURE (°C)

00846-008

Figure 8. Input Bias Current vs. Temperature

140

120

20

10

OUTPUT VOLTAGE SWING (V p-p)

0

10 100 10k1k

VS =±5

LOAD RESISTANCE (Ω)

Figure 6. Output Voltage Swing vs. Load Resistance

00846-006

Rev. E | Page 6 of 20

100

80

SHORT-CIRCUIT CURRENT (mA)

60

40

–60

SINK CURRENT

–40

TEMPERATURE (°C)

SOURCE CURRENT

Figure 9. Short-Circuit Current vs. Temperature

00846-009

140

6040200–20

80

120100

AD797

11

140

10

9

8

7

QUIESCENT SUPPLY CURRENT (mA)

6

+125°C

+25°C

–55°C

10

SUPPLY VOLTAGE (±V)

Figure 10. Quiescent Supply Current vs. Supply Voltage

1

2

FREQ = 1kHz R

= 600Ω

L

G = +10

9

6

3

OUTPUT VOLTAGE (V rms)

120

100

80

60

POWER SUPPLY REJECTION (dB)

40

00846-010

205150

20

10

1

PSR

–SUPPLY

FREQUENCY (Hz)

PSR +SUPPLY

CMR

100k10k1k100

1M

Figure 13. Power Supply and Common-Mode Rejection vs. Frequency

–60

RL = 600Ω G = +10 FREQ = 10kHz NOISE BW = 100kHz

–80

V

=

±5V

S

–100

THD + NOISE (dB)

VS=±1

5V

150

125

100

75

50

COMMON MODE REJECTION (dB)

00846-013

0

±5

±10 ±15

SUPPLY VOLTAGE (±V)

Figure 11. Output Voltage vs. Supply for 0.01% Distortion

1.0

0.8

0.0015%

0.6

0.01%

0.4

SETTLING TIME (μs)

0.2

0

2

STEP SIZE (V)

864

Figure 12. Settling Time vs. Step Size (±)

±20

10

00846-011

00846-012

–120

0.01 0.1 101 OUTPUT LEVEL (V)

Figure 14. Total Harmonic Distortion (THD) + Noise vs. Output Level

30

±15V SUPPLIES

20

10

OUTPUT VOLTAGE (V p-p)

±5V SUPPLIES

0

10k 100k 10M1M

FREQUENCY (Hz)

RL = 600

Ω

Figure 15. Large Signal Frequency Response

00846-014

00846-015

Rev. E | Page 7 of 20

AD797

5

35

120

4

3

2

1

INPUT VOLTAGE NOISE (nV/ Hz)

0

100

10

FREQUENCY (Hz)

Figure 16. Input Voltage Noise Spectral Density

120

100

80

60

40

OPEN-LOOP GAIN (dB)

20

0

100

*RS = 100

1k

PHASE MARGIN

WITH

GAIN

WITH

FREQUENCY (Hz)

Figure 17. Open-Loop Gain and Phase vs. Frequency

Figure 25

*See

300

R

*

S

R

S

WITHOUT

*

1M100k10k1k

WITHOUT

R

*

S

R

*

S

10M1M100k10k

10M

100M

100

80

60

40

20

0

00846-016

00846-017

PHASE MARGIN (Degrees)

30

μs)

25

SLEW RATE (V/

20

15

–60 140–40 100 120806040200–20

GAIN/BANDWIDTH PRODUCT

SLEW RATE

RISING EDGE

SLEW RATE FALLING EDGE

TEMPERATURE (°C)

Figure 19. Slew Rate and Gain/Bandwidth Product vs. Temperature

160

140

120

OPEN-LOOP GAIN (dB)

100

100 10k

LOAD RESISTANCE (Ω)

1k

Figure 20. Open-Loop Gain vs. Resistive Load

100

110

(MHz (G = 1000))

100

90

GAIN/BANDWIDTH PRODUCT

80

00846-019

00846-020

150

0

–150

INPUT OFFSET CURRENT (nA)

–300

–60 140–40 100 120806040200–20

OVER COMPENSATED

UNDER COMPENSATED

TEMPERATURE (°C)

Figure 18. Input Offset Current vs. Temperature

Ω)

10

1

0.1

00846-018

MAGNITUDE OF OUTPUT IMPEDANCE (

0.01 10 1M

100

WITHOUT C

FREQUENCY (Hz)

*

N

WITH CN*

10k 100k1k

Figure 21. Magnitude of Output Impedance vs. Frequency

Figure 32

*See

Rev. E | Page 8 of 20

00846-021

AD797

20pF

1kΩ

+V

S

**

1kΩ

V

IN

2

AD797

3

7

6

4

V

OUT

**

–V

S

00846-022

RS*

V

IN

* VALUE OF SOURCE RESISTANCE SEE TEXT

2

AD797

3

100Ω

+V

4

–V

S

**

7

6

V

OUT

600Ω

**

S

00846-025

Figure 22. Inverter Connection

Figure 35

**See

100 90

10 0%

5V

Figure 23. Inverter Large Signal Pulse Response

100

90

1μs

Figure 25. Follower Connection

Figure 35

**See

1μs

5V

100 90

10 0%

00846-023

00846-026

Figure 26. Follower Large Signal Pulse Response

100ns50mV

100

90

100ns50mV

10 0%

00846-024

10 0%

Figure 24. Inverter Small Signal Pulse Response Figure 27. Follower Small Signal Pulse Response

Rev. E | Page 9 of 20

00846-027

AD797

500ns50mV

100

90

10 0%

00846-028

100

90

10 0%

Figure 28. 16-Bit Settling Time Positive Input Pulse Figure 29. 16-Bit Settling Time Negative Input Pulse

500ns50mV

00846-029

Rev. E | Page 10 of 20

AD797

THEORY OF OPERATION

The architecture of the AD797 was developed to overcome inherent limitations in previous amplifier designs. Previous precision amplifiers used three stages to ensure high open-loop gain (

Figure 30) at the expense of additional frequency compensation components. Slew rate and settling performance are usually compromised, and dynamic performance is not adequate beyond audio frequencies. As can be seen in Figure 30, the first stage gain is rolled off at high frequencies by the compensation network. Second stage noise and distortion then appears at the input and degrade performance. The AD797 on the other hand, uses a single ultrahigh gain stage to achieve dc as well as dynamic precision. As shown in the simplified schematic (

Figure 31), Node A, Node B, and Node C all track in voltage forcing the operating points of all pairs of devices in the signal path to match. By exploiting the inherent matching of devices fabricated on the same IC chip, high open-loop gain, CMRR, PSRR, and low V

are all guaranteed by pairwise

OS

device matching (that is., NPN to NPN and PNP to PNP), and not absolute parameter such as beta and early voltage.

gm

R1

GAIN = gm x R1 x 5 x 10

BUFFER

C1

6

a.

C2

V

OUT

R

L

This matching benefits not just dc precision, but because it holds up dynamically, both distortion and settling time are also reduced. This single stage has a voltage gain of >5 × 10

6

and VOS <80 μV, while at the same time providing THD + noise of less than −120 dB and true 16-bit settling in less than 800 ns. The elimination of second stage noise effects has the additional benefit of making the low noise of the AD797 (<0.9 nV/√Hz) extend to beyond 1 MHz. This means new levels of performance for sampled data and imaging systems. All of this performance as well as load drive in excess of 30 mA are made possible by Analog Devices’ advanced Complementary Bipolar (CB) process.

Another unique feature of this circuit is that the addition of a single capacitor, C

(Figure 31), enables cancellation of

N

distortion due to the output stage. This can best be explained by referring to a simplified representation of the AD797 using idealized blocks for the different circuit elements (

Figure 32).

A single equation yields the open-loop transfer function of this amplifier, solving it (at Node B) yields:

V

O

=

C

V

N

IN

A

gm

N

C

ω−ω−ω

jCj

j

A

where:

gm = the transconductance of Q1 and Q2

gm

A2 A3

R1

C1

R2

GAIN = gm x R1 x A2 x A3

b.

BUFFER

Figure 30. Model of AD797 vs. That of a Typical Three-Stage Amplifier

R2

+IN

Q1 Q2

R3

–IN

C

N

Q3

AB

Q5CQ6

R1 I5

Q4

Q7

C

I7I1 I4

Q12 Q8

Figure 31. AD797 Simplified Schematic

Q9

I6

R

Q10

Q11

V

OUT

L

00846-030

A = the gain of the output stage, (~1)

= voltage at the output

V

O

= differential input voltage

V

IN

When C

is equal to CC this gives the ideal single pole op amp

N

response:

V

gm

V

CC

O

V

IN

=

Cj

ω

The terms in A, which include the properties of the output stage such as output impedance and distortion, cancel by simple subtraction. Therefore, the distortion cancellation does not

OUT

affect the stability or frequency response of the amplifier. With only 500 μA of output stage bias, the AD797 delivers a 1 kHz sine wave into 60 Ω at 7 V rms with only 1 ppm of distortion.

V

SS

00846-031

Rev. E | Page 11 of 20

AD797

I1 I2

Q1 Q2

–IN+IN

I3 C

Figure 32. AD797 Block Diagram

NOISE AND SOURCE IMPEDANCE CONSIDERATIONS

The AD797’s ultralow voltage noise of 0.9 nV/√Hz is achieved with special input transistors running at nearly 1 mA of collector current. It is important then to consider the total input referred noise (e from voltage noise (e (√4 kTr

where rS = total input source resistance.

This equation is plotted for the AD797 in optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total r

At very low source resistance (r noise dominates. As source resistance increases, the Johnson noise of r current noise component is larger than the resistor noise.

).

S

2

dominates until at higher resistances (rS > 2 kΩ); the

S

100

10

NOISE (nV/ Hz)

1

C

N

B

A

C

CURRENT

MIRROR

I4

total), which includes contributions

N

), current noise (iN), and resistor noise

N

C

1

2/12

(1)

])/(4[

rikTretotale ++=

SNSNN

Figure 33. Because

by a factor of two.

S

<50 Ω), the amplifiers’ voltage

S

TOTAL NOISE

RESISTOR NOISE ONLY

OUT

00846-032

The AD797 is the optimum choice for low noise performance provided the source resistance is kept <1 kΩ. At higher values of source resistance, optimum performance with respect to noise alone is obtained with other amplifiers from Analog Devices (

Table 3).

Table 3. Recommended Amplifiers for Different Source Impedances

r

, ohms Recommended Amplifier

S

0 to <1 kΩ AD797 1 kΩ to <10 kΩ AD743/AD745, OP27/OP37, OP07 10 kΩ to <100 kΩ AD743/AD745, OP07 >100 kΩ AD548, AD549, AD711, AD743/AD745

LOW FREQUENCY NOISE

Analog Devices specifies low frequency noise as a peak-to-peak (p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several techniques can be used to make this measurement. The usual technique involves amplifying, filtering, and measuring the amplifier’s noise for a predetermined test time. The noise bandwidth of the filter is corrected for, and the test time is carefully controlled because the measurement time acts as an additional low frequency roll-off.

The plot in FFT based instrument ( “brickwall” filter. A low frequency pole at 0.1 Hz is generated with an external ac coupling capacitor, the instrument being dc coupled.

Several precautions are necessary to get optimum low frequency noise performance.

• Care must be used to account for the effects of rS. Even

• The test setup must be fully warmed up to prevent eOS

• Circuitry must be shielded from air currents. Heat flow out

• The results must be interpreted using valid statistical

Figure 7 uses a slightly different technique. Here an

Figure 34) is used to generate a 10 Hz

a 10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9% when root sum squared with 0.9 nV/√Hz).

drift from erroneously contributing to input noise.

of the package through its leads creates the opportunity for a thermoelectric potential at every junction of different metals. Selective heating and cooling of these by random air currents appears as 1/f noise and obscure the true device noise.

techniques.

0.1 10 100 1000 10000

SOURCE RESISTANCE (Ω)

Figure 33. Noise vs. Source Resistance

00846-033

Rev. E | Page 12 of 20

AD797

0

VSV

1Ω

2

3

100kΩ

+V

7

AD797

4

–V

S

**

1.5μF

6

V

OUT

**

S

HP 3465 DYNAMIC SIGNAL ANALYZER (10Hz)

Figure 34. Test Setup for Measuring 0.1 Hz to 10 Hz Noise

**Use Power Supply Bypassing Shown in

Figure 35

WIDEBAND NOISE

Due to its single stage design, the noise of the AD797 is flat over frequencies from less than 10 Hz to beyond 1 MHz. This is not true of most dc precision amplifiers where second stage noise contributes to input referred noise beyond the audio frequency range. The AD797 offers new levels of performance in wideband imaging applications. In sampled data systems, where aliasing of out of band noise into the signal band is a problem, the AD797 outperforms all previously available IC op amps.

BYPASSING CONSIDERATIONS

Taking full advantage of the very wide bandwidth and dynamic range capabilities of the AD797 requires some precautions. First, multiple bypassing is recommended in any precision application. A 1.0 μF to 4.7 μF tantalum in parallel with 0.1 μF ceramic bypass capacitors are sufficient in most applications. When driving heavy loads a larger demand is placed on the supply bypassing. In this case, selective use of larger values of tantalum capacitors and damping of their lead inductance with small value (1.1 Ω to 4.7 Ω) carbon resistors can be an improvement.

Figure 35 summarizes bypassing recommendations. The symbol (**) is used throughout this data sheet to represent the parallel combination of a 0.1 μF and a 4.7 μF capacitor.

S

0.1μF 4.7μF TO 22.0μF

1.1μF TO 4.7μF

KELVIN RETURN

USE SHORT LEAD LENGTHS (< 5mm)

LOAD CURRENT

.1μF

USE SHORT LEAD LENGTHS (< 5mm)

OR

4.7μF

KELVIN RETURN

LOAD CURRENT

Figure 35. Recommended Power Supply Bypassing

00846-034

00846-035

THE NONINVERTING CONFIGURATION

Ultralow noise requires very low values of rBB (the internal parasitic resistance) for the input transistors (≈6 Ω). This implies very little damping of input and output reactive interactions. With the AD797, additional input series damping is required for stability with direct input to output feedback. A 100 Ω resistor in the inverting input ( the 100 Ω balancing resistor (R2) is recommended but is not required for stability. The noise penalty is minimal (e

2.1 nV/√Hz), which is usually insignificant. Best response flatness is obtained with the addition of a small capacitor (C

< 33 pF) in parallel with the 100 Ω resistor (Figure 37). The

L

input source resistance and capacitance also affects the response slightly, and experimentation may be necessary for best results.

R1

100Ω

+V

S

2

7

3

AD797

4

–V

S

R2

100Ω

V

N

I

Figure 36. Voltage Follower Connection

**Use Power Supply Bypassing Shown in

Low noise preamplification is usually done in the noninverting

Figure 38). For lowest noise, the equivalent resistance of

mode ( the feedback network should be as low as possible. The 30 mA minimum drive current of the AD797 makes it easier to achieve this. The feedback resistors can be made as low as possible with due consideration to load drive and power consumption. Table 4 gives some representative values for the AD797 as a low noise follower. Operation on 5 volt supplies allows the use of a 100 Ω or less feedback network (R1 + R2). Because the AD797 shows no unusual behavior when operating near its maximum rated current, it is suitable for driving the AD600/AD602 (

Figure 50) while preserving their low noise performance.

Optimum flatness and stability at noise gains >1 sometimes require a small capacitor (C resistor (R1, of C

L

100 Ω and C

Figure 38). Table 4 includes recommended values

for several gains. In general, when R2 is greater than

is greater than 33 pF, a 100 Ω resistor should be

L

placed in series with C

) connected across the feedback

L

. Source resistance matching is assumed,

L

and the AD797 should never be operated with unbalanced source resistance >200 kΩ/G.

Figure 36) is sufficient;

N

**

6

**

V

R

L

600Ω

Figure 35

U

O

total ≈

T

00846-036

Rev. E | Page 13 of 20

AD797

C

V

RS*

N

I

*

C

S

*SEE TEXT

Figure 37. Alternative Voltage Follower Connection

**Use Power Supply Bypassing Shown in

2

3

C

L

100Ω

+V

7

AD797

4

–V

S

**

600Ω

V

U

O

T

00846-037

6

**

S

Figure 35

C

L

R2

+V

S

R1

2

AD797

N

I

3

Figure 38. Low Noise Preamplifier

**Use Power Supply Bypassing Shown in

**

7

6

4

**

–V

S

V

T

U

O

R

L

00846-038

Figure 35

Table 4. Values for Follower with Gain Circuit

Noise Gain R1 R2 CL (Excluding r )

S

2 1 kΩ 1 kΩ ≈20 pF 3.0 nV/√Hz 2 300 Ω 300 Ω ≈10 pF 1.8 nV/√Hz 10 33.2 Ω 300 Ω ≈5 pF 1.2 nV/√Hz 20 16.5 Ω 316 Ω 1.0 nV/√Hz >35 10 Ω (G − 1) × 10 Ω 0.98 nV/√Hz

The I-to-V converter is a special case of the follower configuration. When the AD797 is used in an I-to-V converter, for example as a DAC buffer, the circuit of used. The value of C

depends on the DAC and again, if CL

L

Figure 39 should be

is greater than 33 pF, a 100 Ω series resistor is required. A bypassed balancing resistor (R

and CS) can be included to

S

minimize dc errors.

20pF TO 120pF

I

IN

2

AD797

3

*

S

*SEE TEXT

RS*

Figure 39. I-to-V Converter Connection

**Use Power Supply Bypassing Shown in

100Ω

R

1

+V

S

**

7

6

4

**

–V

S

600Ω

V

U

O

T

00846-039

Figure 35

THE INVERTING CONFIGURATION

The inverting configuration (Figure 40) presents a low input impedance, R1, to the source. For this reason, the goals of both low noise and input buffering are at odds with one another. Nonetheless, the excellent dynamics of the AD797 makes it the preferred choice in many inverting applications, and with careful selection of feedback resistors, the noise penalties are minimal. Some examples are presented in Figure 40.

C

L

R

2

+V

S

R1

V

N

I

RS*

*SEE TEXT

2

AD797

3

**

7

6

4

**

–V

S

Figure 40. Inverting Amplifier Connection

**Use Power Supply Bypassing Shown in

Table 5. Values for Inverting Circuit

Noise Gain R1 R2 CL (Excluding r )

−1 1 kΩ 1 kΩ ≈20 pF 3.0 nV/√Hz

−1 300 Ω 300 Ω ≈10 pF 1.8 nV/√Hz

−10 150 Ω 1500 Ω ≈5 pF 1.8 nV/√Hz

Table 4 and

V

T

U

O

R

L

00846-040

Figure 35

S

Rev. E | Page 14 of 20

AD797

DRIVING CAPACITIVE LOADS

The capacitive load driving capabilities of the AD797 are displayed in precautions are necessary. If more drive is desirable the circuit in

Figure 42 should be used. Here a 5000 pF load can be driven

cleanly at any noise gain ≥2.

Figure 41. At gains over 10, usually no special

100nF

10nF

1nF

100pF

10pF

CAPACITIVE LOAD DRIVE CAPABILITY

1pF

11k

CLOSED-LOOP GAIN

10010

Figure 41. Capacitive Load Drive Capability vs. Closed-Loop Gain

20pF

00846-041

226Ω

2x

HP2835

TEKTRONIX

CALIBRATION

FIXTURE

0.47μF

1kΩ 1kΩ

V

IN

1kΩ

1μF 0.1μF

Figure 43. Settling Time Test Circuit

4.26kΩ

2

AD829

3

100Ω

2

3

A2

–V

AD797

TO TEKTRONIX

OSCILLOSCOPE

PREAMP INPUT

SECTION

6

7

4

0.47μF

+V

S

1kΩ

20pF

A1

7

4

1μF 0.1μF

+V

S

–V

S

7A26

1MΩ

(VIA LESS THAN 1FT 50Ω COAXIAL CABLE)

250Ω

6

V

ER

2x HP2835

NOTE: USE CIRCUIT BOARD WITH GROUND PLANE

51pF

20pF

O

R

00846-043

5

X

R

1kΩ

200pF

1kΩ

V

N

I

2

3

Figure 42. Recommended Circuit for Driving a High Capacitance Load

**Use Power Supply Bypassing Shown in

+V

7

AD797

4

–V

100Ω

S

**

6

**

S

33Ω

V

T

U

O

C1

00846-042

Figure 35

SETTLING TIME

The AD797 is unique among ultralow noise amplifiers in that it settles to 16 bits (<150 μV) in less than 800 ns. Measuring this performance presents a challenge. A special test setup (

Figure 43) was developed for this purpose. The input signal was obtained from a resonant reed switch pulse generator, available from Tektronix as calibration Fixture No. 067-0608-00. When open, the switch is simply 50 Ω to ground and settling is purely a passive pulse decay and inherently flat. The low repetition rate signal was captured on a digital oscilloscope after being amplified and clamped twice. The selection of plug-in for the oscilloscope was made for minimum overload recovery.

DISTORTION REDUCTION

The AD797 has distortion performance (THD < −120 dB, @ 20 kHz, 3 V rms, R feedback amplifiers.

At higher gains and higher frequencies, THD increases due to reduction in loop gain. However, in contrast to most conventional voltage feedback amplifiers, the AD797 provides two effective means of reducing distortion as gain and frequency are increased: cancellation of the output stage’s distortion, and gain bandwidth enhancement by decompensation. By applying these techniques, gain bandwidth can be increased to 450 MHz at G = 1000, and distortion can be held to −100 dB at 20 kHz for G = 100.

The unique design of the AD797 provides for cancellation of the output stage’s distortion. To achieve this, a capacitance equal to the effective compensation capacitance, usually 50 pF, is connected between Pin 8 and the output (C2 in Use of this feature improves distortion performance when the closed-loop gain is more than 10 or when frequencies of interest are greater than 30 kHz.

Bandwidth enhancement via decompensation is achieved by connecting a capacitor from Pin 8 to ground (C1 in effectively subtracting from the value of the internal compensation capacitance (50 pF), yielding a smaller effective compensation capacitance and, therefore, a larger bandwidth.

= 600 Ω) unequaled by most voltage

L

Figure 42).

Figure 44)

Rev. E | Page 15 of 20

AD797

V

The benefits of this begin at closed-loop gains of 100 and up. A maximum value of ≈33 pF at gains of 1000 and up is recommended. At a gain of 1000, the bandwidth is 450 kHz.

Table 6 and Figure 45 summarize the performance of the AD797 with distortion cancellation and decompensation.

R1

50pF

R2

N

I

R2

N

I

Figure 44. Recommended Connections for Distortion Cancellation

2

3

2

3

a.

R1

.

b

AD797

8

6

C2

C1

8

6

C1, SEE TABLE C2 = 50pF – C1

00846-044

and Bandwidth Enhancement

Table 6. Recommended External Compensation

A/B A B Gain R1 R2 C1 C2 3 dB C1 C2 3 dB

Ω Ω pF pF BW pF pF BW

10 909 100 0 50 6 MHz 0 50 6 MHz 100 1 k 10 0 50 1 MHz 15 33 1.5 MHz 1000 10 k 10 0 50 110 kHz 33 15 450 kHz

–80

–90

–100

THD (dB)

–110

–120

NOISE LIMIT, G = +1000

NOISE LIMIT, G = +100

300100

FREQUENCY (Hz)

G = +1000 R

= 600Ω

L

G = +1000

= 10kΩ

R

L

G = +100 R

= 600Ω

L

G = +10 R

= 600Ω

L

100k30k10k3k1k

0.01

0.003

0.001

0.0003

0.0001

300k

Figure 45. Total Harmonic Distortion (THD) vs. Frequency @ 3 V rms

for

Figure 44b.

Differential Line Receiver

The differential receiver circuit of Figure 46 is useful for many applications from audio to MRI imaging. It allows extraction of a low level signal in the presence of common-mode noise. As shown in 9 nV/√Hz noise at the output.

Figure 47, the AD797 provides this function with only

Figure 45 shows the AD797’s 20-bit THD performance over the audio band and 16-bit accuracy to 250 kHz.

20pF

1kΩ

DIFFERENTIAL

INPUT

1kΩ

+V

2

3

S

7

AD797

1kΩ

**

50pF*

8

6

4

**

–V

OUTPUT

*OPTIONAL

S

THD (%)

00846-045

20pF

Figure 46. Differential Line Receiver

**Use Power Supply Bypassing Shown in

00846-046

Figure 35

Rev. E | Page 16 of 20

AD797

Ω

16

R2

14

12

10

INPUT

8

OUTPUT VOLTAGE NOISE (nV/ Hz)

6

100

10

FREQUENCY (Hz)

1M100k10k1k

Figure 47. Output Voltage Noise Spectral Density

for Differential Line Receiver

–90

00846-047

10M

Figure 49. A General Purpose ATE/Instrumentation Input/Output Driver

0.003

2

1kΩ

3

**Use Power Supply Bypassing Shown in

+V

7

AD797

4

–V

22pF

S

2kΩ

**

6

**

649Ω

3

2

649Ω

+V

7

AD811

4

–V

S

6

**

S

Figure 35

**

00846-049

Ultrasound/Sonar Imaging Preamp

–100

WITHOUT OPTIONAL 50pF C

N

0.001

The AD600 variable gain amplifier provides the time controlled gain (TCG) function necessary for very wide dynamic range sonar and low frequency ultrasound applications. Under some circumstances, it is necessary to buffer the input of the AD600

(dB)

–110

THD

MEASUREMENT

LIMIT

0.0003

THD (%)

to preserve its low noise performance. To optimize dynamic range this buffer should have at most 6 dB of gain. The combination of low noise and low gain is difficult to achieve. The

300k

0.0001

00846-048

input buffer circuit shown in

Figure 50 provides 1 nV/√Hz

noise performance at a gain of two (dc to 1 MHz) by using

26.1 Ω resistors in its feedback path. Distortion is only −50 dBc @ 1 MHz at a 2 V p-p output level and drops rapidly to better than −70 dBc at an output level of 200 mV p-p.

26.1

–120

WITH

OPTIONAL

50C

–130

300100

FREQUENCY (Hz)

N

Figure 48. Total Harmonic Distortion (THD) vs. Frequency

for Differential Line Receiver

100k30k10k3k1k

A General Purpose ATE/Instrumentation Input/Output Driver

The ultralow noise and distortion of the AD797 may be combined with the wide bandwidth, slew rate, and load drive of a current feedback amplifier to yield a very wide dynamic range general purpose driver. The circuit of

Figure 49 combines

26.1Ω

INPUT

2

3

+V

7

AD797

4

–V

S

**

6

**

S

AD600

VS= ±6Vdc

**

V

OUT

**

the AD797 with the AD811 in just such an application. Using the component values shown, this circuit is capable of better than −90 dB THD with a ±5 V, 500 kHz output signal. The circuit is therefore suitable for driving high resolution A/D converters and as an output driver in automatic test equipment

Figure 50. An Ultrasound Preamplifier Circuit

**Use Power Supply Bypassing Shown in

Figure 35

00846-050

(ATE) systems. Using a 100 kHz sine wave, the circuit drives a 600 Ω load to a level of 7 V rms with less than −109 dB THD and a 10 kΩ load at less than −117 dB THD.

Rev. E | Page 17 of 20

AD797

Amorphous (Photodiode) Detector Professional Audio Signal Processing—DAC Buffers

Large area photodiodes (CS ≥ 500 pF) and certain image detectors (amorphous Si) have optimum performance when used in conjunction with amplifiers with very low voltage rather than very low current noise. with an amorphous Si (C adjusted for flatness using capacitor C

Figure 51 shows the AD797 used

= 1000 pF) detector. The response is

S

, while the noise is

L

dominated by voltage noise amplified by the ac noise gain. The AD797’s excellent input noise performance gives 27 μV rms total noise in a 1 MHz bandwidth, as shown by

C

100Ω

50pF

10kΩ

+V

S

2

7

C

I

S

**Use Power Supply Bypassing Shown in

S

1000pF

3

AD797

4

–V

S

Figure 51. Amorphous Detector Preamp

L

**

6

**

Figure 35

Figure 48.

00846-051

–30

100

The low noise and low distortion of the AD797 make it an ideal choice for professional audio signal processing. An ideal I-to-V converter for a current output DAC would simply be a resistor to ground, were it not for the fact that most DACs do not operate linearly with voltage on their output. Standard practice is to operate an op amp as an I-to-V converter creating a virtual ground at its inverting input. Normally, clock energy and current steps must be absorbed by the op amp’s output stage. However, in the configuration of

Figure 53, Capacitor CF shunts high frequency energy to ground, while correctly reproducing the desired output with extremely low THD and IMD.

C

F

82pF

AD1862

DAC

2000pF

2

C1

AD797

3

Figure 53. A Professional Audio DAC Buffer

**Use Power Supply Bypassing Shown in

3kΩ

+V

–V

100Ω

S

**

7

6

4

**

S

00846-053

Figure 35

OUT

80

60

40

20

VOLTAG E NO ISE (mV rms (0.1Hz FREQUENCY))

0

100M1k100

00846-052

Figure 54. Offset Null Configuration

2

3

AD797

4

–V

S

+V

S

7

6

5

1

20kΩ

VOSADJUST

00846-054

–40

–50

(dB Re 1V/ μA)

–60

OUT

V

–70

–80

V

OUT

FREQUENCY (Hz)

NOISE

10M1M100k10k

Figure 52. Total Integrated Voltage Noise and V

of Amorphous Detector Preamp

Rev. E | Page 18 of 20

AD797

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

8

1

PIN 1

0.100 (2.54)

MAX

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 55. 8-Lead Plastic Dual In-Line Package [PDIP]

5

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

4

BSC

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

COMPLIANT TO JEDEC STANDARDS MS-001-BA

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

MAX

Narrow Body (N-8)

Dimensions shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

Rev. E | Page 19 of 20

AD797

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD797AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD797ANZ AD797AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797ARZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797ARZ-REEL1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797ARZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BRZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BRZ-REEL1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD797BRZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

Z = Pb-free part.

1

−40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8

Rev. E | Page 20 of 20

Datasheet AD797 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES CONNECTION DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

NOISE AND SOURCE IMPEDANCE CONSIDERATIONS

LOW FREQUENCY NOISE

WIDEBAND NOISE

BYPASSING CONSIDERATIONS

THE NONINVERTING CONFIGURATION

THE INVERTING CONFIGURATION

DRIVING CAPACITIVE LOADS

SETTLING TIME

DISTORTION REDUCTION

OUTLINE DIMENSIONS

ORDERING GUIDE