ANALOG DEVICES AD7949 Service Manual

14-Bit, 8-Channel,

V

www.BDTIC.com/ADI

250 kSPS PulSAR ADC

FEATURES

14-bit resolution with no missing codes 8-channel multiplexer with choice of inputs

Unipolar single ended Differential (GND sense)

Pseudobipolar Throughput: 250 kSPS INL/DNL: ±0.5 LSB typical SINAD: 85 dB @ 20 kHz THD: 100 dB @ 20 kHz Analog input range: 0 V to V

with V

REF

up to VDD

REF

Multiple reference types

Internal selectable 2.5 V or 4.096 V

External buffered (up to 4.096 V)

External (up to VDD) Internal temperature sensor Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.7 V to 5.5 V operation with

1.8

V to 5 V logic interface

Serial interface compatible with SPI, MICROWIRE,

SPI, and DSP

Q

Power dissipation

2.9 mW

@ 2.5 V/200 kSPS

10.8 mW @ 5 V/250 kSPS Standby current: 50 nA 20-lead 4 mm × 4 mm LFCSP package

APPLICATIONS

Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Personal digital assistants Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control

IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7

COM

Table 1. Multichannel 14-/16-Bit PulSAR® ADC

Type Channels 250 kSPS 500 kSPS ADC Driver 14-Bit 8 AD7949 ADA4841-x 16-Bit 4 AD7682 ADA4841-x 16-Bit 8 AD7689 AD7699 ADA4841-x

GENERAL DESCRIPTION

The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD.

The AD7949 contains all components for use in a multichannel,

w power data acquisition system, including a true 14-bit SAR

lo ADC with no missing codes; an 8-channel, low crosstalk multiplexer useful for configuring the inputs as single ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7949 uses a simple SPI interface for writing to the co

nfiguration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7949 is housed in a tiny 20-lead LFCSP with operation s

pecified from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

0.5V TO 4.096V

0.1µF

BAND GAP

REF

TEMP

SENSOR

REFIN

MUX

0.5V TO V DD

22µF

ONE-POLE

LPF

Figure 1.

REF

16-BIT SAR

ADC

SEQUENCER

AD7949

SPI SERIAL INTERFACE

2.7V TO 5

VDD

GND

AD7949

1.8V

VIO

TO VDD

CNV

SCK

SDO

DIN

07351-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7949

www.BDTIC.com/ADI

REVISION HISTORY

5/08—Rev. 0 to Rev. A

Changes to Ordering Guide.......................................................... 26

5/08—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD7949

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUT

Voltage Range Unipolar mode 0 +V Bipolar mode −V Absolute Input Voltage Positive input, unipolar and bipolar modes −0.1 V Negative or COM input, unipolar mode −0.1 +0.1 Negative or COM input, bipolar mode V Analog Input CMRR fIN = 250 kHz 68 dB Leakage Current at 25°C Acquisition phase 1 nA Input Impedance

1

THROUGHPUT

Conversion Rate

Full Bandwidth

2

VDD = 4.5 V to 5.5 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 kSPS ¼ Bandwidth

2

VDD = 4.5 V to 5.5 V 0 62.5 kSPS

VDD = 2.3 V to 4.5 V 0 50 kSPS Transient Response Full-scale step, full bandwidth 1.8 s Full-scale step, ¼ bandwidth 14.8 s

ACCURACY

No Missing Codes 14 Bits Integral Linearity Error −1 ±0.5 +1 LSB Differential Linearity Error −1 ±0.25 +1 LSB Transition Noise REF = VDD = 5 V 0.1 LSB Gain Error

4

−5 ±0.5 +5 LSB Gain Error Match −1 ±0.2 +1 LSB Gain Error Temperature Drift ±1 ppm/°C Offset Error

4

±0.5 LSB Offset Error Match −1 ±0.2 +1 LSB Offset Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity

VDD = 5 V ± 5%

= VDD, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

V

3

/2 +V

REF

/2 − 0.1 V

REF

/2 V

REF

/2

REF

+ 0.1 V

REF

/2 + 0.1

REF

±0.2 LSB

Rev. A | Page 3 of 28

AD7949

www.BDTIC.com/ADI

Parameter Conditions/Comments Min Typ Max Unit AC ACCURACY

Dynamic Range 85.6 dB Signal-to-Noise fIN = 20 kHz, VREF = 5 V 84.5 85.5 dB f f SINAD fIN = 20 kHz, VREF = 5 V 84 85 dB f f f Total Harmonic Distortion fIN = 20 kHz −100 dB Spurious-Free Dynamic Range fIN = 20 kHz 108 dB Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s) −125 dB

SAMPLING DYNAMICS

−3 dB Input Bandwidth Selectable 0.425 1.7 MHz Aperture Delay VDD = 5 V 2.5 ns

INTERNAL REFERENCE

REF Output Voltage 2.5 V, @ 25°C 2.490 2.500 2.510 V

4.096 V, @ 25°C 4.086 4.096 4.106 V REFIN Output Voltage

4.096 V, @ 25°C 2.3 V REF Output Current ±300 µA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 10 µF 5 ms

EXTERNAL REFERENCE

Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.2 V Current Drain 250 kSPS, REF = 5 V 50 µA

TEMPERATURE SENSOR

Output Voltage Temperature Sensitivity 1 mV/°C

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Pipeline Delay V

OL

V

OH

5

7

8

6

= 20 kHz, VREF = 4.096 V internal REF 85 dB

IN

= 20 kHz, VREF = 2.5 V internal REF 84 dB

IN

= 20 kHz, VREF = 5 V, −60 dB input 33.5 dB

IN

= 20 kHz, VREF = 4.096 V internal REF 85 dB

IN

= 20 kHz, VREF = 2.5 V internal REF 84 dB

IN

2.5 V, @ 25°C 1.2 V

@ 25°C 283 mV

−0.3 +0.3 × VIO V

0.7 × VIO VIO + 0.3 V

−1 +1 µA

9

10

ISINK = +500 µA 0.4 V ISOURCE = −500 µA VIO − 0.3 V

Rev. A | Page 4 of 28

AD7949

www.BDTIC.com/ADI

Parameter Conditions/Comments Min Typ Max Unit POWER SUPPLIES

VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V

Operating range 1.8 VDD + 0.3 V

Standby Current Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.5 µW VDD = 2.5V, 100 kSPS throughput 1.45 2.0 mW VDD = 2.5 V, 200 kSPS throughput 2.9 4.0 mW VDD = 5 V , 250 kSPS throughput 10.8 12.5 mW

Energy per Conversion 50 nJ

TEMPERATURE RANGE

Specified Performance T

1

See the Analog Inputs section.

2

The bandwidth is set with the configuration register

3

LSB means least significant bit. With the 5 V input range, one LSB = 305 µV.

4

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

5

With VDD = 5 V, unless otherwise noted.

6

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

7

This is the output from the internal band gap.

8

The output voltage is internal and present on a dedicated multiplexer input.

9

Unipolar mode: serial 14-bit straight binary.

Bipolar mode: serial 14-bit twos complement.

10

Conversion results available immediately after completed conversion.

11

With all digital inputs forced to VIO or GND as required.

12

During acquisition phase.

13

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

11, 12

VDD and VIO = 5 V, @ 25°C 50 nA

VDD = 5 V, 250 kSPS throughput with internal

ference

re

13

to T

MIN

MAX

13.5 15.5 mW

−40 +85 °C

Rev. A | Page 5 of 28

AD7949

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications T

Table 3.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width t Data Write/Read During Conversion t SCK Period t SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 16 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 19 ns

CNV Low to SDO D15 MSB Valid t

VIO Above 4.5 V 15 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns CNV High or Last SCK Falling Edge to SDO High Impedance t CNV Low to SCK Rising Edge t DIN Valid Setup Time from SCK Falling Edge t DIN Valid Hold Time from SCK Falling Edge t

1

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

CONV

ACQ

CYC

CNVH

DATA

SCK

SCKL

SCKH

HSDO

DSDO

EN

DIS

CLSCK

SDIN

HDIN

2.2 µs

1.8 µs 4 µs 10 ns

1.0 µs 15 ns 7 ns 7 ns 4 ns

25 ns 10 ns 4 ns 4 ns

Rev. A | Page 6 of 28

AD7949

T

3

www.BDTIC.com/ADI

VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, all specifications T

Table 4.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width t Data Write/Read During Conversion t SCK Period t SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 37 ns

CNV Low to SDO D15 MSB Valid t

VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns

VIO Above 2.3 V 35 ns CNV High or Last SCK Falling Edge to SDO High Impedance t CNV Low to SCK Rising Edge t SDI Valid Setup Time from SCK Falling Edge t SDI Valid Hold Time from SCK Falling Edge t

1

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

CONV

ACQ

CYC

CNVH

DATA

SCK

SCKL

SCKH

HSDO

DSDO

EN

DIS

CLSCK

SDIN

HDIN

3.2 µs

1.8 µs 5 µs 10 ns

1.0 µs 25 ns 12 ns 12 ns 5 ns

50 ns 10 ns 5 ns 5 ns

500µA

OSDO

50pF

C

L

500µA

Figure 2. Load Circuit for Di

I

OL

1.4V

I

OH

07351-002

gital Interface Timing

0% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2V IF VI O ABOVE 2. 5V, VIO – 0.5V IF VIO BEL OW 2.5V.

2

0.8V IF VIO ABOV E 2.5V, 0. 5V IF V IO BELO W 2.5V.

2

Figure 3. Voltage Levels for Timing

70% VIO

t

DELAY

1

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

07351-003

Rev. A | Page 7 of 28

AD7949

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

INx,1 COM

REF, REFIN GND − 0.3 V to VDD + 0.3 V Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V DIN, CNV, SCK to GND2 −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (LFCSP) 47.6°C/W θJC Thermal Impedance (LFCSP) 4.4°C/ W

1

See the Analog Inputs section.

2

CNV must be low during power up. See the Power Supply section.

1

GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 28

AD7949

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

0

IN2

IN3

VDD

IN1

IN

71

61

81

91

02

PIN 1 INDICATOR

1VDD 2REF

AD7949

3REFIN 4GND

TOP VIEW

5GND

(Not to Scale)

8

6

7

IN4

IN5

IN6

Figure 4. 20-Lead LFCSP Pin Configuration

15 VIO 14 SDO 13 SCK 12 DIN 11 CNV

01

9

IN7

COM

07351-004

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1, 20 VDD P

1

Description

Power Supply. Nominally 2.5 V to 5.5 V when using an ex 10 F and 100 nF capacitors.

When using the internal reference for 2.5 V outp When using the internal reference for 4.096 V output, the minimum should be 4.5 V.

2 REF AI/O

Reference Input/Output. See the Voltage Reference Output/Input section.

the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or

When

4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum) useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 F capacitor connected as close to REF as possible. See the

3 REFIN AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input

tion.

sec When using the internal reference, the internal unbuffered reference voltage is present and

s decoupling with a 0.1F capacitor.

need When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is

buffered to the REF pin as described above. 4, 5 GND P Power Supply Ground. 6 to 9 IN4 to IN7 AI Channel 4 through Channel 7 Analog Inputs. 10 COM AI

11 CNV DI

12 DIN DI

Common Channel Input. All channels [7:0] can be referenced to a common mode point of 0 V or

V

/2 V.

REF

Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is

high, the busy indictor is enabled.

held

Data Input. This input is used f

or writing to the 14-bit configuration register. The configuration

register can be written to during and after conversion. 13 SCK DI

Serial Data Clock Input. This input is used t

o clock out the data on ADO and clock in data on DIN

in an MSB first fashion. 14 SDO DO

Serial Data Output. The conversion r

esult is output on this pin synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

15 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

V, 3 V, or 5 V).

2.5

16 to 19 IN0 to IN3 AI Channel 0 through Channel 3 Analog Inputs.

1

AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

ternal reference and decoupled with

ut, the minimum should be 3.0 V.

Reference Decoupling section.

Rev. A | Page 9 of 28

ANALOG DEVICES AD7949 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS