ANALOG DEVICES AD7939 Service Manual

8-Channel, 1.5 MSPS, 12-Bit and 10-Bit

V

www.BDTIC.com/ADI

FEATURES

Throughput rate: 1.5 MSPS
Specified for V
Power consumption

6 mW maximum at 1.5 MSPS with 3 V supplies

13.5 mW maximum at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software-configurable analog inputs

8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo differential inputs
7-channel pseudo differential inputs

Accurate on-chip 2.5 V reference

±0.2% maximum @ 25°C, 25 ppm/°C maximum
70 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 μA maximum
32-lead LFCSP and TQFP packages

of 2.7 V to 5.25 V

DD

Parallel ADCs with a Sequencer

AD7938/AD7939

FUNCTIONAL BLOCK DIAGRAM

AGND

DD

V

V

REFOUT

REFIN/

VIN0

VIN7

2.5V

VREF

I/P

T/H

MUX

SEQUENCER

PARALLEL I NTERFACE/CO NTROL REGISTE R

DB0 DB11

CS DGNDRD WR W/B

Figure 1.

AD7938/AD7939

12-/10-BIT
SAR ADC

AND

CONTROL

CLKIN
CONVST
BUSY

V

DRIVE

03715-001

GENERAL DESCRIPTION

The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to

5.25 V power supply and feature throughput rates up to

1.5 MSPS. The parts contain a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.

The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo
differential analog inputs.

The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of

CONVST

this point.

The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.

and the conversion is also initiated at

These parts use advanced design techniques to achieve very
low power dissipation at high throughput rates. They also
feature flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Eight analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Single-ended, pseudo differential, or fully differential

analog inputs that are software selectable.

5. Single-supply operation with V

function allows the parallel interface to connect directly to
3 V or 5 V processor systems independent of V

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once-off conversion control.

Table 1. Related Devices

Device No. of Bits No. of Channels Speed

AD7933/AD7934 12/10 4 1.5 MSPS
AD7938-6 12 8 625 kSPS
AD7934-6 12 4 625 kSPS

function. The V

DRIVE

DRIVE

.

DD

CONVST

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2007 Analog Devices, Inc. All rights reserved.

AD7938/AD7939

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TABLE OF CONTENTS

Features.............................................................................................. 1

Circuit Information........................................................................ 18

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7938 Specifications................................................................. 3

AD7939 Specifications................................................................. 5

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 13

On-Chip Registers.......................................................................... 15

Control Register.......................................................................... 15

Converter Operation.................................................................. 18

ADC Transfer Function............................................................. 18

Typical Connection Diagram ................................................... 19

Analog Input Structure.............................................................. 19

Analog Inputs ............................................................................. 20

Analog Input Selection.............................................................. 22

Reference ..................................................................................... 23

Parallel Interface......................................................................... 25

Power Modes of Operation....................................................... 28

Power vs. Throughput Rate....................................................... 29

Microprocessor Interfacing....................................................... 29

Application Hints ........................................................................... 31

Grounding and Layout.............................................................. 31

PCB Design Guidelines for Chip Scale Package .................... 31

Evaluating AD7938/AD7939 Performance ............................ 31

Sequencer Operation ................................................................. 16

Shadow Register.......................................................................... 17

REVISION HISTORY

2/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Sequencer Operation Section................................... 16

Updated Outline Dimensions....................................................... 32

7/05—Rev. 0 to Rev. A

Changes to Specifications................................................................ 3

Added Figure 3.................................................................................. 9

Changes to Table 5.......................................................................... 10

Updated Typical Performance Characteristics ...........................13

Changes to Table 11........................................................................ 16

Changes to Analog Input Structure Section ............................... 18

Changes to Analog Inputs Section ...............................................19

Changes to Figure 17...................................................................... 17

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 33

Changes to Figure 20...................................................................... 18

Changes to Figure 21...................................................................... 19

Changes to Figure 22...................................................................... 19

Changes to Figure 24...................................................................... 19

Changes to Figure 28...................................................................... 21

Changes to Figure 29...................................................................... 21

Changes to Figure 41...................................................................... 28

Changes to Figure 43...................................................................... 28

Changes to Figure 44...................................................................... 29

Changes to Figure 45...................................................................... 29

Changes to Figure 46...................................................................... 29

Updated Outline Dimensions....................................................... 31

Changes to Ordering Guide.......................................................... 32

10/04—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD7938/AD7939

www.BDTIC.com/ADI

SPECIFICATIONS

AD7938 SPECIFICATIONS

VDD = V
T

= T

A

= 2.7 V to 5.25 V, internal/external V

DRIVE

MIN

to T

, unless otherwise noted.

MAX

= 2.5 V, unless otherwise noted, f

REF

= 25.5 MHz, f

CLKIN

= 1.5 MSPS;

SAMPLE

Table 2.

Parameter Value

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise and Distortion (SINAD)

2

68 dB min Single-ended mode
Signal-to-Noise Ratio (SNR)

2

69 dB min Single-ended mode
Total Harmonic Distortion (THD)

2

−70 dB max −80 dB typ, single-ended mode
Peak Harmonic or Spurious Noise (SFDR)

Intermodulation Distortion (IMD)

2

2

Second-Order Terms −6 dB typ

Third-Order Terms −90 dB typ
Channel-to-Channel Isolation −85 dB typ fIN = 50 kHz, f
Aperture Delay

Aperture Jitter

Full Power Bandwidth

2

2

2

10 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity

2

±1.5 LSB max Single-ended mode
Differential Nonlinearity

2

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits

Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits
Single-Ended and Pseudo Differential Input Straight binary output coding

Offset Error

Offset Error Match

Gain Error

Gain Error Match

2

2

2

2

Fully Differential Input Twos complement output coding

Positive Gain Error

Positive Gain Error Match

Zero-Code Error

Zero-Code Error Match

Negative Gain Error

Negative Gain Error Match

2

2

2

2

2

2

ANALOG INPUT

Single-Ended Input Range 0 to V
0 to 2 × V
Pseudo Differential Input Range

V

0 to V

IN+

0 to 2 × V

V

−0.3 to +0.7 V typ VDD = 3 V

IN−

−0.3 to +1.8 V typ VDD = 5 V
Fully Differential Input Range

V

and V

IN+

V

IN+

DC Leakage Current

V

IN−

and V

V

IN−

4

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

1

Unit Test Conditions/Comments

70 dB min Differential mode

71 dB min Differential mode

−73 dB max −85 dB typ, differential mode

−73 dB max −82 dB typ

fa = 30 kHz, fb = 50 kHz

= 300 kHz

NOISE

5 ns typ

72 ps typ

50 MHz typ @ 3 dB

±1 LSB max Differential mode

±6 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

±6 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

V RANGE bit = 0

REF

V RANGE bit = 1

REF

V RANGE bit = 0

REF

V RANGE bit = 1

REF

± V

/2 V VCM = common-mode voltage3 = V

CM

REF

± V

V VCM = V

CM

REF

, V

or V

REF

must remain within GND/VDD

IN+

IN−

±1 μA max

Rev. B | Page 3 of 36

/2

REF

AD7938/AD7939

www.BDTIC.com/ADI

Parameter Value

1

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

V

Input Voltage

REF

5

2.5 V ±1% for specified performance
DC Leakage Current ±1 μA max
V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

V

Temperature Coefficient 25 ppm/°C max

REFOUT

5 ppm/°C typ
V

Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth

REF

130 μV typ 0.1 Hz to 1 MHz bandwidth
V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold
LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

2.4 V min

INH

0.8 V max

INL

4

IN

10 pF typ

DRIVE

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I

SOURCE

= 200 μA

SINK

= 200 μA

Floating-State Leakage Current ±3 μA max
Floating-State Output Capacitance

4

10 pF typ

Output Coding Straight (natural) binary CODING bit = 0

Twos complement CODING bit = 1
CONVERSION RATE

Conversion Time t2 + 13 t

ns

CLKIN

Track-and-Hold Acquisition Time 125 ns max Full-scale step input
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7/5.25 V min/max

DRIVE

6

I

DD

Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ f

= 100 kSPS, VDD = 5 V

SAMPLE

160 μA typ Static
Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 μW typ VDD = 5 V
480 μW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V
6 μW max VDD = 3 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

For full common-mode range, see Figure 26 and Figure 27.

4

Sample tested during initial release to ensure compliance.

5

This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information.

6

Measured with a midscale dc analog input.

Rev. B | Page 4 of 36

AD7938/AD7939

www.BDTIC.com/ADI

AD7939 SPECIFICATIONS

VDD = V
T

= T

A

= 2.7 V to 5.25 V, internal/external V

DRIVE

MIN

to T

, unless otherwise noted.

MAX

= 2.5 V, unless otherwise noted, f

REF

= 25.5 MHz, f

CLKIN

= 1.5 MSPS;

SAMPLE

Table 3.

Parameter Value

1

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise and Distortion (SINAD)

2

61 dB min Differential mode
60 dB min Single-ended mode
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)

2

−70 dB max

2

−72 dB max

Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Second-Order Terms −86 dB typ

Third-Order Terms −90 dB typ
Channel-to-Channel Isolation −75 dB typ fIN = 50 kHz, f
Aperture Delay
Aperture Jitter
Full Power Bandwidth

2

2

2

5 ns typ
72 ps typ
50 MHz typ @ 3 dB

= 300 kHz

NOISe

10 MHz typ @ 0.1 dB
DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity
Differential Nonlinearity

2

2

±0.5 LSB max
±0.5 LSB max Guaranteed no missed codes to 10 bits

Single-Ended and Pseudo Differential Input Straight binary output coding

Offset Error

Offset Error Match

Gain Error

Gain Error Match

2

2

2

2

±2 LSB max
±0.5 LSB max
±1.5 LSB max
±0.5 LSB max

Fully Differential Input Twos complement output coding

Positive Gain Error

Positive Gain Error Match

Zero-Code Error

Zero-Code Error Match

Negative Gain Error

Negative Gain Error Match

2

2

2

2

2

2

±1.5 LSB max
±0.5 LSB max
±2 LSB max
±0.5 LSB max
±1.5 LSB max
±0.5 LSB max

ANALOG INPUT

Single-Ended Input Range 0 to V
0 to 2 × V

V RANGE bit = 0

REF

V RANGE bit = 1

REF

Pseudo Differential Input Range

V

0 to V

IN+

0 to 2 × V

V

−0.3 to +0.7 V typ VDD = 3 V

IN−

V RANGE bit = 0

REF

V RANGE bit =1

REF

−0.3 to +1.8 V typ VDD = 5 V
Fully Differential Input Range

V

and V

IN+

V

and V

IN+

DC Leakage Current

V

IN−

V

IN−

4

± V

CM

CM

/2 V VCM = common-mode voltage3 = V

REF

± V

V VCM = V

REF

±1 μA max

, V

or V

REF

IN+

must remain within GND/VDD

IN−

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

REF

/2

Rev. B | Page 5 of 36

AD7938/AD7939

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Parameter Value

1

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

V

Input Voltage

REF

DC Leakage Current
V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

V

Temperature Coefficient 25 ppm/°C max

REFOUT

5

4

2.5 V ±1% for specified performance
±1 μA max External reference applied to pin

5 ppm/°C typ
V

Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth

REF

130 μV typ 0.1 Hz to 1 MHz bandwidth
V

Output Impedance 10 Ω typ

REF

V

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or V
Input Capacitance, C

2.4 V min

INH

0.8 V max

INL

4

IN

10 pF typ

DRIVE

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I
Output Low Voltage, VOL 0.4 V max I

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±3 μA max
Floating-State Output Capacitance

4

10 pF typ
Output Coding Straight (natural) binary CODING bit = 0
Twos complement CODING bit =1

CONVERSION RATE

Conversion Time t2 + 13 t

ns

CLKIN

Track-and-Hold Acquisition Time 125 ns max Full-scale step input
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max
V

2.7/5.25 V min/max

DRIVE

6

I

DD

Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ f

= 100 kSPS, VDD = 5 V

SAMPLE

160 μA typ Static
Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 μW typ VDD = 5 V
480 μW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

For full common-mode range, see Figure 26 and Figure 27.

4

Sample tested during initial release to ensure compliance.

5

This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more details.

6

Measured with a midscale dc analog input.

6 μW max VDD = 3 V

Rev. B | Page 6 of 36

AD7938/AD7939

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TIMING SPECIFICATIONS

VDD = V
T

MAX

Table 4.

Limit at T
Parameter1 AD7938 AD7939 Unit Description

2

f

CLKIN

25.5 25.5 MHz max
t

30 30 ns min

QUIET

t1 10 10 ns min
t2 15 15 ns min
t3 50 50 ns max CLKIN falling edge to BUSY rising edge.

t4 0 0 ns min
t5 0 0 ns min
t6 10 10 ns min
t7 10 10 ns min
t8 10 10 ns min
t9 10 10 ns min New data valid before falling edge of BUSY.
t10 0 0 ns min
t11 0 0 ns min
t12 30 30 ns min

3

t

13

4

t

14

50 50 ns max
t15 0 0 ns min
t16 0 0 ns min
t17 10 10 ns min Minimum time between reads/writes.

t18 0 0 ns min
t19 10 10 ns min
t20 40 40 ns max CLKIN falling edge to BUSY falling edge.

t21 15.7 15.7 ns min CLKIN low pulse width.
t22 7.8 7.8 ns min CLKIN high pulse width.

1

Sample tested during initial release to ensure compliance. All input signals are specified with t

1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).

2

Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.

3

The time required for the output to cross 0.4 V or 2.4 V.

4

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t
bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

, unless otherwise noted.

, T

MIN

MAX

700 700 kHz min CLKIN frequency.

30 30 ns max
3 3 ns min

REF

Minimum time between end of read and start of next conversion; in other words, time

om when the data bus goes into three-state until the next falling edge of CONVST

fr
CONVST
CONVST

CS
CS
WR
Data setup time before WR
Data hold after WR

CS
CS
RD
Data access time after RD
Bus relinquish time after RD
Bus relinquish time after RD
HBEN to RD
HBEN to RD

HBEN to WR
HBEN to WR

, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the

14

= 2.5 V, unless otherwise noted; f

= 25.5 MHz, f

CLKIN

pulse width.
falling edge to CLKIN falling edge setup time.

to WR setup time.
to WR hold time.

pulse width.

.

.

to RD setup time.
to RD hold time.

pulse width.

.

.

.
setup time.
hold time.

setup time.
hold time.

= t

= 5 ns (10% to 90% of VDD) and timed from a voltage level of

RISE

FALL

= 1.5 MSPS; TA = T

SAMPLE

MIN

to

.

Rev. B | Page 7 of 36

AD7938/AD7939

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V
V

to AGND/DGND −0.3 V to VDD + 0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
V

to VDD −0.3 V to VDD + 0.3 V

DRIVE

Digital Output Voltage to DGND −0.3 V to V
V

to AGND −0.3 V to VDD + 0.3 V

REFIN

AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin

Except Supplies

Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 108.2°C/W (LFCSP)
121°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
45°C/W (TQFP)
Lead Temperature, Soldering

Reflow Temperature (10 sec to 30 sec) 255°C
ESD 1.5 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

1

±10 mA

DRIVE

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 8 of 36

AD7938/AD7939

6

5

4

3

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

7

/B

DD

IN

V

W

V

30

31

32

1DB0

PIN 1

2DB1

INDICATOR

3DB2
4DB3

AD7938/AD7939

5DB4

TOP VIEW

6DB5

(Not to Scal e)
7DB6
8DB7

9

11

10

DRIVE

DGND

V

DB8/HBEN

Figure 2. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 8 DB0 to DB7

Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pin
and shadow registers to be programmed. These pins are controlled by CS
levels for these pins are determined by the V
DB1) are always 0 and the LSB of the conversion result is available on DB2.

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at V

10 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.

11 DB8/HBEN

Data Bit 8/High Byte Enable. When W/B
CS
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the

data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to
DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in
reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.

12 to
14

DB9 to
DB11

Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS
logic high/low voltage levels for these pins are determined by the V

15 BUSY

Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the
falling edge of CONVST
result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY on the 13

16 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

17

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track

mode to hold mode on the falling edge of CONVST
power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up
the device.

18
19

Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.

WR

Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

RD

result is placed on the data bus following the falling edge of RD read while CS is low.

20

Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to

CS

the internal registers.

2

IN

IN

IN

IN

IN

V

V

V

V

V

28

27

26

25

29

1

24 V

1

IN

23 V

0

IN

22 V

REFIN/VREFOUT

21 AGND
20 CS
19 RD
18 WR
17 CONVST

12

13

14

15

16

DB9

DB11

DB10

BUSY

CLKIN

03715-006

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

2

3

4

5

6

7

8

7

6

DD

IN

IN

V

V

30

29

28

PIN 1

AD7938/AD7939

TOP VIEW

(Not to Scal e)

10

11

12

13

DB9

DGND

DB8/HBEN

32

9

W/B31V

DRIVE

V

5

4

IN

IN

V

V

27

26

15

DB1014DB11

3

2

IN

IN

V

V

25

24

VIN1

23

VIN0

22

V

REFIN/VREFOUT

21

AGND

20

CS

19

RD

18

WR

17

CONVST

16

BUSY

CLKIN

03715-050

Figure 3. TQFP Pin Configuration

s that provide the conversion result and allow the control

, RD, and WR. The logic high/low voltage

input. When reading from the AD7939, the two LSBs (DB0 and

DRIVE

but should never exceed VDD by more than 0.3 V.

DD

is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by

, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data

Table 1 0). When writing to the device, DB4 to DB7 of the high b

yte must be all 0s. Note that when

, RD, and WR. The

input.

DRIVE

and stays high for the duration of the conversion. Once the conversion is complete and the

th

rising edge of CLKIN. See Figure 36.

. The frequency of the master clock input therefore determines the

2

and the conversion process is initiated at this point. Following

Rev. B | Page 9 of 36

AD7938/AD7939

www.BDTIC.com/ADI

Pin No. Mnemonic Description

21 AGND

22 V

23 to
30

31 VDD

32

REFIN/VREFOUT

V

0 to VIN7

IN

Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit

W/B

Analog Ground. This is the ground reference point for all analog cir
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal i
decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage
range for the external reference is 0.1 V to V
does not exceed V

Analog Input 0 to Analog Input 7. Eigh
hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register
appropriately (see Table 10). The analog input channel to be converted can either be selected by writing to the

ess bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used.

addr
The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be
programmed. The input range for all input channels can either be 0 V to V
be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register.
Any unused input channels should be connected to AGND to avoid noise pickup.

Power Supply Input. The V
AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.

words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the
channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data
lines when operating in byte transfer mode should be tied off to DGND.

nternal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is

; however, care must be taken to ensure that the analog input range

+ 0.3 V. See the Reference section.

DD

range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to

DD

DD

t analog input channels that are multiplexed into the on-chip track-and-

cuitry on the AD7938/AD7939. All analog input

or 0 V to 2 × V

REF

, and the coding can

REF

Rev. B | Page 10 of 36

AD7938/AD7939

–

–

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

60

100mV p-p SINE WAVE ON VDDAND/OR V
NO DECOUPL ING
DIFFERENT IAL/SI NGLE-ENDED MODE

–70

–80

–90

PSRR (dB)

–100

–110

–120

10 210 610410 810 1010

Figure 4. PSRR vs. Supply Ripple Frequency

INT REF

EXT REF

SUPPLY RIPPLE FREQUENCY (kHz)

Without Supply Decoupling

DRIVE

03715-007

0

–10

–20

–30

–40

–50

–60

AMPLI TUDE (d B)

–70

–80

–90

–100

–110

0

100

200

300

FREQUENCY (kHz)

Figure 7. AD7938 FFT @ V

4096 POINT FF T
V

=5V

DD

F

=1.5MSPS

SAMPLE

F

= 49.62kHz

IN

SINAD = 70.94dB
THD = –90. 09dB
DIFFERENTIAL MODE

400

500

= 5 V

DD

600

03715-009

700

70

INTERNAL/EXTERNAL RE FERENCE
V

=5V

DD

–75

–80

–85

ISOLATION (dB)

–90

–95

0 100 400200 300 600500 80 0700

NOISE F REQUENCY (kHz)

Figure 5. AD7938 Channel-to-Channel Isolation

80

70

60

50

SINAD (dB)

40

30

F

=1.5MSPS

SAMPLE

RANGE = 0 TO V
DIFFERENTIAL MODE

20

0 100 400200 3 00 600500 1000700 800 900

REF

FREQUENCY (kHz)

VDD=5V

VDD=3V

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

03715-021

–1.0

0 500 20001000 1500 30002500 40003500

Figure 8. AD7938 Typical DNL @ V

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (L SB)

–0.4

–0.6

–0.8

03715-008

–1.0

0 500 20001000 1500 30002500 40003500

CODE

CODE

VDD=5V
DIFFERENT IAL MODE

= 5 V

DD

VDD=5V
DIFFERENT IAL MODE

03715-010

03715-011

Figure 6. AD7938 SINAD vs. Analog Input Frequency

or Various Supply Voltages

f

Figure 9. AD7938 Typical INL @ V

Rev. B | Page 11 of 36

DD

= 5 V