Datasheet AD7939 Datasheet (ANALOG DEVICES)

8-Channel, 1.5 MSPS, 12-Bit and 10-Bit

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FEATURES

Throughput rate: 1.5 MSPS Specified for V Power consumption

6 mW maximum at 1.5 MSPS with 3 V supplies

13.5 mW maximum at 1.5 MSPS with 5 V supplies 8 analog input channels with a sequencer Software-configurable analog inputs

8-channel single-ended inputs 4-channel fully differential inputs 4-channel pseudo differential inputs 7-channel pseudo differential inputs

Accurate on-chip 2.5 V reference

±0.2% maximum @ 25°C, 25 ppm/°C maximum 70 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes Full shutdown mode: 2 μA maximum 32-lead LFCSP and TQFP packages

of 2.7 V to 5.25 V

Parallel ADCs with a Sequencer

AD7938/AD7939

FUNCTIONAL BLOCK DIAGRAM

AGND

REFOUT

REFIN/

VIN0

VIN7

2.5V

VREF

I/P

T/H

MUX

SEQUENCER

PARALLEL I NTERFACE/CO NTROL REGISTE R

DB0 DB11

CS DGNDRD WR W/B

Figure 1.

AD7938/AD7939

12-/10-BIT SAR ADC

AND

CONTROL

CLKIN CONVST BUSY

DRIVE

03715-001

GENERAL DESCRIPTION

The AD7938/AD7939 are 12-bit and 10-bit, high speed, low power, successive approximation (SAR) analog-to-digital converters (ADCs). The parts operate from a single 2.7 V to

5.25 V power supply and feature throughput rates up to

1.5 MSPS. The parts contain a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz.

The AD7938/AD7939 feature eight analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. These parts can operate with either single-ended, fully differential, or pseudo differential analog inputs.

The conversion process and data acquisition are controlled using standard control inputs that allow easy interfacing with microprocessors and DSPs. The input signal is sampled on the falling edge of

CONVST

this point.

The AD7938/AD7939 have an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference.

and the conversion is also initiated at

These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Eight analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Single-ended, pseudo differential, or fully differential

analog inputs that are software selectable.

5. Single-supply operation with V

function allows the parallel interface to connect directly to 3 V or 5 V processor systems independent of V

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once-off conversion control.

Table 1. Related Devices

Device No. of Bits No. of Channels Speed

AD7933/AD7934 12/10 4 1.5 MSPS AD7938-6 12 8 625 kSPS AD7934-6 12 4 625 kSPS

function. The V

DRIVE

CONVST

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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TABLE OF CONTENTS

Features.............................................................................................. 1

Circuit Information........................................................................ 18

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7938 Specifications................................................................. 3

AD7939 Specifications................................................................. 5

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 13

On-Chip Registers.......................................................................... 15

Control Register.......................................................................... 15

Converter Operation.................................................................. 18

ADC Transfer Function............................................................. 18

Typical Connection Diagram ................................................... 19

Analog Input Structure.............................................................. 19

Analog Inputs ............................................................................. 20

Analog Input Selection.............................................................. 22

Reference ..................................................................................... 23

Parallel Interface......................................................................... 25

Power Modes of Operation....................................................... 28

Power vs. Throughput Rate....................................................... 29

Microprocessor Interfacing....................................................... 29

Application Hints ........................................................................... 31

Grounding and Layout.............................................................. 31

PCB Design Guidelines for Chip Scale Package .................... 31

Evaluating AD7938/AD7939 Performance ............................ 31

Sequencer Operation ................................................................. 16

Shadow Register.......................................................................... 17

REVISION HISTORY

2/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Sequencer Operation Section................................... 16

Updated Outline Dimensions....................................................... 32

7/05—Rev. 0 to Rev. A

Changes to Specifications................................................................ 3

Added Figure 3.................................................................................. 9

Changes to Table 5.......................................................................... 10

Updated Typical Performance Characteristics ...........................13

Changes to Table 11........................................................................ 16

Changes to Analog Input Structure Section ............................... 18

Changes to Analog Inputs Section ...............................................19

Changes to Figure 17...................................................................... 17

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 33

Changes to Figure 20...................................................................... 18

Changes to Figure 21...................................................................... 19

Changes to Figure 22...................................................................... 19

Changes to Figure 24...................................................................... 19

Changes to Figure 28...................................................................... 21

Changes to Figure 29...................................................................... 21

Changes to Figure 41...................................................................... 28

Changes to Figure 43...................................................................... 28

Changes to Figure 44...................................................................... 29

Changes to Figure 45...................................................................... 29

Changes to Figure 46...................................................................... 29

Updated Outline Dimensions....................................................... 31

Changes to Ordering Guide.......................................................... 32

10/04—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD7938/AD7939

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SPECIFICATIONS

AD7938 SPECIFICATIONS

VDD = V T

= T

= 2.7 V to 5.25 V, internal/external V

DRIVE

MIN

to T

, unless otherwise noted.

MAX

= 2.5 V, unless otherwise noted, f

REF

= 25.5 MHz, f

CLKIN

= 1.5 MSPS;

SAMPLE

Table 2.

Parameter Value

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise and Distortion (SINAD)

68 dB min Single-ended mode Signal-to-Noise Ratio (SNR)

69 dB min Single-ended mode Total Harmonic Distortion (THD)

−70 dB max −80 dB typ, single-ended mode Peak Harmonic or Spurious Noise (SFDR)

Intermodulation Distortion (IMD)

Second-Order Terms −6 dB typ

Third-Order Terms −90 dB typ Channel-to-Channel Isolation −85 dB typ fIN = 50 kHz, f Aperture Delay

Aperture Jitter

Full Power Bandwidth

10 MHz typ @ 0.1 dB DC ACCURACY

Resolution 12 Bits Integral Nonlinearity

±1.5 LSB max Single-ended mode Differential Nonlinearity

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits

Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits Single-Ended and Pseudo Differential Input Straight binary output coding

Offset Error

Offset Error Match

Gain Error

Gain Error Match

Fully Differential Input Twos complement output coding

Positive Gain Error

Positive Gain Error Match

Zero-Code Error

Zero-Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT

Single-Ended Input Range 0 to V 0 to 2 × V Pseudo Differential Input Range

0 to V

IN+

0 to 2 × V

−0.3 to +0.7 V typ VDD = 3 V

IN−

−0.3 to +1.8 V typ VDD = 5 V Fully Differential Input Range

and V

IN+

DC Leakage Current

IN−

and V

IN−

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

Unit Test Conditions/Comments

70 dB min Differential mode

71 dB min Differential mode

−73 dB max −85 dB typ, differential mode

−73 dB max −82 dB typ

fa = 30 kHz, fb = 50 kHz

= 300 kHz

NOISE

5 ns typ

72 ps typ

50 MHz typ @ 3 dB

±1 LSB max Differential mode

±6 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

±6 LSB max

±1 LSB max

±3 LSB max

±1 LSB max

V RANGE bit = 0

REF

V RANGE bit = 1

REF

V RANGE bit = 0

REF

V RANGE bit = 1

REF

± V

/2 V VCM = common-mode voltage3 = V

REF

± V

V VCM = V

REF

, V

or V

REF

must remain within GND/VDD

IN+

IN−

±1 μA max

Rev. B | Page 3 of 36

REF

AD7938/AD7939

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Parameter Value

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

Input Voltage

REF

2.5 V ±1% for specified performance DC Leakage Current ±1 μA max V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

Temperature Coefficient 25 ppm/°C max

REFOUT

5 ppm/°C typ V

Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth

REF

130 μV typ 0.1 Hz to 1 MHz bandwidth V

Output Impedance 10 Ω typ

REF

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

2.4 V min

INH

0.8 V max

INL

10 pF typ

DRIVE

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I Output Low Voltage, VOL 0.4 V max I

SOURCE

= 200 μA

SINK

= 200 μA

Floating-State Leakage Current ±3 μA max Floating-State Output Capacitance

10 pF typ

Output Coding Straight (natural) binary CODING bit = 0

Twos complement CODING bit = 1 CONVERSION RATE

Conversion Time t2 + 13 t

CLKIN

Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max V

2.7/5.25 V min/max

DRIVE

Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ f

= 100 kSPS, VDD = 5 V

SAMPLE

160 μA typ Static Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 μW typ VDD = 5 V 480 μW typ VDD = 3 V Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V 6 μW max VDD = 3 V

Temperature range is −40°C to +85°C.

See the Terminology section.

For full common-mode range, see Figure 26 and Figure 27.

Sample tested during initial release to ensure compliance.

This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information.

Measured with a midscale dc analog input.

Rev. B | Page 4 of 36

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AD7939 SPECIFICATIONS

VDD = V T

= T

= 2.7 V to 5.25 V, internal/external V

DRIVE

MIN

to T

, unless otherwise noted.

MAX

= 2.5 V, unless otherwise noted, f

REF

= 25.5 MHz, f

CLKIN

= 1.5 MSPS;

SAMPLE

Table 3.

Parameter Value

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise and Distortion (SINAD)

61 dB min Differential mode 60 dB min Single-ended mode Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR)

−70 dB max

−72 dB max

Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Second-Order Terms −86 dB typ

Third-Order Terms −90 dB typ Channel-to-Channel Isolation −75 dB typ fIN = 50 kHz, f Aperture Delay Aperture Jitter Full Power Bandwidth

5 ns typ 72 ps typ 50 MHz typ @ 3 dB

= 300 kHz

NOISe

10 MHz typ @ 0.1 dB DC ACCURACY

Resolution 10 Bits Integral Nonlinearity Differential Nonlinearity

±0.5 LSB max ±0.5 LSB max Guaranteed no missed codes to 10 bits

Single-Ended and Pseudo Differential Input Straight binary output coding

Offset Error

Offset Error Match

Gain Error

Gain Error Match

±2 LSB max ±0.5 LSB max ±1.5 LSB max ±0.5 LSB max

Fully Differential Input Twos complement output coding

Positive Gain Error

Positive Gain Error Match

Zero-Code Error

Zero-Code Error Match

Negative Gain Error

Negative Gain Error Match

±1.5 LSB max ±0.5 LSB max ±2 LSB max ±0.5 LSB max ±1.5 LSB max ±0.5 LSB max

ANALOG INPUT

Single-Ended Input Range 0 to V 0 to 2 × V

V RANGE bit = 0

REF

V RANGE bit = 1

REF

Pseudo Differential Input Range

0 to V

IN+

0 to 2 × V

−0.3 to +0.7 V typ VDD = 3 V

IN−

V RANGE bit = 0

REF

V RANGE bit =1

REF

−0.3 to +1.8 V typ VDD = 5 V Fully Differential Input Range

and V

IN+

and V

IN+

DC Leakage Current

IN−

± V

/2 V VCM = common-mode voltage3 = V

REF

± V

V VCM = V

REF

±1 μA max

, V

or V

REF

IN+

must remain within GND/VDD

IN−

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

REF

Rev. B | Page 5 of 36

AD7938/AD7939

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Parameter Value

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

Input Voltage

REF

DC Leakage Current V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

Temperature Coefficient 25 ppm/°C max

REFOUT

2.5 V ±1% for specified performance ±1 μA max External reference applied to pin

5 ppm/°C typ V

Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth

REF

130 μV typ 0.1 Hz to 1 MHz bandwidth V

Output Impedance 10 Ω typ

REF

Input Capacitance 15 pF typ When in track

REF

25 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

2.4 V min

INH

0.8 V max

INL

10 pF typ

DRIVE

LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V min I Output Low Voltage, VOL 0.4 V max I

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±3 μA max Floating-State Output Capacitance

10 pF typ Output Coding Straight (natural) binary CODING bit = 0 Twos complement CODING bit =1

CONVERSION RATE

Conversion Time t2 + 13 t

CLKIN

Track-and-Hold Acquisition Time 125 ns max Full-scale step input 80 ns typ Sine wave input Throughput Rate 1.5 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max V

2.7/5.25 V min/max

DRIVE

Digital inputs = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V

2.0 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ f

= 100 kSPS, VDD = 5 V

SAMPLE

160 μA typ Static Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 13.5 mW max VDD = 5 V 6 mW max VDD = 3 V Autostandby Mode (Static) 800 μW typ VDD = 5 V 480 μW typ VDD = 3 V Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V

Temperature range is −40°C to +85°C.

See the Terminology section.

For full common-mode range, see Figure 26 and Figure 27.

Sample tested during initial release to ensure compliance.

This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more details.

Measured with a midscale dc analog input.

6 μW max VDD = 3 V

Rev. B | Page 6 of 36

AD7938/AD7939

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TIMING SPECIFICATIONS

VDD = V T

MAX

Table 4.

Limit at T Parameter1 AD7938 AD7939 Unit Description

CLKIN

25.5 25.5 MHz max t

30 30 ns min

QUIET

t1 10 10 ns min t2 15 15 ns min t3 50 50 ns max CLKIN falling edge to BUSY rising edge.

t4 0 0 ns min t5 0 0 ns min t6 10 10 ns min t7 10 10 ns min t8 10 10 ns min t9 10 10 ns min New data valid before falling edge of BUSY. t10 0 0 ns min t11 0 0 ns min t12 30 30 ns min

50 50 ns max t15 0 0 ns min t16 0 0 ns min t17 10 10 ns min Minimum time between reads/writes.

t18 0 0 ns min t19 10 10 ns min t20 40 40 ns max CLKIN falling edge to BUSY falling edge.

t21 15.7 15.7 ns min CLKIN low pulse width. t22 7.8 7.8 ns min CLKIN high pulse width.

Sample tested during initial release to ensure compliance. All input signals are specified with t

1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).

Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.

The time required for the output to cross 0.4 V or 2.4 V.

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

, unless otherwise noted.

, T

MIN

MAX

700 700 kHz min CLKIN frequency.

30 30 ns max 3 3 ns min

REF

Minimum time between end of read and start of next conversion; in other words, time

om when the data bus goes into three-state until the next falling edge of CONVST

fr CONVST CONVST

CS CS WR Data setup time before WR Data hold after WR

CS CS RD Data access time after RD Bus relinquish time after RD Bus relinquish time after RD HBEN to RD HBEN to RD

HBEN to WR HBEN to WR

, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the

= 2.5 V, unless otherwise noted; f

= 25.5 MHz, f

CLKIN

pulse width. falling edge to CLKIN falling edge setup time.

to WR setup time. to WR hold time.

pulse width.

to RD setup time. to RD hold time.

pulse width.

. setup time. hold time.

setup time. hold time.

= t

= 5 ns (10% to 90% of VDD) and timed from a voltage level of

RISE

FALL

= 1.5 MSPS; TA = T

SAMPLE

MIN

Rev. B | Page 7 of 36

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V V

to AGND/DGND −0.3 V to VDD + 0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V V

to VDD −0.3 V to VDD + 0.3 V

DRIVE

Digital Output Voltage to DGND −0.3 V to V V

to AGND −0.3 V to VDD + 0.3 V

REFIN

AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin

Except Supplies

Operating Temperature Range

Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 108.2°C/W (LFCSP) 121°C/W (TQFP) θJC Thermal Impedance 32.71°C/W (LFCSP) 45°C/W (TQFP) Lead Temperature, Soldering

Reflow Temperature (10 sec to 30 sec) 255°C ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

±10 mA

DRIVE

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 36

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1DB0

PIN 1

2DB1

INDICATOR

3DB2 4DB3

AD7938/AD7939

5DB4

TOP VIEW

6DB5

(Not to Scal e) 7DB6 8DB7

DRIVE

DGND

DB8/HBEN

Figure 2. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 8 DB0 to DB7

Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pin and shadow registers to be programmed. These pins are controlled by CS levels for these pins are determined by the V DB1) are always 0 and the LSB of the conversion result is available on DB2.

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that at V

10 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

11 DB8/HBEN

Data Bit 8/High Byte Enable. When W/B CS being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the

data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.

12 to 14

DB9 to DB11

Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the control and shadow registers to be programmed in word mode. These pins are controlled by CS logic high/low voltage levels for these pins are determined by the V

15 BUSY

Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13

16 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938/AD7939 takes 13 clock cycles + t conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track

mode to hold mode on the falling edge of CONVST power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up the device.

18 19

Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.

Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of RD read while CS is low.

Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to

the internal registers.

24 V

23 V

22 V

REFIN/VREFOUT

21 AGND 20 CS 19 RD 18 WR 17 CONVST

DB9

DB11

DB10

BUSY

CLKIN

03715-006

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

PIN 1

AD7938/AD7939

TOP VIEW

(Not to Scal e)

DB9

DGND

DB8/HBEN

W/B31V

DRIVE

DB1014DB11

VIN1

VIN0

REFIN/VREFOUT

AGND

CONVST

BUSY

CLKIN

03715-050

Figure 3. TQFP Pin Configuration

s that provide the conversion result and allow the control

, RD, and WR. The logic high/low voltage

input. When reading from the AD7939, the two LSBs (DB0 and

DRIVE

but should never exceed VDD by more than 0.3 V.

is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by

, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data

Table 1 0). When writing to the device, DB4 to DB7 of the high b

yte must be all 0s. Note that when

, RD, and WR. The

input.

DRIVE

and stays high for the duration of the conversion. Once the conversion is complete and the

rising edge of CLKIN. See Figure 36.

. The frequency of the master clock input therefore determines the

and the conversion process is initiated at this point. Following

Rev. B | Page 9 of 36

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Pin No. Mnemonic Description

21 AGND

22 V

23 to 30

31 VDD

REFIN/VREFOUT

0 to VIN7

Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit

W/B

Analog Ground. This is the ground reference point for all analog cir signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal i decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to V does not exceed V

Analog Input 0 to Analog Input 7. Eigh hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register appropriately (see Table 10). The analog input channel to be converted can either be selected by writing to the

ess bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used.

addr The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be programmed. The input range for all input channels can either be 0 V to V be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. Any unused input channels should be connected to AGND to avoid noise pickup.

Power Supply Input. The V AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.

words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND.

nternal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is

; however, care must be taken to ensure that the analog input range

+ 0.3 V. See the Reference section.

range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to

t analog input channels that are multiplexed into the on-chip track-and-

cuitry on the AD7938/AD7939. All analog input

or 0 V to 2 × V

REF

, and the coding can

REF

Rev. B | Page 10 of 36

AD7938/AD7939

–

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TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

100mV p-p SINE WAVE ON VDDAND/OR V NO DECOUPL ING DIFFERENT IAL/SI NGLE-ENDED MODE

–70

–80

–90

PSRR (dB)

–100

–110

–120

10 210 610410 810 1010

Figure 4. PSRR vs. Supply Ripple Frequency

INT REF

EXT REF

SUPPLY RIPPLE FREQUENCY (kHz)

Without Supply Decoupling

DRIVE

03715-007

–10

–20

–30

–40

–50

–60

AMPLI TUDE (d B)

–70

–80

–90

–100

–110

100

200

300

FREQUENCY (kHz)

Figure 7. AD7938 FFT @ V

4096 POINT FF T V

=5V

=1.5MSPS

SAMPLE

= 49.62kHz

SINAD = 70.94dB THD = –90. 09dB DIFFERENTIAL MODE

400

500

= 5 V

600

03715-009

700

INTERNAL/EXTERNAL RE FERENCE V

=5V

–75

–80

–85

ISOLATION (dB)

–90

–95

0 100 400200 300 600500 80 0700

NOISE F REQUENCY (kHz)

Figure 5. AD7938 Channel-to-Channel Isolation

SINAD (dB)

=1.5MSPS

SAMPLE

RANGE = 0 TO V DIFFERENTIAL MODE

0 100 400200 3 00 600500 1000700 800 900

REF

FREQUENCY (kHz)

VDD=5V

VDD=3V

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

03715-021

–1.0

0 500 20001000 1500 30002500 40003500

Figure 8. AD7938 Typical DNL @ V

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (L SB)

–0.4

–0.6

–0.8

03715-008

–1.0

0 500 20001000 1500 30002500 40003500

CODE

VDD=5V DIFFERENT IAL MODE

= 5 V

VDD=5V DIFFERENT IAL MODE

03715-010

03715-011

Figure 6. AD7938 SINAD vs. Analog Input Frequency

or Various Supply Voltages

Figure 9. AD7938 Typical INL @ V

Rev. B | Page 11 of 36

= 5 V

AD7938/AD7939

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SINGL E-ENDE D MOD E

DNL (LSB)

–1

0.25 0. 50 1.250.75 1.00 2.001.751.50 2.752.502.25

Figure 10. AD7938 DNL vs. V

DIFFERENTIAL MODE

EFFECTIVE NUMBER OF BITS

POSITIVE DNL

NEGATIVE DNL

(V)

REF

VDD=5V

SINGL E-ENDE D MOD E

VDD=3V DIFFERENT IAL MO DE

VDD=5V

VDD=3V SINGLE-ENDED MODE

03715-012

for VDD = 3 V

10000

DIFFERENT IAL MO DE

9000

8000

7000

6000

5000

???

4000

3000

2000

1000

0 2046 2047 2048 2049 2050

9997

CODES

CODE

Figure 13. AD7938 Histogram of Codes for

10k

Samples @ V

120

DIFFERENTIAL MODE

110

100

CMRR (dB)

= 5 V with the Internal Reference

3CODES

INTERNAL

REF

03715-015

00.5 1.51.0 2.52.0 4.03.53.0 V

(V)

REF

Figure 11. AD7938 ENOB vs. V

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

OFFSET (LSB)

–3.5

–4.0

–4.5

–5.0

00.5 1.51.0 2.52.0 3.53.0

VDD=5V

VDD=3V

(V)

REF

Figure 12. AD7938 Offset vs. V

REF

SINGL E-ENDE D MOD E

REF

03715-013

03715-014

0 200 400 800600 12001000

RIPPLE F REQUENCY (kHz)

Figure 14. CMRR vs. Ripple Frequency with V

= 5 V and 3 V

03715-017

Rev. B | Page 12 of 36

AD7938/AD7939

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TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

rough the endpoints of the ADC transfer function. The

th endpoints of the transfer function are zero scale, 1 LSB below the first code transition, and full scale, 1 LSB above the last code transition.

Negative Gain Error

This applies when using the twos complement output coding opt

ion, in particular to the 2 × V

biased about the V

REF

input range with −V

REF

point. It is the deviation of the first

code transition (100…000) to (100…001) from the ideal (that is,

−V

+ 1 LSB) after the zero-code error has been adjusted out.

REFIN

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

ange between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00…000) to (00…001) f

rom the ideal (that is, AGND + 1 LSB).

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111…110) to (111…111) f

rom the ideal (that is, V

− 1 LSB) after the offset

REF

error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero-Code Error

This applies when using the twos complement output coding

ion, in particular to the 2 × V

opt +V

biased about the V

REF

REFIN

input range with −V

REF

point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal V (that is, V

REF

voltage

Zero-Code Error Match

This is the difference in zero-code error between any two cha

nnels.

Positive Gain Error

This applies when using the twos complement output coding

ion, in particular to the 2 × V

opt +V

biased about the V

REF

input range with −V

REF

point. It is the deviation of the last

REFIN

REF

code transition (011…110) to (011…111) from the ideal (that is, V

− 1 LSB) after the zero-code error has been adjusted out.

REF

Positive Gain Error Match

This is the difference in positive gain error between any two

nnels.

cha

Negative Gain Error Match

This is the difference in negative gain error between any two

nnels.

cha

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

osstalk between channels. It is measured by applying a full-

cr scale sine wave signal to all seven nonselected input channels and applying a 50 kHz signal to the selected channel. The channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the noise signal on the unselected channels that appears in the FFT of this channel. The noise frequency on the unselected channels varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × V while the signal amplitude is at 1 × V

. See Figure 5.

REF

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in the ADC output at f

ull-scale frequency, f, to the power of a 100 mV p-p sine wave

applied to the ADC V

supply of frequency, fS. The frequency

of the noise varies from 1 kHz to 1 MHz.

PSRR (dB) = 10 log(Pf/Pf

)

where:

Pf is t

he power at frequency f in the ADC output.

is the power at frequency fS in the ADC output.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at

ull-scale frequency, f, to the power of a 100 mV p-p sine wave

f applied to the common-mode voltage of V frequency, f

CMRR (dB) = 10 log(Pf/Pf

)

and V

IN+

IN−

where:

Pf is t

he power at frequency f in the ADC output.

is the power at frequency fS in the ADC output.

Rev. B | Page 13 of 36

AD7938/AD7939

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Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

f conversion. The track-and-hold acquisition time is the time

o required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of conversion.

Signal-to-Noise and Distortion Ratio (SINAD)

This is the measured ratio of signal-to-noise and distortion at

he output of the ADC. The signal is the rms amplitude of the

t fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.

The theoretical signal-to-noise and distortion ratio for an ideal N-

bit converter with a sine wave input is given by

SINAD = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit co

nverter, it is 62 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the

undamental. For the AD7938/AD7939, it is defined as

⎛

()

THD

where:

is the rms amplitude of the fundamental.

, V3, V4, V5, and V6 are the rms amplitudes of the second

through the sixth harmonics.

⎜

log20dB

−= ⎜

⎝

/2), excluding dc. The

SAMPLE

22222

⎞

VVVVV

++++

⎟ ⎟

⎠

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the r

ms value of the next largest component in the ADC output spectrum (up to f the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

, any active device with nonlinearities creates distortion

fb products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7938/AD7939 are tested using the CCIF standard where tw

o input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The intermodulation distortion is calculated per the THD specification, as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB.

/2 and excluding dc) to the rms value of

SAMPLE

Rev. B | Page 14 of 36

AD7938/AD7939

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ON-CHIP REGISTERS

The AD7938/AD7939 have two on-chip registers that are necessary for the operation of the device. These are the control register, which is used to set up different operating conditions, and the shadow register, which is used to program the analog input channels to be converted.

Table 7. Control Register Bits

MSB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PM1 PM0 CODING REF ADD2 ADD1 ADD0 MODE1 MODE0 SHDW SEQ RANGE

Table 8. Control Register Bit Function Description

Bit No. Mnemonic Description

11, 10 PM1, PM0

9 CODING

8 REF

7 to 5

4, 3

2 SHDW

1 SEQ

0 RANGE

Power Management Bits. These two bits are used to select the power mode of operation. The user can choose

ween either normal mode or various power-down modes of operation, as shown in Tab le 9.

bet This bit selects the output coding of the conversion result. I

(natural) binary. If this bit is set to 1, the output coding is twos complement. This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an

ternal reference should be applied to the V

ex Reference section.

ADD2 to ADD0

MODE1, MODE0

These three address bits are used to either select which analog input channel is converted in the next conversion if the sequenc described in Table 11. The selected input channel is decoded as shown in Table 10.

The two mode pins select the type of analog input on the eight V single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential inputs. See Table 10.

The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and

cess the SHDW register. See Table 11.

ac The SEQ bit in the control register is used in conjunction with the SHDW bit t

access the SHDW register. See Table 1 1. This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, the

0 V to V be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. See the Analog Inputs section for more information.

er is not used, or to select the final channel in a consecutive sequence when the sequencer is used, as

. If it is set to 1, the analog input range extends from 0 V to 2 × V

REF

CONTROL REGISTER

The control register on the AD7938/AD7939 is a 12-bit, writeonly register. Data is written to this register using the WR

pins. The control register is shown in Tabl e 7 and the functions of the bits are described in Ta b le 8 . At power up, the defa

ult bit settings in the control register are all 0s.

f this bit is set to 0, the output coding is straight

pin. If this bit is Logic 1, the internal reference is selected. See the

REF

pins. The AD7938/AD7939 can have either eight

o control the sequencer function and

analog input range extends from

. When this range is selected, VDD must

REF

LSB

and

Table 9. Power Mode Selection Using the Power Man

PM1 PM0 Mode Description

0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times. 0 1 Autoshutdown

1 0 Autostandby

1 1 Full Shutdown

When operating in autoshutdown mode, the AD7938/AD7939 en each conversion. In this mode, all circuitry is powered down.

When the AD7938/AD7939 enter this mode, all circuitry is po reference buffer. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 μs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information.

When the AD7938/AD7939 enter this mode, all circuitry is po register is retained.

agement Bits in the Control Register

wered down except for the reference and

wered down. The information in the control

Rev. B | Page 15 of 36

ter full shutdown mode at the end of

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SEQUENCER OPERATION

The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Tab le 1 1 outlines the four modes of op

eration of the sequencer.

Writing to the Control Register to Program the Sequencer

The AD7938/AD7939 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN

Table 10. Analog Input Type Selection

MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1

Channel Address

ADD2 ADD1 ADD0 V

0 0 0 VIN0 AGND VIN0 VIN1 VIN0 VIN1 VIN0 VIN7 0 0 1 VIN1 AGND VIN1 VIN0 VIN1 VIN0 VIN1 VIN7 0 1 0 VIN2 AGND VIN2 VIN3 VIN2 VIN3 VIN2 VIN7 0 1 1 VIN3 AGND VIN3 VIN2 VIN3 VIN2 VIN3 VIN7 1 0 0 VIN4 AGND VIN4 VIN5 VIN4 VIN5 VIN4 VIN7 1 0 1 VIN5 AGND VIN5 VIN4 VIN5 VIN4 VIN5 VIN7 1 1 0 VIN6 AGND VIN6 VIN7 VIN6 VIN7 VIN6 VIN7 1 1 1 VIN7 AGND VIN7 VIN6 VIN7 VIN6 Not Allowed

Eight Single-Ended Input Cha

nnels

IN+

IN−

Four Fully Differential Input Channels

IN+

IN−

periods, the conversion aborts. If a conversion is aborted after applying 12.5 CLKIN periods to the ADC, ensure that a rising

CONVST

edge of

or a falling edge of CLKIN is applied to the part before writing to the control register to program the sequencer. If these conditions are not met, the sequencer will not be in the correct state to handle being reprogrammed for another sequence of conversions and the performance of the converter is not guaranteed.

Four Pseudo Differential Input Channels (Pseudo Mode 1)

IN+

IN−

Seven Pseudo Differential Input Channels (Pseudo Mode 2)

IN+

IN−

Table 11. Sequence Selection

SEQ SHDW Sequence Type

0 0

This configuration is selected when the sequence function is n individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7938/AD7939 selects the next channel for conversion.

0 1

This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to DB7 to the shado falling edge. See the Shadow Register section and Table 12.

1 0

If the SEQ and SHDW bits are set in this w operation. This allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle.

1 1

This configuration is used in conjunction with the channel addr conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the channel address bits in the control register.

ot used. The analog input channel selected on each

w register. This programs the sequence of channels to be converted continuously after each CONVST

ay, the sequence function is not interrupted upon completion of the write

ess bits (ADD2 to ADD0) to program continuous

Rev. B | Page 16 of 36

AD7938/AD7939

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SHADOW REGISTER

The shadow register on the AD7938/AD7939 is an 8-bit, writeonly register. Data is loaded from DB0 to DB7 on the rising

edge of information is written into the shadow register provided that the SEQ and SHDW bits in the control register were set to 0 and 1, respectively, in the previous write to the control register. Each bit represents an analog input from Channel 0 through Channel 7. A sequence of channels can be selected through which the AD7938/AD7939 cycles with each consecutive conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in single-ended mode or Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When

Table 12. Shadow Register Bit Functions

MSB LSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0

. The eight LSBs load into the shadow register. The

operating in fully differential mode or Pseudo Mode 1, the associated pair of channel bits must be set for each pair of analog inputs required in the sequence. With each consecutive CONVST

AD7938/AD7939 progress through the selected channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and SHDW bits configured in any way except 1, 0 (see W Mode 1, the ADC does not convert on the inverse pairs (that is, V

outlined in Tab l e 1 2. See the Analog Input Selection section for

urther information on using the sequencer.

pulse after the sequencer has been set up, the

Tabl e 11 ).

hen a sequence is set up in fully differential mode or Pseudo

1, VIN0). The bit functions of the shadow register are

Rev. B | Page 17 of 36

AD7938/AD7939

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CIRCUIT INFORMATION

The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit, single-supply, successive approximation analog-to-digital converters. The parts can operate from a 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS.

The AD7938/AD7939 provide the user with an on-chip trackand-hold, an accurate internal reference, an analog-to-digital converter, and a parallel interface housed in a 32-lead LFCSP or TQFP package.

The AD7938/AD7939 have eight analog input channels that can be configured to be eight single-ended inputs, four fully differential pairs, four pseudo differential pairs, or seven pseudo differential inputs with respect to one common input. There is an on-chip user-programmable channel sequencer that allows the user to select a sequence of channels through which the ADC can progress and cycle with each consecutive falling edge of

CONVST

The analog input range for the AD7938/AD7939 is 0 V to V or 0 V to 2 × V

, depending on the status of the RANGE bit in

REF

the control register. The output coding of the ADC can be either binary or twos complement, depending on the status of the CODING bit in the control register.

The AD7938/AD7939 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the control register.

CONVERTER OPERATION

The AD7938/AD7939 are successive approximation ADCs based around two capacitive digital-to-analog converters (DACs). Figure 15 and Figure 16 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, an SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo differential mode. Single-ended mode operation is similar but

is internally tied to AGND. In acquisition phase, SW3 is

IN−

closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

When the ADC starts a conversion (Figure 16), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the output code of the ADC. The output impedances of the sources driving the V

and the V

IN+

pins must match;

IN−

otherwise, the two inputs have different settling times, resulting in errors.

CAPACITIVE

DAC

IN+

IN–

B A

A B

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03715-024

Figure 16. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7938/AD7939 is either straight binary or twos complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (1 LSB, 2 LSBs, and so on) and the LSB size is V V

/1,024 for the AD7939. The ideal transfer characteristics

REF

of the AD7938/AD7939 for both straight binary and twos complement output coding are shown in Figure 17 and Figure 18, respectively.

111...111

111...110

111...000

011...111

ADC CODE

/4,096 for the AD7938 and

REF

1LSB=V 1LSB=V

/4096 (AD7938)

REF

/1024 (AD7939)

REF

CAPACITIVE

DAC

IN+

IN–

B A

A B

SW1

SW2

REF

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

03715-023

000...010

000...001

000...000 1LSB +V

NOTES

1. V

IS EITHER V

REF

Figure 17. AD7938/AD7939 Ideal Transfer Characteristic

with Straight Binary Output Coding

Figure 15. ADC Acquisition Phase

Rev. B | Page 18 of 36

ANALOG INPUT

OR 2 × V

REF

–1LSB

REF

03715-025

AD7938/AD7939

www.BDTIC.com/ADI

/4096 (AD7938)

REF

/1024 (AD7939)

REF

–1LSB

REF

03715-026

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000

1LSB= 2×V 1LSB= 2×V

+1LSB V

–V

REF

Figure 18. AD7938/AD7939 Ideal Transfer Characteristic

wit

h Twos Complement Output Coding and 2 × V

Range

REF

TYPICAL CONNECTION DIAGRAM

Figure 19 shows a typical connection diagram for the AD7938/AD7939. The AGND and DGND pins are connected together at the device for good noise suppression. The V

REFIN/VREFOUT

capacitor to avoid noise pickup if the internal reference is used. Alternatively, V reference source. In this case, the reference pin should be decoupled with a 0.1 μF capacitor. In both cases, the analog input range can either be 0 V to V 2 × V

REF

be either eight single-ended inputs, four differential pairs, four pseudo differential pairs, or seven pseudo differential inputs (see

Tabl e 10 ). The V supply. The voltage applied to the V voltage of the digital interface. Here, it is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the

0 TO V

TO 2 × V

2.5V

pin is decoupled to AGND with a 0.47 μF

REFIN/VREFOUT

can be connected to an external

(RANGE bit = 0) or 0 V to

REF

(RANGE bit = 1). The analog input configuration can

pin is connected to either a 3 V or 5 V

input controls the

DRIVE

Digital Inputs section).

3V/5 SUPPLY

W/B

CLKIN

BUSY

CONVST

DB0

DB11/DB9

DRIVE

REF

0.1µF

+ +

10µF

SUPPLY

MICROCONTRO LLER/

REF

+ +

0.1µF 10µF

AD7938/AD7939

VIN0

REF

AGND

DGND

REFIN/VREFOUT

0.1µF EXT ERNAL V

0.47µF INTERNAL V

Figure 19. Typical Connection Diagram

MICROPROCESSOR

03715-027

ANALOG INPUT STRUCTURE

Figure 20 shows the equivalent circuit of the analog input structure of the AD7938/AD7939 in differential/pseudo differential mode. In single-ended mode, V tied to AGND. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. Doing so causes these diodes to become forwardbiased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part.

The C1 capacitors in Figure 20 are typically 4 pF and can

imarily be attributed to pin capacitance. The resistors are

pr lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors are the sampling capacitors of the ADC and typically have a capacitance of 45 pF.

For ac applications, removing high frequency components from t

he analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

IN+

IN–

Figure 20. Equivalent Analog Input Circuit,

Conv

ersion Phase: Switches Open, Track Phase: Switches Closed

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades.

raph of the THD vs. source impedance with a 50 kHz input

g tone for both V

= 5 V and 3 V in single-ended mode and fully

Figure 21 and Figure 22 show a

differential mode, respectively.

IN−

R1 C2

is internally

03715-028

Rev. B | Page 19 of 36

AD7938/AD7939

–

www.BDTIC.com/ADI

FIN= 50kHz

–45

–50

–55

–60

–65

THD (dB)

–70

–75

–80

–85

–90

10 100 1k

SOURCE

VDD=3V

VDD=5V

(Ω)

03715-018

Figure 21. THD vs. Source Impedance in Single-Ended Mode

FIN= 50kHz

–65

–70

–75

–80

THD (dB)

–85

VDD=3V

–90

–95

–100

10 100 1k

VDD=5V

SOURCE

(Ω)

03715-019

Figure 22. THD vs. Source Impedance in Fully Differential Mode

Figure 23 shows a graph of the THD vs. the analog input frequency for various supplies while sampling at 1.5 MHz with an SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω.

VDD=3V

–60

–70

–80

–90

THD (dB)

–100

SINGLE-E NDED MODE

VDD=5V SINGL E-ENDE D MOD E

VDD=5V/3V DIFFERENT IAL MO DE

ANALOG INPUTS

The AD7938/AD7939 have software-selectable analog input configurations. The user can choose eight single-ended inputs, four fully differential pairs, four pseudo differential pairs, or seven pseudo differential inputs. The analog input configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see

Single-Ended Mode

The AD7938/AD7939 can have eight single-ended analog input channels by setting the MODE0 and MODE1 bits in the control register to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. An op amp suitable for this function is the

AD8021. The analog input range of the AD7938/AD7939

n be programmed to be either 0 V to V

If the analog input signal to be sampled is bipolar, the internal

eference of the ADC can be used to externally bias up this

r signal to make it the correct format for the ADC.

Figure 24 shows a typical connection diagram when operating

he ADC in single-ended mode. This diagram shows a bipolar

t signal of amplitude ±1.25 V being preconditioned before it is applied to the AD7938/AD7939. In cases where the analog input amplitude is ±2.5 V, the 3R resistor can be replaced with a resistor of value R. The resultant voltage on the analog input of the AD7938/AD7939 is a signal ranging from 0 V to 5 V. In this case, the 2 × V

+1.25V

1.25V

*ADDITIONAL PINS OMITTED FOR CLARITY.

mode can be used.

REF

Figure 24. Single-Ended Mod

Differential Mode

The AD7938/AD7939 can have four differential analog input pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1, respectively.

Tabl e 1 0 ).

+2.5

e Connection Diagram

or 0 V to 2 × V

REF

VIN0

AD7938/

AD7939*

REFOUT

0.47µF

REF

03715-031

–110

=1.5MSPS

SAMPLE

RANGE = 0 TO V

–120

0 100 400200 300 600500 700

REF

INPUT FRE QUENCY (kHz)

03715-020

Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages

Rev. B | Page 20 of 36

Differential signals have some benefits over single-ended

gnals, including noise immunity based on the device’s

si common-mode rejection and improvements in distortion performance.

put of the AD7938/AD7939.

Figure 25 defines the fully differential analog

AD7938/AD7939

www.BDTIC.com/ADI

COMMON-MODE

VOLTAGE

Figure 25. Differential Input Definition

REF

p-p

REF

p-p

*ADDITIONAL PINS O MITTED F OR CLARITY.

IN+

AD7938/ AD7939*

IN–

03715-032

The amplitude of the differential signal is the difference

IN−

IN+

). V

and V

IN+

between the signals applied to the V differential pair (that is, V

IN+

− V simultaneously driven by two signals each of amplitude V 2 × V

depending on the range chosen) that are 180° out of

REF

phase. The amplitude of the differential signal is therefore −V to +V

peak-to-peak (that is, 2 × V

REF

). This is regardless of

REF

IN−

and V

pins in each

should be

IN−

REF

(or

REF

the common mode (CM). The common mode is the average of the two signals (that is, (V

IN+

+ V

)/2) and is therefore the

IN−

voltage on which the two inputs are centered. This results in the span of each input being CM ± V up externally and its range varies with the reference value V As the value of V

increases, the common-mode range

REF

/2. This voltage has to be set

REF

decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output voltage swing.

Figure 26 and Figure 27 show how the common-mode range

ically varies with V

typ to V

range or 2 × V

REF

for a 5 V power supply using the 0 V

REF

range, respectively. The common

REF

mode must be in this range to guarantee the functionality of the AD7938/AD7939.

When a conversion takes place, the common mode is rejected,

esulting in a virtually noise-free signal of amplitude −V

r +V

, corresponding to the digital codes of 0 to 4096 for the

REF

AD7938 and 0 to 1024 for the AD7939. If the 2 × V used, the input signal amplitude extends from −2 V

REF

range is

REF

to +2 V

REF

after conversion.

3.5 TA=25°C

3.0

2.5

2.0

1.5

4.5 TA= 25°C

4.0

3.5

3.0

2.5

2.0

1.5

COMMON-MO DE RANGE (V)

1.0

0.5

0.1 0. 6 1.61.1 2.1 2. 6

Figure 27. Input Common-Mode Range vs. V

(V)

REF

(2 × V

REF

Range, VDD = 5 V)

REF

03715-034

Driving Differential Inputs

Differential operation requires that V

and V

IN+

IN−

be simultaneously driven with two equal signals that are 180° out of phase. The common mode must be set up externally and has

a range that is determined by V particular amplifier used to drive the analog inputs. Differential

, the power supply, and the

REF

modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-todifferential conversion.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7938/AD7939. The circuit configurations shown in Figure 28 and Figure 29 s

how how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively.

The voltage applied to Point A sets up the common-mode vol

tage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. A suitable dual op amp that can be used in this configuration to provide differential drive to the AD7938/AD7939 is the AD8022.

Take care when choosing the op amp; the selection depends on t

he required power supply and system performance objectives. The driver circuits in Figure 28 and Figure 29 are optimized for dc co

upling applications requiring best distortion performance.

1.0

COMMON-MO DE RANGE (V)

0.5

00.5 1.51.0 2.0 2.5 3.0

Figure 26. Input Common-Mode Range vs. V

REF

(V)

(0 V to V

REF

Range, VDD = 5 V)

REF

03715-033

Rev. B | Page 21 of 36

The differential op amp driver circuit in Figure 28 is configured

convert and level shift a single-ended, ground-referenced

to (bipolar) signal to a differential signal centered at the V of the ADC.

The circuit configuration shown in Figure 29 converts a uni

polar, single-ended signal into a differential signal.

REF

level

AD7938/AD7939

www.BDTIC.com/ADI

GND

2×V

REF

p-p

440Ω

220Ω

20kΩ

220Ω

V+

27Ω

V–

220Ω

V+

10kΩ

27Ω

V–

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

IN+

AD7938/ AD7939

IN–

0.47µF

REF

Figure 28. Dual Op Amp Circuit to Convert a Single-Ended

Bipo

lar Signal into a Differential Unipolar Signal

440Ω

20kΩ

220Ω

V+

V–

220Ω

V+

V–

10kΩ

int

o a Differential Signal

27Ω

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

IN+

AD7938/ AD7939

IN–

0.47µF

REF

p-p

REF

GND

Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

Another method of driving the AD7938/AD7939 is to use the

AD8138 differential amplifier. The AD8138 can be used as a

gle-ended-to-differential amplifier or as a differential-to-

sin differential amplifier. The device is as easy to use as an op amp and greatly simplifies differential signal amplification and driving.

Pseudo Differential Mode

The AD7938/AD7939 can have four pseudo differential pairs (Pseudo Mode 1) or seven pseudo differential inputs (Pseudo Mode 2) by setting the MODE0 and MODE1 bits in the control register to 1, 0 and 1, 1, respectively. In the case of the four pseudo differential pairs, V which must have an amplitude of V

is connected to the signal source,

IN+

(or 2 × V

REF

depending

REF

on the range chosen) to make use of the full dynamic range of the part. A dc input is applied to the V

pin. The voltage

IN−

applied to this input provides an offset from ground or a pseudo ground for the V

input. In the case of the seven pseudo

IN+

differential inputs, the seven analog input signals inputs are referred to a dc voltage applied to V

IN7

The benefit of pseudo differential inputs is that they separate th

e analog input signal ground from the ADC ground, allowing dc common-mode voltages to be cancelled. Typically, this range can extend from −0.3 V to +0.7 V when V +1.8 V when V

= 5 V. Figure 30 shows a connection diagram

= 3 V or −0.3 V to

for pseudo differential mode.

p-p

REF

IN+

AD7938/ AD7939*

IN–

03715-035

ADDITIONAL PINS O MITTED FOR CLARIT Y.

Figure 30. Pseudo Differential M

DC INPUT

VOLTAGE

ode Connection Diagram

REF

0.47µF

03715-037

ANALOG INPUT SELECTION

As shown in Ta ble 10 , users can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the control register. Assuming the configuration has been chosen, there are different ways of selecting the analog input to be converted depending on the state of the SEQ and SHDW bits in the control register.

Traditional Multichannel Operation (SEQ = SHDW = 0)

Any one of eight analog input channels or four pairs of channels

03715-036

can be selected for conversion in any order by setting the SEQ and SHDW bits in the control register to 0. The channel to be converted is selected by writing to the address bits, ADD2 to ADD0, in the control register to program the multiplexer prior to the conversion. This mode of operation is that of a traditional multichannel ADC where each data write selects the next channel for conversion. m

ode of operation. The channel configurations are shown in

Figure 31 shows a flowchart of this

Tabl e 1 0 .

POWER ON

WRITE TO T HE CONTRO L REGISTER TO

SET UP OPERAT ING MODE, ANALOG I NPUT

AND OUTPUT CONF IGURATION.

SET SEQ = SHDW = 0. SELECT THE DESIRED

CHANNEL TO CONVERT (ADD2 T O ADD0).

ISSUE CONVST PULSE TO INITIATE A CONVERSION

Figure 31. Traditional Multichannel Operation Flow Chart

ON THE SELECTED CHANNEL.

INITIAT E A READ CYCL E TO READ THE DATA

FROM THE SELECTED CHANNEL.

INITIAT E A WRITE CYCLE TO SELECT THE NEXT

CHANNEL TO BE CONVE RTED BY

CHANGING THE VALUES OF BI TS ADD2 TO ADD0

IN THE CONTROL REGISTER. SEQ = SHDW = 0.

03715-038

Rev. B | Page 22 of 36

AD7938/AD7939

www.BDTIC.com/ADI

Using the Sequencer: Programmable Sequence (SEQ = 0, SHDW = 1)

The AD7938/AD7939 can be configured to automatically cycle through a number of selected channels using the on-chip programmable sequencer by setting SEQ = 0 and SHDW = 1 in the control register. The analog input channels to be converted are selected by setting the relevant bits in the shadow register to 1 (see Table 12).

Once the shadow register has been programmed with the required sequence, the next conversion executed is on the lowest channel programmed in the SHDW register. The next conversion executed is on the next highest channel in the sequence and so on. When the last channel in the sequence is converted, the internal multiplexer returns to the first channel selected in the shadow register and commences the sequence again.

It is not necessary to write to the control register again once a

sequencer operation has been initiated. The

input must be kept high to ensure that the control register is not accidentally overwritten or that a sequence operation is not interrupted. If the control register is written to at any time during the sequence, ensure that the SEQ and SHDW bits are set to 1, 0 to avoid interrupting the conversion sequence. The sequence program remains in force until such time as the AD7938/AD7939 is written to and the SEQ and SHDW bits are configured with any bit combination except 1, 0. Figure 32 shows a flow chart of the programmable sequence operation.

POWER ON

WRITE TO THE CONTROL REG ISTER TO

SET UP OPERATING MO DE , ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ = 0 SHDW = 1.

THIS WRI T E CYCLE IS TO PRO GRAM THE SHADOW REGIST E R.

THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.

CONTINUOUS LY CONVERT

CONSECUTIVE

CHANNELS SELECTED

IN THE SHADOW REGIST E R

WITH EACH CONV ST PULSE.

INITIATE A WRITE CYCLE.

SET RELEVANT BITS TO SELECT

WR = HIGH

SEQ BIT = 0

SHDW BIT = 1

Figure 32. Programmable Sequence Flow Chart

SEQ BIT = 1 SHDW BIT = 0

CONTINUOUS LY CONVERT

CONSECUTIVE

CHANNELS SELECTED

WITH EACH CONVST PULSE

BUT ALLOWS THE RANGE,

CODING, ANAL OG INPUT TYPE,

ETC BITS IN THE CONTROL

WITHOUT INTERRUPTING

THE SEQUENCE.

04751-039

Consecutive Sequence (SEQ = 1, SHDW = 1)

A sequence of consecutive channels can be converted beginning with Channel 0 and ending with a final channel selected by writing to the ADD2 to ADD0 bits in the control register. This is done by setting the SEQ and SHDW bits in the control register to 1. In this mode, the sequencer can be used without having to write to the shadow register. To set this mode up, the next conversion, once the control register is written to, is on Channel 0, then Channel 1, and so on, until the channel selected by the address bits (ADD2 to ADD0) is reached. The cycle begins again provided the

input is tied high. If low,

the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to continue its preprogrammed sequence uninterrupted. Figure 33 shows the flowchart of the consecutive sequence mode.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MO DE, ANALOG INPUT

AND OUTPUT CONFIGURATIO N SELECT

FINAL CHANNEL (ADD2 TO ADD0) IN

CONSECUTIVE SEQUENCE.

SET SEQ = 1 SHDW = 1.

CONTINUOUSLY CONVERT A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0

UP TO AND INCL UDING THE PRE V IOUSLY

SELECTED FINAL CHANNEL ON ADD2 TO ADD0

WITH EACH CONVST PULSE.

SEQ BIT = 1 SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE CHANNELS SELECTED

WITH EACH CONVST PULSE BUT

ALLOWS THE RANGE, CODING, ANALOG

INPUT TYPE, ETC. BITS IN THE

CONTROL REGISTER TO BE CHANGED

WITHOUT INTERRUPTI NG

THE SEQUENCE.

03715-040

Figure 33. Consecutive Sequence Mode Flow Chart

REFERENCE

The AD7938/AD7939 can operate with either the on-chip reference or external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. A block diagram of the internal reference circuitry is shown in Figure 34. The internal reference circuitry includes an on-chip 2.5 V band gap reference and a reference buffer. When using the internal reference, the V

REFIN/VREFOUT

decoupled to AGND with a 0.47 μF capacitor. This internal reference not only provides the reference for the analog-todigital conversion, but it can also be used externally in the system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system.

pin should be

REFIN

REFOUT

Rev. B | Page 23 of 36

Figure 34. Internal Reference Circuit Block Diagram

BUFFER

ADC

REFERENCE

AD7938/ AD7939

03715-041

AD7938/AD7939

www.BDTIC.com/ADI

Alternatively, an external reference can be applied to the V

pin of the AD7938/AD7939. An external reference

REFOUT

input is selected by setting the REF bit in the internal control register to 0. The external reference input range is 0.1 V to V It is important to ensure that, when choosing the reference value, the maximum analog input range (V greater than V

+ 0.3 V, to comply with the maximum ratings

IN MAX

) is never

of the device. For example, if operating in differential mode and the reference is sourced from V

, the 0 V to 2 × V

REF

range cannot be used. This is because the analog input signal range now extends to 2 × V

, which exceeds the maximum rating

conditions. In the pseudo differential modes, the user must ensure that V or when using the 2 × V

REF

+ (V

) ≤ VDD when using the 0 V to V

IN−

range that 2 × V

REF

+ (V

REF

) ≤ VDD.

IN−

In all cases, the specified reference is 2.5 V.

The performance of the part with different reference values is

n Figure 10 to Figure 12. The value of the reference sets

shown i t

he analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7938/AD7939 transfer function and add to specified fullscale errors on the part.

Tabl e 1 3 lists examples of suitable voltage references available

rom Analog Devices that can be used. Figure 35 shows a typical

nnection diagram for an external reference.

REFIN

range,

Digital Inputs

The digital inputs applied to the AD7938/AD7939 are not

limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the V

+ 0.3 V limit as on the analog inputs.

Another advantage of the digital inputs not being restricted by

+ 0.3 V limit is the fact that power supply sequencing

e V

issues are avoided. If any of these inputs are applied before V

, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to V

Input

DRIVE

The AD7938/AD7939 have a V voltage at which the parallel interface operates. V

DRIVE

feature. V

DRIVE

DD.

controls the

allows the

ADC to easily interface to 3 V and 5 V processors.

For example, if the AD7938/AD7939 are operated with an V of 5 V and the V

pin is powered from a 3 V supply, the

DRIVE

AD7938/AD7939 have better dynamic performance with an V

of 5 V while still being able to interface directly to 3 V

processors. Care should be taken to ensure V exceed V

by more than 0.3 V (see the Absolute Maximum

DRIVE

does not

Ratings section).

Table 13. Examples of Suitable Voltage Re

Reference

Output V

oltage (V)

Initial Accuracy (% Max)

ferences

Operating Current (μA)

AD780 2.5/3 0.04 1000 ADR421 2.5 0.04 500 ADR420 2.048 0.05 500

AD780

10nF 0.1µF

0.1µF

*ADDITIONAL PINS OMIT TED FOR CL ARITY.

Figure 35. Typical V

O/P SELECT

TEMP

GND

NC = NO CONNECT

REF

2.5V

OUT

TRIM

Connection Diagram

AD7938/ AD7939*

0.1µF

REF

03715-029

Rev. B | Page 24 of 36

AD7938/AD7939

www.BDTIC.com/ADI

PARALLEL INTERFACE

The AD7938/AD7939 have a flexible, high speed, parallel interface. This interface is 12-bits (AD7938) or 10-bits (AD7939) wide and is capable of operating in either word

(W/

tied high) or byte (W/B tied low) mode. The signal is used to initiate conversions; when operating in autoshutdown or autostandby mode, it is used to initiate power-up.

A falling edge on the

CONVST

signal is used to initiate conversions and it puts the ADC track-and-hold into track. Once the

CONVST

signal goes low, the BUSY signal goes high for the duration of the conversion. In between conversions, CONVST must happen after the 14

must be brought high for a minimum time of t1. This

falling edge of CLKIN; otherwise, the

conversion is aborted and the track-and-hold goes back into track.

CONVST

12 345 121314

CLKIN

BUSY

CONVST

CONVERT

At the end of the conversion, BUSY goes low and can be used to

tivate an interrupt service routine. The

and RD lines are then activated in parallel to read the 12- or 10-bits of conversion data. When power supplies are first applied to the device, a rising edge on

CONVST

is necessary to put the track-and-hold into track. The acquisition time of 125 ns minimum must be allowed before The ADC then goes into hold on the falling edge of and back into track on the 13

CONVST

is brought low to initiate a conversion.

CONVST

rising edge of CLKIN after this (see Figure 36). When operating the device in autoshutdown or a

utostandby mode, where the ADC powers down at the end of

each conversion, a rising edge on the

CONVST

signal is used to

power up the device.

INTERNAL

TRACK/HOLD

DB0 TO DB11

WITH CS AND RD TI ED LOW

Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/

THREE-STATE

ACQUISITION

DATA

DATAOLD DATADB0 TO DB11

THREE-STATE

QUIET

= 1)

03715-004

Rev. B | Page 25 of 36

AD7938/AD7939

www.BDTIC.com/ADI

Reading Data from the AD7938/AD7939

With the W/B pin tied logic high, the AD7938/AD7939 interface operates in word mode. In this case, a single read operation from the device accesses the conversion data-word on Pins DB0/DB2 to Pin DB11. The DB8/HBEN pin assumes its DB8 function. With the W/

pin tied to logic low, the AD7938/AD7939 interface operates in byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. Conversion data from the AD7938/AD7939 must be accessed in two read operations with eight bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the 12-bit or 10-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For 10-bit operation, the two LSBs of the low byte are 0s, followed by six bits of conversion data. For a high byte read, DB0 to DB3 provide the four MSBs of the 12-bit or10-bit word. DB5 to DB7 of the high byte provide the channel ID. dia

gram for a 12-bit or 10-bit transfer. When operating in word

Figure 36 shows the read cycle timing

mode, the HBEN input does not exist, and only the first read operation is required to access data from the device. When operating in byte mode, the two read cycles shown in

required to access the full data-word from the device.

are

Figure 37

The

and RD signals are gated internally and the level is

triggered active low. In either word mode or byte mode, RD

can be tied together because the timing specifications for t10

and t

are 0 ns minimum. This means the bus is constantly

and

driven by the AD7938/AD7939.

The data is placed onto the data bus a time t RD

go low. The RD rising edge can be used to latch data out of

the device. After a time, t

Alternatively,

and RD can be tied permanently low and the

, the data lines become three-stated.

conversion data is valid and placed onto the data bus a time, t

after both CS and

before the falling edge of BUSY.

Note that if

is pulsed during the conversion time, this

causes a degradation in linearity performance of approximately

0.25 LSB. Reading during conversion by way of tying RD

low does not cause any degradation.

and

HBEN/DB8

DB0 TO DB7

Figure 37. AD7938/AD7939 Parallel Interface—Read Cyc

LOW BYTE HIGH BYT E

le Timing for Byte Mode Operation (W/

03715-005

= 0)

Rev. B | Page 26 of 36

AD7938/AD7939

www.BDTIC.com/ADI

Writing Data to the AD7938/AD7939

With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the AD7938/AD7939. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB11 inputs, with DB0 being the LSB of the data-word. With W/

tied logic low, the AD7938/AD7939 requires two write operations to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word should be written first with DB0 being the LSB of the full dataword. For the high byte write, HBEN should be high and the data on the DB0 input should be data Bit 8 of the 12-bit word. In both word and byte mode, a single write operation to the shadow register is always sufficient since it is only eight bits wide.

Figure 38 shows the write cycle timing diagram of the AD7938/AD79

39 in word mode. When operating in word mode, the HBEN input does not exist and only one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. When operating in byte mode, the two write cycles shown in

o write the full data-word to the AD7938/AD7939. In Figure 39,

he first write transfers the lower eight bits of the data-word

Figure 39 are required

from DB0 to DB7, and the second write transfers the upper four bits of the data-word. When writing to the AD7938/AD7939, the top four bits in the high byte must be 0s.

The data is latched into the device on the rising edge of The data needs to be setup a time, t and held for a time, t WR

signals are gated internally. CS and WR can be tied

, after the WR rising edge. The CS and

together as the timing specifications for t minimum (assuming

and RD have not already been tied

, before the WR rising edge

and t5 are 0 ns

together).

DB0 TO DB11

Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/

DATA

03715-002

= 1)

HBEN/DB8

DB0 TO DB11

Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/

LOW BYTE HIGH BYTE

03715-003

= 0)

Rev. B | Page 27 of 36

AD7938/AD7939

www.BDTIC.com/ADI

POWER MODES OF OPERATION

The AD7938/AD7939 have four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the control register, as detailed in AD7938/AD79 that the default power-up condition is normal mode.

Note that, after power-on, the track-and-hold is in hold mode a

nd the first rising edge of

into track mode.

Normal Mode (PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times associated with the AD7938/AD7939. It remains fully powered up at all times. At power-on reset, this mode is the default setting in the control register.

Autoshutdown (PM1 = 0; PM0 = 1)

In this mode of operation, the AD7938/AD7939 automatically enter full shutdown at the end of each conversion, which is shown at Point A in Figure 36 and Figure 40. In shutdown m

ode, all internal circuitry on the device is powered down. The parts retain information in the control register during shutdown. The track-and-hold also goes into hold at this point and remains in hold as long as the device is in shutdown. The AD7938/AD7939 remains in shutdown mode until the next rising edge of In order to keep the device in shutdown for as long as possible, CONVST

Figure 40. On this rising edge, the part begins to power-up and t

he track-and-hold returns to track mode. The power-up time required is 10 ms minimum regardless of whether the user is operating with the internal or external reference. The user should ensure that the power-up time has elapsed before initiating a conversion.

Tabl e 9 . When power is first applied to the

39, an on-chip, power-on reset circuit ensures

CONVST

should idle low between conversions, as shown in

(see Point B in Figure 36 or Figure 40).

places the track-and-hold

Autostandby (PM1 = 1; PM0 = 0)

In this mode of operation, the AD7938/AD7939 automatically enter standby mode at the end of each conversion, which is shown as Point A in Figure 36. When this mode is entered, all cir

cuitry on the AD7938/AD7939 is powered down except for the reference and reference buffer. The track-and-hold goes into hold at this point also and remains in hold as long as the device is in standby. The parts remain in standby until the next rising

CONVST

edge of required depends on whether the internal or external reference is used. With an external reference, the power-up time required is a minimum of 600 ns, while when using the internal reference, the power-up time required is a minimum of 7 μs. The user should ensure this power-up time has elapsed before initiating another conversion as shown in

sing edge of

ri into track mode.

powers up the device. The power-up time

Figure 40. This

CONVST

also places the track-and-hold back

Full Shutdown Mode (PM1 =1; PM0 = 1)

When this mode is programmed, all circuitry on the AD7938/AD7939 is powered down upon completion of the write operation, that is, on the rising edge of and-hold enters hold mode at this point. The parts retain the information in the control register while the part is in shutdown. The AD7938/AD7939 remain in full shutdown mode, with the track-and-hold in hold mode, until the power management bits (PM1 and PM0) in the control register are changed. If a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to PM0 = PM1 = 0 (normal mode), the part begins to power up on the to track. To ensure the part is fully powered up before a conversion is initiated, the power-up time of 10 ms minimum should be allowed before the next invalid data is read.

Note that all power-up times quoted apply with a 470 nF ca

pacitor on the V

rising edge and the track-and-hold returns

REFIN

CONVST

pin.

falling edge; otherwise,

. The track-

POWER-UP

CONVST

1 114 14

CLKIN

BUSY

Figure 40. Autoshutdown/Autostandb

Rev. B | Page 28 of 36

y Mode

03715-049

AD7938/AD7939

www.BDTIC.com/ADI

POWER vs. THROUGHPUT RATE

A considerable advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7938/AD7939 are only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. sh

ows a plot of the power vs. throughput rate when operating in

autostandby mode for both V

= 5 V and 3 V. For example, if

the maximum CLKIN frequency of 25.5 MHz is used to minimize the conversion time, this accounts for only 0.525 μs of the overall cycle time while the AD7938/AD7939 remains in standby mode for the remainder of the cycle. If the devices run at a throughput rate of 10 kSPS, for example, the overall cycle time is 100 μs.

Figure 42 shows a plot of the power vs. throughput rate when o

perating in normal mode for both V

= 5 V and VDD = 3 V. In

both plots, the figures apply when using the internal reference. If an external reference is used, the power-up time reduces to 600 ns; therefore, the AD7938/AD7939 remain in standby for a greater time in every cycle. Additionally, the current consumption, when converting, should be lower than the specified maximum of 2.7 mA with V

1.8

1.6

1.4

1.2

1.0

0.8

POWER (mW)

0.6

0.4

0.2

0 20 40 60 80 100 120 140

= 5 V, or 2.0 mA with VDD = 3 V.

TA= 25°C

THROUGHPUT (kSPS)

Figure 41. Power vs. Throughput in

Autostandby Mode Using Internal

VDD=5V

VDD=3V

Reference

Figure 41

03715-042

TA= 25°C

POWER (mW)

0 200 400 600 800 1000 1200 16001400

THROUGHPUT (kSPS)

VDD=5V

VDD=3V

03715-043

Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference

MICROPROCESSOR INTERFACING

AD7938/AD7939 to ADSP-21xx Interface

Figure 43 shows the AD7938/AD7939 interfaced to the ADSP21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD7938/AD7939 to the ADSP-21xx depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family User’s Manual for details). The following instruction reads from the AD7938/AD7939:

MR = DM (AD

where AD

*ADDITIONAL PINS O MITTED F OR CLARITY.

C is the address of the AD7938/AD7939.

A0 TO A15

ADSP-21xx*

D0 TO D23

ADDRESS BUS

DMS

IRQ2

ADDRESS DECODER

DATA BUS

Figure 43. Interfacing to the ADSP-21xx

DSP

USER SYSTEM

CONVST

AD7938/ AD7939*

BUSY

DB0 TO DB11

03715-045

Rev. B | Page 29 of 36

AD7938/AD7939

www.BDTIC.com/ADI

DSP

AD7938/AD7939 to ADSP-21065L Interface

Figure 44 shows a typical interface between the AD7938/AD7939 and the ADSP-21065L SHARC® processor. This i

nterface is an example of one of three DMA handshake modes. The lines. Internal ADDR lines are then asserted as chip selects. The

control line is actually three memory select

are decoded into

25-24

3 to 0

DMAR

, and these

(DMA request 1) is used in this setup as the interrupt to signal the end of conversion. The rest of the interface is a standard handshaking operation.

DSP

USER SYSTEM

TO ADDR

ADDR

ADSP-21065L*

DMAR

D0 TO D31

*ADDITIONAL PINS OMIT TED FOR CL ARITY.

ADDRESS BUS

ADDRESS

LATCH

ADDRESS BUS

ADDRESS

DECODER

DATA BUS

CONVST

AD7938/ AD7939*

BUSY

RDRD

DB0 TO DB11

Figure 44. Interfacing to the ADSP-21065L

AD7938/AD7939 to TMS32020, TMS320C25, and TMS320C5x Interface

Parallel interfaces between the AD7938/AD7939 and the TMS32020, TMS320C25, and TMS320C5x family of DSPs are shown in Figure 45. The memory mapped address chosen for th

e AD7938/AD7939 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7938/AD7939 is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic, such as 74AS devices, is used to drive the

and the WR lines when interfacing to the TMS320C25, no wait states are necessary. However, if slower logic is used, data accesses can be slowed sufficiently when reading from, and writing to, the part to require the insertion of one wait state. Extra wait states are necessary when using the TMS320C5x at their fastest clock speeds (see the TMS320C5x User’s Guide for details).

Data is read from the ADC using the following instruction

IN D, AD

A0 TO A15

TMS32020/

TMS320C25/

TMS320C50*

READY

MSC

STRB

INT

*ADDITIONAL PINS O MITTED F OR CLARITY.

R/W

ADDRESS BUS

ADDRESS DECODER

DATA BUS

TMS320C25

ONLY

Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x

AD7938/AD7939 to 80C186 Interface

Figure 46 shows the AD7938/AD7939 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7938/AD7939 finish a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1).

03715-046

Because of the interrupt, the processor performs a DMA read operation that also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request is serviced before the completion of the next conversion.

AD0 TO AD15

A16 TO A19

80C186*

ADDITIO NAL PINS OMIT TED FOR C LARITY.

ADDRESS/DAT A BUS

ALE

DRQ1

ADDRESS

LATCH

ADDRESS DECODER

ADDRESS BUS

Figure 46. Interfacing to the 80C186

DATA BUS

USER SYSTEM

CONVST

AD7938/ AD7939*

CSEN

BUSY

DB11 TO DB0DMD0 TO DMD15

MICROPRO CESSOR/

USER SYSTEM

CONVST

AD7938/ AD7939*

BUSY

RDRD

DB0 TO DB11

03715-047

03715-048

where:

s the data memory address.

D i ADC is the AD7938/AD7939 address.

Rev. B | Page 30 of 36

AD7938/AD7939

www.BDTIC.com/ADI

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7938/AD7939 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Generally, a minimum etch technique is best for ground planes since it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the AD7938/AD7939 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7938/AD7939 to avoid noise coupling. The power supply lines to the AD7938/AD7939 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with d

igital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should b

e decoupled with 10 μF tantalum capacitors in parallel with

0.1 μF capacitors to GND. To achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the chip scale package (CP-32-2) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.

EVALUATING AD7938/AD7939 PERFORMANCE

The recommended layout for the AD7938/AD7939 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7938/AD7939 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate and evaluate the ac and dc performance of the AD7938/AD7939.

The software allows the user to perform ac (fast Fourier

ransform) and dc (histogram of codes) tests on the

t AD7938/AD7939. The software and documentation are on the CD that ships with the evaluation board.

Rev. B | Page 31 of 36

AD7938/AD7939

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.08

9.00 BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.80 BSC

LEAD PITCH

0.60 MAX

EXPOSED

PAD

(BOTTOM VIEW)

0.45

0.37

0.30

3.50 REF

7.00

BSC SQ

PIN 1 INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

5.00

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

1.20

0.75 MAX

0.60

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0° MIN

0.08 MAX COPLANARITY

0.20

0.09 7°

3.5° 0°

0.45

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AB A

Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

Rev. B | Page 32 of 36

020607-A

AD7938/AD7939

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)

AD7938BCP –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7938BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7938BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7938BCPZ AD7938BCPZ-REEL7 AD7938BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7938BSUZ AD7938BSUZ-REEL7 EVAL-AD7938CB AD7939BCP –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7939BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7939BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 AD7939BCPZ AD7939BCPZ-REEL7 AD7939BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 AD7939BSUZ AD7939BSUZ-REEL7 EVAL-AD7939CB EVAL-CONTROL-BRD2

Linearity error here refers to integral linearity error.

Z = Pb-free part.

This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.

Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the letters

CB. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (for example, EVAL AD7938CB), the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See the relevant evaluation board data sheet for more details.

–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2

–40°C to +85°C ±1 32-Lead TQFP SU-32-2 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 Evaluation Board

–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2

–40°C to +85°C ±1 32-Lead TQFP SU-32-2 –40°C to +85°C ±1 32-Lead TQFP SU-32-2 Evaluation Board Controller Board

Package Description Package Option

Rev. B | Page 33 of 36

AD7938/AD7939

www.BDTIC.com/ADI

NOTES

Rev. B | Page 34 of 36

AD7938/AD7939

www.BDTIC.com/ADI

NOTES

Rev. B | Page 35 of 36

AD7938/AD7939

www.BDTIC.com/ADI

NOTES

Rev. B | Page 36 of 36

Datasheet AD7939 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

REVISION HISTORY

SPECIFICATIONS

AD7938 SPECIFICATIONS

AD7939 SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

ON-CHIP REGISTERS

CONTROL REGISTER

SEQUENCER OPERATION

Writing to the Control Register to Program the Sequencer

SHADOW REGISTER

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT STRUCTURE

SINGLE-E NDED MODE

ANALOG INPUTS

Differential Mode

Driving Differential Inputs

Using an Op Amp Pair

Pseudo Differential Mode

ANALOG INPUT SELECTION

Traditional Multichannel Operation (SEQ = SHDW = 0)

Using the Sequencer: Programmable Sequence (SEQ = 0, SHDW = 1)

Consecutive Sequence (SEQ = 1, SHDW = 1)

REFERENCE

Digital Inputs

PARALLEL INTERFACE

Reading Data from the AD7938/AD7939

Writing Data to the AD7938/AD7939

POWER MODES OF OPERATION

Normal Mode (PM1 = PM0 = 0)

Autoshutdown (PM1 = 0; PM0 = 1)

Autostandby (PM1 = 1; PM0 = 0)

Full Shutdown Mode (PM1 =1; PM0 = 1)

POWER vs. THROUGHPUT RATE

MICROPROCESSOR INTERFACING

AD7938/AD7939 to ADSP-21xx Interface

AD7938/AD7939 to ADSP-21065L Interface

AD7938/AD7939 to TMS32020, TMS320C25, and TMS320C5x Interface

AD7938/AD7939 to 80C186 Interface

APPLICATION HINTS

GROUNDING AND LAYOUT

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

EVALUATING AD7938/AD7939 PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE