Analog Devices AD7923 Datasheet

4-Channel, 200 kSPS, 12-Bit ADC

with Sequencer in 16-Lead TSSOP

FEATURES Fast Throughput Rate: 200 kSPS Specified for AV

of 2.7 V to 5.25 V

Low Power:

3.6 mW Max at 200 kSPS with 3 V Supply

7.5 mW Max at 200 kSPS with 5 V Supply 4 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth:

70 dB Min SNR at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI™/QSPI™/

MICROWIRE™/DSP Compatible Shutdown Mode: 0.5

␮A Max

16-Lead TSSOP Package

GENERAL DESCRIPTION

The AD7923 is a 12-bit, high speed, low power, 4-channel, successive approximation ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates up to 200 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part.

The AD7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7923 consumes 1.2 mA maximum with 3 V supplies, and with 5 V supplies the current consumption is 1.5 mA maximum.

Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REF to 2 ¥ REF

, with either straight binary or twos complement

or 0 V

output coding. The AD7923 features four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially.

The conversion time for the AD7923 is determined by the SCLK frequency, as this is also used as the master clock to control the conversion. The conversion time may be as short as 800 ns with a 20 MHz SCLK.

AD7923

FUNCTIONAL BLOCK DIAGRAM

REF

VIN0

•

• 3

I/P

MUX

AD7923

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The AD7923 offers up to 200 kSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7923 dissipates just 3.6 mW of power maximum.

2. Four Single-Ended Inputs with a Channel Sequencer. A consecutive sequence of channels, through which the ADC will cycle and convert on, can be selected.

3. Single-Supply Operation with V The AD7923 operates from a single 2.7 V to 5.25 V supply. The V

function allows the serial interface to connect

DRIVE

directly to either 3 V or 5 V processor systems independent of AV

4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 mA maximum when in full shutdown.

5. No Pipeline Delay. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.

T/H

SEQUENCER

APPROXIMATION

CONTROL LOGIC

GND

DRIVE

12-BIT

SUCCESSIVE

ADC

Function.

SCLK

DOUT

DIN

DRIVE

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

AD7923–SPECIFICATIONS

(AVDD = V

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

unless otherwise noted.)

= 20 MHz, TA = T

SCLK

MIN

to T

MAX

Parameter B Version

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) (SINAD)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

70 dB min @ 5 V 69 dB min @ 3 V Typically 70 dB

70 dB min –77 dB max @ 5 V Typically –84 dB

Unit Test Conditions/Comments

= 50 kHz Sine Wave, f

SCLK

= 20 MHz

–73 dB max @ 3 V Typically –77 dB

Peak Harmonic or Spurious Noise –78 dB max @ 5 V Typically –86 dB

(SFDR)

Intermodulation Distortion (IMD)

–76 dB max @ 3 V Typically –80 dB

fa = 40.1 kHz, fb = 41.5 kHz Second Order Terms –90 dB typ Third Order Terms –90 dB typ

Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

–85 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits Integral Nonlinearity ± 1 LSB max Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits. 0 V to REF

Input Range Straight Binary Output Coding

Offset Error ± 8 LSB max Typically ± 0.5 LSB Offset Error Match ± 0.5 LSB max Gain Error ± 1.5 LSB max Gain Error Match ± 0.5 LSB max

0 V to 2 ¥ REF

Input Range –REFIN to +REFIN Biased about REFIN with

Positive Gain Error ± 1.5 LSB max Twos Complement Output Coding Positive Gain Error Match ± 0.5 LSB max Zero Code Error ± 8 LSB max Typically ± 0.8 LSB Zero Code Error Match ± 0.5 LSB max Negative Gain Error ± 1 LSB max Negative Gain Error Match ± 0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

0 to 2 ¥ REF

V RANGE Bit Set to 1

V RANGE Bit Set to 0, AVDD/V

= 4.75 V to 5.25 V

DRIVE

DC Leakage Current ± 1 mA max Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ± 1% Specified Performance DC Leakage Current ± 1 mA max REFIN Input Impedance 36 kW typ f

SAMPLE

= 200 kSPS

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

0.7 ¥ V

DRIVE

0.3 ¥ V

DRIVE

± 1 mA max Typically 10 nA, V 10 pF max

V min V max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ± 1 mA max Floating-State Output Capacitance

– 0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 mA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 mA

SINK

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

–2– REV. 0

AD7923

Parameter B Version1Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input

300 ns max Full-Scale Step Input

Throughput Rate 200 kSPS max See Serial Interface Section

POWER REQUIREMENTS

DRIVE

During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, f

Normal Mode (Static) 600 mA typ AV Normal Mode (Operational) f

Using Auto Shutdown Mode f

= 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, f

SAMPLE

= 200 kSPS 900 mA typ AVDD = 4.75 V to 5.25 V, f

SAMPLE

Auto Shutdown (Static) 0.5 mA max SCLK On or Off (20 nA typ) Full Shutdown Mode 0.5 mA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) f

= 200 kSPS 7.5 mW max AVDD = 5 V, f

SAMPLE

Auto Shutdown (Static) 2.5 mW max AV

Full Shutdown Mode 2.5 mW max AV

NOTES

Temperature ranges as follows: B Version: –40∞C to +85∞C.

See Terminology section.

Sample tested @ 25∞C to ensure compliance.

See Power versus Throughput Rate section.

Specifications subject to change without notice.

2.7/5.25 V min/max

2.7/5.25 V min/max Digital I/Ps = 0 V or V

2.0 mA max AV

1.2 mA max AV

650 mA typ AV

3.6 mW max AV

1.5 mW max AV

= 2.7 V to 3.6 V, f

= 2.7 V to 5.25 V, SCLK On or Off

= 2.7 V to 3.6 V, f

= 3 V, f

= 5 V

= 3 V

= 5 V

1.5 mW max AVDD = 3 V

= 20 MHz

SCLK

= 20 MHz

SCLK

DRIVE

SCLK

SAMPLE

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

= 200 kSPS

SAMPLE

= 200 kSPS

–3–REV. 0

AD7923

TIMING SPECIFICATIONS

Limit at T

(AVDD = 2.7 V to 5.25 V, V

, T

MAX

AD7923

MIN

ⱕ AVDD, REFIN = 2.5 V, TA = T

DRIVE

MIN

to T

, unless otherwise noted.)

MAX

Parameter AVDD = 3 V AVDD = 5 V Unit Description

SCLK

10 10 kHz min 20 20 MHz max

CONVERT

QUIET

16 ¥ t

SCLK

50 50 ns min Minimum Quiet Time Required between CS Rising

16 ¥ t

SCLK

Edge and Start of Next Conversion

10 10 ns min CS to SCLK Setup Time 35 30 ns max Delay from CS until DOUT Three-State Disabled 40 40 ns max Data Access Time after SCLK Falling Edge

0.4 ¥ t

SCLK

0.4 ¥ t

SCLK

ns min SCLK Low Pulsewidth

ns min SCLK High Pulsewidth 10 10 ns min SCLK to DOUT Valid Hold Time 15/45 15/35 ns min/max SCLK Falling Edge to DOUT High Impedance 10 10 ns min DIN Setup Time Prior to SCLK Falling Edge 55 ns min DIN Hold Time after SCLK Falling Edge 20 20 ns min Sixteenth SCLK Falling Edge to CS High 11 ms max Power-Up Time from Full Power-Down/Auto

Shutdown Mode

NOTES

Sample tested at 25∞C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ V

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish time of the part and is independent of the bus loading.

Specifications subject to change without notice.

DRIVE

1.6V

OUTPUT

200␮A

50pF

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

–4–

REV. 0

AD7923

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

DRIVE

Analog Input Voltage to AGND . . . . –0.3 V to AV

+ 0.3 V

Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to AGND . . . . –0.3 V to AV

REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Input Current to Any Pin Except Supplies

. . . . . . . . ± 10 mA

+ 0.3 V

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

ORDERING GUIDE

Temperature Linearity Package Package

Model Range Error (LSB)

AD7923BRU –40∞C to +85∞C ±1 RU-16 TSSOP EVAL-AD7923CB EVAL-CONTROL BRD2

NOTES

Linearity error here refers to integral linearity error.

This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

To order a complete evaluation kit, the you will need to order the particular ADC evaluation board, e.g., EVAL-AD7923CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . 150.4∞C/W (TSSOP)

Thermal Impedance . . . . . . . . . . . . . 27.6∞C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

Option Description

Evaluation Board Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7923 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. 0

AD7923

PIN CONFIGURATION

16-Lead TSSOP

SCLK AGND

DIN V

AD7923

AGND AGND

REF

AGND VIN3

TOP VIEW

(Not to Scale)

DRIVE

DOUT

VIN0

VIN1

VIN2

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock

input is also used as the clock source for the AD7923 conversion process.

2DIN Data In. Logic Input. Data to be written to the AD7923 Control Register is provided on this input and is

clocked into the register on the falling edge of SCLK (see the Control Register section).

3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7923 and framing the serial data transfer.

4, 8, 13, 16 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input

signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.

5, 6 AV

7 REF

Analog Power Supply Input. The AVDD range for the AD7923 is from 2.7 V to 5.25 V. For the 0 V to 2 ¥ REF

range, AVDD should be from 4.75 V to 5.25 V.

Reference Input for the AD7923. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance.

12–9 V

0–VIN3Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed

into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD1 and ADD0 of the Control Register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REF

or from 0 V to 2 ¥ REFIN as selected via the RANGE bit in the Control Register.

Any unused input channels must be connected to AGND to avoid noise pickup.

14 DOUT Data Out. Logic Output. The conversion result from the AD7923 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7923 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be selected as straight binary or twos complement via the CODING bit in the Control Register.

15 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface of the AD7923 will operate.

–6–

REV. 0

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