Analog Devices AD7910 20 b Datasheet

250 kSPS,

10-/12-Bit ADCs in 6-Lead SC70

FEATURES
Throughput Rate: 250 kSPS
Specified for V

of 2.35 V to 5.25 V

DD

Low Power:

3.6 mW Typ at 250 kSPS with 3 V Supplies

12.5 mW Typ at 250 kSPS with 5 V Supplies

Wide Input Bandwidth:

71 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface

®

/QSPI™/MICROWIRE™/DSP Compatible

SPI
Standby Mode: 1 ␮A Max
6-Lead SC70 Package
8-Lead MSOP Package

APPLICATIONS
Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors

GENERAL DESCRIPTION

The AD7910/AD7920 are, respectively, 10-bit and 12-bit, high
speed, low power, successive-approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.

The AD7910/AD7920 use advanced design techniques to achieve
very low power dissipation at high throughput rates.

AD7910/AD7920

*

FUNCTIONAL BLOCK DIAGRAM

V

DD

10-/12-BIT

V

T/H

IN

The reference for the part is taken internally from V

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

AD7910/AD7920

GND

SCLK

SDATA

CS

DD.

This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to V

. The conversion rate

DD

is determined by the SCLK.

PRODUCT HIGHLIGHTS

1. 10-/12-Bit ADCs in SC70 and MSOP Packages.

2. Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management.

The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption to
be reduced when power-down mode is used while not convert­ing. The part also features a power-down mode to maximize
power efficiency at lower throughput rates. Current consumption
is 1 A max and 50 nA typically when in power-down mode.

4. Reference Derived from the Power Supply.

5. No Pipeline Delay.

The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.

*Protected by U.S.Patent No. 6,681,332.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7910–SPECIFICATIONS

(V

= 2.35 V to 5.25 V, f

1

DD

otherwise noted.)

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

MIN

to T

MAX

, unless

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

3

3

3

61 dB min
–72 dB max

3

–73 dB max

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave

IN

Second-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 13.5 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity ± 0.5 LSB max
Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error
Gain Error
Total Unadjusted Error (TUE)

3, 4

3, 4

3, 4

± 1LSB max
± 1LSB max
± 1.2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

V
DC Leakage Current ± 0.5 mA max
Input Capacitance 20 pF typ

Track-and-Hold in Track, 6 pF Typ when in Hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I
Input Current, IIN, CS Pin ± 10 nA typ
Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 mA max Typically 10 nA, V

IN

5

IN

2.4 V min

0.8 V max V

0.4 V max V

5 pF max

DD

DD

= 5 V
= 3 V

= 0 V or V

IN

DD

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 mA max
Floating-State Output Capacitance

OH

OL

5

– 0.2 V min I

DD

0.4 V max I

5 pF max

SOURCE

= 200 mA

SINK

= 200 mA, V

= 2.35 V to 5.25 V

DD

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 2.8 ms max 14 SCLK Cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time

3

250 ns max

Throughput Rate 250 kSPS max

POWER REQUIREMENTS

V

DD

I

DD

Normal Mode(Static) 2.5 mA typ V

Normal Mode (Operational) 3 mA max V

Full Power-Down Mode 1 mA max Typically 50 nA

Power Dissipation

6

Normal Mode (Operational) 15 mW max V

Full Power-Down 5 mW max V

NOTES

1

Temperature range from –40∞C to +85∞C.

2

Operational from V

3

See Terminology section.

4

SC70 values guaranteed by characterization.

5

Guaranteed by characterization.

6

See Power Vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input high voltage (V

DD

2.35/5.25 V min/max

1.2 mA typ V

1.4 mA max V

4.2 mW max V

3 mW max V

) 1.8 V min.

INH

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK On or Off

DD

= 2.35 V to 3.6 V, SCLK On or Off

DD

= 4.75 V to 5.25 V, f

DD

= 2.35 V to 3.6 V, f

DD

= 5 V, f

DD

= 3 V, f

DD

= 5 V

DD

= 3 V

DD

SAMPLE

SAMPLE

DD

SAMPLE

SAMPLE

= 250 kSPS
= 250 kSPS

= 250 kSPS

= 250 kSPS

–2–

REV. B

AD7920–SPECIFICATIONS

(V

= 2.35 V to 5.25 V, f

1

DD

otherwise noted.)

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

AD7910/AD7920

to T

MAX

, unless

MIN

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)

3

70 70 dB min VDD = 2.35 V to 3.6 V, TA = 25∞C

1, 2

B Grade

69 69 dB min V

71.5 71.5 dB typ V
69 69 dB min V

Signal-to-Noise Ratio (SNR)

3

68 68 dB min V
71 71 dB min VDD = 2.35 V to 3.6 V, TA = 25∞C
70 70 dB min V
70 70 dB min V

Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

3

3

69 69 dB min V
–80 –80 dB typ

3

–82 –82 dB typ

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave

IN

= 2.4 V to 3.6 V

DD

= 2.35 V to 3.6 V

DD

= 4.75 V to 5.25 V, TA = 25∞C

DD

= 4.75 V to 5.25 V

DD

= 2.4 V to 3.6 V

DD

= 4.75 V to 5.25 V, TA = 25∞C

DD

= 4.75 V to 5.25 V

DD

Second-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Aperture Delay 10 10 ns typ
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 13.5 13.5 MHz typ @ 3 dB

22MHz typ @ 0.1 dB

DC ACCURACY B Grade

Resolution 12 12 Bits
Integral Nonlinearity

3

± 1.5 LSB max

4

± 0.75 LSB typ

Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits

Offset Error

Gain Error

Total Unadjusted Error (TUE)

3, 5

3, 5

3,5

± 0.75 LSB typ

± 1.5 LSB max

± 1.5 ±0.2 LSB typ

± 1.5 LSB max

± 1.5 ±0.5 LSB typ

± 2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

0 to V

DD

V
DC Leakage Current ± 0.5 ±0.5 mA max
Input Capacitance 20 20 pF typ

Track-and-Hold in Track, 6 pF Typ when in Hold

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I
Input Current, IIN, CS Pin ± 10 ± 10 nA typ
Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 ± 0.5 mA max Typically 10 nA, V

IN

6

IN

2.4 2.4 V min

1.8 1.8 V min V

0.8 0.8 V max V

0.4 0.4 V max V

5 5pF max

= 2.35 V

DD

= 3.6 V to 5.25 V

DD

= 2.35 V to 3.6 V

DD

= 0 V or V

IN

DD

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 ± 1 mA max
Floating-State Output Capacitance

OH

OL

6

– 0.2 V

DD

0.4 0.4 V max I

55pF max

– 0.2 V min I

DD

SOURCE

= 200 mA

SINK

= 200 mA, V

= 2.35 V to 5.25 V

DD

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 3.2 3.2 ms max 16 SCLK Cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time

3

250 250 ns max

Throughput Rate 250 250 kSPS max See Serial Interface Section

REV. B

–3–

AD7910/AD7920

AD7920–SPECIFICATIONS

Parameter A Grade

1

(continued)

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

POWER REQUIREMENTS

V

DD

I

DD

Normal Mode (Static) 2.5 2.5 mA typ V

Normal Mode (Operational) 3 3 mA max V

Full Power-Down Mode 1 1 mA max Typically 50 nA

Power Dissipation

7

Normal Mode (Operational) 15 15 mW max V

Full Power-Down 5 5 mW max V

NOTES

1

Temperature range from –40∞C to +85∞C.

2

Operational from V

3

See Terminology section.

4

B Grade, maximum specs apply as typical figures when VDD = 4.75 V to 5.25 V.

5

SC70 values guaranteed by characterization.

6

Guaranteed by characterization.

7

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input low voltage (V

DD

TIMING SPECIFICATIONS

2.35/5.25 2.35/5.25 V min/max

1.2 1.2 mA typ V

1.4 1.4 mA max V

4.2 4.2 mW max V

33mW max V

) 0.35 V max.

INL

1

(V

= 2.35 V to 5.25 V, TA = T

DD

MIN

to T

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK On or Off

DD

= 2.35 V to 3.6 V, SCLK On or Off

DD

= 4.75 V to 5.25 V, f

DD

= 2.35 V to 3.6 V, f

DD

= 5 V, f

DD

= 3 V, f

DD

= 5 V

DD

= 3 V

DD

, unless otherwise noted.)

MAX

SAMPLE

SAMPLE

DD

SAMPLE

SAMPLE

= 250 kSPS
= 250 kSPS

= 250 kSPS

= 250 kSPS

AD7910/AD7920

Parameter Limit at T

f

SCLK

2

10 kHz min

MIN, TMAX

Unit Description

3

5 MHz max

t

CONVERT

t

QUIET

14  t
16  t

SCLK

SCLK

AD7910
AD7920

50 ns minMinimum Quiet Time Required between Bus Relinquish and

Start of Next Conversion

t

1

t

2

4

t

3

4

t

4

t

5

t

6

5

t

7

6

t

8

t

POWER-UP

NOTES

1

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Minimum f

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V

5

Measured with a 50 pF load capacitor.

6

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

7

t7 values apply to t8 minimum values also.

8

See Power-Up Time section.

Specifications subject to change without notice.

8

at which specifications are guaranteed.

SCLK

10 ns min Minimum CS Pulse Width
10 ns min CS to SCLK Setup Time
22 ns max Delay from CS until SDATA Three-State Disabled
40 ns max Data Access Time after SCLK Falling Edge

0.4  t

0.4  t

SCLK

SCLK

ns min SCLK Low Pulse Width
ns min SCLK High Pulse Width

SCLK to Data Valid Hold Time

10 ns min V

9.5 ns min 3.3 V < V
7 ns min V

£ 3.3 V

DD

> 3.6 V

DD

£ 3.6 V

DD

36 ns max SCLK Falling Edge to SDATA Three-State
See Note 7 ns min SCLK Falling Edge to SDATA Three-State
1 ms max Power-Up Time from Full Power-Down

= 2.35 V and 0.8 V or 2.0 V for V

DD

> 2.35 V.

DD

–4–

REV. B

AD7910/AD7920

I

OL

1.6V

I

OH

TO OUTPUT

PIN

50pF

200␮A

C

L

200␮A

Figure 1. Load Circuit for Digital Output Timing
Specifications

CS

t

CONVERT

t

6

t

7

SCLK

SDATA

STATE

t

2

12 345 1314 15 16

t

3

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

Z

4 LEADING ZEROS

t

4

Figure 2. AD7920 Serial Interface Timing Diagram

TIMING EXAMPLES

Figures 2 and 3 show some of the timing parameters from the
Timing Specifications table.

Timing Example 1

From Figure 3, having f
250 kSPS gives a cycle time of t

= 10 ns min, this leaves t

With t

2

satisfies the requirement of 250 ns for t
comprises 2.5(1/f

SCLK

allows a value of 954 ns for t

= 5 MHz and a throughput rate of

SCLK

) + t8 + t

+ 12.5(1/f

2

to be 1.49 ms. This 1.49 ms

ACQ

ACQ

, where t8 = 36 ns max. This

QUIET

satisfying the minimum re-

QUIET,

) + t

SCLK

. From Figure 3, t

ACQ

= 4 ms.

ACQ

quirement of 50 ns.

t

1

B

t

5

t

8

t

QUIET

THREE-STATETHREE-

CS

t

SCLK

CONVERT

)

1/THROUGHPUT

SCLK

t

2

1 2345 13141516

12.5(1/f

Figure 3. Serial Interface Timing Example

Timing Example 2

The AD7920 can also operate with slower clock frequencies.
From Figure 3, having f
of 150 kSPS gives a cycle time of t

6.66 ms. With t

= 10 ns min, this leaves t

2

2.97 ms satisfies the requirement of 250 ns for t
Figure 3, t

comprises 2.5(1/f

ACQ

= 3.4 MHz and a throughput rate

SCLK

2

SCLK

+ 12.5(1/f

ACQ

) + t8 + t

) + t

SCLK

to be 2.97 ms. This

. From

ACQ

, t8 = 36 ns

QUIET

ACQ

=

B

max. This allows a value of 2.19 ms for t

C

t

8

t

ACQ

t

QUIET

, satisfying the

QUIET

minimum requirement of 50 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary to leave
50 ns minimum t

between conversions. In this example, the

QUIET

signal should be fully acquired at approximately point C in
Figure 3.

REV. B

–5–

AD7910/AD7920

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . –0.3 V to V

+ 0.3 V

DD

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . –0.3 V to V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ± 10 mA

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Grade) . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

MSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 205.9∞C/W

q

JA

SC70 Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 340.2∞C/W

q

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 228.9∞C/W

q

JC

Lead Temperature, Soldering

Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . 235 (0/+5)∞C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

qJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 43.74∞C/W

ORDERING GUIDE

Temperature Linearity Package

Model Range Error (LSB)

1

Option

2

Branding

AD7910AKS-500RL7 –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910AKS-REEL –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910AKS-REEL7 –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910ARM –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7910ARM-REEL –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7910ARM-REEL7 –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7920AKS-500RL7 –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920AKS-REEL –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920AKS-REEL7 –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920BKS –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BKS-REEL –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BKS-REEL7 –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BRM –40∞C to +85∞C ± 1.5 max RM-8 CUB
AD7920BRM-REEL –40∞C to +85∞C ± 1.5 max RM-8 CUB
AD7920BRM-REEL7 –40∞C to +85∞C ± 1.5 max RM-8 CUB
EVAL-AD7910CB
EVAL-AD7920CB
EVAL-CONTROL BRD2

NOTES

1

Linearity error refers to integral nonlinearity.

2

KS = SC70, RM = MSOP.

3

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

4

This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a
complete evaluation kit, a particular ADC evaluation board must be ordered, e.g., EVAL-AD7920CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer.
See relevant evaluation board technical note for more information.

3

3

4

Evaluation Board
Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7910/AD7920 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. B