ANALOG DEVICES AD7908, AD7918, AD7928 Service Manual

8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs

with Sequencer in 20-Lead TSSOP

AD7908/AD7918/AD7928

FEATURES Fast Throughput Rate: 1 MSPS Specified for AV

of 2.7 V to 5.25 V

Low Power:

6.0 mW Max at 1 MSPS with 3 V Supply

13.5 mW Max at 1 MSPS with 5 V Supply 8 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth:

AD7928, 70 dB Min SINAD at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI

/QSPI™/

MICROWIRE™/DSP Compatible Shutdown Mode: 0.5

␮A Max

20-Lead TSSOP Package

GENERAL DESCRIPTION

The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 8-channel, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1MSPS. The parts contain a low noise, wide bandwidth trackand-hold amplifier that can handle input frequencies in excess of 8 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part.

The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7908/AD7918/AD7928 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum.

Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REF 2 ⫻ REF

, with either straight binary or twos complement out-

or 0 V to

put coding. The AD7908/AD7918/AD7928 each feature eight single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially.

The conversion time for the AD7908/AD7918/AD7928 is determined by the SCLK frequency, which is also used as the master clock to control the conversion.

FUNCTIONAL BLOCK DIAGRAM

REF

VIN0

•

• 7

I/P

MUX

AD7908/AD7918/AD7928

T/H

SEQUENCER

APPROXIMATION

CONTROL LOGIC

GND

8-/10-/12-BIT

SUCCESSIVE

ADC

SCLK

DOUT

DIN

DRIVE

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The AD7908/AD7918/AD7928 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7908/AD7918/AD7928 dissipate just 6 mW of power maximum.

2. Eight Single-Ended Inputs with a Channel Sequencer. A sequence of channels can be selected, through which the ADC will cycle and convert on.

3. Single-Supply Operation with V

DRIVE

Function.

The AD7908/AD7918/AD7928 operate from a single 2.7 V to

5.25 V supply. The V

function allows the serial interface

DRIVE

to connect directly to either 3 V or 5 V processor systems independent of AV

4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 µA max when in full shutdown.

5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

AD7908/AD7918/AD7928

(AVDD = V

AD7908–SPECIFICATIONS

otherwise noted.)

Parameter B Version

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise

(SFDR)

Intermodulation Distortion (IMD)

49 dB min

–66 dB max

–64 dB max

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

Unit Test Conditions/Comments

fa = 40.1 kHz, fb = 41.5 kHz

= 20 MHz, TA = T

SCLK

= 50 kHz Sine Wave, f

SCLK

to T

MIN

= 20 MHz

Second Order Terms –90 dB typ

Third Order Terms –90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

–85 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed No Missed Codes to 8 Bits 0 V to REF

Input Range Straight Binary Output Coding

Offset Error ±0.5 LSB max

Offset Error Match ±0.05 LSB max

Gain Error ±0.2 LSB max

Gain Error Match ±0.05 LSB max 0 V to 2 ⫻ REF

Input Range –REFIN to +REFIN Biased about REFIN with

Positive Gain Error ±0.2 LSB max Twos Complement Output Coding

Positive Gain Error Match ±0.05 LSB max

Zero Code Error ±0.5 LSB max

Zero Code Error Match ±0.1 LSB max

Negative Gain Error ±0.2 LSB max

Negative Gain Error Match ±0.05 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF

0 to 2 ⫻ REF

V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V

= 4.75 V to 5.25 V

DRIVE

DC Leakage Current ±1 µA max Input Capacitance 20 pF typ

REFERENCE INPUT

REF

Input Voltage 2.5 V ±1% Specified Performance

DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f

SAMPLE

= 1 MSPS

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

0.7 ⫻ V

0.3 ⫻ V

DRIVE

V min

V max ±1 µA max Typically 10 nA, V 10 pF max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance

– 0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 µA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input

300 ns max Full-Scale Step Input

Throughput Rate 1 MSPS max See Serial Interface Section

, unless

MAX

–2–

REV. A

AD7908/AD7918/AD7928

Parameter B Version

Unit Test Conditions/Comments

POWER REQUIREMENTS

AV V

DRIVE

2.7/5.25 V min/max

2.7/5.25 V min/max Digital I/Ps = 0 V or V

DRIVE

Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV

2 mA max AVDD = 2.7 V to 3.6 V, f

Using Auto Shutdown Mode 960 µA typ f

SAMPLE

= 4.75 V to 5.25 V, f

= 250 kSPS

SCLK

= 20 MHz

SCLK

= 20 MHz

0.5 µA max (Static)

Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f

Auto Shutdown Mode (Static) 2.5 µW max AV

= 20 MHz

6 mW max AVDD = 3 V, f

= 5 V

1.5 µW max AV

= 3 V

SCLK

= 20 MHz

SCLK

Full Shutdown Mode 2.5 µW max AVDD = 5 V

1.5 µW max AVDD = 3 V

NOTES

Temperature ranges as follows: B Version: –40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REV. A

–3–

AD7908/AD7918/AD7928

(AVDD = V

AD7918–SPECIFICATIONS

otherwise noted.)

Parameter B Version

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise

(SFDR)

Intermodulation Distortion (IMD)

61 dB min 61 dB min

–72 dB max

–74 dB max

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

Unit Test Conditions/Comments

= 50 kHz Sine Wave, f

SCLK

fa = 40.1 kHz, fb = 41.5 kHz

= 20 MHz, TA = T

SCLK

to T

MIN

= 20 MHz

Second Order Terms –90 dB typ

Third Order Terms –90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

–85 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 10 Bits 0 V to REF

Input Range Straight Binary Output Coding

Offset Error ±2 LSB max

Offset Error Match ±0.2 LSB max

Gain Error ±0.5 LSB max

Gain Error Match ±0.2 LSB max 0 V to 2 ⫻ REF

Input Range –REFIN to +REFIN Biased about REFIN with

Positive Gain Error ±0.5 LSB max Twos Complement Output Coding

Positive Gain Error Match ±0.2 LSB max

Zero Code Error ±2 LSB max

Zero Code Error Match ±0.2 LSB max

Negative Gain Error ±0.5 LSB max

Negative Gain Error Match ±0.2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF

0 to 2 ⫻ REF

V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V

= 4.75 V to 5.25 V

DRIVE

DC Leakage Current ±1 µA max Input Capacitance 20 pF typ

REFERENCE INPUT

Input Voltage 2.5 V ±1% Specified Performance

REF

DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f

SAMPLE

= 1 MSPS

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

0.7 ⫻ V

0.3 ⫻ V

DRIVE

±1 µA max Typically 10 nA, V 10 pF max

V min V max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance

– 0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 µA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input

300 ns max Full-Scale Step Input

Throughput Rate 1 MSPS max See Serial Interface Section

–4–

, unless

MAX

REV. A

AD7908/AD7918/AD7928

Parameter B Version

Unit Test Conditions/Comments

POWER REQUIREMENTS

AV V

DRIVE

2.7/5.25 V min/max

2.7/5.25 V min/max Digital I/Ps = 0 V or V

DRIVE

Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV

2 mA max AVDD = 2.7 V to 3.6 V, f

Using Auto Shutdown Mode 960 µA typ f

SAMPLE

= 4.75 V to 5.25 V, f

= 250 kSPS

SCLK

= 20 MHz

SCLK

= 20 MHz

0.5 µA max (Static)

Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f

Auto Shutdown Mode (Static) 2.5 µW max AV

= 20 MHz

6 mW max AVDD = 3 V, f

= 5 V

1.5 µW max AV

= 3 V

SCLK

= 20 MHz

SCLK

Full Shutdown Mode 2.5 µW max AVDD = 5 V

1.5 µW max AVDD = 3 V

NOTES

Temperature ranges as follows: B Version: –40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REV. A

–5–

AD7908/AD7918/AD7928

(AVDD = V

AD7928–SPECIFICATIONS

otherwise noted.)

Parameter B Version

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) (SINAD)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

70 dB min @ 5 V 69 dB min @ 3 V Typically 70 dB

70 dB min –77 dB max @ 5 V Typically –84 dB

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

Unit Test Conditions/Comments

= 20 MHz, TA = T

SCLK

= 50 kHz Sine Wave, f

SCLK

to T

MIN

= 20 MHz

–73 dB max @ 3 V Typically –77 dB

Peak Harmonic or Spurious Noise –78 dB max @ 5 V Typically –86 dB

(SFDR)

Intermodulation Distortion (IMD)

–76 dB max @ 3 V Typically –80 dB

fa = 40.1 kHz, fb = 41.5 kHz Second Order Terms –90 dB typ Third Order Terms –90 dB typ

Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation

–85 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits 0 V to REF

Input Range Straight Binary Output Coding

Offset Error ±8 LSB max Typically ±0.5 LSB Offset Error Match ±0.5 LSB max Gain Error ±1.5 LSB max Gain Error Match ±0.5 LSB max

0 V to 2 ⫻ REF

Input Range –REFIN to +REFIN Biased about REFIN with

Positive Gain Error ±1.5 LSB max Twos Complement Output Coding Positive Gain Error Match ±0.5 LSB max Zero Code Error ±8 LSB max Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF

0 to 2 ⫻ REF

V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V

= 4.75 V to 5.25 V

DRIVE

DC Leakage Current ±1 µA max Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ±1% Specified Performance DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f

SAMPLE

= 1 MSPS

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

0.7 ⫻ V

0.3 ⫻ V

DRIVE

V min

V max ±1 µA max Typically 10 nA, V 10 pF max

= 0 V or V

DRIVE

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance

– 0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 µA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

MAX

, unless

–6–

REV. A

AD7908/AD7918/AD7928

Parameter B Version

Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input

300 ns max Full-Scale Step Input

Throughput Rate 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

AV V

DRIVE

2.7/5.25 V min/max

2.7/5.25 V min/max Digital I/Ps = 0 V or V

DRIVE

Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV

2 mA max AV

Using Auto Shutdown Mode 960 µA typ f

SAMPLE

= 4.75 V to 5.25 V, f

= 2.7 V to 3.6 V, f

= 250 kSPS

SCLK

= 20 MHz

SCLK

= 20 MHz

0.5 µA max (Static)

Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f

Auto Shutdown Mode (Static) 2.5 µW max AV

Full Shutdown Mode 2.5 µW max AV

= 20 MHz

6 mW max AV

1.5 µW max AV

= 3 V, f

= 5 V

= 3 V

= 5 V

SCLK

= 20 MHz

SCLK

1.5 µW max AVDD = 3 V

NOTES

Temperature ranges as follows: B Version: –40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REV. A

–7–

AD7908/AD7918/AD7928

TIMING SPECIFICATIONS

Limit at T

MIN

(AVDD = 2.7 V to 5.25 V, V

, T

AD7908/AD7918/AD7928

MAX

< AVDD, REFIN = 2.5 V, TA = T

DRIVE

MIN

to T

, unless otherwise noted.)

MAX

Parameter AVDD = 3 V AVDD = 5 V Unit Description

SCLK

10 10 kHz min 20 20 MHz max

CONVERT

QUIET

16 ⫻ t

SCLK

16 ⫻ t

SCLK

50 50 ns min Minimum Quiet Time Required between CS Rising Edge

and Start of Next Conversion

NOTES

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ⫻ V

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time time of the part and is independent of the bus loading.

Specifications subject to change without notice.

10 10 ns min CS to SCLK Setup Time 35 30 ns max Delay from CS until DOUT Three-State Disabled 40 40 ns max Data Access Time after SCLK Falling Edge

0.4 ⫻ t

SCLK

0.4 ⫻ t

SCLK

ns min SCLK Low Pulse Width

ns min SCLK High Pulse Width 10 10 ns min SCLK to DOUT Valid Hold Time 15/45 15/35 ns min/max SCLK Falling Edge to DOUT High Impedance 10 10 ns min DIN Setup Time Prior to SCLK Falling Edge 55 ns min DIN Hold Time after SCLK Falling Edge 20 20 ns min Sixteenth SCLK Falling Edge to CS High 11 µs max Power-Up Time from Full Power-Down/Auto Shutdown Mode

DRIVE

,t8, quoted in the timing characteristics is the true bus relinquish

1.6V

OUTPUT

200␮A

50pF

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

–8–

REV. A

+ 16 hidden pages