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ANALOG DEVICES
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AD7908
Service Manual
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ANALOG DEVICES AD7908, AD7918, AD7928 Service Manual

Download
with Sequencer in 20-Lead TSSOP
AD7908/AD7918/AD7928
FEATURES Fast Throughput Rate: 1 MSPS Specified for AV
of 2.7 V to 5.25 V
DD
Low Power:
6.0 mW Max at 1 MSPS with 3 V Supply
13.5 mW Max at 1 MSPS with 5 V Supply 8 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth:
AD7928, 70 dB Min SINAD at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI
®
/QSPI™/
MICROWIRE™/DSP Compatible Shutdown Mode: 0.5
␮A Max
20-Lead TSSOP Package

GENERAL DESCRIPTION

The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 8-channel, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1MSPS. The parts contain a low noise, wide bandwidth track­and-hold amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily inter­face with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part.
The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7908/AD7918/AD7928 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum.
Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REF 2 ⫻ REF
, with either straight binary or twos complement out-
IN
or 0 V to
IN
put coding. The AD7908/AD7918/AD7928 each feature eight single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially.
The conversion time for the AD7908/AD7918/AD7928 is deter­mined by the SCLK frequency, which is also used as the master clock to control the conversion.

FUNCTIONAL BLOCK DIAGRAM

AV
DD
REF
IN
VIN0
•
•
•
•
•
•
•
•
•
•
•
•
• 7
V
IN
I/P
MUX
AD7908/AD7918/AD7928
T/H
SEQUENCER
APPROXIMATION
CONTROL LOGIC
GND
8-/10-/12-BIT
SUCCESSIVE
ADC
SCLK
DOUT
DIN
CS
V
DRIVE

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The AD7908/AD7918/AD7928 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7908/AD7918/AD7928 dissipate just 6 mW of power maximum.
2. Eight Single-Ended Inputs with a Channel Sequencer. A sequence of channels can be selected, through which the ADC will cycle and convert on.
3. Single-Supply Operation with V
DRIVE
Function.
The AD7908/AD7918/AD7928 operate from a single 2.7 V to
5.25 V supply. The V
function allows the serial interface
DRIVE
to connect directly to either 3 V or 5 V processor systems independent of AV
DD
.
4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 µA max when in full shutdown.
5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7908/AD7918/AD7928
(AVDD = V

AD7908–SPECIFICATIONS

otherwise noted.)
Parameter B Version
DYNAMIC PERFORMANCE f
Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
49 dB min
2
2
49 dB min
–66 dB max
–64 dB max
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
1
Unit Test Conditions/Comments
IN
fa = 40.1 kHz, fb = 41.5 kHz
= 20 MHz, TA = T
SCLK
= 50 kHz Sine Wave, f
SCLK
to T
MIN
= 20 MHz
Second Order Terms –90 dB typ
Third Order Terms –90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation
2
–85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
2
Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed No Missed Codes to 8 Bits 0 V to REF
Input Range Straight Binary Output Coding
IN
Offset Error ±0.5 LSB max
Offset Error Match ±0.05 LSB max
Gain Error ±0.2 LSB max
Gain Error Match ±0.05 LSB max 0 V to 2 ⫻ REF
Input Range –REFIN to +REFIN Biased about REFIN with
IN
Positive Gain Error ±0.2 LSB max Twos Complement Output Coding
Positive Gain Error Match ±0.05 LSB max
Zero Code Error ±0.5 LSB max
Zero Code Error Match ±0.1 LSB max
Negative Gain Error ±0.2 LSB max
Negative Gain Error Match ±0.05 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to REF
0 to 2 ⫻ REF
IN
V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V
IN
= 4.75 V to 5.25 V
DRIVE
DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
REFERENCE INPUT
REF
Input Voltage 2.5 V ±1% Specified Performance
IN
DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f
SAMPLE
= 1 MSPS
LOGIC INPUTS
Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C
INL
IN
IN
INH
3
0.7 ⫻ V
0.3 ⫻ V
DRIVE
DRIVE
V min
V max ±1 µA max Typically 10 nA, V 10 pF max
= 0 V or V
IN
DRIVE
LOGIC OUTPUTS
Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance
OH
OL
3
V
– 0.2 V min I
DRIVE
0.4 V max I
10 pF max
= 200 µA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary Coding Bit Set to 1
Twos Complement Coding Bit Set to 0
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input
300 ns max Full-Scale Step Input
Throughput Rate 1 MSPS max See Serial Interface Section
, unless
MAX
–2–
REV. A
AD7908/AD7918/AD7928
Parameter B Version
1
Unit Test Conditions/Comments
POWER REQUIREMENTS
AV V
DRIVE
I
DD
DD
4
2.7/5.25 V min/max
2.7/5.25 V min/max Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV
2 mA max AVDD = 2.7 V to 3.6 V, f
Using Auto Shutdown Mode 960 µA typ f
SAMPLE
= 4.75 V to 5.25 V, f
DD
= 250 kSPS
SCLK
= 20 MHz
SCLK
= 20 MHz
0.5 µA max (Static)
Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)
Power Dissipation
Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f
Auto Shutdown Mode (Static) 2.5 µW max AV
4
= 20 MHz
6 mW max AVDD = 3 V, f
= 5 V
DD
1.5 µW max AV
DD
= 3 V
SCLK
= 20 MHz
SCLK
Full Shutdown Mode 2.5 µW max AVDD = 5 V
1.5 µW max AVDD = 3 V
NOTES
1
Temperature ranges as follows: B Version: –40°C to +85°C.
2
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–3–
AD7908/AD7918/AD7928
(AVDD = V

AD7918–SPECIFICATIONS

otherwise noted.)
Parameter B Version
DYNAMIC PERFORMANCE f
Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
2
2
61 dB min 61 dB min
–72 dB max
–74 dB max
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
1
Unit Test Conditions/Comments
= 50 kHz Sine Wave, f
IN
SCLK
fa = 40.1 kHz, fb = 41.5 kHz
= 20 MHz, TA = T
SCLK
to T
MIN
= 20 MHz
Second Order Terms –90 dB typ
Third Order Terms –90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation
2
–85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
2
Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 10 Bits 0 V to REF
Input Range Straight Binary Output Coding
IN
Offset Error ±2 LSB max
Offset Error Match ±0.2 LSB max
Gain Error ±0.5 LSB max
Gain Error Match ±0.2 LSB max 0 V to 2 ⫻ REF
Input Range –REFIN to +REFIN Biased about REFIN with
IN
Positive Gain Error ±0.5 LSB max Twos Complement Output Coding
Positive Gain Error Match ±0.2 LSB max
Zero Code Error ±2 LSB max
Zero Code Error Match ±0.2 LSB max
Negative Gain Error ±0.5 LSB max
Negative Gain Error Match ±0.2 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to REF
0 to 2 ⫻ REF
IN
V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V
IN
= 4.75 V to 5.25 V
DRIVE
DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
REFERENCE INPUT
Input Voltage 2.5 V ±1% Specified Performance
REF
IN
DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f
SAMPLE
= 1 MSPS
LOGIC INPUTS
Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C
INL
IN
IN
INH
3
0.7 ⫻ V
0.3 ⫻ V
DRIVE
DRIVE
±1 µA max Typically 10 nA, V 10 pF max
V min V max
= 0 V or V
IN
DRIVE
LOGIC OUTPUTS
V
Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance
OH
OL
3
– 0.2 V min I
DRIVE
0.4 V max I
10 pF max
= 200 µA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary Coding Bit Set to 1
Twos Complement Coding Bit Set to 0
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input
300 ns max Full-Scale Step Input
Throughput Rate 1 MSPS max See Serial Interface Section
–4–
, unless
MAX
REV. A
AD7908/AD7918/AD7928
Parameter B Version
1
Unit Test Conditions/Comments
POWER REQUIREMENTS
AV V
DRIVE
I
DD
DD
4
2.7/5.25 V min/max
2.7/5.25 V min/max Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV
2 mA max AVDD = 2.7 V to 3.6 V, f
Using Auto Shutdown Mode 960 µA typ f
SAMPLE
= 4.75 V to 5.25 V, f
DD
= 250 kSPS
SCLK
= 20 MHz
SCLK
= 20 MHz
0.5 µA max (Static)
Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)
Power Dissipation
Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f
Auto Shutdown Mode (Static) 2.5 µW max AV
4
= 20 MHz
6 mW max AVDD = 3 V, f
= 5 V
DD
1.5 µW max AV
DD
= 3 V
SCLK
= 20 MHz
SCLK
Full Shutdown Mode 2.5 µW max AVDD = 5 V
1.5 µW max AVDD = 3 V
NOTES
1
Temperature ranges as follows: B Version: –40°C to +85°C.
2
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–5–
AD7908/AD7918/AD7928
(AVDD = V

AD7928–SPECIFICATIONS

otherwise noted.)
Parameter B Version
DYNAMIC PERFORMANCE f
Signal-to-(Noise + Distortion) (SINAD)
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
70 dB min @ 5 V 69 dB min @ 3 V Typically 70 dB
2
70 dB min –77 dB max @ 5 V Typically –84 dB
= 2.7 V to 5.25 V, REFIN = 2.5 V, f
DRIVE
2
Unit Test Conditions/Comments
= 20 MHz, TA = T
SCLK
= 50 kHz Sine Wave, f
IN
SCLK
to T
MIN
= 20 MHz
–73 dB max @ 3 V Typically –77 dB
Peak Harmonic or Spurious Noise –78 dB max @ 5 V Typically –86 dB
(SFDR)
Intermodulation Distortion (IMD)
2
2
–76 dB max @ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz Second Order Terms –90 dB typ Third Order Terms –90 dB typ
Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation
2
–85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
2
Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits 0 V to REF
Input Range Straight Binary Output Coding
IN
Offset Error ±8 LSB max Typically ±0.5 LSB Offset Error Match ±0.5 LSB max Gain Error ±1.5 LSB max Gain Error Match ±0.5 LSB max
0 V to 2 ⫻ REF
Input Range –REFIN to +REFIN Biased about REFIN with
IN
Positive Gain Error ±1.5 LSB max Twos Complement Output Coding Positive Gain Error Match ±0.5 LSB max Zero Code Error ±8 LSB max Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to REF
0 to 2 ⫻ REF
IN
V RANGE Bit Set to 1 V RANGE Bit Set to 0, AVDD/V
IN
= 4.75 V to 5.25 V
DRIVE
DC Leakage Current ±1 µA max Input Capacitance 20 pF typ
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% Specified Performance DC Leakage Current ±1 µA max REFIN Input Impedance 36 k⍀ typ f
SAMPLE
= 1 MSPS
LOGIC INPUTS
Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C
INL
IN
IN
INH
3
0.7 ⫻ V
0.3 ⫻ V
DRIVE
DRIVE
V min
V max ±1 µA max Typically 10 nA, V 10 pF max
= 0 V or V
IN
DRIVE
LOGIC OUTPUTS
Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance
OH
OL
3
V
– 0.2 V min I
DRIVE
0.4 V max I
10 pF max
= 200 µA, AVDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary Coding Bit Set to 1
Twos Complement Coding Bit Set to 0
MAX
, unless
–6–
REV. A
AD7908/AD7918/AD7928
Parameter B Version
1
Unit Test Conditions/Comments
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine Wave Input
300 ns max Full-Scale Step Input
Throughput Rate 1 MSPS max See Serial Interface Section
POWER REQUIREMENTS
AV V
DRIVE
I
DD
DD
4
2.7/5.25 V min/max
2.7/5.25 V min/max Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static) 600 µA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV
2 mA max AV
Using Auto Shutdown Mode 960 µA typ f
SAMPLE
= 4.75 V to 5.25 V, f
DD
= 2.7 V to 3.6 V, f
DD
= 250 kSPS
SCLK
= 20 MHz
SCLK
= 20 MHz
0.5 µA max (Static)
Full Shutdown Mode 0.5 µA max SCLK On or Off (20 nA typ)
Power Dissipation
Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f
Auto Shutdown Mode (Static) 2.5 µW max AV
Full Shutdown Mode 2.5 µW max AV
4
= 20 MHz
6 mW max AV
1.5 µW max AV
= 3 V, f
DD
= 5 V
DD
= 3 V
DD
= 5 V
DD
SCLK
= 20 MHz
SCLK
1.5 µW max AVDD = 3 V
NOTES
1
Temperature ranges as follows: B Version: –40°C to +85°C.
2
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–7–
AD7908/AD7918/AD7928

TIMING SPECIFICATIONS

Limit at T
MIN
1
(AVDD = 2.7 V to 5.25 V, V
, T
AD7908/AD7918/AD7928
MAX
< AVDD, REFIN = 2.5 V, TA = T
DRIVE
MIN
to T
, unless otherwise noted.)
MAX
Parameter AVDD = 3 V AVDD = 5 V Unit Description
f
SCLK
2
10 10 kHz min 20 20 MHz max
t
CONVERT
t
QUIET
16 ⫻ t
SCLK
16 ⫻ t
SCLK
50 50 ns min Minimum Quiet Time Required between CS Rising Edge
and Start of Next Conversion
t
2
3
t
3
3
t
4
t
5
t
6
t
7
4
t
8
t
9
t
10
t
11
t
12
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ⫻ V
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time time of the part and is independent of the bus loading.
Specifications subject to change without notice.
10 10 ns min CS to SCLK Setup Time 35 30 ns max Delay from CS until DOUT Three-State Disabled 40 40 ns max Data Access Time after SCLK Falling Edge
0.4 ⫻ t
0.4 ⫻ t
SCLK
SCLK
0.4 ⫻ t
0.4 ⫻ t
SCLK
SCLK
ns min SCLK Low Pulse Width
ns min SCLK High Pulse Width 10 10 ns min SCLK to DOUT Valid Hold Time 15/45 15/35 ns min/max SCLK Falling Edge to DOUT High Impedance 10 10 ns min DIN Setup Time Prior to SCLK Falling Edge 55 ns min DIN Hold Time after SCLK Falling Edge 20 20 ns min Sixteenth SCLK Falling Edge to CS High 11 µs max Power-Up Time from Full Power-Down/Auto Shutdown Mode
.
DRIVE
,t8, quoted in the timing characteristics is the true bus relinquish
I
OL
1.6V
I
OH
OUTPUT
PIN
200␮A
TO
C
L
50pF
200␮A
Figure 1. Load Circuit for Digital Output Timing Specifications
–8–
REV. A
AD7908/AD7918/AD7928

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)
1
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
V
DRIVE
Analog Input Voltage to AGND . . . . –0.3 V to AV
+ 0.3 V
DD
Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to AGND . . . –0.3 V to AV
to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF
IN
+ 0.3 V
DD
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

ORDERING GUIDE

Temperature Linearity Package Package
Model Range Error (LSB)
AD7908BRU –40°C to +85°C ⫾0.2 RU-20 TSSOP AD7908BRU-REEL –40°C to +85°C ⫾0.2 RU-20 TSSOP AD7908BRU-REEL7 –40°C to +85°C ⫾0.2 RU-20 TSSOP AD7918BRU –40°C to +85°C ⫾0.5 RU-20 TSSOP AD7918BRU-REEL –40°C to +85°C ⫾0.5 RU-20 TSSOP AD7918BRU-REEL7 –40°C to +85°C ⫾0.5 RU-20 TSSOP AD7928BRU –40°C to +85°C ⫾1 RU-20 TSSOP AD7928BRU-REEL –40°C to +85°C ⫾1 RU-20 TSSOP AD7928BRU-REEL7 –40°C to +85°C ⫾1 RU-20 TSSOP EVAL-AD79x8CB EVAL-CONTROL BRD
NOTES
1
Linearity error here refers to integral linearity error.
2
This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. The board comes with one chip of each the AD7908, AD7918, and AD7928.
3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, order the particular ADC evaluation board, e.g., EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant Evaluation Board Technical Note for more information.
2
3
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . 143°C/W (TSSOP)
q
JA
Thermal Impedance . . . . . . . . . . . . . . 45°C/W (TSSOP)
q
JC
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
1
Option Description
Evaluation Board Controller Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7908/AD7918/AD7928 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–9–
AD7908/AD7918/AD7928

PIN CONFIGURATION

20-Lead TSSOP
1
SCLK AGND
2
DIN V
3
CS
AD7908/ AD7918/
4
AGND AGND
AV
AV
REF
AGND VIN3
AD7928
5
DD
TOP VIEW
6
DD
(Not to Scale)
7
IN
8
9
VIN7V
10
VIN6V
20
19
DRIVE
18
DOUT
17
16
VIN0
15
VIN1
14
VIN2
13
12
4
IN
11
5
IN

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function
1 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7908/AD7918/AD7928’s conversion process.
2DIN Data In. Logic input. Data to be written to the AD7908/AD7918/AD7928’s Control Register is provided on
this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).
3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7908/AD7918/AD7928, and also frames the serial data transfer.
4, 8, 17, 20 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7908/AD7918/AD7928.
All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6 AV
7 REF
DD
IN
Analog Power Supply Input. The AVDD range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V to 2 ⫻ REF
range, AVDD should be from 4.75 V to 5.25 V.
IN
Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance.
16–9V
0–VIN7Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed
IN
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD2 through ADD0 of the Control Register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the Sequencer to be programmed. The input range for all input channels can extend from 0 V to REF
or 0 V to 2 ⫻ REFIN as selected via the RANGE bit in the Control
IN
Register. Any unused input channels must be connected to AGND to avoid noise pickup.
18 DOUT Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding may be selected as straight binary or twos complement via the CODING bit in the Control Register.
19 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7908/AD7918/AD7928 will operate.
–10–
REV. A
AD7908/AD7918/AD7928
TERMINOLOGY Integral Nonlinearity
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the offset error has been adjusted out.

Gain Error Match

This is the difference in Gain Error between any two channels.

Zero Code Error

This applies when using the twos complement output coding option, in particular to the 2 ⫻ REF to +REFIN biased about the REF the midscale transition (all 0s to all 1s) from the ideal V i.e., REF

Zero Code Error Match

– 1 LSB.
IN
input range with –REF
IN
point. It is the deviation of
IN
voltage,
IN
IN
This is the difference in Zero Code Error between any two channels.

Positive Gain Error

This applies when using the twos complement output coding option, in particular to the 2 ⫻ REF to +REFIN biased about the REF
input range with –REF
IN
point. It is the deviation of
IN
IN
the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +REF
– 1 LSB) after the Zero Code Error has been
IN
adjusted out.

Positive Gain Error Match

This is the difference in Positive Gain Error between any two channels.

Negative Gain Error

This applies when using the twos complement output coding option, in particular to the 2 ⫻ REF to +REFIN biased about the REF
input range with –REF
IN
point. It is the deviation of
IN
IN
the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., –REF
+ 1 LSB) after the Zero Code Error has
IN
been adjusted out.

Negative Gain Error Match

This is the difference in Negative Gain Error between any two channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all seven nonselected input channels and deter­mining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/AD7928.

PSR (Power Supply Rejection)

Variations in power supply will affect the full scale transition, but not the converter’s linearity. Power supply rejection is the maxi­mum change in full-scale transition point due to a change in power-supply voltage from the nominal value. See Typical Performance Curves.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f
/2), excluding dc. The ratio
S
is dependent on the number of quantization levels in the digiti­zation process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:
Signal to Noise Distortion N dB--()(..)+=+602 176
Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter, this is 62 dB; and for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/ AD7928, it is defined as:
2
() log=
THD dB
20
++++
VVVVV
223242526
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
, V5, and V6 are the rms amplitudes of the second through the
V
4
sixth harmonics.
REV. A
–11–
AD7908/AD7918/AD7928–Typical Performance Characteristics

PERFORMANCE CURVES

TPC 1 shows a typical FFT plot for the AD7928 at 1 MSPS sample rate and 50 kHz input frequency. TPC 2 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz.
TPC 3 shows the power supply rejection ratio versus supply ripple frequency for the AD7928 when no decoupling is used. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AVDD supply of frequency fS:
PSRR dB Pf Pfs() log( / )= 10
Pf is equal to the power at frequency f in ADC output; PfS is
equal to the power at frequency f supply. Here a 200 mV p-p sine wave is coupled onto the AV
coupled onto the ADC AV
S
DD
DD
supply.
–10
–30
–50
SNR (dB)
–70
4096 POINT FFT AV
= 5V
DD
f
= 1MSPS
SAMPLE
f
= 50kHz
IN
SINAD = 71.147dB THD = –87.229dB SFDR = –90.744dB
TPC 4 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages, while TPC 5 shows a graph of total harmonic distortion versus analog input frequency for various source impedances. See the Analog Input section.
TPC 6 and TPC 7 show typical INL and DNL plots for the AD7928.
0
AVDD = 5V 200mV p-p SINE WAVE ON AV
–10
REFIN = 2.5V, 1␮F CAPACITOR T
= 25ⴗC
A
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
0 1000
SUPPLY RIPPLE FREQUENCY (kHz)
500
DD
900800700600400300200100
TPC 3. AD7928 PSRR vs. Supply Ripple Frequency
–50
f
= 1MSPS
SAMPLE
T
= 25ⴗC
A
–55
RANGE = 0 TO REF
–60
IN
= V
DRIVE
= 2.7V
AV
DD
–90
–110
50 150 250 350 450
0 100 200 300 400 500
FREQUENCY (kHz)
TPC 1. AD7928 Dynamic Performance at 1 MSPS
75
AV
= V
DD
AV
DD
70
AV
65
SINAD (dB)
60
f
= 1MSPS
SAMPLE
= 25ⴗC
T
A
RANGE = 0 TO REF
55
10 1000
IN
INPUT FREQUENCY (kHz)
AVDD = V
100
= 5.25V
DRIVE
= V
= 4.75V
DRIVE
= V
DRIVE
DRIVE
= 3.6V
= 2.7V
DD
TPC 2. AD7928 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS
–65
AV
DD
AVDD = V
AVDD = V
= V
DRIVE
–70
THD (dB)
–75
–80
–85
–90
10 1000
INPUT FREQUENCY (kHz)
100
DRIVE
DRIVE
= 4.75V
= 5.25V
= 3.6V
TPC 4. AD7928 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS
–50
f
= 1MSPS
SAMPLE
T
= 25ⴗC
A
–55
–60
–65
–70
THD (dB)
–75
–80
–85
RANGE = 0 TO REF AVDD = 5.25V
IN
RIN = 1000⍀
R
IN
= 100⍀
R
= 10⍀
IN
R
= 50⍀
IN
–90
10 1000
INPUT FREQUENCY (kHz)
100
TPC 5. AD7928 THD vs. Analog Input Frequency for Various Source Impedances
–12–
REV. A
AD7908/AD7918/AD7928
1.0 AV
= V
DRIVE
= 5V
2048 CODE
2560 3072 3584512 1024 1536
DD
0.8 TEMP = 25ⴗC
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 4096
TPC 6. AD7928 Typical INL
1.0 AVDD = V
0.8 TEMP = 25ⴗC
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 4096
DRIVE
= 5V
2048 CODE
2560 3072 3584512 1024 1536
TPC 7. AD7928 Typical DNL

CONTROL REGISTER

The Control Register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conver­sion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
Table I. Control Register Bit Functions
MSB LSB
WRITE SEQ DONTC ADD2 ADD1 ADD0 PM1 PM0 SHADOW DONTC RANGE CODING
Bit Mnemonic Comment
11 WRITE The value written to this bit of the Control Register determines whether or not the following 11 bits will be
loaded to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register; if it is a 0, the remaining 11 bits are not loaded to the Control Register, and it remains unchanged.
10 SEQ The SEQ bit in the Control Register is used in conjunction with the SHADOW bit to control the use of the
sequencer function and access the SHADOW Register. (See Table IV.)
9 DONTCARE
8–6ADD2–ADD0 These three address bits are loaded at the end of the present conversion sequence and select which analog
input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on will be selected by the mux on the 14th SCLK falling edge.
5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928
as shown in Table III.
3 SHADOW The SHADOW bit in the Control Register is used in conjunction with the SEQ bit to control the use of the
sequencer function and access the SHADOW Register. (See Table IV.)
2 DONTCARE
1 RANGE This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the
analog input range will extend from 0 V to 2 ⫻ REF 0 V to REF
(for the next conversion). For 0 V to 2 ⫻ REFIN, AVDD = 4.75 V to 5.25 V.
IN
. If it is set to 1, the analog input range will extend from
IN
0 CODING This bit selects the type of output coding the AD7908/AD7918/AD7928 will use for the conversion result.
If this bit is set to 0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the part will be straight binary (for the next conversion).
REV. A
–13–
AD7908/AD7918/AD7928
Table II. Channel Selection
ADD2 ADD1 ADD0 Analog Input Channel
00 0 V 00 1 V 01 0 V 01 1 V 10 0 V 10 1 V 11 0 V 11 1 V
Table III. Power Mode Selection
0
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
PM1 PM0 Mode
11Normal Operation. In this mode, the AD7908/
AD7918/AD7928 remain in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928.
10
Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The AD7908/AD7918/ AD7928 retains the information in the Control Register while in full shutdown. The part remains in full shutdown until these bits are changed.
01Auto Shutdown. In this mode, the AD7908/
AD7918/AD7928 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 µs and the user should ensure that 1 µs has elapsed before attempting to perform a valid conversion on the part in this mode.
00Invalid Selection. This configuration is not allowed.

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the Control Register allows the user to select a particular mode of operation of the sequencer function. Table IV outlines the four modes of operation of the Sequencer.
Table IV. Sequence Selection
SEQ SHADOW Sequence Type
00 This configuration means that the sequence
function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADD0 through ADD2 in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the Sequencer function being used, where each write to the AD7908/AD7918/ AD7928 selects the next channel for conversion. (See Figure 2.)
01 This configuration selects the SHADOW
Register for programming. The following write operation will load the contents of the SHADOW Register. This will program the sequence of channels to be converted on continuously with each successive valid CS falling edge. (See SHADOW Register section, Table V, and Figure 3.) The channels selected need not be consecutive.
10 If the SEQ and SHADOW bits are set in
this way, then the sequence function will not be interrupted upon completion of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a sequence, without terminating the cycle.
11 This configuration is used in conjunction
with the channel address bits ADD2 to ADD0 to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the Control Register. (See Figure 4.)
–14–
REV. A
AD7908/AD7918/AD7928
CS
POWER-ON
DUMMY CONVERSION DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A2–A0 FOR CONVERSION. SEQ = 0 SHADOW = 1
DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A2–A0. DIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECTED NEED NOT BE CONSECUTIVE CHANNELS
WRITE BIT = 1, SEQ = 1, SHADOW = 0
CS
CS
WRITE BIT = 0 WRITE BIT = 1
SEQ = 1 SHADOW = 0
CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS
WRITE BIT = 0
WRITE BIT = 0
CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0

SHADOW REGISTER

The SHADOW Register on the AD7908/AD7918/AD7928 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that a conversion result is read from the part. This requires 16 serial clock falling edges for the data transfer. The information is clocked into the SHADOW Register, provided that the SEQ and SHADOW bits were set to 0,1, respectively, in the previous write to the Control Register. MSB denotes the first bit in the data stream. Each bit represents an analog input from Channel 0 to Channel 7. Through programming the SHADOW Register, two sequences of channels may be selected, through which the AD7908/AD7918/AD7928 will cycle with each consecutive conversion after the write to the SHADOW Register. Sequence One will be performed first and then Sequence Two.
If the user does not wish to perform a second sequence option, then all 0s must be written to the last 8 LSBs of the SHADOW Register. To select a sequence of channels, the associated channel bit must be set for each analog input. The AD7908/AD7918/ AD7928 will continuously cycle through the selected channels
in ascending order beginning with the lowest channel, until a write operation occurs (i.e., the WRITE bit is set to 1) with the SEQ and SHADOW bits configured in any way except 1,0. (See Table IV.) The bit functions are outlined in Table V.
Figure 2 reflects the traditional operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation the Sequencer function is not used.
Figure 3 shows how to program the AD7908/AD7918/AD7928 to continuously convert on a particular sequence of channels. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 2), ensure that the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer. Figure 4 shows how a sequence of consecutive channels can be converted on without having to program the SHADOW Register or write to the part on each serial transfer. Again to exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 2), ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer.
Table V. SHADOW Register Bit Functions
MSB LSB
VIN0VIN1VIN2VIN3VIN4VIN5VIN6VIN7VIN0VIN1VIN2VIN3VIN4VIN5VIN6VIN7
------------------SEQUENCE ONE-------------------------------------------------------SEQUENCE TWO-----------------------
POWER-ON
DUMMY CONVERSION DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
CS
CS
WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A2–A0 FOR CONVERSION. SEQ = SHADOW = 0
DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A2–A0.
DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT A2–A0 FOR CONVERSION. SEQ = SHADOW = 0
WRITE BIT = 1, SEQ = SHADOW = 0
Figure 2. SEQ Bit = 0, SHADOW Bit = 0 Flowchart
REV. A
Figure 3. SEQ Bit = 0, SHADOW Bit = 1 Flowchart
–15–
AD7908/AD7918/AD7928
POWER-ON
DUMMY CONVERSION DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
CS
CS
CS
WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A2–A0 FOR CONVERSION. SEQ = 1 SHADOW = 1
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED A2–A0 IN THE CONTROL REGISTER
CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0
WRITE BIT = 0
WRITE BIT = 1, SEQ = 1, SHADOW = 0
Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart

CIRCUIT INFORMATION

The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit, 10-bit, and 12-bit, single supply, A/D converters, respectively. The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7908/AD7918/ AD7928 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock.
The AD7908/AD7918/AD7928 provide the user with an on-chip track-and-hold, A/D converter, and a serial interface housed in a 20-lead TSSOP package. The AD7908/AD7918/AD7928 each have eight single-ended input channels with a channel sequencer, allowing the user to select a channel sequence through which the ADC can cycle with each consecutive CS falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation A/D converter. The analog input range for the AD7908/AD7918/AD7928 is 0 V to REF to 2 ⫻ REF Register. For the 0 to 2 ⫻ REF
, depending on the status of Bit 1 in the Control
IN
range, the part must be oper-
IN
or 0 V
IN
ated from a 4.75 V to 5.25 V supply.
The AD7908/AD7918/AD7928 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by pro­gramming the power management bits, PM1 and PM0, in the Control Register.

CONVERTER OPERATION

The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit succes­sive approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7908/AD7918/AD7928 can convert analog input signals in the range 0 V to REF to 2 ⫻ REF
. Figures 5 and 6 show simplified schematics of
IN
or 0 V
IN
the ADC. The ADC is comprised of control logic, SAR, and
a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 5 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected V
IN
channel.
CAPACITIVE
DAC
VIN0
V
IN
7
AGND
A
SW1
B
4k⍀
SW2
COMPARATOR
CONTROL
LOGIC
Figure 5. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 6), SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The Control Logic and the Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figures 8 and 9 show the ADC transfer functions.
CAPACITIVE
DAC
VIN0
V
IN
. .
7
AGND
A
SW1
B
4k⍀
SW2
COMPARATOR
CONTROL
LOGIC
Figure 6. ADC Conversion Phase

Analog Input

Figure 7 shows an equivalent circuit of the analog input structure of the AD7908/AD7918/AD7928. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The capacitor C1 in Figure 7 is typically about 4 pF and can primarily be attrib­uted to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of the track-and-hold switch and also includes the on resistance of the input multiplexer. The total resistance is typically about 400 ⍀. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low­pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer ampli­fier. The choice of the op amp will be a function of the particular application.
–16–
REV. A
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases, and performance will degrade. (See TPC 5.)
AV
DD
D1
V
IN
4pF
C1
D2
CONVERSION PHASE: SWITCH OPEN TRACK PHASE: SWITCH CLOSED
C2
30pF
R1
Figure 7. Equivalent Analog Input Circuit

ADC TRANSFER FUNCTION

The output coding of the AD7908/AD7918/AD7928 is either straight binary or twos complement, depending on the status of the LSB in the Control Register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is REF AD7918, and REF
/256 for the AD7908, REFIN/1024 for the
IN
/4096 for the AD7928. The ideal transfer
IN
characteristic for the AD7908/AD7918/AD7928 when straight binary coding is selected is shown in Figure 8, and the ideal transfer characteristic for the AD7908/AD7918/AD7928 when twos complement coding is selected is shown in Figure 9.
111…111 111…110
•
•
111…000
•
011…111
•
• 000…010 000…001 000…000
NOTE: V
1 LSB
0V
REF
IS EITHER REF
1LSB ⴝ V 1LSB ⴝ V 1LSB ⴝ V
ANALOG INPUT
OR 2 ⴛ REF
IN
/256 AD7908
REF
/1024 AD7918
REF
/4096 AD7928
REF
+V
ⴚ 1 LSB
REF
IN
Figure 8. Straight Binary Transfer Characteristic
AD7908/AD7918/AD7928
011…111 011…110
•
• 000…001 000…000 111…111
•
ADC CODE
• 100…010 100…001 100…000
–V
ⴙ 1 LSB
REF
1LSB ⴝ 2 ⴛ V 1LSB ⴝ 2 ⴛ V 1LSB ⴝ 2 ⴛ V
ⴚ 1LSB
V
REF
ANALOG INPUT
+V
Figure 9. Twos Complement Transfer Characteristic with REFIN ± REFIN Input Range

Handling Bipolar Input Signals

Figure 10 shows how useful the combination of the 2 ⫻ REF input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REF selected, then REF negative full scale and +REF a dynamic range of 2 ⫻ REF
and twos complement output coding is
IN
becomes the zero code point, –REFIN is
IN
becomes positive full scale, with
IN
.
IN

TYPICAL CONNECTION DIAGRAM

Figure 11 shows a typical connection diagram for the AD7908/ AD7918/AD7928. In this setup, the AGND pin is connected to the analog ground plane of the system. In Figure 11, REF connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7908/AD7918/AD7928 is connected to a V serial interface is connected to a 3 V microprocessor. The V pin of the AD7908/AD7918/AD7928 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a 16-bit word. This 16-bit data stream consists of a leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the AD7928 (10 bits of data for the AD7918 and 8 bits of data for the AD7908, each followed by two and four trailing zeros, respec­tively). For applications where power consumption is of
REF
REF
REF
REF
ⴚ 1 LSB
Ⲑ256 AD7908 Ⲑ1024 AD7918 Ⲑ4096 AD7928
DD
IN
is
IN
of 5 V, the
DRIVE
REV. A
V
V
REF
0.1␮F
AV
DD
REF
IN
V
DRIVE
V
R3
R2
0V
V
R4
R1
R1 ⴝ R2 ⴝ R3 ⴝ R4
AD7908/ AD7918/ AD7928
V
0
IN
•
•
VIN7
DOUT
TWOS
COMPLEMENT
+REF
IN
REF
IN
–REF
IN
(= 2 ⴛ REF
(= 0V)
DD
V
DD
DSP/␮P
IN
011…111
)
000…000
100…000
Figure 10. Handling Bipolar Signals
–17–
AD7908/AD7918/AD7928
concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance. (See the Modes of Operation section.)
5V
SERIAL
INTERFACE
10␮F
␮C/␮P
3V
SUPPLY
V
DRIVE
SUPPLY
SCLK
DOUT
CS
DIN
0.1␮F
0.1␮F
AV
DD
0
V
IN
IN
0.1␮F
7
V
IN
AGND
•
•
0V TO REF
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND
AD7908/ AD7918/ AD7928
REF
IN
10␮F
2.5V
AD780
Figure 11. Typical Connection Diagram

Analog Input Selection

Any one of eight analog input channels may be selected for conversion by programming the multiplexer with the address bits ADD2–ADD0 in the Control Register. The channel configurations are shown in Table II. The AD7908/AD7918/AD7928 may also be configured to automatically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ and SHADOW bits in the Control Register. (See Table IV.)
The AD7908/AD7918/AD7928 can be programmed to continu­ously convert on a selection of channels in ascending order. The analog input channels to be converted on are selected through programming the relevant bits in the SHADOW Register (see Table V). The next serial transfer will then act on the sequence programmed by executing a conversion on the lowest channel in the selection. The next serial transfer will result in a conversion on the next highest channel in the sequence, and so on.
It is not necessary to write to the Control Register once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the Control Register is not accidently overwritten, or the sequence operation inter­rupted. If the Control Register is written to at any time during the sequence, then it must be ensured that the SEQ and SHADOW bits are set to 1,0 to avoid interrupting the automatic conversion sequence. This pattern will continue until such time as the AD7908/AD7918/AD7928 is written to and the SEQ and SHADOW bits are configured with any bit combination except 1,0. On completion of the sequence, the AD7908/AD7918/ AD7928 sequencer will return to the first selected channel in the SHADOW Register and commence the sequence again.
Rather than selecting a particular sequence of channels, a num­ber of consecutive channels beginning with Channel 0 may also be programmed via the Control Register alone, without needing to write to the SHADOW Register. This is possible if the SEQ and SHADOW bits are set to 1,1. The channel address bits ADD2 through ADD0 will then determine the final channel in the consecutive sequence. The next conversion will be on Chan­nel 0, then Channel 1, and so on until the channel selected via the address bits ADD2 through ADD0 is reached. The cycle will begin again on the next serial transfer, provided the WRITE bit is set to low, or if high, that the SEQ and SHADOW bits are set to 1,0; then the ADC will continue its preprogrammed auto­matic sequence uninterrupted.
Regardless of which channel selection method is used, the 16-bit word output from the AD7928 during each conversion will always contain a leading zero, three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result; the AD7918 will output a leading zero, three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7908 will output a leading zero, three channel address bits that the conversion result corresponds to, followed by the 8-bit conver­sion result and four trailing zeros. (See the Serial Interface section.)

Digital Inputs

The digital inputs applied to the AD7908/AD7918/AD7928 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AV
+ 0.3 V limit as on the analog inputs.
DD
Another advantage of SCLK, DIN, and CS not being restricted by the AV
+ 0.3 V limit is the fact that power supply sequenc-
DD
ing issues are avoided. If CS, DIN, or SCLK are applied before
, there is no risk of latch-up as there would be on the analog
AV
DD
inputs if a signal greater than 0.3 V was applied prior to AV
V
DRIVE
The AD7908/AD7918/AD7928 also have the V V
controls the voltage at which the serial interface operates.
DRIVE
allows the ADC to easily interface to both 3 V and 5 V
V
DRIVE
DRIVE
feature.
DD
.
processors. For example, if the AD7908/AD7918/AD7928 were operated with an AV
of 5 V, the V
DD
pin could be powered
DRIVE
from a 3 V supply. The AD7908/AD7918/AD7928 have better dynamic performance with an AV
of 5 V while still being able
DD
to interface to 3 V processors. Care should be taken to ensure
does not exceed AVDD by more than 0.3 V. (See the
V
DRIVE
Absolute Maximum Ratings.)

Reference

An external reference source should be used to supply the 2.5 V reference to the AD7908/AD7918/AD7928. Errors in the refer­ence source will result in gain errors in the AD7908/AD7918/ AD7928 transfer function and will add to the specified full-scale errors of the part. A capacitor of at least 0.1 µF should be placed on the REF
pin. Suitable reference sources for the AD7908/
IN
AD7918/AD7928 include the AD780, REF193, AD1582, ADR03, ADR381, ADR391, and ADR421.
If 2.5 V is applied to the REF
pin, the analog input range can
IN
either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the Control Register.

MODES OF OPERATION

The AD7908/AD7918/AD7928 have a number of different modes of operation. These modes are designed to provide flex­ible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for dif­fering application requirements. The mode of operation of the AD7908/AD7918/AD7928 is controlled by the power manage­ment bits, PM1 and PM0, in the Control Register, as detailed in Table III. When power supplies are first applied to the AD7908/ AD7918/AD7928, care should be taken to ensure that the part is placed in the required mode of operation. (See the Powering Up the AD7908/AD7918/AD7928 section.)
–18–
REV. A
AD7908/AD7918/AD7928

Normal Mode (PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7908/AD7918/AD7928 remaining fully powered at all times. Figure 12 shows the general diagram of the operation of the AD7908/AD7918/AD7928 in this mode.
The conversion is initiated on the falling edge of CS and the track-and-hold will enter hold mode as described in the Serial Interface section. The data presented to the AD7908/AD7918/ AD7928 on the DIN line during the first 12 clock cycles of the data transfer are loaded into the Control Register (provided WRITE bit is set to 1). If data is to be written to the SHADOW Register (SEQ = 0, SHADOW = 1 on previous write), data pre­sented on the DIN line during the first 16 SCLK cycles is loaded into the SHADOW Register. The part will remain fully powered up in Normal mode at the end of the conversion as long as PM1 and PM0 are both loaded with 1 on every data transfer.
Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track-and-hold will go back into track on the 14th SCLK falling edge. CS may then idle high until the next conversion or may idle low until sometime prior to the next conversion, (effectively idling CS low).
Once a data transfer is complete (DOUT has returned to three­state), another conversion can be initiated after the quiet time, t
has elapsed by bringing CS low again.
QUIET,
CS
SCLK
DOUT
DIN
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES
1
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
12
16
Figure 12. Normal Mode Operation

Full Shutdown (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the Control Register during full shutdown. The AD7908/AD7918/ AD7928 remains in full shutdown until the power management bits in the Control Register, PM1 and PM0, are changed.
If a write to the Control Register occurs while the part is in Full Shutdown, with the power management bits changed to PM0 = PM1 = 1, Normal mode, the part will begin to power up on the CS rising edge. The track-and-hold that was in hold while the part was in Full Shutdown will return to track on the 14th SCLK falling edge.
To ensure that the part is fully powered up, t
POWER UP
, should have
elapsed before the next CS falling edge. Figure 13 shows the general diagram for this sequence.

Auto Shutdown (PM1 = 0, PM0 = 1)

In this mode, the AD7908/AD7918/AD7928 automatically enters shutdown at the end of each conversion when the control register is updated. When the part is in shutdown, the track and hold is in hold mode. Figure 14 shows the general diagram of the operation of the AD7908/AD7918/AD7928 in this mode. In shutdown mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the Control Register during shutdown. The AD7908/AD7918/ AD7928 remains in shutdown until the next CS falling edge it receives. On this CS falling edge, the track-and-hold that was in hold while the part was in shutdown will return to track. Wake­up time from auto shutdown is 1 µs, and the user should ensure that 1 µs has elapsed before attempting a valid conversion. When running the AD7908/AD7918/AD7928 with a 20 MHz clock, one dummy cycle should be sufficient to ensure the part is fully powered up. During this dummy cycle the contents of the Control Register should remain unchanged; therefore the WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. In this mode, the power consumption of the part is greatly reduced with the part enter­ing shutdown at the end of each conversion. When the Control Register is programmed to move into Auto Shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS signal.

Powering Up the AD7908/AD7918/AD7928

When supplies are first applied to the AD7908/AD7918/AD7928, the ADC may power up in any of the operating modes of the part. To ensure the part is placed into the required operating mode, the user should perform a dummy cycle operation as out­lined in Figure 15.
The three dummy conversion operation outlined in Figure 15 must be performed to place the part into the Auto Shutdown mode. The first two conversions of this dummy cycle operation are performed with the DIN line tied high; for the third conver­sion of the dummy cycle operation, the user should write the desired Control Register configuration to the AD7908/AD7918/ AD7928 in order to place the part into the Auto Shutdown mode. On the third CS rising edge after the supplies are applied, the Control Register will contain the correct information and valid data will result from the next conversion.
Therefore, to ensure the part is placed into the correct operating mode, when supplies are first applied to the AD7908/AD7918/ AD7928, the user must first issue two serial write operations with the DIN line tied high, and on the third conversion cycle the user can then write to the Control Register to place the part into any of the operating modes. The user should not write to the SHADOW Register until the fourth conversion cycle after the supplies are applied to the ADC, in order to guarantee the Control Register contains the correct data.
If the user wants to place the part into either the Normal mode or Full Shutdown mode, the second dummy cycle with DIN tied high can be omitted from the three dummy conversion operation outlined in Figure 15.
REV. A
–19–
AD7908/AD7918/AD7928
PA R T IS IN FULL SHUTDOWN
CS
SCLK
DOUT
DIN
CS
SCLK
DOUT
PA RT BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1
t
11416114 16
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
THE PART IS FULLY POWERED UP
t
ONCE
POWER UP
12
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER
HAS ELAPSED
DATA IN TO CONTROL/SHADOW REGISTER
Figure 13. Full Shutdown Mode Operation
PA R T ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 ⴝ 0, PM0 ⴝ 1
1
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
12
16
PA RT BEGINS TO POWER UP ON CS FA LLING EDGE
DUMMY CONVERSION
1161
INVALID DATA
PA R T IS FULLY POWERED UP
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
PA R T ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 ⴝ 0, PM0 ⴝ 1
16
1212
DIN
DATA IN TO CONTROL/SHADOW REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 ⴝ 0, PM0 ⴝ 1
CONTROL REGISTER CONTENTS SHOULD NOT CHANGE, WRITE BIT ⴝ 0
Figure 14. Auto Shutdown Mode Operation
CS
SCLK
DOUT
DIN
DUMMY CONVERSION
1
INVALID DATA INVALID DATA
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
12
16
DUMMY CONVERSION
1161
INVALID DATA
Figure 15. Placing AD7928 into the Required Operating Mode after Supplies are Applied

POWER VS. THROUGHPUT RATE

By operating in Auto Shutdown mode on the AD7908/AD7918/ AD7928, the average power consumption of the ADC decreases at lower throughput rates. Figure 16 shows how as the through­put rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly.
For example if the AD7928 is operated in a continuous sam­pling mode, with a throughput rate of 100 kSPS and an SCLK of 20 MHz (AV
= 5 V), and the device is placed in Auto
DD
Shutdown mode, i.e., if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows:
The maximum power dissipation during normal operation is
13.5 mW (AV
= 5 V). If the power-up time from Auto Shutdown
DD
–20–
DATA IN TO CONTROL/SHADOW REGISTER
TO KEEP PART IN THIS MODE, LOAD PM1 ⴝ 0, PM0 ⴝ 1 IN CONTROL REGISTER OR SET WRITE BIT = 0
CORRECT VALUE IN CONTROL REGISTER, VALID DATA FROM NEXT CONVERSION, USER CAN WRITE TO SHADOW REGISTER IN NEXT CONVERSION
16
1212
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCK EDGES
is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7928 can be said to dissipate 13.5 mW for 2 µs during each conversion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in Auto Shutdown mode. The AD7928 can be said to dissipate 2.5 µW for the remaining 8 µs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (2/10) ⫻ (13.5 mW) + (8/10) ⫻ (2.5 µW) = 2.702 mW.
Figure 16 shows the maximum power versus throughput rate when using the Auto Shutdown mode with 3 V and 5 V supplies.
REV. A
AD7908/AD7918/AD7928
10
Writing of information to the Control Register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, i.e., the WRITE bit, has been set to 1. If the Control
AVDD = 5V
1
AVDD = 3V
Register is programmed to use the SHADOW Register, then writing of information to the SHADOW Register will take place on all 16 SCLK falling edges in the next serial transfer as shown for example on the AD7928 in Figure 20. Two sequence options can be programmed in the SHADOW Register. If the user does
POWER (mW)
0.1
not want to program a second sequence, then the eight LSBs should be filled with zeros. The SHADOW Register will be updated upon the rising edge of CS and the track-and-hold will begin to track the first channel selected in the sequence.
0.01
Figure 16. AD7928 Power vs. Throughput Rate

SERIAL INTERFACE

50 150 250 350
0 100 200 300
THROUGHPUT (kSPS)
Figures 17, 18, and 19 show the detailed timing diagrams for serial interfacing to the AD7908, AD7918, and AD7928, respectively. The serial clock provides the conversion clock and
The AD7908 will output a leading zero, three channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result, and four trailing zeros. The AD7918 will output a leading zero, three channel address bits that the con­version result corresponds to, followed by the 10-bit conversion result, and two trailing zeros. The 16-bit word read from the AD7928 will always contain a leading zero, three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result.
also controls the transfer of information to and from the AD7908/AD7918/AD7928 during each conversion.
The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state; the analog input is sampled at this point. The conversion is also initiated at this point and will require 16 SCLK cycles to complete. The track-and-hold will go back into track on the 14th SCLK falling edge as shown in Figures 17,
18, and 19 at point B, except when the write is to the SHADOW Register, in which case the track-and-hold will not return to track until the rising edge of CS, i.e., point C in Figure 20. SCLK falling edge, the DOUT line will go back into
On the 16th
three-
state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated, the DOUT line will go back into three-state, and the Control Register will not be updated; otherwise DOUT returns to three-state on the SCLK falling edge as shown in Figures serial clock cycles are required to perform
17, 18, and 19. Sixteen
the conversion process
and to access data from the AD7908/AD7918/AD7928.
16th
For the AD7908/AD7918/AD7928 the 8/10/12 bits of data are preceded by a leading zero and the three channel address bits, ADD2 to ADD0, identify which channel the result corre­sponds to. CS going low provides the leading zero to be read in by the
microcontroller or DSP. The three remaining address bits and data bits are then clocked out by subsequent SCLK falling edges the first falling clock provided and also clocks the data transfer is valid on the
beginning with the first address bit ADD2, thus
edge on the serial clock has a leading zero
out address bit ADD2. The final bit in
16th
falling edge, having been

MICROPROCESSOR INTERFACING

The serial interface on the AD7908/AD7918/AD7928 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7908/AD7918/AD7928 with some of the more common microcontroller and DSP serial interface protocols.

AD7908/AD7918/AD7928 to TMS320C541

The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7908/AD7918/AD7928. The CS input allows easy interfacing between the TMS320C541 and the AD7908/AD7918/AD7928 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (Tx serial clock on serial port 0) and FSX0 (Tx frame sync from serial port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 21. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provides equidistant sampling. The V AD7928 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, i.e., TMS320C541, if necessary.
clocked out on the previous (15th) falling edge.
pin of the AD7908/AD7918/
DRIVE
REV. A
–21–
AD7908/AD7918/AD7928
CS
SCLK
DOUT
DIN
CS
SCLK
DOUT
DIN
t
t
2
t
3
THREE­STATE
123456111213141516
t
4
ADD2 ADD1 ADD0 DB7 DB6 DB0 ZERO ZERO ZERO ZERO
ZERO
t
WRITE SEQ1 DONTC ADD2 ADD1 ADD0 CODING DONTC DONTC DONTC DONTC
BITS
9
CONVERT
t
6
t
7
t
10
B
t
5
4 TRAILING ZEROS3 IDENTIFICATION
Figure 17. AD7908 Serial Interface Timing Diagram
t
t
2
t
3
THREE­STATE
123456111213141516
t
4
ADD2 ADD1 ADD0 DB9 DB8 DB2 DB1 DB0 ZERO ZERO
ZERO
t
WRITE SEQ DONTC ADD2 ADD1 ADD0 CODING DONTC DONTC DONTC DONTC
BITS
9
CONVERT
t
6
t
7
t
10
B
t
5
2 TRAILING ZEROS3 IDENTIFICATION
Figure 18. AD7918 Serial Interface Timing Diagram
CS
SCLK
DOUT
DIN
THREE­STATE
t
2
12345 13141516
t
3
ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
3 IDENTIFICATION BITS
ZERO
WRITE
t
9
SEQ DONTC
t
CONVERT
t
6
t
t
4
t
10
ADD2
ADD1 ADD0 DONTC DONTC
7
B
t
5
t
8
DONTC
t
t
t
11
THREE­STATE
t
11
THREE­STATE
t
11
THREE­STATE
t
QUIET
t
QUIET
8
8
t
QUIET
SCLK
DOUT
DIN
CS
Figure 19. AD7928 Serial Interface Timing Diagram
t
CONVERT
t
6
t
4
t
t
7
t
10
5
5VIN6VIN7
IN
THREE­STATE
t
2
12345 13141516
t
3
ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
ADD2
3 IDENTIFICATION BITS
ZERO
t
9
0VIN1VIN2VIN3VIN4VIN5V
V
IN
SEQUENCE 1 SEQUENCE 2
Figure 20. AD7928 Writing to SHADOW Register Timing Diagram
–22–
C
t
11
t
8
THREE­STATE
REV. A
AD7908/AD7918/AD7928
AD7908/ AD7918/ AD7928
*
DSP563xx*
SCK
SRD
STD
SC2
V
DD
SCLK
DOUT
CS
DIN
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7908/ AD7918/
*
AD7928
SCLK
DOUT
DIN
CS
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
TMS320C541*
CLKX
CLKR
DR
DT
FSX
FSR
V
DD
Figure 21. Interfacing to the TMS320C541

AD7908/AD7918/AD7928 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the AD7908/AD7918/AD7928 without any glue logic required. The
pin of the AD7908/AD7918/AD7928 takes the same supply
V
DRIVE
voltage as that of the ADSP-218x. This allows the ADC to operate at a higher voltage than the serial interface, i.e., ADSP-218x, if necessary.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1
The connection diagram is shown in Figure 22. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and as with all signal processing applications equi­distant sampling is necessary. However, in this example the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling may not be achieved.
AD7908/ AD7918/ AD7928
V
DRIVE
*
SCLK
DOUT
CS
DIN
ADSP-218x*
SCLK
DR
RFS
TFS
DT
The Timer Register, for example, is loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone High, Low, and High before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge.
For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV register was loaded with the value 3, then an SCLK of 5 MHz is obtained, and eight master clock periods will elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs will occur between interrupts and subsequently between transmit instruc­tions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling will be implemented by the DSP.

AD7908/AD7918/AD7928 to DSP563xx

The connection diagram in Figure 23 shows how the AD7908/ AD7918/AD7928 can be connected to the ESSI (Synchronous Serial Interface) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in Synchronous mode (SYN bit in CRB = 1) with internally generated word length frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidis­tant sampling.
In the example shown in Figure 23, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. The V
pin of the AD7908/AD7918/AD7928 takes the same
DRIVE
supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than the serial interface, i.e., DSP563xx, if necessary.
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 22. Interfacing to the ADSP-218x
REV. A
V
DD
Figure 23. Interfacing to the DSP563xx
–23–
AD7908/AD7918/AD7928
APPLICATION HINTS Grounding and Layout
The AD7908/AD7918/AD7928 have very good immunity to noise on the power supplies as can be seen by the PSRR versus Supply Ripple Frequency plot, TPC 3. However, care should still be taken with regard to grounding and layout.
The printed circuit board that houses the AD7908/AD7918/AD7928 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facili­tates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. All three AGND pins of the AD7908/ AD7918/AD7928 should be sunk in the AGND plane. Digital and analog ground planes should be joined at only one place. If the AD7908/AD7918/AD7928 is in a system where multiple devices require an AGND to DGND connection, the connec­tion should still be made at one point only, a star ground point that should be established as close as possible to the AD7908/ AD7918/AD7928.
Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7908/AD7918/AD7928 to avoid noise coupling. The power supply lines to the AD7908/AD7918/AD7928 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid cross­over of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double­sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 µF capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Evaluating the AD7908/AD7918/AD7928 Performance

The recommended layout for the AD7908/AD7918/AD7928 is outlined in the AD7908/AD7918/AD7928 evaluation board. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the Eval-Board Controller.
The Eval-Board Controller can be used in conjunction with the AD7908/AD7918/AD7928 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7908/AD7918/AD7928.
The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7908/AD7918/ AD7928. The software and documentation are on a CD shipped with the evaluation board.
C03089–0–9/03(A)

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
PIN 1
0.15
0.05
COPLANARITY
0.10
20
1
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AC
0.65
BSC
11
10
1.20
MAX
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09 8ⴗ
0ⴗ
0.75
0.60
0.45

Revision History

Location Page
9/03—Data Sheet changed from REV. 0 to REV. A.
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
–24–
REV. A
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