ANALOG DEVICES AD7890 Service Manual
LC2MOS 8-Channel, 12-Bit
A
V
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FEATURES
Fast 12-bit ADC with 5.9 μs conversion time
Eight single-ended analog input channels
Selection of input ranges:
±10 V for AD7890-10
0 V to 4.096 V for AD7890-4
0 V to 2.5 V for AD7890-2
Allows separate access to multiplexer and ADC
On-chip track/hold amplifier
On-chip reference
High-speed, flexible, serial interface
Single supply, low-power operation (50 mW maximum)
Power-down mode (75 μW typ)
GENERAL DESCRIPTION
The AD7890 is an 8-channel 12-bit data acquisition system. The
part contains an input multiplexer, an on-chip track/hold
amplifier, a high speed 12-bit ADC, a 2.5 V reference, and a
high speed, serial interface. The part operates from a single 5 V
supply and accepts an analog input range of ±10 V (AD7890-10),
0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2).
Serial Data Acquisition System
AD7890
FUNCTIONAL BLOCK DIAGRAM
MUX
SH
DD
V
V
V
V
V
V
V
V
SIGNAL
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
AGND AGND DGND SCLK TFS RFS DATA
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
SIGNAL
SCALING
AD7890
1
1
1
1
1
1
1
1
MUX
CLOCK
OUT
TRACK/HOL D
CLK
IN
REF OUT/
IN
REF IN
2kΩ
OUTPUT/CONTROL REGISTER
1
NO SCALING ON AD7890-2
Figure 1.
REFERENCE
12-BIT
ADC
OUT
2.5V
DATAINSMODE
C
EXT
CONVST
01357-001
The multiplexer on the part is independently accessible. This
al
lows the user to insert an antialiasing filter or signal
conditioning, if required, between the multiplexer and the
ADC. This means that one antialiasing filter can be used for all
eight channels. Connection of an external capacitor allows the
user to adjust the time given to the multiplexer settling to
include any external delays in the filter or signal conditioning
circuitry.
Output data from the AD7890 is provided via a high speed
b
idirectional serial interface port. The part contains an on-chip
control register, allowing control of channel selection,
conversion start, and power-down via the serial port. Versatile,
high speed logic ensures easy interfacing to serial ports on
microcontrollers and digital signal processors.
In addition to the traditional dc accuracy specifications such as
linea
rity, full-scale, and offset errors, the AD7890 is also
specified for dynamic performance parameters including
harmonic distortion and signal-to-noise ratio.
Power dissipation in normal mode is low at 30 mW typical and the
part can be placed in a standby (power-down) mode if it is not
required to perform conversions. The AD7890 is fabricated in
Analog Devices, Inc.’s Linear Compatible CMOS (LC
2
MOS)
process, a mixed technology process that combines precision
bipolar circuits with low power CMOS logic. The part is available
in a 24-lead, 0.3" wide, plastic or ceramic dual-in-line package or in
a 24-lead small outline package (SOIC_W).
PRODUCT HIGHLIGHTS
1. Complete 12-Bit Data Acquisition System-on-a-Chip.
The AD7890 is a complete monolithic ADC combining an
8-channel multiplexer, 12-bit ADC, 2.5 V reference, and a
track/hold amplifier on a single chip.
eparate Access to Multiplexer and ADC.
2. S
The AD7890 provides access to the output of the
multiplexer allowing one antialiasing filter for 8 channels—
a considerable savings over the 8 antialiasing filters required if
the multiplexer is internally connected to the ADC.
gh Speed Serial Interface.
3. Hi
The part provides a high speed serial interface for easy
connection to serial ports of microcontrollers and DSP
processors.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD7890
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TABLE OF CONTENTS
Features.............................................................................................. 1
Serial Interface ................................................................................ 17
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Control Register.............................................................................. 10
Theory of Operation ...................................................................... 11
Converter Details........................................................................ 11
Circuit Description..................................................................... 11
Track/Hold Amplifier ................................................................ 12
Self-Clocking Mode ................................................................... 17
External Clocking Mode ........................................................... 18
Simplifying the Interface........................................................... 19
Microprocessor/Microcontroller Interface................................. 20
AD7890 to 8051 Interface ......................................................... 20
AD7890 to 68HC11 Interface................................................... 20
AD7890 to ADSP-2101 Interface ............................................. 21
AD7890 to DSP56000 Interface ............................................... 21
AD7890 to TMS320C25/30 Interface...................................... 21
Antialiasing Filter....................................................................... 22
Performance.................................................................................... 23
Linearity....................................................................................... 23
Noise ............................................................................................ 23
Dynamic Performance............................................................... 24
Effective Number of Bits ........................................................... 24
Reference ..................................................................................... 13
Timing and Control ................................................................... 13
C
Functioning......................................................................... 16
EXT
REVISION HISTORY
9/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide.......................................................... 27
2/01—Rev. A to Rev. B
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 27
Rev. C | Page 2 of 28
AD7890
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SPECIFICATIONS
VDD = 5 V, AGND = DGND = 0 V, REF IN = 2.5 V, f
T
, unless otherwise noted.
MAX
Table 1.
Parameter A Versions1B Versions S Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio270 70 70 dB min fIN = 10 kHz sine wave, f
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise2
Intermodulation Distortion
2nd Order Terms −80 −80 −80 dB typ
3rd Order Terms −80 −80 −80 dB typ
Channel-to-Channel Isolation2
DC ACCURACY
Resolution 12 12 12 Bits
Min. Resolution for Which No
Missing Codes Are Guaranteed
Relative Accuracy2
Differential Nonlinearity2
Positive Full-Scale Error2
Full-Scale Error Match
AD7890-2, AD7890-4
Unipolar Offset Error2
Unipolar Offset Error Match 2 2 2 LSB max
AD7890-10 Only
Negative Full-Scale Error2
Bipolar Zero Error2
Bipolar Zero Error Match 2 2 2 LSB max
ANALOG INPUTS
AD7890-10
Input Voltage Range ±10 ±10 ±10 Volts
Input Resistance 20 20 20 kΩ min
AD7890-4
Input Voltage Range 0 to 4.096 0 to 4.096 0 to 4.096 Volts
Input Resistance 11 11 11 kΩ min
AD7890-2
Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts
Input Current 50 50 200 nA max
MUX OUT OUTPUT
Output Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts
Output Resistance
AD7890-10, AD7890-4 3/5 3/5 3/5 kΩ min/kΩ max
AD7890-2 2 2 2 kΩ max Assuming VIN is driven from low impedance
SHA IN INPUT
Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts
Input Current ±50 ±50 ±50 nA max
REFERENCE OUTPUT/INPUT
REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5%
Input Impedance 1.6 1.6 1.6 kΩ min Resistor connected to internal reference node
Input Capacitance
REF OUT Output Voltage 2.5 2.5 2.5 V nom
REF OUT Error @ 25°C ±10 ±10 ±10 mV max
T
to T
MIN
MAX
REF OUT Temperature Coefficient 25 25 25 ppm/°C typ
REF OUT Output Impedance 2 2 2 kΩ nom
4
5
±20 ±20 ±25 mV max
−77 −77 −77 dB max
−78 −78 −78 dB max
−80 −80 −80 dB max f
12 12 12 Bits
±1 ±0.5 ±1 LSB max
±1 ±1 ±1 LSB max
±2.5 ±2.5 ±2.5 LSB max
2 2 2 LSB max
±2 ±2 ±2 LSB max
±2 ±2 ±2 LSB max
±5 ±5 ±5 LSB max
10 10 10 pF max
= 2.5 MHz external, MUX OUT connect to SHA IN. All specifications T
CLK IN
CONVST
Rev. C | Page 3 of 28
Using external
fIN = 10 kHz sine wave, f
fIN = 10 kHz sine wave, f
fa = 9 kHz, fb = 9.5 kHz, f
= 1 kHz sine wave
IN
, any channel
= 100 kHz
SAMPLE
= 100 kHz3
SAMPLE
= 100 kHz3
SAMPLE
= 100 kHz3
SAMPLE
MIN
to
3
AD7890
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Parameter A Versions1B Versions S Version Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±10 ±10 ±10 μA max VIN = 0 V to VDD
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, VOH 4.0 4.0 4.0 V min I
Output Low Voltage, VOL 0.4 0.4 0.4 V max I
Serial Data Output Coding
AD7890-10 Twos Complement
AD7890-4 Straight (Natural) Binary
AD7890-2 Straight (Natural) Binary
CONVERSION RATE
Conversion Time 5.9 5.9 5.9 μs max f
Track/Hold Acquisition Time2, 5
POWER REQUIREMENTS
VDD 5 5 5 V nom ± 5% for specified performance
IDD (Normal Mode) 10 10 10 mA max Logic inputs = 0 V or VDD
IDD (Standby Mode)6 @ 25°C 15 15 15 μA typ Logic inputs = 0 V or VDD
Power Dissipation
Normal Mode 50 50 50 mW max Typically 30 mW
Standby Mode @ 25°C 75 75 75 μW typ
1
Temperature ranges are as follows: A, B Versions: −40°C to +85°C; S Version: −55°C to +125°C.
2
See the Terminology section.
3
This sample rate is only achievable when using the part in external clocking mode.
4
Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.
5
Sample tested @ 25°C to ensure compliance.
6
Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.
2.4 2.4 2.4 V min VDD = 5 V ± 5%
INH
0.8 0.8 0.8 V max VDD = 5 V ± 5%
INL
5
IN
10 10 10 pF max
= 200 μA
SOURCE
= 1.6 mA
SINK
= 2.5 MHz, MUX OUT, connected to
CLK IN
SHA IN
2 2 2 μs max
Rev. C | Page 4 of 28
AD7890
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TIMING SPECIFICATIONS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
Parameter1,
3
f
CLKIN
2.5 MHz max
t
CLKIN IN LO
t
CLK IN HI
4
tr
tf4
t
CONVERT
t
100 ns min
CST
Self-Clocking Mode
t1 t
5
t
25 ns max
2
t3 t
t4 t
5
t
5
t6 40 ns max
6
t
7
t8 0 ns min
t
t9 0 ns min
t10 20 ns min Data Valid to SCLK Falling Edge Setup Time.
t11 10 ns min Data Valid to SCLK Falling Edge Hold Time.
t12 20 ns min
External Clocking Mode
t13 20 ns min
5
t
14
t15 50 ns min SCLK High Pulse Width.
t16 50 ns min SCLK Low Pulse Width.
5
t
17
t18 20 ns min
6
t
19
6
t
19A
t20 20 ns min
t21 10 ns min Data Valid to SCLK Falling Edge Setup Time.
t22 15 ns min Data Valid to SCLK Falling Edge Hold Time.
t23 40 ns min
1
Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 10 to Figure 13.
3
The AD7890 is production tested with f
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
2
Limit at T
, T
(A, B, S Versions) Unit Conditions/Comments
MIN
MAX
100 kHz min Master Clock Frequency. For specified performance.
0.3 × t
0 3 × t
ns min Master Clock Input Low Time.
CLK IN
ns min Master Clock Input High Time.
CLK IN
25 ns max Digital Output Rise Time. Typically 10 ns.
25 ns max Digital Output Fa
5.9 μs max Conversion Time.
+ 50 ns max
CLK IN HI
ns nom SCLK High Pulse Width.
CLK IN HI
ns nom SCLK Low Pulse Width.
CLK IN LO
20 ns max SCLK Rising Edge to Data Valid De
50 ns max Bus Relinquish Time after Rising Edge of SCLK.
+ 50 ns max
CLK IN
40 ns max
35 ns max SCLK Rising Edge to Data Valid De
50 ns max
90 ns max Bus Relinquish Time after Rising Edge of SCLK.
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
CLK IN
= 2.5 MHz external, MUX OUT connected to SHA IN.
CLK IN
ll Time. Typically 10 ns.
CONVST
Pulse Width.
RFS
Low to SCLK Falling Edge.
RFS
Low to Data Valid Delay.
SCLK Rising Edge to
TFS
Low to SCLK Falling Edge.
Data Valid to
TFS
to SCLK Falling Edge Hold Time.
RFS
Low to SCLK Falling Edge Setup Time.
RFS
Low to Data Valid Delay.
RFS
to SCLK Falling Edge Hold Time.
RFS
Delay.
TFS
Falling Edge Setup Time (A2 Address Bit).
Bus Relinquish Time after Rising Edge of
TFS
Low to SCLK Falling Edge Setup Time.
TFS
to SCLK Falling Edge Hold Time.
lay.
lay.
RFS
.
1.6mA
TO OUTPUT
PIN
50pF
200µA
2.1V
01357-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. C | Page 5 of 28
AD7890
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ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Parameter Rating
VDD to AGND −0.3 V to +7 V
VDD to DGND −0.3 V to +7 V
Analog Input Voltage to AGND
AD7890-10, AD7890-4 ±17 V
AD7890-2 −5 V, +10 V
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) −40°C to +85°C
Extended (S Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature
PDIP Package, Power Dissipation 450 mW
θJA Thermal Impedance
Lead Temperature (Soldering, 10 sec)
CERDIP Package, Power Dissipation 450 mW
θJA Thermal Impedance 70°C/W
Lead Temperature (Soldering, 10 sec)
SOIC_W Package, Power Dissipation 450 mW
θJA Thermal Impedance 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
150°C
105°C/W
260°C
300°C
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings
ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
y cause permanent damage to the device. This is a stress
Rev. C | Page 6 of 28
AD7890
N
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
SMODE
DGND
C
EXT
CONVST
CLK IN
SCLK
TFS
RFS
DATA OUT
DATA IN
V
DD
1
2
3
4
AD7890
5
TOP VIEW
(Not to Scale)
6
7
8
9
10
11
12
24
REF OUT/RE F I
V
23
IN8
V
22
IN7
V
21
IN6
V
20
IN5
V
19
IN4
V
18
IN3
V
17
IN2
V
16
IN1
AGND
15
SHA IN
14
MUX OUT
13
01357-003
Figure 3. Pin Configuration
Table 2. Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC.
2 SMODE
Control Input. Determines whether the part operates in its external clocking (slave) or self-clocking (master)
serial mode. With SMODE at a logic low, the part is in its self-clocking serial mode with RFS
outputs. This self-clocking mode is useful for connection to shift registers or to serial ports of DSP processors.
With SMODE at a logic high, the part is in its external clocking serial mode with SCLK and RFS
external clocking mode is useful for connection to the serial port of microcontrollers, such as the 8xC51 and
the 68HCxx, and for connection to the serial ports of DSP processors.
3 DGND
4 C
EXT
Digital Ground. Ground reference for digital circuitry.
External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse
(see the Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time
delays through an external antialiasing filter or signal conditioning circuitry.
5
CONVST
Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts the track/hold into hold
and initiates conversion if the internal pulse has timed out (see the Control Register section). If the internal
pulse is active when the CONVST
goes high, the track/hold does not proceed to hold until the pulse times out.
If the internal pulse times out when CONVST goes high, the rising edge of CONVST drives the track/hold into
hold and initiates conversion.
6 CLK IN
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source for the
conversion sequence. In the self-clocking serial mode, the SCLK output is derived from this CLK IN pin.
7 SCLK
Serial Clock Input. In the external clocking (slave) mode (see the Serial Interface section), this is an externally
applied serial clock used to load serial data to the control register and to access data from the output register.
In the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN),
appears on this pin. Once again, it is used to load serial data to the control register and to access data from the
output register.
8
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of
TFS
this signal.
9
Receive Frame Synchronization Pulse. In the external clocking mode, this pin is an active low logic input with
RFS
RFS
provided externally as a strobe or framing pulse to access serial data from the output register. In the selfclocking mode, it is an active low output, which is internally generated and provides a strobe or framing pulse
for serial data from the output register. For applications which require that data be transmitted and received at
10 DATA OUT
the same time,
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three address
RFS and TFS should be connected together.
bits of the control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for
sixteen edges after RFS
goes low. Output coding from the ADC is twos complement for the AD7890-10 and
straight binary for the AD7890-4 and AD7890-2.
11 DATA IN
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first five bits of
serial data are loaded to the control register on the first five falling edges of SCLK after TFS
12 V
Positive Supply Voltage, 5 V ± 5%.
DD
13 MUX OUT
on subsequent SCLK edges is ignored while TFS
Multiplexer Output. The output of the multiplexer appears a
remains low.
t this pin. The output voltage range from this
output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this
output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN.
and SCLK as
as inputs. This
goes low. Serial data
Rev. C | Page 7 of 28
AD7890
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Pin No. Mnemonic Description
14 SHA IN
15 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC.
16 V
17 V
18 V
19 V
20 V
21 V
22 V
23 V
24 REF OUT/REF IN
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
Track/Hold Input. The input to the on-chip track/hold is applied t
input voltage range is 0 V to 2.5 V.
Analog Input Channel 1. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 2. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 3. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 4. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 5. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 6. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 7. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Analog Input Channel 8. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to
V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and
4.096
A2 bits in the control register. The multiplexer has guaranteed break-before-make operation.
Voltage Reference Output/Input. The part can be used with either its own internal reference or with an external
ference source. The on-chip 2.5 V reference voltage is provided at this pin. When using this internal reference
re
as the reference source for the part, REF OUT should decoupled to AGND with a 0.1 μF disc ceramic capacitor.
The output impedance of this reference source is typically 2 kΩ. When using an external reference source as
the reference voltage for the part, the reference source should be connected to this pin. This overdrives the
internal reference and provides the reference source for the part. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7890 is 2.5 V.
o this pin. It is a high impedance input and the
Rev. C | Page 8 of 28
AD7890
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TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
utput of the A/D converter. The signal is the rms amplitude of
o
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
/2), excluding dc.
S
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02
N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
rmonics to the fundamental. For the AD7890, it is defined as
ha
2
2
2
2
THD
2
2
log20)dB(
=
4
3
V
1
VVVVV
++++
5
6
where:
is the rms amplitude of the fundamental and
V
1
V
, V3, V4, V5, and V6 are the rms amplitudes of the second
2
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
ms value of the next largest component in the ADC output
r
spectrum (up to f
/2 and excluding dc) to the rms value of the
S
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it is
determined by a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb
, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7890 is tested using the CCIF standard where two input
f
requencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the fundamental expressed in dBs.
Rev. C | Page 9 of 28
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
etween channels. It is measured by applying a full-scale 1 kHz
b
signal to any one of the other seven inputs and determining how
much that signal is attenuated in the channel of interest. The figure
given is the worst case across all eight channels.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
de
viation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
ch
ange between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7890-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) f
rom the ideal (4 × REF IN − 1 LSB) after the
bipolar zero error has been adjusted out.
Positive Full-Scale Error (AD7890-4)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) f
rom the ideal (1.638 × REF IN − 1 LSB) after the
unipolar offset error has been adjusted out.
Positive Full-Scale Error (AD7890-2)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) f
rom the ideal (REF IN − 1 LSB) after the unipolar
offset error has been adjusted out.
Bipolar Zero Error (AD7890-10)
This is the deviation of the midscale transition (all 0s to all 1s)
f
rom the ideal 0 V (AGND).
Unipolar Offset Error (AD7890-2, AD7890-4)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) f
rom the ideal 0 V (AGND).
Negative Full-Scale Error (AD7890-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) f
rom the ideal (−4 × REF IN + 1 LSB) after bipolar
zero error has been adjusted out.
Trac k / Hold Ac q u isiti o n Ti me
Track/hold acquisition time is the time required for the output
o
f the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected V
input of the AD7890. It means that the user
IN
must wait for the duration of the track/hold acquisition time
after the end of conversion or after a channel change/step input
change to V
before starting another conversion, to ensure that
IN
the part operates to specification.
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