Analog Devices AD7888 Datasheet

+2.7 V to +5.25 V, Micropower, 8-Channel,

SAR + ADC

CONTROL LOGIC

AGND

REF IN/REF OUT

AIN8

AIN1

SCLKDOUTDIN

AGND

AD7888

V

DD

CS

T/H

I/P

MUX

BUF

2.5V
REF

CHARGE

REDISTRIBUTION

DAC

SPORT

COMP

a

FEATURES
Specified for V
Flexible Power/Throughput Rate Management
Shutdown Mode: 1 ␮A Max
Eight Single-Ended Inputs
Serial Interface: SPI™/QSPI™/MICROWIRE™/DSP

Compatible

16-Lead Narrow SOIC and TSSOP Packages

APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)
Instrumentation and Control Systems
High Speed Modems

GENERAL DESCRIPTION

of +2.7 V to +5.25 V

DD

125 kSPS, 12-Bit ADC in 16-Lead TSSOP

The AD7888 is a high speed, low power, 12-bit ADC that oper­ates from a single +2.7 V to +5.25 V power supply. The AD7888
is capable of a 125 kSPS throughput rate. The input track-and­hold acquires a signal in 500 ns and features a single-ended
sampling scheme. The AD7888 contains eight single-ended
analog inputs, AIN1 through AIN8. The analog input on each
of these channels is from 0 to V

. The part is capable of con-

REF

verting full power signals up to 2.5 MHz.

The AD7888 features an on-chip 2.5 V reference that can be
used as the reference source for the A/D converter. The REF
IN/REF OUT pin allows the user access to this reference. Alter­natively, this pin can be overdriven to provide an external refer­ence voltage for the AD7888. The voltage range for this external
reference is from 1.2 V to V

DD

.

CMOS construction ensures low power dissipation of typically

2 mW for normal operation and 3 µW in power-down mode.

The part is available in a 16-lead narrow body small outline
(SOIC) and a 16-lead thin shrink small outline (TSSOP) package.

AD7888

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Smallest 12-bit 8-channel ADC; 16-lead TSSOP is the same
area as an 8-lead SOIC and less than half the height.

2. Lowest Power 12-bit 8-channel ADC.

3. Flexible power management options including automatic
power-down after conversion.

4. Analog input range from 0 V to V

REF (VDD

5. Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP
Compatible).

).

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD7888–SPECIFICATIONS

otherwise noted; f

Parameter A Version1B Version

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio
Total Harmonic Distortion2 (THD) –80 –80 dB typ f
Peak Harmonic or Spurious Noise

= 2 MHz (VDD = +2.7 V to +5.25 V); TA = T

SCLK

2, 3

(SNR) 71 71 dB typ fIN = 10 kHz Sine Wave, f

2

–80 –80 dB typ fIN = 10 kHz Sine Wave, f

(VDD = +2.7 V to +5.25 V, REFIN/REFOUT = +2.5 V External/Internal Reference unless

to T

MIN

, unless otherwise noted)

MAX

1

Units Test Conditions/Comments

= 10 kHz Sine Wave, f

IN

SAMPLE

SAMPLE

SAMPLE

= 125 kSPS

= 125 kSPS

= 125 kSPS

Intermodulation Distortion2 (IMD)

Second Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
Third Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
Channel-to-Channel Isolation

2

–80 –80 dB typ fIN = 25 kHz

SAMPLE

SAMPLE

= 125 kSPS
= 125 kSPS

Full Power Bandwidth 2.5 2.5 MHz typ @ 3 dB

DC ACCURACY Any Channel

Resolution 12 12 Bits
Integral Nonlinearity
Differential Nonlinearity

2

2

±2 ±1 LSB max
±2 ±1 LSB max Guaranteed No Missed Codes to 11 Bits (A Grade)

Guaranteed No Missed Codes to 12 Bits (B Grade)

Offset Error ±6 ±6 LSB max VDD = 4.75 V to 5.25 V (Typically ±3 LSB)

±4.5 ±4.5 LSB max VDD = 2.7 V to 3.6 V (Typically ±2 LSB)

2 2 LSB typ

±2 ±2 LSB max Typically 30 LSB with Internal Reference

2 2 LSB max

Offset Error Match
Gain Error
Gain Error Match

2

2

2

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts

Leakage Current ±1 ±1 µA max

Input Capacitance 38 38 pF typ When in Track

4 4 pF typ When in Hold

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 2.5/V

DD

2.5/V

DD

V min/max Functional from 1.2 V

Input Impedance 5 5 kΩ typ Very High Impedance If Internal Reference Disabled

REFOUT Output Voltage 2.45/2.55 2.45/2.55 V min/max

REFOUT Tempco ±50 ±50 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 V min VDD = +4.75 V to +5.25 V

2.1 2.1 V min VDD = +2.7 V to +3.6 V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

IN

INL

4

0.8 0.8 V max VDD = +2.7 V to +5.25 V

±10 ±10 µA max Typically 10 nA, V

= 0 V or V

IN

10 10 pF max

DD

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V

Floating-State Leakage Current ±10 ±10 µA max

Floating-State Output Capacitance

OL

OH

V

DD –

0.5 V

0.5 V min VDD = +2.7 V to +5.25 V

DD –

0.4 0.4 V max I

5

10 10 pF max

I

SOURCE

SINK

= 200 µA

= 200 µA

Output Coding Straight (Natural) Binary

CONVERSION RATE

Throughput Time 16 16 SCLK Cycles Conversion Time + Acquisition Time. 125 kSPS with

2 MHz Clock

Track/Hold Acquisition Time

2

1.5 1.5 SCLK Cycles

Conversion Time 14.5 14.5 SCLK Cycles 7.25 µs (2 MHz Clock)

–2–

REV. 0

Parameter A Version1B Version

WARNING!

ESD SENSITIVE DEVICE

1

Units Test Conditions/Comments

POWER REQUIREMENTS

V

DD

I

DD

Normal Mode
Normal Mode

5

(Static) 700 700 µA max

(Operational) 700 700 µA typ f
Using Standby Mode 450 450 µA typ f
Using Shutdown Mode 80 80 µA typ f

Standby Mode
Shutdown Mode

6

6

+2.7/+5.25 +2.7/+5.25 V min/max

12 12 µA typ f
200 200 µA max V
22 µA max V
11 µA max V

= 125 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 1 kSPS

SAMPLE

= +2.7 V to +5.25 V

DD

= +4.75 V to +5.25 V (0.5 µA typ)

DD

= +2.7 V to +3.6 V

DD

Normal-Mode Power Dissipation 3.5 3.5 mW max VDD = +5 V

2.1 2.1 mW max VDD = +3 V

Shutdown Power Dissipation 10 10 µW max V

33 µW max V

= +5 V

DD

= +3 V

DD

Standby Power Dissipation 1 1 mW max VDD = +5 V

600 600 µW max V

NOTES

1

Temperature ranges as follows: A Version: –40°C to +105°C; B Version: 0°C to +105°C.

2

See Terminology.

3

SNR calculation includes distortion and noise components.

4

Sample tested @ +25°C to ensure compliance.

5

All digital inputs @ GND except CS @ VDD. No load on the digital outputs. Analog inputs @ GND.

6

SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ VDD. No load on the digital outputs. Analog inputs @ GND.

Specifications subject to change without notice.

= +3 V

DD

AD7888

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND . . . . . –0.3 V to V

Digital Input Voltage to AGND . . . . . . –0.3 V to V

Digital Output Voltage to AGND . . . . –0.3 V to V

REFIN/REFOUT to AGND . . . . . . . . –0.3 V to V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial

(A Version) . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C

(B Version) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +105°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC, TSSOP Package, Power Dissipation . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . 124.9°C/W (SOIC)

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP)

Thermal Impedance . . . . . . . . . . . . . 42.9°C/W (SOIC)

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Linearity
Error Package Package

Model (LSB)1Descriptions Options

AD7888AR ±2 SOIC R-16A

AD7888BR

AD7888ARU ±2 TSSOP RU-16

AD7888BRU
EVAL-AD7888CB
EVAL-CONTROL BOARD

NOTES

1

Linearity error here refers to integral linearity error.

2

Contact factory for availability.

3

This can be used as a stand-alone evaluation board or in conjunction with the

EVAL-CONTROL BOARD for evaluation/demonstration purposes.

4

This board is a complete unit allowing a PC to control and communicate with all

Analog Devices evaluation boards ending in the CB designators.

2

2

3

±1 SOIC R-16A
±1 TSSOP RU-16

4

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7888 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 –3–

AD7888

TIMING SPECIFICATIONS

1

(TA = T

MIN

to T

, unless otherwise noted)

MAX

Limit at T

MIN

, T

MAX

(A, B Versions)

Parameter +4.75 V to +5.25 V +2.7 V to +3.6 V Units Description

2

f

SCLK

t

CONVERT

t

ACQ

t

1

3

t

2

3

t

3

t

4

t

5

t

6

t

7

4

t

8

t

9

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
cross 0.4 V or 2.0 V with V

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

Specifications subject to change without notice.

2 2 MHz max

14.5 t

1.5 t

SCLK

SCLK

14.5 t

1.5 t

SCLK

SCLK

Throughput Time = t

CONVERT

+ t

ACQ

= 16 t

SCLK

10 10 ns min CS to SCLK Setup Time
30 60 ns max Delay from CS until DOUT 3-State Disabled
75 100 ns max Data Access Time after SCLK Falling Edge
20 20 ns min Data Setup Time Prior to SCLK Rising Edge
20 20 ns min Data Valid to SCLK Hold Time

0.4 t

0.4 t

SCLK

SCLK

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth

80 80 ns max CS Rising Edge to DOUT High Impedance
55µs typ Power-Up Time from Shutdown

) and timed from a voltage level of 1.6 V.

DD

= 5 V ± 10% and time for an output to

= 3 V ± 10%.

DD

, quoted in the timing characteristics is the true bus relinquish

8

DD

I

OL

+1.6V

I

OH

TO

OUTPUT

PIN

50pF

200mA

C

L

200mA

Figure 1. Load Circuit for Digital Output Timing Specifications

–4–

REV. 0

PIN CONFIGURATIONS

SOIC AND TSSOP

AD7888

CS

REF IN/REF OUT

V

AGND

AIN1
AIN2
AIN3
AIN4

DD

1

2

3

AD7888

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

SCLK

15

DOUT

14

DIN

13

AGND

12

AIN8

11

AIN7

10

AIN6

9

AIN5

PIN FUNCTION DESCRIPTIONS

Pin Pin
No. Mnemonic Function

1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7888 and also frames the serial data transfer.

2 REF IN/REF OUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888.

Alternatively, the internal reference can be disabled and an external reference applied to this input.

3V

DD

The voltage range for the external reference is from +1.2 V to V
Power Supply Input. The VDD range for the AD7888 is from +2.7 V to +5.25 V.

DD

.

4, 13 AGND Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and

any external reference signals should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system.

5–12 AIN1–AIN8 Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed

into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0
through ADD2 bits of the Control Register. The input range for all input channels is 0 to V

REF

. Any

unused input channels should be connected to AGND to avoid noise pickup.

14 DIN Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input

and is clocked into the register on the rising edge of SCLK (see Control Register section).

15 DOUT Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first.

16 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing

serial data to the Control Register. This clock input is also used as the clock source for the AD7888’s
conversion process.

REV. 0

–5–