Analog Devices AD7864BS-1, AD7864AS-3, AD7864AS-2, AD7864AS-1 Datasheet

4-Channel, Simultaneous

STBY

FRSTDATA

INT/EXT CLOCK

SELECT

OUTPUT

DATA

REGISTERS

12.5V

REFERENCE

SIGNAL

SCALING

V

IN1A

V

IN1B

V

IN2A

V

IN2B

V

IN3A

V

IN3B

V

IN4A

V

IN4B

BUSY

SIGNAL

SCALING

SIGNAL

SCALING

SIGNAL

SCALING

TRACK/HOLD

3 4

EOC

WR

CS

DB0

DB11

RD

AGND

DGND

V

DRIVE

DV

DD

V

REF GND

V

REF

AV

DD

6kV

AD7864

12-BIT

ADC

SOFTWARE

LATCH

CONVERSION

CONTROL LOGIC

MUX

CONVST

SL1 SL2 SL3 SL4

H/S

SEL

CLKIN

INT/EXT

CLK

AGND AGND

INT

CLOCK

DB0–DB3

a

FEATURES
High Speed (1.65␣ ␮s) 12-Bit ADC
Four Simultaneously Sampled Inputs
Four Track/Hold Amplifiers

0.35␣ ␮s Track/Hold Acquisition Time

1.65 ␮s Conversion Time per Channel
HW/SW Select of Channel Sequence for Conversion
Single Supply Operation
Selection of Input Ranges:

ⴞ10 V, ⴞ5 V for AD7864-1
ⴞ2.5 V for AD7864-3

0 V to 2.5 V, 0 V to 5 V for AD7864-2

High Speed Parallel Interface Which Also Allows

Interfacing to 3 V Processors
Low Power, 90 mW Typ
Power Saving Mode, 20␣ ␮W Typ
Overvoltage Protection on Analog Inputs

APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications

GENERAL DESCRIPTION

The AD7864 is a high speed, low power, 4-channel simulta­neous sampling 12-bit A/D converter that operates from a single

+5␣ V supply. The part contains a 1.65 µs successive approxima-

tion ADC, four track/hold amplifiers, 2.5 V reference, on-chip
clock oscillator, signal conditioning circuitry and a high speed
parallel interface. The input signals on four channels are
sampled simultaneously, thus preserving the relative phase infor­mation of the signals on the four analog inputs. The part accepts

analog input ranges of ±10␣ V, ±5 V (AD7864-1), 0 V to 2.5 V,
0 V to 5 V for AD7864-2 and ±2.5␣ V (AD7864-3).

The part allows any subset of the four channels to be converted
in order to maximize the throughput rate on the selected se­quence. The channels to be converted can be selected via either
hardware (channel select input pins) or software (programming
the channel select register).

A single conversion start signal (CONVST) simultaneously
places all the track/holds into hold and initiates conversion se­quence for the selected channels. The EOC signal indicates the end
of each individual conversion in the selected conversion sequence.
The BUSY signal indicates the end of the conversion sequence.

Data is read from the part by means of a 12-bit parallel data
bus using the standard CS and RD signals. Maximum through­put for a single channel is 500 kSPS. For all four channels the

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Sampling, High Speed, 12-Bit ADC

AD7864

FUNCTIONAL BLOCK DIAGRAM

maximum throughput is 130 kSPS for the read during conver­sion sequence operation. The throughput rate for the read after
conversion sequence operation will depend on the read cycle
time of the processor. See Timing and Control section.

The AD7864 is available in a small (0.3 sq. inch area) 44-lead
MQFP.

PRODUCT HIGHLIGHTS

1. The AD7864 features four Track/Hold amplifiers and a fast

(1.65 µs) ADC allowing simultaneous sampling and then

conversion of any subset of the four channels.

2. The AD7864 operates from a single +5␣ V supply and consumes
only 90 mW typ making it ideal for low power and portable
applications. Also see Standby Mode Operation.

3. The part offers a high speed parallel interface for easy con­nection to microprocessors, microcontrollers and digital
signal processors.

4. The part is offered in three versions with different analog
input ranges. The AD7864-1 offers the standard industrial

input ranges of ±10 V and ±5 V; the AD7864-3 offers the
common signal processing input range of ±2.5 V; the

AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V
applications.

5. The part features very tight aperture delay matching between
the four input sample-and-hold amplifiers.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(VDD = +5 V ⴞ 5%, AGND = DGND = 0 V, V

AD7864–SPECIFICATIONS

cations T

Parameter A Version

to T

MIN

1

unless otherwise noted.)

MAX

B Version Units Test Conditions/Comments

= Internal. Clock = Internal; all specifi-

REF

SAMPLE AND HOLD

–3 dB Full Power Bandwidth 3 3 MHz typ
Aperture Delay 20 20 ns max
Aperture Jitter 50 50 ps typ
Aperture Delay Matching 4 4 ns max

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio

2

3

fIN = 100.0 kHz, fS = 500 kSPS

@ +25°C 70 72 dB min

to T

T

MIN

Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion

MAX

3

3

3

70 70 dB min
–80 –80 dB max
–80 –80 dB max

fa = 49 kHz, fb = 50 kHz
2nd Order Terms –80 –80 dB typ
3rd Order Terms –80 –80 dB typ

Channel-to-Channel Isolation

3

–80 –80 dB max fIN = 50 kHz Sine Wave

DC ACCURACY Any Channel

Resolution 12 12 Bits
Relative Accuracy
Differential Nonlinearity
AD7864-1

Positive Gain Error
Positive Gain Error Match
Negative Gain Error
Negative Gain Error Match

3

3

3

3

3

3

±1 ±1/2 LSB max
±0.9 ±0.9 LSB max No Missing Codes

±3 ±3LSB max
3 ±3LSB max
±3 ±3LSB max

3 ±3LSB max
Bipolar Zero Error ±4 ±3LSB max
Bipolar Zero Error Match 2 ±2LSB max

AD7864-3

Positive Gain Error
Positive Gain Error Match
Negative Gain Error
Negative Gain Error Match

3

3

3

3

±3LSB max

2LSB max

±3LSB max

2LSB max

Bipolar Zero Error ±3LSB max

Bipolar Zero Error Match 2 LSB max

AD7864-2

Positive Gain Error
Positive Gain Error Match

3

3

±3LSB max

3LSB max

Unipolar Offset Error ±3LSB max

Unipolar Offset Error Match 2 LSB max

ANALOG INPUTS

AD7864-1

Input Voltage Range ±5, ±10␣ ±5,␣ ±10␣ Volts
Input Resistance 9, 18 9, 18 kΩ min

AD7864-3

Input Voltage Range ±2.5␣ ±2.5␣ Volts
Input Resistance 4.5 4.5 kΩ min

AD7864-2

Input Voltage Range +2.5, +5␣ +2.5, +5␣ ␣ Volts

Input Current (0 V–2.5 V Option) ±100 ±100 nA max
Input Resistance (0 V–5 V Option) 9 9 kΩ min

REFERENCE INPUT/OUTPUT

V

IN Input Voltage Range 2.375/2.625 2.375/2.625 V

REF

IN Input Capacitance

V

REF

OUT Output Voltage 2.5 2.5 V␣ nom

V

REF

OUT Error @ +25°C ±10 ±10 mV max

V

REF

OUT Error T

V

REF

OUT Temperature Coefficient 25 25 ppm/°C typ

V

REF

V

OUT Output Impedance 6 6 kΩ typ See Reference Section

REF

MIN

to T

4

MAX

10 10 pF max

±20 ±20 mV max

MIN/VMAX

2.5 V ± 5%

–2– REV. A

AD7864

Parameter A Version

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

2.4 2.4 V min V

0.8 0.8 V max V

±10 ±10 µA max

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

DB11–DB0

High Impedance

Leakage Current ±10 ±10 µA max

Capacitance

4

10 10 pF max

Output Coding

AD7864-1, AD7864-3 Twos Complement
AD7864-2 Straight (Natural) Binary

CONVERSION RATE

Conversion Time 1.65 1.65 µs max For One Channel

Track/Hold Acquisition Time

2, 3

0.35 0.35 µs max

Throughput Time 130 130 kSPS max For All Four Channels

POWER REQUIREMENTS

V

DD

I

DD

+5 +5 V nom ±5% for Specified Performance

Normal Mode 24 24 mA max

Standby Mode 20 20 µA max Typically 4␣ µA

Power Dissipation

Normal Mode 120 120 mW max Typically 90␣ mW

Standby Mode 100 100 µW max Typically 20␣ µW

NOTES

1

Temperature ranges are as follows: A, B Versions: –40°C to +85°C. Note: The A Version is fully specified up to +105°C with degraded INL and DNL specifications
of ±2 LSBs max.

2

Performance measured through full channel (SHA and ADC).

3

See Terminology.

4

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

1

B Version Units Test Conditions/Comments

= 5 V ± 5%

DD

= 5 V ± 5%

DD

= 400 µA

SOURCE

= 1.6 mA

SINK

(5 µA typ) Logic Inputs = 0 V or V

DD

–3–REV. A

AD7864

TIMING CHARACTERISTICS

(VD = +5 V ⴞ 5%, AGND = DGND = 0 V, V

1, 2

T

to T

MIN

unless otherwise noted.)

MAX

= Internal, Clock = Internal; all specifications

REF

Parameter A, B Versions Units Test Conditions/Comments

t

CONV

1.65 µs max Conversion Time, Internal Clock

13 Clock Cycles Conversion Time, External Clock

2.6 µs max CLKIN = 5 MHz

t

ACQ

t

BUSY

t

WAKE-UP

t

WAKE-UP

t

1

t

2

—External V
—Internal V

REF

REF

3

0.34 µs max Acquisition Time

No. of Channels Selected Number of Channels Multiplied by
x (t

CONV

+ t9) – t

µs max (t

9

+ EOC Pulsewidth)—EOC Pulsewidth

CONV

2 µs max STBY Rising Edge to CONVST Rising Edge
6ms maxSTBY Rising Edge to CONVST Rising Edge

35 ns min CONVST Pulsewidth
70 ns min CONVST Rising Edge to BUSY Rising Edge

Read Operation
t

3

t

4

t

5

4

t

6

5

t

7

0 ns min CS to RD Setup Time
0 ns min CS to RD Hold Time
35 ns min Read Pulsewidth
35 ns max Data Access Time After Falling Edge of RD, V
40 ns max Data Access Time After Falling Edge of RD, V
5 ns min Bus Relinquish Time After Rising Edge of RD

DRIVE

DRIVE

= 5 V
= 3 V

30 ns max

t

8

t

9

10 ns min Time Between Consecutive Reads
75 ns min EOC Pulsewidth
180 ns max

t

10

t

11

t

12

70 ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling)
15 ns max EOC Falling Edge to FRSTDATA Falling Delay
0 ns min EOC to RD Delay

Write Operation
t

13

t

14

t

15

t

16

t

17

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6␣ V.

2

See Figures 7, 8 and 9.

3

Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1 µF decoupling capacitor on the V

4

Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8␣ V or 2.4 V.

5

These times are derived from the measured time taken by the data outputs to change 0.5␣ V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

20 ns min WR Pulsewidth
0 ns min CS to WR Setup Time
0 ns min WR to CS Hold Time
5 ns min Input Data Setup Time of Rising Edge of WR
5 ns min Input Data Hold Time

pin.

REF

1.6mA

TO

OUTPUT

50pF

400mA

11.6V

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4– REV. A

AD7864

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

V

DD

Analog Input Voltage to AGND

AD7864-1 (±10 V Input Range) . . . . . . . . . . . . . . . . ±20 V

AD7864-1 (±5 V Input Range) . . . . . . . . . . . –7 V to +20 V

AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V to +20 V

AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . .–1 V to +20 V

Reference Input Voltage to AGND . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . –0.3 V to V

+ 0.3␣ V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C

ORDERING GUIDE

Input Relative Temperature Package Package

Model Ranges Accuracy Range* Description Option

AD7864AS-1 ±5 V, ±10 V ±1 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44
AD7864BS-1 ±5 V, ±10 V ±0.5 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44
AD7864AS-3 ±2.5 V ±1 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44
AD7864AS-2 0 V to 2.5 V, 0 V to 5 V ±1 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44

*The A Version is fully specified up to +105°C with degraded INL and DNL specifications of ±2 LSBs max.

PIN CONFIGURATION

DD

DRIVE

V

IN1B

V

DV

IN1A

V

DB6

STBY

DB7

33

DB8

32

DB9

31
30

DB10
DB11

29

CLKIN

28
27

INT/EXT CLK
AGND

26

AV

25

DD

V

24

REF

V

23

REF

GND

BUSY

FRSTDATA

CONVST

CS

RD

WR

SL1
SL2
SL3
SL4

H/S SEL

DB0

DB2

DB1

EOC

1

PIN 1
IDENTIFIER

2
3
4
5
6
7
8

9
10
11

12 13 14 15 16 17 18 192021 22

IN4A

IN4B

V

V

AGND

DB4

DB3

40 39 3841424344 36 35 3437

AD7864

TOP VIEW

(Not to Scale)

IN3B

IN3A

V

V

AGND

DB5

IN2B

V

DGND

IN2A

V

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. A

AD7864

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until

conversion is completed on all selected channels.

2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data

Register Pointer is addressing Register 1—See Accessing the Output Data Registers.

3 CONVST Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their

hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence

Selection is also latched on the rising edge of CONVST.
4 CS Chip Select Input. Active Low Logic Input. The device is selected when this input is active.
5 RD Read Input. Active Low Logic Input that is used in conjunction with CS low to enable the data out-

puts. Ensure the WR pin is at logic high while performing a read operation.
6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0

to DB3 into the channel select register.
7–10 SL1–SL4 Hardware Channel Select. Conversion sequence selection can also be made via the SL1–SL4 pins if

H/S SEL is logic zero. The selection is latched on the rising edge of CONVST. See Selecting a Conver-

sion Sequence.
11 H/S SEL Hardware/Software Select Input. When this pin is at a Logic 0, the AD7864 conversion sequence selec-

tion is controlled via the SL1–SL4 input pins. When this pin is at Logic 1, the sequence is controlled

via the channel select register. See Selecting a Conversion Sequence.
12 AGND Analog Ground. General Analog Ground. This AGND␣ pin should be connected to the system’s

AGND
13–16 V

IN4X

, V

IN3X

Analog Inputs. See Analog Input section.
17 AGND Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND␣ pin should be

connected to the system’s AGND
18–21 V

IN2X

, V

IN1X

Analog Inputs. See Analog Input section.
22 STBY Standby Mode Input. TTL-compatible input that is used to put the device into the power save or

standby mode. The STBY input is high for normal operation and low for standby operation.
23 V

GND Reference Ground. Ground reference for the part’s on-chip reference buffer. The V

REF

should be connected to the system’s AGND
24 V

REF

Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also

allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1 µF decou-

pling capacitor should be connected between this pin and AGND.
25 AV

DD

Analog Positive Supply Voltage, +5.0 V ± 5%.

26 AGND Analog Ground. Analog Ground reference for the DAC circuitry.
27 INT/EXT CLK Internal/External Clock Select Input. When this pin is at a Logic 0, the AD7864 uses its internally

generated master clock. When this pin is at Logic 1, the master clock is generated externally to the

device.
28 CLKIN Conversion Clock Input. This is an externally applied clock that allows the user to control the conver-

sion rate of the AD7864. Each conversion needs fourteen clock cycles in order for the conversion to be

completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than

60/40. See Using an External Clock.
29–34 DB11–DB6 Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output

coding is 2s complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary

for the AD7864-2.
35 DV

DD

Positive supply voltage for digital section, +5.0 V ± 5%. A 0.1 µF decoupling capacitor should be con-

nected between this pin and AGND. Both DV
36 V

DRIVE

This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC and

FRSTDATA. It is normally tied to DV

improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V proces-

sors and DSPs the output data drivers may also be powered by a 3 V ± 10% supply .

37 DGND Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the

system’s AGND
38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL Outputs.
40–43 DB3–DB0 Data Bit 3 to Data Bit 0. Bidirectional Data Pins. When a read operation takes place, these pins are three-

state TTL outputs. The channel select register is programmed with the data on the DB0–DB3 pins with

standard CS and WR signals. DB0 represents Channel 1 and DB3 which represents Channel 4.
44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in

a conversion sequence is indicated by a low-going pulse on this line.

plane.

plane.

DD

plane at the AGND pin.

plane.

and AVDD should be externally tied together.

DD

. V

should be decoupled with a 0.1 µF capacitor. It allows

DRIVE

␣ GND pin

REF

–6– REV. A